Interconnection structures:-

To form a working computer, individual components must be connected in an organized way. The
collection of path connecting components is called the interconnection structure. The design of
this structure is depends on the exchanges that must be made between modules.

When a word of data is transferred between modules, all its bits are transferred in parallel.
A group of wires that connects several devices is called a bus.

1. Single bus structure:-

The simplest way to interconnect functional units of a computer is to use a single system
bus. System bus consists of:-

i) Data bus ii) Address Bus iii) Control Bus

This bus is time shared. Only two units can communicate at any given instant.

Data Bus:- The data lines provide a path for moving data between system modules. These lines,
collectively are called the data bus. Data lines are bidirectional.

Address Bus:- Every device connected to bus has an address. A memory unit is given block of
addresses, depending on number of words in it. For example, if the CPU wishes t read a word of
data from memory, it puts the address of the desired word on the address lines. The address lines
are always unidirectional.

Control Bus:- Control lines are used to control the various units like memory and I/O, processor
uses control signals to control various modules. Control signals transmit both command and
timing information. Control signals specify operation to be performed. Typical control signals
include:- memory read & write, I/O read & write, bus request and bus grant.

The operation of the Bus:- if one module wishes to send data to other, it must do the following:

I. obtain control of Bus.

II. Transfer data via the bus

Receive data from other, then steps:-

 I. Obtain control of Bud.
II. Makes a request to other module over the appropriate control lines and address lines.
III. It must than wait for the requested module to send data.

2. Multiple Bus Hierarchies:-

If a greater number of devices are connected to the bus, performance will suffer due to following
reasons:-

Greater propagation delay.

The bus may become bottleneck as the aggregate data transfer demand approaches the
capacity of the bus.

The principle use of the system bus is high-speed data transfer between the CPU and memory.
Most I/O devices are slower than memory and they are put on the local bus. These devices are
connected to the system bus via interface circuit called I/O controller.

3. Other interconnection structures:- A systems interconnection structure can be

defined by graph whose nodes denote components such a s computers, memory, I/O controller etc.
Edges between these components are known as communication path or buses.

A path designed to link only two devices is said to be dedicated.

A path used to transfer information between different sets of devices at different times is
said to be shared or multiplexed.

There is a dedicated bus between all pairs of components that need to communicate. The general
case in which n units must be connected in possible ways need n*(n-1)/2 dedicated buses. There
will not be any delay due to busy connection. This system will be more reliable as a link failure
effects only two units connected to that link. These units may still be able to communicate via
other units. The main drawback of dedicated buses is their high cost.

Performance of a computer:- The total time needed to execute application

program is the most important measure of computer performance.

1) Performance of a program is affected by the way in which the compiler translates

programs into machine code.
2) The ideal program performance demands a perfect match between machine capability and
program behaviours.
3) Machine capability can be enhanced with: i) better hardware technology ii)
innovative architectural features iii) efficient resource management.
4) A program can be made efficient: i) with better algorithm ii) with better data
structure iii) language efficiency iv) compiler technology.
5) It is impossible to achieve a perfect match between hardware & software by merely
improving only a few factors without touching others.
6) Machine performance may vary from program to program.

The simplest measure of program performance is its turn around time, which includes:-

a) Disk and memory access

b) Input and output activities
c) Compilation time
d) OS overhead
e) CPU time
Standard Buses:- Various components of a system, CPU, cache, main memory, I/O
devices communicate along themselves via buses. Buses consists of physical links & mechanism
for controlling exchange of information.

When two components try to get into communication, one initiating, the communication gets the
control of the bus and is known as master & other is known as slave. Master is responsible for
initiate & terminates the communication. Slave has to respond to each operation initiated by
master.

Data is transmitted over data bus

Address of device or memory is sent over address bus.
Control lines perform the function of identifying the transaction type and synchronizing
communication between fast and slow devices.
Synchronization is handled through timing signals. Timing of data transfer can be handled
by either synchronous or asynchronous bus.

Bus Controller:-
A central arbitration scheme uses a bus controller. It decides about the processor to be granted
access of the bus among requesting processors. The bus controller may be separate module or can
be constructed as the part of the CPU. For example, I/O processor may need control of the bus for
transferring data to memory. Similarly CPU also needs the bus for various activities. Therefore,
the system buses have I/O processor and CPU that need control of bus for data transfer. This is up
to bus controller to resolve the simultaneous data transfer requests on the bus. Completing
requests must be arbitrated on the basis of fairness or priority.

Bus Arbitration:- The process of selecting a processor among requesting processors is known
as arbitration. A selection process must be based on fairness or priority bases. There are three
schemes:-

1) Daisy Chaining:- It is characterized by Bus Grant signal connected serially from master to
master. The process involves three control signals Bus Busy, Bus Request and Bus grant.
 The bus controller responds to Bus request signal only if Bus Busy is inactive. Bus Busy
signal remains active during the period it is being used by any of the processors.
All processor are connected to the Bus request line. A Processor must
request by activating it. The bus controller responds to the bus request signal by placing
the Bus Grant signal on the bus grant line. This device then block further propagation of
signal, activates Bus Busy signal and starts using the bus.
When a non-requesting processor receives the Bus Grant signal, it forwards the signal to
next processor. Selection priority is determined by the proximity of the requesting
processor from the controller.

Advantages:-

Simple arbitration scheme.

Requires very few control lines.
Devices can be added easily.

Disadvantages:-

Priority is wired. So change in priority complex.

Problem of starvation.. If the master 1 is generating Bus request at a high rate than rest of
the masters may not get the bus.
If an ith processor is not working than all processors ahead of it will never get bus grant
line.
2) Polling:- It is the process of calling each master turn by turn. A master is called by its
address. Address of master is generated on poll count lines. These lines are connected to
each device.
A request to use the bus is made on the bus request line. The bus controller responds to a
signal on bus request line by generating addresses in sequence on poll count lines. Each
master is assigned to unique address. When the poll count matches, the master activates
the bus busy signal and starts using the bus.
Advantages:-

Priority can be changed by changing the sequence of the generation of addresses on the
poll count lines.
Failure of one master will not effect other.

Disadvantages:-

Polling requires more control lines.

Maximum number of masters to be connected by bus is restricted by poll count lines. Max.
2^n masters for n poll lines.
Delay in granting control of bus could become large if the number of devices to be polled
in large.
3) Independent Requesting:- In this scheme each master has its independent Bus
Request & Bus grant line. In this scheme the identification of requesting master is almost
immediate and request can be responded quickly. In case of multiple requests, a requesting
master can be selected on the basis of priority. We use priority based policy for I/O
transactions and fairness based policy among the processors.
Register Transfer Logic:- Information stored in one register can be transferred to another
register. A register consists of cells.

A0 A1 A2 .......... ......... An-1 Cells of Register A

Register A

A register transfer operation may be designed as :- R1 R2

Register Transfer Language:- It is a symbolic notation for representing registers, for
specifying operations on the contents of registers and for specifying control functions. A statement
in a register transfer language consists of a control function and a list of micro-operations.

The control function specifies the control condition and timing sequence for executing the
listed micro-operations.
The micro operations specify the elementary operations to be performed on the
information stored in registers. These micro-operations can be classified into four
categories:-
a) Inter register Transfer:- Information moves from one register to other.
b) Arithmetic:- Performed on numbers stored in registers.
c) Logic:- AND, OR, NOT is performed on information stored in registers.
d) Shift:- Micro-operations specify operations for shift registers.

Basic symbols for Register Transfer Language:-

Symbol Description Example

Upper case letters Denotes a Register A, R1
Subscript An Individual Cell A5, B9
Parenthesis A portion of register PC (H), MDR (ADR)
Arrow A Transfer R1 R2
Colon Terminates a control Function x.T1:
Comma Multiple Operations X:R1 R2, R3 R4
Square Brackets Address for memory MDR M[MAR]

Bus Transfer:- A Bus consists of number of lines, each line carries 1 bit of data. A common bus
system is used to reduce the wiring density. Binary information can be transferred from one
register to another register using the bus. For parallel transfer, the number of lines in the bus is
equal to the number of bits in the register. A common bus system can be constructed using
multiplexers. Destination register can be selected by means of decoder.

Memory Transfer:- Two operations are performed on memory:

Read: from memory to a register

Write: from register to memory

Each memory transfer operation should specify the address of the memory (M) location and the
control signal R (Read) for reading or W (write) for writing.

Fig. 1.48

Address of memory location can be stored in MAR (memory address register). Buffer register
MBR (memory buffer register) can be used to transfer data into and out of memory.

The read operation transfers a data from the selected memory location into MBR. Read operation
can be written as:

R: MBR M[MAR]

Control function R initiates the read operation. This causes a transfer of information into MBR
from the selected memory location of M specified by the address in MAR. Write operation can be
written as :

W: M[MAR} MBR

Control function W initiates the write operation. This causes a transfer of information from MBR
into the memory location specified by the address in MAR