Four 64K Code Banks

This example demonstrates the configuration required to bank switch using one 256 KByte
EPROM and four 64 KByte banks. The following figure illustrates the hardware schematic.

The following figure illustrates the memory map for this example.

One 256 KByte EPROM is used in this hardware configuration. Bank switching is implemented
using two bank select address lines (Port 1.5 and Port 3.3). The configuration file
(L51_BANK.A51) is configured as follows:

?N_BANKS EQU 4 ; Four banks are required.

?B_MODE EQU 4 ; user-provided bank switch code.

The section in L51_BANK.A51 that begins with IF ?B_MODE = 4 defines the code that
switches code banks. This section must be configured as follows:

P1 DATA 90H ; I/O Port Addresses

P3 DATA 0B0H ; "

SWITCH0 MACRO ; Switch to Memory Bank #0

CLR P3.3 ; Clear Port 3 Bit 3
CLR P1.5 ; Clear Port 1 Bit 5
ENDM

SWITCH1 MACRO ; Switch to Memory Bank #1

SETB P3.3 ; Set Port 3 Bit 3
CLR P1.5 ; Clear Port 1 Bit 5
ENDM

SWITCH2 MACRO ; Switch to Memory Bank #2

CLR P3.3 ; Clear Port 3 Bit 3
SETB P1.5 ; Set Port 1 Bit 5
ENDM

SWITCH3 MACRO ; Switch to Memory Bank #3

SETB P3.3 ; Set Port 3 Bit 3
SETB P1.5 ; Set Port 1 Bit 5
ENDM

Add the following to your startup code (STARTUP.A51) to ensure that the CPU starts in a
defined state at reset:

MOV SP,#?STACK-1

P1 DATA 90H ; I/O Port Addresses

P3 DATA 0B0H
EXTRN DATA (?B_CURRENTBANK)
MOV ?B_CURRENTBANK,#0 ; Select code bank 0
CLR P3.3 ; Clear Port 3 Bit 3
CLR P1.5 ; Clear Port 1 Bit 5

JMP ?C_START

The linker automatically adjusts the size of the common area places copies of it into each bank.
This makes the contents of all code banks identical in the address range of the common area.
The BANKAREA directive is not required (the default address range is 0-0xFFFF).

32K Common Area

The following schematic shows hardware that has a 32 KByte common area and seven
32 KByte code banks. A single EPROM is used for all code space. Due to the address decoding
logic, code bank 0 is identical to the common area. Therefore, it should not be used by the
application.

This design provides 256 KBytes of xdata memory that is mapped like the code memory but is
accessed using the /RD and /WR lines (instead of the /PSEN line). The xdata space may be
used for variable banking.

The following figure illustrates the memory map for this example.

For this hardware the configuration file (L51_BANK.A51) is configured as follows:

?N_BANKS EQU 8 ; Eight banks are required.

?B_MODE EQU 0 ; banking via on-chip I/O Port.
?B_VAR_BANKING EQU 1 ; you may use also variable banking.
?B_PORT EQU 090H ; Port address of P1.
?B_FIRSTBIT EQU 2 ; Bit 2 is the first address line.

You must not use code bank 0 in your application (this memory is identical to the
common area). Therefore, no module of your application may be assigned to code bank
0.

The BANKAREA directive must be set as follows:

LX51 BANK1 {A.OBJ}, ..., BANK7{G.OBJ} ... BANKAREA (0x8000,0xFFFF)

To use variable banking you must define the additional memory

using HDATA and HCONST memory classes as follows:

LX51 BANK1 {A.OBJ}, ..., BANK7{G.OBJ} ... BANKAREA (0x8000,0xFFFF)

CLASSES (XDATA (X:0-X:0x7FFF),

HDATA (X:0x18000-X:0x1FFFF,X:0x28000-X:0x2FFFF,

X:0x38000-X:0x3FFFF,X:0x48000-X:0x4FFFF,

X:0x58000-X:0x5FFFF,X:0x68000-X:0x6FFFF,

X:0x78000-X:0x7FFFF),

HCONST (C:0x18000-C:0x1FFFF,C:0x28000-C:0x2FFFF,

C:0x38000-C:0x3FFFF,C:0x48000-C:0x4FFFF,

C:0x58000-C:0x5FFFF,C:0x68000-C:0x6FFFF,

C:0x78000-C:0x7FFFF))

XDATA Port

A latch or I/O device mapped into the XDATA space may be used to extend the address lines of
the 8051 device. The following example illustrates hardware that uses a latch mapped into the
XDATA space to address a 512 KByte EPROM.

The following figure illustrates the memory map for this example.

The configuration file (L51_BANK.A51) is configured as follows:

?N_BANKS EQU 8 ; Eight banks are required.

?B_MODE EQU 1 ; bank switch via xdata port.
?B_XDATAPORT EQU 0 ; any I/O address can be given for the example.
?B?FIRSTBIT EQU 0 ; bit 0 is used as first address line.

No changes are required in the startup code (STARTUP.A51).

The linker automatically adjusts the size of the common area places copies of it into each bank.
This makes the contents of all code banks identical in the address range of the common area.
The BANKAREA directive is not required (the default address range is 0-0xFFFF).
5

 On-chip ROM

Many 8051 derivatives have SFRs that configure on-chip code space which you may use to
introduce code banking to existing hardware designs.

For example, if your hardware uses a Dallas 80C320 (ROM-less device) and an external 64
KByte ROM, you may increase the code space of this design with a Dallas 80C520 which offers
16 KBytes of on-chip ROM. The Dallas 520 has a ROMSIZE SFR which enables or disables the
16K on-chip ROM block.

The figure on the right shows the memory layout for such a configuration.

The following settings in the code banking configuration file (L51_BANK.A51) are required.

?N_BANKS EQU 2 ; Two banks are required.

?B_MODE EQU 4 ; User-provided bank switch code.

The section in L51_BANK.A51 that begins with IF ?B_MODE = 4 defines the code that
switches code banks. This section must be configured as follows:

ROMSIZE DATA 0C2H ; SFR Address

SWITCH0 MACRO ; Switch to Memory Bank #0

MOV ROMSIZE,#05H ; Enable on-chip 16KB ROM
ENDM

SWITCH1 MACRO ; Switch to Memory Bank #1

MOV ROMSIZE,#00H ; Disable on-chip 16KB ROM
ENDM

Add the following to your startup code (STARTUP.A51) to ensure that the CPU starts in a
defined state at reset:

MOV SP,#?STACK-1

ROMSIZE DATA 0C2H ; SFR Address

EXTRN DATA (?B_CURRENTBANK)
MOV ?B_CURRENTBANK,#0 ; select code bank 0
MOV ROMSIZE,#05H ; start with on-chip ROM enabled

JMP ?C_START

The linker BANKAREA directive is configured as follows:

LX51 ... BANKAREA (0,0x3FFF)