IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO.

9, SEPTEMBER 2011 2265

A Novel Frequency Control Loop

for Tunable Notch Filters
Javier R. De Luis, Member, IEEE, Qizheng Gu,
Arthur S. Morris, Senior Member, IEEE, and Franco De Flaviis, Senior Member, IEEE

AbstractIn this paper, a novel frequency control loop system

for tunable notch filters is presented. The frequency control loop is
designed for automatically tuning a microelectromechancial sys-
tems tunable notch filter, which has 22-dB rejection in the notch
band and less than 0.8-dB insertion loss over a 5-MHz passband
bandwidth in the International Mobile Telecommunications band
(2.1 GHz). The filter frequency control loop is based on sensing the
reflection phase change of a reference signal (in this case, the trans-
mitter carrier) and is developed to track the transmitter operation
frequency.
Index TermsActuation delay, filter frequency control loop,
loop convergence, notch filter, RF microelectromechanical systems
Fig. 1. RF front-end block diagram of CDMA/WCDMA mobile transceivers.
(MEMS), tunable capacitors, tunable filter.

requirements. However, the frequency of these SAW filters is

I. INTRODUCTION
N A frequency division duplex (FDD) wireless transceiver,
I such as code division multiple access (CDMA) and wide-
band code division multiple access (WCDMA), the transmitter
and receiver sections of a mobile station must operate simultane-
ously. A typical RF FDD front-end single-band block diagram
of the wireless transceiver is shown in Fig. 1 [1].
The duplexer in the RF front-end is used to separate the trans-
mission and reception signals. The duplexer specification re-
quirements on suppressing unwanted signal and/or interference
are very high. Typically, 55 dB or greater of isolation is required
to suppress the transmission signal leaking into the receiver and
a minimum of 45 dB is required to suppress the transmitter noise
in the receiver frequency band. Excessive transmission leakage
through the duplexer to the receiver will cause inter-modula-
tion and/or cross-modulation interference desensitizing the re-
ceiver [1]. An external bandpass surface acoustic wave (SAW)
filter having out-of-band rejection level of approximately 20 dB
can be placed after the low-noise amplifier (LNA), as shown
in Fig. 1, to relax the mixer linearity and duplexer rejection
Manuscript received December 21, 2010; revised June 11, 2011; accepted
June 20, 2011. Date of publication August 08, 2011; date of current version
September 14, 2011.
J. R. De Luis is with Wispry Inc., Irvine, CA 92618 USA, and also with the
Electrical Engineering and Computer Science Department, University of Cali-
fornia at Irvine, Irvine, CA 92697 USA (e-mail: jrodrig2@uci.edu).
Q. Gu and A. S. Morris are with Wispry Inc., Irvine, CA 92618 USA (e-mail:
qizheng.gu@wispry.com; art.morris@wispry.com).
F. de Flaviis is with the Electrical Engineering and Computer Science De-
partment, University of California at Irvine, Irvine, CA 92697 USA (e-mail:
franco@uci.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2011.2160962
0018-9480/$26.00 2011 IEEE
not tunable, and thus multiple SAW filters may be needed for
a multiband transceiver resulting in increased size, component
count, and cost.
In order to address these problems, tunable solutions such
as YIG filters have been proposed [2], which exhibit low
loss and broad tuning bandwidth characteristics, but require
an externally applied magneto-static field, suffer from slow
tuning times due to hysteresis effects and exhibit high power
consumption.
Tunable filters based on distributed circuit designs, using
topologies such as combline, interdigitated, slotted, and cou-
pled lines, have been reported in [3][8]. However, the large
footprint required becomes the main disadvantage for any
distributed filter implementation when designed for operation
in typical cell phone frequency bands (700 MHz2.7 GHz). In
general, either acoustic or tunable lumped element filters must
be used to meet cell-phone real-estate constraints.
In this paper, an improved version of the notch filter of [9],
having less than 0.8-dB passband insertion loss is presented.
Section II presents the theoretical analysis of the filter, while
Section IV-A focuses on its implementation and measurement
results.
In the application of wireless mobile station transceivers, the
narrow band notch filter frequency needs to have frequency ac-
curacy within 100 kHz for 2.5G and 3G mobile stations where
the channel spacing is 200 kHz. Therefore, accurate frequency
selection and tracking capabilities are required. A novel filter
frequency control loop based on sensing the reflection phase
of the leaking transmitter signal has been developed and de-
signed for this objective. The filter frequency control loop uses
the transmitter carrier itself as a reference signal to keep the filter
tracking the transmitter operation frequency.
A mathematical model is developed to theoretically analyze
the notch filter frequency control loop. A closed-form solution
2266 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011

Fig. 3. S -parameter response of notch filter without the nearby coexisisting

Fig. 2. Circuit schematic of the SPSZ tunable filter design. passband.

to the frequency control loop equation is derived in Section III.

Circuit model simulations in Section III-C are employed to vali-
date the theoretical solution, to investigate the loop control tran-
sient behavior, and to consider design parameter tradeoffs. Fi-
nally, Section IV-B describes the implementation and perfor-
mance assessment of the control loop and its interaction with the
tunable filter to conform the overall autonomous tunable filter
system.

II. MICROELECTROMECHANICAL SYSTEMS (MEMS)

TUNABLE NOTCH FILTER DESIGN BRIEFING
In practical notch filter designs, a single bandpass is usu-
ally designed to coexist near the notch frequency. When this
is the case, the design is also referred to as a single-pole single-
Fig. 4. Block diagram of tunable notch filter automatic frequency control loop
zero (SPSZ) filter denoting a unique pole and zero in the filter utilizing reflected reference signal.
transfer function. The proposed notch filter consists of a se-
ries- resonator (dashed box in Fig. 2) providing the signal
notch or rejection at a transmitter frequency, and two shunt ca- Capacitor serves the purpose of effectively decreasing
pacitors and that combine with the excess reactance of the tunable capacitance step size and increasing the fre-
the series- resonator to form a low-loss passband at the cor- quency tuning resolution. Note that is not necessary if
responding receiving frequency. The proposed tunable notch was an analog continuously adjusted capacitor or digitally tun-
filter circuit using tunable components is shown in Fig. 2. This able capacitor with high resolution, i.e., small enough step size.
topology allows for the notch filter suppression and the band- The center frequency of this notch filter should be capable of
pass filter insertion loss to be tuned separately. All the tunable being tuned to cover the entire International Mobile Telecom-
capacitors, and , used in this filter are RF MEMS ca- munications (IMT) transmission frequency band (from 1.92 to
pacitors.1 1.98 GHz).
This series- block comprising and , which can On the other hand, the bandpass filter is comprised of
resonate at the notch frequency the series- in combination with the tunable capacitors
and , which are located in a symmetrical fashion on
(1) both sides of the resonator. This arrangement allows for
impedance matching conditions at ports 1 and 2 to be as
where represents the resonator composite capacitance re- identical as possible.
sulting from the series connection of and that can be ex- The total capacitance of plus for resonating at the
pressed as receiver frequency can be obtained from (3) as follows:

(2)
(3)
1Wispry Inc. Tunable RF Solutions, Irvine, CA. [Online]. Available: www.
wispry.com
DE LUIS et al.: NOVEL FREQUENCY CONTROL LOOP FOR TUNABLE NOTCH FILTERS 2267

Fig. 5. Mathematical model of notch filter frequency automatic control loop utilizing the reflection signal.

The -parameters for the notch and bandpass combination from the filter (i.e., the phase information of the around
filter can be derived and expressed as the notch frequency). The advantage of sensing is that the
magnitude of the reflection coefficient of the notch filter near
its notch frequency is very high. In addition, the reflection
phase behavior versus frequency is continuous across its notch
frequency in a quasi-linear fashion, as shown in Fig. 3.
(4)
The block diagram of a proposed novel tunable notch filter
(5) automatic frequency control loop utilizing the reflected refer-
ence signal is shown in Fig. 4. This control loop will tune the
where filter notch frequency to suppress the transmitter leakage by uti-
lizing the transmitter carrier with a frequency as the refer-
ence signal. Fig. 4 visually explains the operation principle of
(6) this frequency control loop and its fundamental building blocks.

where is the reference impedance. It is expected that B. Mathematical Model and Formulation
(symmetric matching condition) only if the capacitors Under the assumption that the notch filter can be modeled
and are identical. as a voltage-controlled analog tunable filter, the notch filter au-
tomatic frequency control loop can be fully characterized by a
III. NOTCH FILTER FREQUENCY CONTROL LOOP BASED ON
mathematical model, as presented in Fig. 5.
REFLECTED REFERENCE SIGNAL
The transfer function of the notch filter reflection
A. System Description versus input reference signal can be found and expressed as
The notch filter in Section II provides an inherent narrow re-
jection bandwidth. To achieve the accurate frequency tuning of
the narrowband notch filter, a frequency automatic control loop
is required for applications in cellular mobile transceivers. This
loop utilizes the transmitter carrier as a reference signal and
uses its reflection phase change from the notch filter to tune
the notch filter frequency in order to track the mobile station (7)
transmitter signal. To the authors knowledge, a frequency con-
trol loop for automatically tuning a narrow bandwidth notch where
filter has not been reported to date, although a frequency auto-
matic control loop for monolithic microwave integrated circuit (8)
(MMIC) bandpass filters has been discussed in [10][13]. The
bandpass filter frequency control loops are usually based upon
(9)
sensing the transmission coefficient phase (or phase).
One key difference to bandpass filters is that the signal
passing through the notch filter should be suppressed to a very and are the inductance and capacitance of the series-
weak level. Additionally, the notch filter presents a 180 notch filter (refer to Fig. 4)
phase jump at its notch (or center) frequency (Fig. 3). As a Note that for the mathematical description in this section a
consequence, it is difficult to utilize the transmission phase simple notch filter (a series- filter , as seen in Fig. 4) is con-
information for the frequency control loop to tune the filter sidered to simplify the expressions. However, the same proce-
frequency. dure can be made analogously in the case of having a nearby
In the case of notch or other narrowband rejection filters, we passband (Fig. 2) working from (5) at the expense of a consid-
can use the phase information of the reflected reference signal erable increase in the solution complexity. From the frequency
2268 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011

control loop mathematical model of Fig. 5, we can derive the

automatic frequency control loop equation of the notch filter as
(see Appendix A for its derivation)

(10)

Fig. 6. Comparison of closed-form expressions and ADS simulations for the

where is the low-pass filter cutoff frequency , second-order filter response with ! = 20
kHz, A = 0 12 1 = 15
: ; ! MHz,
and is the MEMS capacitor actuation delay time. Q = 1000 , and  =0 and 10 s.
Equation (10) is a second-order nonlinear differential equa-
tion. From this equation, we can see that the output signal level
from the phase detector (P.D.) is not only dependent on the
phase difference between the reference signal and the reflected
signal by the notch filter, but also upon the magnitude of the
reflected signal. However, the magnitude variation near the fre-
quency within the notch filter bandwidth is very small. In ad-
dition, the logarithmic amplifier further reduces the P.D. output
signal amplitude difference.
Considering and in the filter both having a finite factor,
they can be expressed as

(11)
(12)
and
(13) Fig. 7. Simulated filter frequency control loop transient response for different
Q values with ! = 20 kHz, A = 0 12
: and ! 1 = 15 MHz,  =0 s.

Substituting (13) and into (10) and

where is the maximum frequency control range
considering the magnitude of the P.D. inputs being constant,
achieved when , which is determined by the
and , we obtain a differential equation of
overall loop gain and the P.D. output low-frequency signal level
as

(16)

The process of solving (15) by using Laplace transformation

is not described here in detail as it involves lengthy manipula-
(14) tions. During this solution process, in order to find a closed-form
solution for the inverse Laplace transform, we need to assume
that the MEMS capacitor actuation delay is small (to linearize
). Equation (15) can be approximately
With the above assumptions, the right-hand side of (14) can be
solved by using Laplace transformation and the final time-do-
further linearized as (15)
main solution is shown in (17), at the bottom of the following
page, where

(18)
(19)
(15)
DE LUIS et al.: NOVEL FREQUENCY CONTROL LOOP FOR TUNABLE NOTCH FILTERS 2269

TABLE I
FINAL FREQUENCY ERROR VERSUS Q VALUE

and is the initial filter frequency error when . The fre- conclude that
quency control error of the filter control loop depends upon the
factor of the notch filter and the value of the fixed inductor (24)
. The final frequency error can be obtained by using (17) and
letting
C. Calculations and Simulations of Notch Filter Frequency
(20) Control Loop Performance
In this section, the effect of several parameters in the per-
Note that (20) can be also interpreted as the final frequency formance of the tunable notch filter and control loop system
error related to the notch/rejection bandwidth if we consider (locking time, final frequency error, and exponential behavior)
. The gain loop parameters and can are studied in detail.
be set during the design or selection of the building blocks in The notch filter under the study is implemented by using a fix
the control loop (integrator, P.D., amplifier gain, and input ref- value inductor nH and a pF, which produces a
erence signal level, respectively). The parameter , frequency notch frequency at 2 GHz. Other variables that are kept constant
tuning rate per volt, can be derived as follows. The capacitance in this study are and .
versus control voltage equation can be expressed as When kHz, , and s
(close to real MEMS actuation delay), the transient responses
of this frequency control to an initial frequency offset (
(21)
MHz) derived from (17) and ADS simulations are shown
Using (21), the filter instantaneous notch frequency can be in Fig. 6. Good agreement of the results obtained from both
written as approaches can be observed for both cases of actuation delay,
which validates the theoretical approach solution.
Using the same loop parameters as above, the locking time
responses for the filter when and are
shown in Fig. 7. All responses have similar exponential be-
havior, but the final frequency error decreases with a in-
crease. Table I shows the numerical final frequency error for all
(22) considered values.
The low-pass filter cutoff frequency or the loop bandwidth
where is the capacitance when the control voltage impacts the filter frequency locking time. The locking time re-
(i.e., ) and is a constant that depends on the MEMS sponses for different and
tunable capacitor design that relates capacitance to applied bias MHz, and are shown in Fig. 8. Small values create
voltage. We can linearize (22) using a Taylor series expansion damped oscillations in the transient responses, and therefore,
series as longer frequency locking times. To achieve a shorter frequency
convergence time for this loop, we choose the cutoff frequency
kHz in the final design.
(23) The overall loop gain (controlled by parameter , etc.) im-
pacts the locking time and oscillatory behavior. A high loop
The terms in (23) can be associated with those from the gain may cause frequency divergence situations. Fig. 9 shows
frequency voltage tuning equation to the filter frequency control error transient response for different

(17)
2270 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011
Fig. 8. Simulated filter frequency control loop transient response for different
! values with Q = 80 = 0 12
; A : and ! 1 = 15 MHz,  =0 s.
Fig. 9. Simulated filter frequency control loop transient response for different
values of A with ! = 20 kHz, Q = 80 1 = 15
and ! MHz,  =0 s.
values of . The number of oscillations and locking time in-
creases with an increasing gain. It was found that a gain value
higher than results in a divergent situation. Due to the
loop gain importance, good care must be given not to exceed the
convergence threshold during the control loop design.
The capacitor actuation delay time can also affect the fre-
quency locking time of the filter and may cause a divergent so-
lution. The filter frequency control error transient response for
different MEMS capacitor actuation delays is shown in Fig. 10.
The time scale has been expanded to 3 ms in order to observe
convergence. For delay times larger than 150 s, the filter fre-
quency control loop becomes unstable and the frequency is di-
vergent. It is important to choose the overall loop gain in con-
sonance with the actuation delay time to make the loop operate
in the convergent region with the fastest locking time. A low
loop gain should be chosen for large actuation delays of tunable
capacitors. In this case, the price of achieving convergence is a
longer locking time.
Fig. 10. Simulated filter frequency control loop transient response for different
 values with Q = 80 ;! = 20 kHz and !1 = 15 MHz, A = 0 03
: .
IV. IMPLEMENTATIONS AND MEASUREMENTS
In this section, the standalone tunable filter implementation
is first discussed. The filter is then integrated with a discrete im-
plementation of the control loop to confirm the overall tunable
filter system. The total system performance is evaluated through
the filter transient response and reference signal tracking capa-
bility.
A. Standalone Tunable Filter
An existing high- tunable digital capacitor array flip-chip
solution from Wispry Inc., Irvine, CA, was utilized in the de-
sign. The capacitor array consists of 20 tunable capacitor cells
of nominal value 1 or 0.875 pF depending on the specific cell.
The minimum capacitance step resolution is 0.125 pF. The cells
in the array can be interconnected with traces on the printed cir-
cuit board (PCB) in order to achieve any desired topology.
The of the die level capacitors was measured to be greater
than 150 at 2 GHz, allowing low insertion-loss designs. In addi-
tion, the value of capacitance is highly repeatable, which is an
important feature for narrowband tunable filtering circuits. The
third-order intercept point (IP3) level for this device is 65 dBm.
The group-delay distortion is below 1 ns in the received signal
passband. The CMOS biasing circuitry is integrated in the same
chip and transforms a 3.3-V supply voltage to the required 35-V
voltage actuation level. The current consumption is 6 and 90 A
in the sleep and the active mode (charge pump on), respectively.
A serial peripheral interface (SPI) is used to control the capac-
itor banks states. A USB port is used to transmit the tuning com-
mands from PC control software.
Two identical filters were designed using a single tunable ca-
pacitor array die. The objective is to involve one of the filters
in the control loop system and replicate any action taken in the
remaining filter that is used for monitoring and reproducibility
testing purposes. The final PCB layout distribution can be seen
in Fig. 11, where the tunable capacitors cells that group to form
and are clearly indicated. 6 bits control capacitor ,
DE LUIS et al.: NOVEL FREQUENCY CONTROL LOOP FOR TUNABLE NOTCH FILTERS
Fig. 11. Detailed capacitor cell routing underneath flip chip die. C and C
use two basic cells with 1.875 pF total, while C is composed of six cells for a
total of 5.875 pF. Two identical filters are shown having a mirror configuration
and sharing the same die.
Fig. 12. Measurement results for the transmission and return-loss characteris-
tics of the SPSZ tunable filter when tuning resonator block capacitor C .
while 4 bits are used for and . Fig. 11 also provides infor-
mation on how the cells are interconnected underneath the chip
showing that half of the chip cells where used for each filter.
The SPSZ filter of Section II was fabricated using a
0.254-mm-thick Rogers 4003C substrate (
at 2.5 GHz) backed with 14- m-thick copper. The
components used for the filter are an SMD 0402 Murata high-
multilayer ceramic capacitor of value pF and 0603
chip CoilCraft inductors of value nH.
The measured transmission and return loss of the filter for
all different tuning states of the resonator block are shown in
Fig. 12. The measured suppression in the transmitter band is
equal or higher than 22 dB within a 5-MHz bandwidth, and the
insertion loss in the receiver band is less than 0.8 dB within the
reception signal of 5-MHz bandwidth. The return loss is better
than 20 dB in the passband on the receiver side. The suppres-
sion level is almost constant, as shown in Fig. 12, when the
notch filter is tuned over the entire transmitter operating band
(19201980 MHz). Table II summarizes the suppression and
insertion-loss levels achieved by tuning the tunable capacitor
2271
TABLE II
SUMMARY OF SUPPRESSION AND INSERTION
LOSSES WITHIN 5-MHz BANDWIDTH
Fig. 13. Discrete component implementation of the proposed notch filter con-
trol loop.
array chip for the two limiting frequency pairs 1.922.11 GHz
and 1.982.17 GHz.
B. Notch Filter Frequency Control Loop
The notch filter control loop was implemented using discrete
components, as shown in Fig. 13, to prove the concept (the inte-
grated circuit (IC) implementation is reserved as future work).
A 20-dB directional coupler (Meca 722S-20-1.950) distributes
the input and reflected leakage signals. An analog adjustable
phase shifter (Narda 3752) was used to provide the 90 phase
difference at the P.D. input when the transmit leakage and notch
frequency are aligned. The P.D. board (AD8302) includes the
logarithmic amplifiers and provides a single-ended output with
dynamic range between 02 V. The integrator is implemented
using an operational amplifier (THS3091DDA). The low-pass
filter is a single-stage RC circuit with a cutoff frequency of
kHz. The analog-to-digital convertor (ADC) (NI USB-6009)
is used to convert the output voltage from the integrator into a
digital signal. A PC was used here as an encoder in order to gen-
erate the tuning words that actuate the tunable RF MEMS capac-
itors. The communication link between the PC and the tunable
capacitor die is based on SPI commands sent via the USB-SPI
interface (Total Phase Cheetah). The left tunable filter ports are
connected to a vector network analyzer (VNA) for monitoring
purposes.
Due to the unknown delay associated with the ADC and PC
processing speed, it is very difficult to accurately determine the
fast filter locking response time. Therefore, in order to check the
filter convergence, the time axis is considered here as number
of iterations (or tuning words) required for the filter to achieve
the frequency tracking. The locking time can then be estimated
by multiplying the number of iterations by the MEMS actuation
delay (typically 10 s with this technology). The final estimated
value would be reasonably close to the expected locking time in
a future IC implementation.
2272 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011
Fig. 14. Measured filter frequency control loop transient response for A
1 = 49
and ! MHz.
Fig. 15. Measured filter frequency control loop transient response for A
1 = 49
and ! MHz.
The loop performance and locking time will be evaluated in
high or low loop gain conditions. Due to the digital nature of
the tunable notch filter, only certain discrete frequency states are
possible, which explains the expected step behavior of locking
time response curves.
Fig. 14 shows the filter transient response when the initial fre-
quency offset MHz and the loop gain . In
this case, approximately 35 iterations where needed to achieve
convergence yielding an estimated locking time of 350 s. The
behavior matches reasonably well with the predicted behavior of
Fig. 9. It is important to note that the longer locking time is due
to additional system delays of this large-scale discrete imple-
mentation such as, long cables, ADC, PC data collection, VNA
data refresh, general purpose interface bus (GPIB) acquisition,
etc.
Fig. 15 shows the transient response when the gain is in-
creased to . The system then presents oscillations that
are eventually damped to reach convergence in approximately
125 iterations (1250 s). This control loop may result in diver-
gence when . integrator, as shown in Fig. 16. From this figure, we can obtain
Fig. 16. Low-pass loop filter and integrator.
The estimation of the filter frequency error in this practical
discrete implementation is a very challenging task for several
reasons, which are: 1) the tuning resolution of the present die
being 0.125 pF, the tunable digital filter can only achieve cer-
tain frequencies; 2) the noise pick-up of the discrete system
is not negligible; and 3) the ADC number of bits is limited.
= 0:3 The final frequency error of this experimental filter frequency
control loop will not exclusively depend on the quality factor
of the components, but will be considerably affected by the
above-mentioned factors.
Assuming these limitations, we tried to estimate the final
frequency for our discrete implementation by changing the
filter external components to nH and pF
(Fig. 2), which reduces the step resolution to a maximum
of 500 kHz at the expense of reduced notch tuning range of
5.6 MHz. The loop gain was chosen as in Fig. 14 to avoid
oscillations in the response. An experiment was conducted
choosing a different MHz. The maximum recorded
frequency error is 277 kHz for this particular implementation.
The final frequency control error could be further reduced
if the filter frequency tuning resolution and the overall
factor increase. Reducing the capacitance step size in order
to increase the tuning resolution could be achieved by using
smaller capacitor beams.
=3
V. CONCLUSION
A novel frequency control loop for tunable MEMS notch fil-
ters has been presented. The theoretical analysis and the derived
closed-form solutions and formulas have been proved useful to
understand the design and provide an implementation of the
notch filter frequency control loop. The control loop and the
tunable MEMS notch filter presented in this paper can be prac-
tically used in wireless mobile stations transceivers after they
are possibly integrated into RF ICs. The notch filter frequency
control loop formulation developed here is not only applicable
to this specific filter topology, but can be applied to any narrow-
band bandstop tunable filters. Concepts of this tunable filtering
system may be also used in the design of a more complex future
tunable duplexer system.
APPENDIX A
DERIVATION OF THE FREQUENCY CONTROL LOOP
DIFFERENTIAL EQUATION
We derive the differential equation of the notch filter fre-
quency control loop starting with the low-pass loop filter and
DE LUIS et al.: NOVEL FREQUENCY CONTROL LOOP FOR TUNABLE NOTCH FILTERS
the following equations:
(25)
(26)
(27)
(28)
Substituting (26)(28) into (25) and rearranging its terms, we
have the second-order nonlinear differential equation
(29)
where
(30)
The frequency voltage tuning equation of the notch filter is
(31)
(32)
Substituting (32) into (29), we derive the differential equation
(33)
Finally, using the transfer function (7) of the notch filter reflec-
tion coefficient, we finally obtain the differential equation (10).
ACKNOWLEDGMENT
The authors would like to acknowledge J. Hilbert, Wispry
Inc., Irvine, CA, for providing them with the opportunity to
work on these projects and his constant encouragement. Spe-
cials thanks to L. Tranh for his effort in creating the initial
ADS program for the frequency control loop simulations, and
H. Guron, Wispry Inc., Irvine, CA, for programming the ADC
used in the experimental control loop.
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High Power Microw. Electron. Meas., Identification, Appl. Conf., 1999,
pp. IV7I12.
[13] L. Billonnet et al., Recent advances in microwave active filter design,
part 2: Tunable structure and frequency control techniques, Int. J. RF
Microw., vol. CAE 12, pp. 177189, 2002.
Javier R. De Luis (S09M11) was born in Elche,
Spain, in 1982. He received the Telecommunication
Engineer degree from the Universitat Politcnica
de Catalunya (UPC), Barcelona, Spain, in 2006,
the M.S. degree from the University of California
at Irvine (UCI), in 2008, and is currently working
toward the Ph.D. degree in electrical engineering at
UCI.
His current research is focused on reconfigurable
antennas for tunable RF handset front-end and smart
systems.
Qizheng Gu graduated from Fudan University,
Shanghai, China, and received the Doctoral degree
from Nihon University, Tokyo, Japan.
From 1983 to 1993, he was a Visiting Scientist
and then a Research Scientist with the Research
Laboratory of Electronics, Massachusetts Institute
of Technology (MIT). He worked in industry with
Pacific Science Communications Inc. (PCSI), and
since 1993, with Rockwell Semiconductor System,
San Diego, CA. In 1998, he joined the San Diego
Research and Development Center, Nokia Inc.,
where he was a Technology Fellow of RF System Architecture and Engi-
neering. He is currently with Wispry Inc., Irvine, CA, as a Director of RF
Systems Architecture. He has authored or coauthored many journal papers
and three books, including RF Systems Design of Transceivers for Wireless
Communications (Springer, 2005). He has also authored two books in Chinese.
He holds and has applied for over eight patents in RF system architecture area.
2274 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 9, SEPTEMBER 2011
Arthur S. Morris (S89M91SM04) received the
B.S. degrees in physics and electrical engineering and
M.S. and Ph.D. degrees in electrical engineering from
North Carolina State University (NCSU), Raleigh, in
1983, 1986, and 1993, respectively.
As a Scientist/Engineer concentrating on phys-
ical electronics and electromagnetic fields for
over 30 years, he has contributed to device tech-
nologies ranging from traveling-wave tubes to
millimeter-wave heterojunction bipolar transistors
and has developed products for markets from
high-voltage instrumentation to broadband communication systems. In 1999,
he joined Coventor, to lead software and hardware development to drive the
transition of MEMS and microsystems from the laboratory into products for RF
and optical applications. A cofounder of Wispry Inc., Irvine, CA (which spun
out of Coventor in 2002), he is the Chief Technical Officer (CTO), leading the
development of programmable RF products for high-volume markets utilizing
MEMS, CMOS, and microstructures. He is an Adjunct Professor at NCSU.
Dr. Morris is a member of Phi Kappa Phi, Eta Kappa Nu, and Tau Beta Pi.
Franco De Flaviis (M99SM07) was born in
Teramo, Italy, in 1963. He received the Laurea de-
gree in electronics engineering from the University
of Ancona, Ancona, Italy, in 1990, and the M.S.
and Ph.D. degrees in electrical engineering from the
University of California at Los Angeles (UCLA), in
1994 and 1997, respectively.
In 1991, he was with Alcatel, where, as Re-
searcher, he specialized in the area of microwave
mixer design. In 1992, he was a Visiting Researcher
with UCLA, where he was involved with low
intermodulation mixers. He is currently a Professor with the Department of
Electrical Engineering and Computer Science, University of California at
Irvine. He has authored or coauthored over 100 papers in refereed journals and
conference proceedings. He has authored one book and three book chapters.
He has filed several international patents. His research interests include the
development of microelectromechanical systems (MEMS) for RF applications
fabricated on unconventional substrates such as PCB and microwave laminates
with particular emphasis on reconfigurable antenna systems. He is also active
in the research field of highly integrated packaging for RF and wireless
applications.
Dr. De Flaviis is a member of URSI Commission B.