Lecture #29

ANNOUNCEMENTS
HW#15 will be for extra credit
Quiz #6 (Thursday 5/8) will include MOSFET C-V
No late Projects will be accepted after Thursday 5/8
The last Coffee Hour will be held this Thursday at 5/8
Prof. King & TAs will hold office hours through 5/22

OUTLINE
MOSFET scaling (reprise)
SOI technology
MOS memory devices

Spring 2003 EE130 Lecture 29, Slide 1

Moores Law
# transistors/chip doubles every 1.5 to 2 years
1,000,000,000
Heading toward 1 billion transistors in 2007
100,000,000

Pentium 4 Processor
10,000,000
Pentium III Processor
Pentium II Processor
Pentium Processor 1,000,000
486 DX Processor
386 Processor 100,000
286
8086
10,000
8080
8008
4004 1,000
1970 1980 1990 2000 2010
Spring 2003 EE130 Lecture 29, Slide 2

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 Intrinsic Gate Delay (CgateVDD / IDsat)

0.85V
VDD=0.75V

Spring 2003 EE130 Lecture 29, Slide 3

Silicon on Insulator (SOI) Technology

TSOI

Transistors are fabricated in a thin single-crystal Si

layer on top of an electrically insulating layer of SiO2
9 Simpler device isolation savings in circuit layout area
9 Low junction capacitances faster circuit operation
9 Better soft-error immunity
9 No body effect
8 Higher cost
Spring 2003 EE130 Lecture 29, Slide 4

2
 Partially Depleted SOI (PD-SOI)
2 s ( 2 B )
TSOI > Wdm , where Wdm =
qN body
Floating body effect (history dependent):
1. When a PD-SOI NMOSFET is in the ON state, at
moderate-to-high VDS, holes are generated via impact
ionization near the drain
2. Holes are swept into the neutral body, collecting at the
source junction
3. The body-source pn junction is forward biased
4. VT is lowered IDsat increases
kink in output ID vs. VDS curve

Spring 2003 EE130 Lecture 29, Slide 5

Fully Depleted SOI (FD-SOI)

2 s ( 2 B )
TSOI < Wdm , where Wdm =
qN body

No floating body effect!

VT is sensitive to SOI film thickness
Poorer control of short-channel effects due to fringing
electric field from drain
Gate
Elevated S/D contact structure Source SOI Drain
needed to reduce RS, RD
SiO2

Silicon Substrate
Spring 2003 EE130 Lecture 29, Slide 6

3
 Semiconductor Memory
Volatile
Static random access memory (SRAM)
Dynamic random access memory (DRAM)

Non-Volatile
Mask programmed ROM
Programmable Read-Only Memory (PROM)
Electrically programmable ROM (EPROM)
Electrically erasable PROM (E2PROM)
Flash EPROM

Spring 2003 EE130 Lecture 29, Slide 7

6-Transistor CMOS SRAM Cell

~1 ns read time
<10 ns write time
WL

V DD
M2 M4
Q
M5 Q M6

M1 M3

BL BL

Spring 2003 EE130 Lecture 29, Slide 8

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 6T-SRAM: Layout
Modern processes can
VDD
fit a 6T SRAM cell in
~1.0m2 M2 M4

Q Q
M1 M3

GND
M5 M6 WL

BL BL

Spring 2003 EE130 Lecture 29, Slide 9

SRAM Scaling Challenges

Low standby power
low OFF current (e.g. 1 pA/cell)
large VT is required

Soft error immunity

Spring 2003 EE130 Lecture 29, Slide 10

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 1-Transistor DRAM Cell
~10 ns read time
BL ~100 ns write time
WL Write "1" Read "1"
WL

M1 CS X GND VDD VT

VDD
BL
VDD/2 VDD /2
CBL sensing

Write: CS is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL V PRE = ( V BIT V PRE ) ------------------------
C S + CBL

Voltage swing is small; typically around 250 mV.

Spring 2003 EE130 Lecture 29, Slide 11

DRAM Cell Structure

Desired characteristics:
9 low power consumption Capacitor
9 long retention time
9 fast access time
9 soft error immunity

25fF/cell is required for Transistor

sensing signal margin and Gate
retention time Drain Source

Body

Spring 2003 EE130 Lecture 29, Slide 12

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 Advanced DRAM Capacitor Structures
Trench Capacitor Stacked Capacitor
Word line
Cell plate Capacitor dielectric layer
Insulating Layer

Cell Plate Si

Capacitor Insulator Transfer gate Isolation

Refilling Poly Storage electrode

Storage Node Poly

Si Substrate
2nd Field Oxide

Spring 2003 EE130 Lecture 29, Slide 13

DRAM Scaling Challenge

Long retention time low OFF current (~1 fA)
large VT is required
Fast access time high ON current (~100 A)
large (VGS-VT) is required Capacitor

=> VDD cannot be 4

Possible charge
scaled down leakage paths
aggressively, shown here:
for low power
consumption Gate
(WL)

STI
1
Spring 2003 EE130 Lecture 29, Slide 14
3
2

7
 Flash EPROM Cell Structure
Control Gate
Inter-poly Oxide To program this device,
electrons are injected from
the channel inversion layer
Floating gate into the floating gate through
the tunnel oxide.
Tunnel Oxide
N+ Source N+ Drain The inter-poly oxide is thick,
to prevent electrons from
Substrate tunneling through it.
Tunnel oxide: 8 nm thermal oxide
Floating gate: 100 nm N+ poly-Si
Inter-poly oxide: 16 nm CVD oxide or
Oxide/Nitride/Oxide stack

Spring 2003 EE130 Lecture 29, Slide 15

Program by Hot Electron Injection

+10V

0V FG +5V 3.15eV
Source Drain
A Floating
channel Tunnel gate
Substrate oxide

Electrons are accelerated by the lateral E-field and gain

enough kinetic energy at point A (near the drain) to
surmount the potential barrier.
Because of the control-gate bias, electrons are injected
into the floating gate.
Spring 2003 EE130 Lecture 29, Slide 16

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Program by Fowler-Nordheim Tunneling

+18V
3.15eV

0V FG 0V

Source Drain channel

A Tunnel Floating
oxide gate
Substrate

For a sufficiently high control-gate bias, electrons can

tunnel from the channel inversion layer into the floating gate.

Spring 2003 EE130 Lecture 29, Slide 17

Erase Operation
-18V

0V 0V 3.15eV

Source Drain

channel Tunnel Floating

oxide gate
Substrate

Under a large negative control-gate bias, electrons tunnel

out of the floating gate into the substrate.
Spring 2003 EE130 Lecture 29, Slide 18

9
 Sensing the Stored Data
(1) Programmed state
Two VT states: VT= VT2=5V, IDS=0
VR=3V
IDS 0V VDS=2V
Erased Programmed Source Drain
50uA Substrate

(2) Erased state

VT= VT1=1V, IDS=50 uA
0A VCG
VT1 VR VT2 VR=3V

0V VDS=2V
Source Drain
Spring 2003 EE130 Lecture 29, Slide 19
Substrate

NOR Flash Memory Architecture

Each memory cell
can be addressed
individually by its
word line (gate) and
bit line (drain)

Spring 2003 EE130 Lecture 29, Slide 20

10
 NAND Flash Memory Architecture

For each bit line, 16 or

32 cells are connected,
with one select transistor
at each end of the bit line.

Programmed VT > 0 V
Erased VT < 0 V
The source/drain region
between each two
adjacent cells are shared
high density

Spring 2003 EE130 Lecture 29, Slide 21

NOR vs. NAND Architecture

NOR NAND
Chip Density Medium (64MB) Very high (2GB)

Programming Hot electron injection F-N tunneling

mechanism
Programming speed 1us ~10us 1ms

Erasing speed ms byte/block erase ms block erase

Random access Yes No

Application Code storage Data storage

Vendor Intel, AMD SanDisk, Toshiba,
Samsung
Spring 2003 EE130 Lecture 29, Slide 22

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 Flash E2PROM Scaling Challenges
hTo achieve fast programming
speed and low voltage
operation, the tunnel oxide
thickness must be scaled
down.
hDefects in the tunnel oxide
reduce the retention time and
thereby limit the tunnel oxide
Source Drain scaling, however.
h Today >8nm tunnel oxide is
Substrate used in commercial flash
products.

Spring 2003 EE130 Lecture 29, Slide 23

Semiconductor Memory Trends

Capacity increases 4X every 3-4 years

Today:
1 Gb DRAM
512 MB SRAM
(2MB on-chip cache SRAM)
1 Gb flash E2PROM

Spring 2003 EE130 Lecture 29, Slide 24

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