A Dual-Functional Medium Voltage Level DVR to Limit Downstream Fault Currents
Yun Wei Li, D. Mahinda Vilathgamuwa, Poh Chiang Loh and Frede Blaabjerg*
Centre for Advanced Power Electronics
School of Electrical and Electronic Engineering
Nanyang Technological University, Singapore
Email: YW1_ pmai1ntu.edsg,
Abstract - Dynamic Voltage Restorer (DVR) is a modern
custom power device used in power distribution networks to
protect consumers from sudden sags (and swells) in grid
voltage. Implemented at medium voltage level, the DVR can be
used to protect a group of medium voltage or low voltage
consumers. With the implementation at medium voltage level
the DVR would also suffer from faults those involving
downstream loads. Large fault currents would flow through
the DVR during a downstream fault before the opening of a
circuit breaker. Large fault currents will cause the voltage at
Point of Common Coupling (PCC) to drop, which would affect
the loads on the other parallel feeders connected to PCC.
Furthermore, if not controlled properly, the DVR might also
contribute to this PCC voltage sag in the process of
compensating the missing voltage thus further worsening the
fault situation. To limit the flow of large line currents, and
therefore restore the PCC voltage as well as protect the DVR
system components, a downstream fault limiting function is
proposed and integrated in the DVR operation. A flux-charge-
model feedback algorithm is implemented so that the DVR
would act as a large virtual inductance in series with the
distribution feeder in fault situations. Controlling the DVR as a
virtual inductor would also ensure zero real power absorption
during the DVR compensation and thus minimize the stress in
the DC link. Finally the proposed fault current limiting
algorithm has been tested experimentally on a medium voltage
level DVR system with symmetrical and unsymmetrical
downstream fault conditions with the results verifying the
effectiveness of the proposed strategy for limiting the
downstream fault conditions.
The dynamic voltage restorer (DVR) is a series custom
power device used in protecting sensitive loads from
adverse effects of voltage disturbances at the Point of
Common Coupling (PCC). A typical DVR connected
system circuit at medium voltage (MV) distribution network
is shown in Fig. 1. The DVR essentially consists of a series
connected injection transformer, a Voltage Source Inverter
(VSI), inverter output filter and an energy storage device
connected to the DC link. The high voltage (HV) power
system upstream to the DVR is represented by an equivalent
voltage source which is transformed to MV level by a step-
down transformer. The basic operation principle of the DVR
is to inject an appropriate voltage in series with the supply
through injection transformer when a PCC voltage sag is
detected. MV loads or low voltage (LV) loads connected
downstream after another step-down transformer are thus
protected from the PCC voltage sag.
*Institute of Energy Technology
Aalborg University
DK-9220 Aalborg East, Denmark
Email: fb1gietaaudl
PCC DVR Load bus
SrD
Supply impedance VpCC ILoad
/ Filter
..|.T.| circuit.
L
Energy -T-
Storage
Series vsI
Fig 1 TypicalDVRcircuittopology
Operating a DVR at medium voltage level would protect
high power applications or a group of medium voltage or
low voltage consumers, reduce the effective impedance
inserted by a DVR, eliminate the control consideration of
,
zero-sequence voltage due to the three-wire medium voltage
distribution system (in most countries) and achieve more
cost efficient operation per MVA[1]. Indeed, implemented
at MV level, the DVR requires semiconductor devices,
energy storage devices and injection transformers with
ener rag. di a.n injecti transfR with
lrger rauti in a th issuectsite. D Vr to uor
frequent faults in the downstream load side. Large fault
currents will flow through the DVR during a downstream
fault before the opening of a circuit breaker. This large fault
current will also cause PCC voltage drop, which would
affect the MV or LV loads on the other feeders connected to
PCC. Furthermore, if not controlled properly, DVR might
try to compensate this PCC voltage sag by generating the
missing voltage and therefore further worsening the fault
situation.
During downstream faults, passive control methods are
often used to protect the DVR by enabling a bypass circuit
(usually a slow mechanical bypass together with a fast solid-
state switch) [1-3], while allowing a large fault current to
flow which could cause PCC voltage to drop. Active control
of series connected devices during a fault by limiting the
fault current is reported in [4-6]. Compared to the passive
protection of DVR, active control of DVR during a
downstream fault makes the additional protection circuits
unnecessary and the implementation easy.
In this paper, a downstream fault limiting function is
proposed and integrated in DVR operation to limit the flow
of large fault currents, and therefore to restore the PCC
voltage and protect the DVR system components. Flux-
charge-model feedback algorithm is implemented for
 MV Z2 MV
Zi =VS Zi
* Load
Z3
0 V DVR -o-Load DVR
Fig. 2. DVR connected system with PCC voltage sag.

Fig. 3. DVR connected system with downstream fault.

controlling the DVR to act asthea DVRlarge virtual inductance in
.Controlling .as a
series with the distribution feeder. ControllingtheDVR
An often used option for DVR operation during a
virtual inductor would also ensure zero real power downstream fault is to passively protect the DVR by
enabling the bypass circuit (usually a slow mechanical
absorption during downstream fault compensation and thus bypass together with a fast solid-state switch) [1-3].
guaranteeing a constant DC ... link voltage. Finally, the
proposed fault current limiting algorithm . '
has been tested ~~~~~However large fault current flow would sustain and PCC
voltage would drop. A more promising approach is thus to
experimentally on a 10 kV medium voltage DVR system. control the DVR actively to reduce the large fault current
II. NORMAL OPERATION OF DVR AT MEDIUM and restore the PCC voltage. Note that the fault current
VOLTAGE LEVEL limiting function requires a relatively large DVR, say one
with 100% sag compensation capacity, since almost all the
Voltage sags are commonly accepted as the most voltage drop would appear across the DVR when a
common and costly power quality problem, which is mainly downstream short circuit fault occurs.
caused by the faults in the grid. The fault clearance time of
various protection devices determines the sag duration. The A. Downstream fault in a DVR connected system
sag origins can be upstream transmission system faults
(location 1 in Fig. 2) or distribution system faults at the Fig. 3 shows a downstream fault occurring in the DVR
paralelfeeer
parallel feeder onncte toPCC(loatin
connected ig.2).connected system. lwvlag
2 in Fig.
to PCC (location 2in 2).lelorath The fault can be at the medium voltage
lvlafrasepd n
The normal operation principle of the DVR is to level or at the low voltage level after a step-down
compensate theraPCCnvoltagple
compnsat thePCC oltge sags sgs byb
he

Di
injcting an
an
transformer. Using the voltage divider concept, the fault
current and PCC voltage in this fault situation can
can be
appropriate voltage in series and in synchronism with the curred PC voltage intis u iation be
incoming PCC voltage, so that the load voltage (the sum of calculated as (without consideraton of other fed
PCC voltage and insertion voltage) can be restored to its ca
desired level. For proper operation of the DVR, the voltage 'fault = VS (1)
at PCC is sensed. Once a PCC voltage sag is detected +3
(decrease of Vpcc is sensed), the DVR is controlled with a VCC Z3 V (2)
reference voltage of Vre= Vpcc ref -Vpcc, where Vpcc ref is (5 +
usually obtained by a PLL locked to the pre-sag PCC where Z1 is the source impedance and Z3 is the
voltage. The magnitude and phase of load voltage VLoad is downstream feeder impedance including the fault
therefore unchanged and this compensation is known as pre- impedance. Due to the very low line impedance, the fault
sag compensation (or voltage quality optimized current would be significant as it can be seen from (1). This
compensation). Some other compensation techniques such large fault current is harmful to the series connected
as in-phase compensation (or voltage amplitude optimized equipment and system components. As illustrated in (2), the
compensation) and energy optimized compensation are also PCC voltage will drop and the remaining voltage can be
proposed for the DVR and are not further discussed here [1, very low with a small Z3 (a nearby fault). The sag in PCC
7, 8]. voltage will affect the loads on the other parallel feeders
connected to PCC too.
III. USING DVR FOR DOWNSTREAM FAULT
CURRENT LIMITATION B. Using DVR to limit fault current
Despite the advantages of implementing at medium As discussed, the bypass circuit would only protect the
voltage level, the DVR is subjected to increased downstream DVR during a downstream fault but the large fault current
faults as it covers large number of loads. The downstream flow and PCC voltage sag would sustain. A more promising
faults could cause large fault current flow, which might approach is to control the DVR actively and reduce the large
damage the series connected equipment (such as DVR) and fault current and restore the PCC voltage.
system components. The large fault current will also cause To reduce the fault current flow due to a downstream
voltage at PCC to drop and affect most other loads on the fault, the DVR can be controlled to inject a suitable series
parallel feeders connected to PCC. The DVR might further voltage, which makes the DVR to act like an additional
complicate the fault situation in the process of compensating virtual line impedance in series with the distribution feeder.
the PCC voltage sag which could result in even large fault A phasor diagram of the DVR limiting the fault current by
current, if not controlled properly.
 -* across LO. This load bus voltage drop will help to detect the
VI:n fault and trip loads at downstream side with minimized
Vine interference of the protection system, although over-current
tripping is not possible in this case unless additional
communication between the DVR and the downstream side
.... over-current circuit breaker is available. If it is necessary to
VS operate the over-current circuit breaker at PCC, a
Fig. 4. Phasor diagram of DVR injected voltages during downstream fault. communication between the DVR and the PCC breaker
might have to be made and this can be easily done by
series voltage injection is illustrated in Fig. 4, where VLne is sending a signal to the breaker when the DVR is in fault
the voltage drop across total feeder impedance (including current limiting mode since the DVR is just located after
the source impedance, downstream feeder impedance and PCC [5].
fault impedance, denoted as Z1+Z3), and V_S -- v7VInl +VLine
( is the C. Detection and recovery from a downstreamfault
source voltage. Given a fault current magnitude limited to a For fast downstream fault detection and therefore fast
fixed level, the voltage drop across Z1+Z3 will be on the DVR reaction to the fault current, instantaneous current
dashed circle shown in Fig. 4. Comparing these voltage magnitude is calculated in stationary u-P reference frame.
phasors, it is obvious that the injected voltage phasor of the Once the current magnitude exceeds a preset threshold IT,
series inverter is minimized by orientating v to be in the DVR would inject a series voltage so that it would act as
phase with (l * This implies that for minimal voltage a virtual inductor to limit the fault current and to restore the
injection,~ ~seisivre.oldatlk
injection, the
impedance whose
Z0 ~
th series inverter would act like a virtual
RIX
ita
ratio proportional to that of the
is
PCC voltage.
Recovery from a downstream ffault can be done by
Recove fom a downstreamcde by
betalfoundein Z*Z3
tota fede imeac sensing
A mor deaie anlyi can the load voltage V/oad (voltage at downstream side of
[6]..
pedance analysis can
A more detailed
the DVR injection transformer) as in Fig. 3. When the fault
Note that t e i m n t r is cleared, the load voltage will increase. Once Vload is
restored to a preset level VT the fault current limitingg
impedance will cause the DVR to absorb real power during ftfunction of DVR can be terminated.
DVR compensation is not tured Furthermore,
the faultthecompensation.
aulcopenatio. The
Te ral owerabsrpton
real power absorptionvolt ill to ensure
off by any spurious
tohrise.tWithClargeafaultfore
to be damagi currentnflow,sthehcapacitorkcharging
aubetterwche will thenb transient distortion or measurement noises, a low pass filter
like characteristic is added to this recovery detection. This is
control te dVRmtoiactlikeraepre virtualinducto TL with
c
c
done by turning off the DVR when V/oad> VT iS sustained for
no real power involved during the compensation. At the a specific
p pperiod of time and no other downstream fault is
medium voltage level, the feeder impedance (including the detected durng ths perod (n ths paper 20 ms iS used for
line/cable impedance and transfoer leakage impedance) is symmetrcal faults, and 50 ms iS used for unsymmetrical
mainly inductive. This means the DVR would limit the fault magntude due to the unbalanced effects.)
current with minimal voltage vVIn , which is almost in phase
with . IV. FLUX-CHARGE-MODEL CONTROL
For a nearby fault, where Xo0= jLo> > Z1 +Z3, magnitudes ALGORITHM FOR DVR
of vo and K'I,j would be similar and are much larger than This section presents the algorithm for controlling the
VInj tDVR during a downstream fault. The DVR control scheme
that of VLn (see Fig. 4). The DVR, acting as an inductance, is illustrated in Fig. 5, where a fault detection unit is first
would therefore compensate the fault current by generating implemented by measuring the line current (for over-current
nearly 1 per-unit voltage in quadrature with the fault current detection) and load voltage (fault recovery detection) as
with no real power absorption. By representing the DVR as discussed in Section III. The fault detection unit functions to
an inductance in series, the fault current and PCC voltage bring the DVR into active mode when an over-current is
can be re-calculated as: sensed and turn the DVR into passive mode after detection
I- VS (3) of a fault recovery. Upon the occurrence of a downstream
fa- fault, the distribution feeder to limit the fault current and
the DVR is controlled as a virtual inductor in series
~~~~~with
+V +
1 9 o
V'+x, vs
~~~~~~by
(4)
restore the PCC voltage. The DVR is turned to passive mode
forcing all the PWM signals to be zero after a
It is obvious that the fault current is reduced and the PCC dwsra al eoeyi eetd
voltge cn berestred wit X03Z1 by ddin an One way of controlling a series inverter as a virtual
additional LO in series with the line. Another effect is the inutrstosehefx-dlcnrlcneprpredn
load voltage will further be reduced due to the voltage drop [,1] npsig ti omne httepeitv lx
 VLoad(abc)
am=
'Line(abFau)t
abc Faultbc)ref
L0 +
aIDetection - Regulator
VD VRDV(b)
(a ab b|
1s
'L(abc 1
0-'S
Fig. 5. Proposed DVR control scheme for fault current limiting.
Charge Regulator
!dre k____ Qre
|Flux Regu
Fig. 6. Flux-charge model based control for DVR implementation.
model control presented in [9, 10] is highly sensitive to
system parameter variations, which is a common feature for
most predictive schemes. An alternative robust flux-charge-
model control, with an outer flux-model and an inner
charge-model loop [6], is therefore adopted in this paper for
controlling the DVR.
A. FluxC-Charge based COntrOl
The flux-charge model control scheme for the DVR is
illustrated in Figs.5 and 6. The control variable used for the
outer flux-model is the inverter filtered terminal flux,
defined as cP=IVDVRdt where VDVR is the filter capacitor
voltage of the DVR (at DVR power converter side of the
injection transformer). In stationary oc- frame, the flux
variable is compared against a reference flux given by
Pref-LOILine where 'Line is the line current (at DVR power
converter side ofthe injection transformer) and the negative
sign is to indicate that 'Line is drawn flowing out of the series
inverter (see Fig. 8). The flux error is then fed to the flux
regulator, implemented using the Presonant compensator,
which is actually a stationary frame equivalent form of the
synchronous frame PI controller [11]. A practical form of
the Presonant controller implementation is shown in (5):
(- k+
GFU rhl(S) +2k1wCUtS+a2
2w2C,,s
where, kp is the proportional, k1 is the integral term for
fundamental frequency (w0 2 *w*ferad/s, fr5OHz) and 0t)Ut
is the cutoff bandwidth for adjusting the controller
performance for frequency variations[11]. With alarge gain
at the positive and negative fundamental frequency (50 Hz)
by selecting a large k1, the Presonant controller therefore
has the ability to regulate the positive- and negative-
sequence fundamental components with very good steady-
state performance.
In [6] it is shown through classical control analysis that a
single flux-model would not dampen out the resonant peak
of the LC filter connected to the output of inverter. To
Q e
Flux aI + Charge
l'etrac
Jnrt(b)
ac - Regulator To PWM
Generator
..DVR Plant
K jt Ln
_ / . V:
Regulator
stabilize the system, an inner charge-model is therefore
added to force the filter inductor charge, defined as Q=IILdt
(where IL is the current through the DVR filter inductor) to
track the reference charge Qrej (output of the flux regulator).
The calculated charge error is then fed to the charge
regulator in a-b-c frame with transfer function shown in (6):
'C(harge(S) = Ch l+(s/ N)?(6
which is actually a practical form of the derivative
compensator, where the added pole is used for limiting the
regulator gain to N at high frequencies to prevent noise
amplification. To further avoid the possible filter inductor
current measurement noise amplification by the
differentiation, the derivative term, s/(1s/N), of charge
loop compensator is moved to the front of charge loop (after
the flux regulator) as shown in Fig. 6, by acting only on the
control signal (flux regulator output). The integral term
added on the filter inductor current can then be removed
correspondingly. As a result, the charge loop would become
more robust to measurement noise and more computational
efficient (with three integrations of filter inductor currents
removed).
Intuitively, the derivative term in s/(1+sN) neutralizes
(5) the
of effects of voltage and current
the flux-charge-model, integrations
resulting in theat the inputs
proposed
algorithm having the same regulation performance as the
multi-loop voltage-current feedback control, with the only
difference being the presence of an additional low pass filter
in the flux control loop in the form of 1/(1s/N). The
bandwidth of this low pass filter is tuned (through varying
N) with consideration of measurement noise attenuation,
DVR LC-filter transient resonance attenuation and system
stability margins as well as system bandwidth.
Although sharing common control principles, the flux-
charge control does have an implementation advantage over
voltage-current control. The additional integration in flux-
charge control would allow its outer loop flux reference to
be easily computed by multiplying Lo and 'Line without
ate~
C 270

1B:0!XS|QT5
iW0thth -des---i---
50

-100

curnt co-rnt-ro) Th reutn flu

a5s a4s a1-a0
kche l
I3sa2s
1-1 10o
> 2>221144X>
7 zaBode
Fig

10

differentiation (differentiation of ILi,, is needed for voltage-

cu 2entcontrol). The resulting flux reference is therefore
more accurately calculated (without phase delay and noise
amplofication assocnatedwsth differentiation), and the flux-
charge controlled DVR would emulate virtual inductance Lo
more

B.
a

a5 = N ; 4 =

a3 x

a2=
1
closely.
Open-loop transferfunction
With the designed control scheme, flux and charge
regulators are as shown in Fig 6, and the open-loop transfer
function for flux control can be derivass en

~ ( 2L~ + 2c, ~ero.As8hw.nFg

outpt ota
CO2( +C)2
N
0),,,S +kkP
kpkCh s2 + 2(kp + kI )kCh CalraI
programa5b 4 5 k 2V 3
C (f kh+2c,j )+ L7)
N
f
u
~Fg ~ ~~~~~~~~~~~~~
R s
+f
F

f
8d (7)u

Ch 2

Lf;
httefnlfu
+
in

400 +VCf (Rf+skCh +2ctrmf

u 0C(f +2CuR +2CCh)+';

a, coo9 tN + Cf Rf + Cf kChiZ + 2oc,,t; ao) = 0)

)
oto
'J
102
FreCLety (Hz
,~ ~ ~ ~ ~ ~ ~ ~. . . . . . .
Bode Diagram

nro-l scee---f--rge

)
10
, ,,,,, ,,, , ,,,,, ,,, , , ,#&,, ,,, ...

> .........
open24 loopYflux
plot>1Hof_X

1Q0
model

referec

i
~ ~
Frequency(Hz)

is-threforer
-
X X

~
>2X

medium voltage prototype DVR is connected at the 10 kV

~
DC-bus

using two DC supplies, which provide a maximum of 4680 J

energy in the 26 mF of DCcapacitin for

Devices
Notemeta
2coc k )1implementationalhuh tha of controlkhVabrtr
soC167 Microcontroller for
algorithm DVR
PWM
and asystem
Siemens SAB
signal generation
six IGBT phase-legs. A Dual Port RAM unit (DPRAM) is
used as a communication link between the DSP and
Microcontroller, whereby the results from the DSP are
for

transferred to DPRAM and are read by the Microcontroller.

Co

The open-loop Bode plot o f flux transfer fiunction is Analog signals are converted to digital form with two eight
drawn in Fig. 7 with kp=0.4, 2k, =150, 9o)=314 rad/s and channel AD 7891 A/D converters from Analog Devices and
N=1000 (see Table I for other system parameters). The read by the DSP once in each switching cycle. Three
0.4 kV/ 10 kV

>AC 4 2

yZ
o

loscopes
DV) gn

transient use in
the DVR sag ride-through capabilities during PCC voltage
sag compensation.
Control of the DVR is realized using a dual DSP-
Microcontroller system, with a 32-bit 33 MHz Analog
AD2 1026 floating-point Sharc DSP for
isup
the
. .V
:::

2sAD7891
drawn in Fig. 7 wih
0.29 kV/ 29 kV

Control of the DVR is realizedhusingca dual DSP-

s~~~~~~~~~~~~mdu
Fig. 7. Bode plot of open-loop flux model. CualSharx |
2s
IGs
8
volta1ge
ual
system,
..
80Ca1i67
M icrocontroller
(PWM Generation)
d anr S
:prototyp DVR is conce at th 10 kV
mmunicato ln b
cPort

Ml
o
w
l
P nost

l a AeDconvertero
CC.............

Lf
fo t

to capture v
e
th linerrenta aRreored

level through three single-phase injection transformers. The

DC-bus voltage for the DVR can be charged up to 600V
rt

e (
,

D
:

c b

(Control Algorithms)
10 kV 0.4 kV

::........

|||>
IL Lgf
u

..

Oscilsc, lope
thDS
i
to 600

j
3a

open-loop response shows a significant gain at the oscilloscopes are used to capture voltages (PCC, load and
fundamental frequency, which ensures nearly zero steady- DVR), and the neshcuwient data are recorded in the DSP.
state error. Also shown in Fig. 7 is that the final flux control Note that although the laboratory DVR system is
loop exhibits a band-pass filter like characteristic, with good designed and operated at 10 kV voltage level for normal
attenuation of the low frequency measurement DC offset, operation, the limited rating of the AC supply (15 kVA)
high frequency switching noises and filter LC resonance. used does not allow the system to operate at nominal power
Phase and gain margins of 59.8 deg and 11.9 dB are rating. The fault condition testing at 10 kV is therefore
obtained respectively to ensure good stability of the overall impossible with the AC supply, and the experiment has to be
control scheme. run at 3 kV.
 - -- - -- 2

ID' ' XD o'

-2 - ----3--- ----I3II
120 140 160 180 200 220 240 260 280 300 320 120 140 160 180 200 220 240 260 280 300 320
Time (ms) Time (ms)
Fig. 9. Load voltages during three-phase short circuit. Fig. 12. PCC voltages during three-phase short circuit.

,>' 1 ''ln~~~~~~~~~~~~~~~~~2 140:H

160 18020 220 240 260 280 300 320
-2 - - ----/

-1 - 21 -

120 140 160 180 200 220 240 260 280 300 320
Time (me) Time (me)
Fig. 10. DVR injected voltages during three-phase short circuit. Fig. 13. Real and reactive power injected by DVR during three-phase short
~~~~~~~~~~circuit.
40 rTl -

30 -______I______J__f\__l_______l______l______>______J_______l______l______ 3.5 cycles. The load voltages

shown
areinFig.14.The
andflwefetvlysetoe)C
-10
2 --
-~ curreTim
woud limit thefault
DVR injected voltages controlled short circuit line
10 0 currents are depicted in Figs. 15 and 16 respectively, where
30 ------- - --T -- ----
-- -1 --I-- - -- L--r- -- -- -T- -- -- -s- -- -- -n- -- -- --r-L--
-- -r--- -----
-

@0 |r it can be seen that by acting as a virtual inductance the DVR

Fig.
10.DV injeced volages dringtree-phseshotcircit. Fvoltages are shown in Fig. 17. Finally, the DVR injected real
-20- 3and reactive p owercomponents are shown in Fig. 1. Note
-30 -___|______I___l___l______|___l______ that longer recovery time from a downstream fault (around
1 00 1601i 0 200Time22(m-)24 2i
26 3i
3 320 50 ins) is used during the unsymmetrical fault to eliminate
the effects of oscillatory load voltage magnitude due to the
Fig. 11. Line currents (DVR side) during three-phase short circuit. unbalanced effects.

during the fault. The DVR reacts to the fault (after detection VI. CONCLUSION
of an over current) by injecting voltages lagging the fault In this paper, a downstream fault current limiting
current by 900 as shown in Fig. 10. The controlled fault function is proposed and integrated in DVR operation to
currents are shown in Fig. 11, where the DC component of limit the flow of large fault line currents, and therefore
the short circuit current decays in several cycles during the restore the PCC voltage and protect the DVR system
fault due to the large system X/R ratio. Fig. 12 shows the components in downstream fault conditions. A flux-charge-
PCC voltages, which are effectively restored by limiting the model feedback algorithm is implemented for controlling
short circuit current flow. The effectiveness of flux-charge the DVR so that it would act as a large virtual inductance in
model based control is further validated by the nearly zero series with the distribution feeder. Controlling the DVR as a
real power injectionvby the DVR during fault as canabe seen virtual inductance would also ensure zero real power
in Fig. 13. Note that the negative reactive power is due to absorption during DVR compensation and thus minimizing
the identical terminal locations at each side of the injection the stress on DC-link energy storage device. Finally, the
transformer in Fig.8. proposed fault current limiting algorithm has beenested
experimentally on a medium voltage level (10 kV)
B. Single-phase short circuit laboratory DVR system under both symmetrical and
An unsymmetrical downstream fault condition is also unsymmetrical fault conditions. Those experimental results
tested in the experiment. A single-phase short circuit is verify the effectiveness ofthe proposed strategy for limiting
created across the load from t = 160 ms and lasts for about the down stream fault conditions.
[1]

[3]

[4]

[5]

[6]

[7]
2

-2

120

-2-1-

20

10

-10
140

@1~~

(exclude
-

160

X
| . l
<
-10
..
180

. . L ~~~~-
'-

200 220 240

Time (ms)

-1205 140 160 130 200 220 240 260 230 300 32 0
30~~~~~~~~~~~~~~~~~~~
Time (ins)

-20-------- ---'---^------n----------r--

120 140 160 180 200 220 240 260 280 300 320

ISBN: 87-89179-42-0.
Time (ms)
. ~ ~Power
260

Fig. 14. Load voltages during single-phase short circuit.

-----

Fig. 15. DVR injected voltages during single-phase short circuit.

- ------

: t ,/ 0 >,
rh -

9
280

Fig. 16. Line currents (DVR side) during single-phase short circuit.

REFERENCES
----

J. G. Nielsen, "Design and control of a dynamic voltage restorer", Ph.

D thesis, Aalborg University, Institute of Energy Technology, 2002.
N. H. Woodley, L. Morgan, and A. Sundaram, "Experience with an

inverter-based dynamic voltage restorer", IEEE Trans. Power

Delivery, vol. 14, pp. 1181-1186, July. 1999.
N. H. Woodley, A. Sundaram, T. Holden, and T. C. Einarson, "Field
experience with the new platform-mounted DVR", in Proc. IEEE-
PowerCon '00, 2000, pp. 1323-1328.
W. C Lee, T. K. Lee, C. S. Ma, and D. S. Hyun, "A fault protection
scheme for series active compensators", IEEE Trans. Power
Delivery., vol. 19, pp. 1434-1441, Jul. 2004.
5. 5. Choi, T. X. Wang, and D. M. Vilathgamuwa, "A series
compensator with fault current limiting function", IEEE Trans.
Power Delivery., vol. 20, pp. 2248-2256, Jul. 2005.
D. M. Vilathgamuwa, P. C. Loh, and Y. W. Li, "Protection of Micro-
Grids during Utility Voltage Sags", IEEE Trans. Ind. Electron., in
press.
5. 5. Choi, B. H. Li, and D. M. Vilathgamuwa, "Dynamic voltage
restoration with minimum energy injection", IEEE Trans. Power
System, vol. 15, pp. 51-57, Feb. 2000.
300

------I
320

..
.

M
. .

[8]
D

injection
-2
2

120

1-20

1 20
140

140

140

~~~~~~~~~~~transformer)
ransf2orme

(11 )
Step-up
Transformer
(1 25)

Step-down
Transformer
(25:1)
160

160

160
180

180

130 200
200 220 240

1
Time (ms)
Fig. 17. PCC voltages during single-phase short circuit.

200 220

Inete ilteri ianpducgtancqe

Inverter filter resistance
Inverter filter capacitance
DC link capacitance

Primary voltage
Secondary voltage (DVR side)
Leakage impedance
Power
Primary voltage 0P4EkV
Secondary voltage
Leakage impedance
Power
Primary voltage
Secondary voltage

Leakage impedance
240

220 240
Time (ins)

0.03 pu
J. G. Nielsen, and F. Blaabjerg, "Control strategies for dynamic
260

260

260

Fig. 18. Real and reactive power injected by DVR during single-phase short

~~~~~~~~~~~~TABLE I.

~~~~~~
t ~~~~~~~~
---.
circuit.
SYSTEM PARAMETERS.

Grid Nominal grid line-line voltage

~~~~~~~~~~~Frequency
~~arameter
lt~~~~~~~ ~ ~ ~ Vailue
380 V

voltage restorer compensating voltage sags with phase jump", in

Proc. IFEE-APEC'01, 2001, pp. 1267-1273.
[9] H. Funato, T. Ishikawa, and K. Kamiyama, "Transient response of
three phase variable inductance realized by variable active-passive
reactance (VAPAR)", inProc. IFEE-APEC'01, 2001, pp. 1281-1286.
[10] H. Funato, K. Kamiyama, and A. Kawamura, "Transient performance
of power circuit including virtual inductance realized by fully
digital controlled variable active-passive reactance (VAPAR)", in
Proc. IEEE-PESC'00, 2000, pp. 1195-1200.
[11] D. N. Zmood, D. G. Holmes, and G. H. Bode, "Frequency-domain
280

280

analysis of three-phase linear current regulators", IEEE Trans. Ind.

Applicat., vol. 37, pp. 601-610, Mar/Apr. 2001.
[12] J. G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, "Control
and testing of a dynamic voltage restorer (DVR) at medium voltage
level," IEEE Trans. Power Electron., vol. 19, pp. 806-813, May
2004.
300

300

230 300

50 Hz
320

320

32 0

2*260 uiH
25 mQ
120 [[F
26 mF

2.9kV
0.29 kV
0.05 pu
50 kVA

10 kV
0.03 pu
50 kVA
10 kV
0.4kV