Professional Documents
Culture Documents
R. Saleh
Dept. of ECE
University of British Columbia
res@ece.ubc.ca
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g
Look at cross-section
s d
nMOS pMOS
n+ n+ p+ p+
p n
n+ to p substrate
substrate must be p substrate must be n
• CMOS devices require two types of substrate for isolation of
transistors
• n-type for pMOS (usually in an N-well)
• p-type for nMOS (usually substrate material)
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EECE481
Fabrication Steps
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Making Chips
20-30 masks
Masks
100-1000 chips
Layout
Chips
Fabrication
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EECE481
Two parts:
1) Transfer an image of the design to the wafer
2) Using that image as a guide, create the desired layer on silicon
– diffusion (add impurities to the silicon)
– oxide (create an insulating layer)
– metal (create a wire layer)
Basic Processing
Spin on a photoresist
UV light
Glass mask
Pattern photoresist with mask
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• Repeat:
– Create a layer on the wafer
– Put a photo-sensitive material (resist) on top of the wafer
– Optically project an image of the pattern you desire on the wafer
– Develop the resist
– Use the resist as a mask to prevent the etch (or other process) from
reaching the layer under the resist, transferring the pattern to the
layer
– Remove the resist
• Key point is that all the chips (die) on the wafer are processed in
parallel, and for some chemical steps, many wafers are processed in
parallel.
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Making Transistors
shallow trench
isolation regions
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Making Transistors
n+ implant p+ implant
4. Implant source
and drain
shallow
trench spacers polycide
isolation salicide
n+ n+ p+ p+
Drain/source extensions
substrate
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Making Wires
Insulating material
1. Deposit insulator
may be polished
to make it flat
contact cuts
contact cuts filled with tungsten
2. Etch contacts to Si
fill with conductor
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Making Wires
3. Deposit first
metal layer and
then pattern to
provide desired
connections Deposited and patterened metal 2
Metal 1 Metal 2
4. Repeat same
steps for all
subsequent layers
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EECE481
M6
via5
Cu
M5
low-k between wires via4
via1 M4
via3
M1 M3
contact via2
(W) M2
silicon
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Fabrication Information
“tapeout”
Layout
Design (mask data) Foundry
House (Fab)
Design Rules
(layout)
Process Parameters
(simulation)
• We don’t care about the real details of the fab, but we have to
define the patterning of the layers (that meet their rules) to
specify our design.
• Sometimes knowing more about the fab details is useful when
you need to debug a part.
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(a) Resolution
3λ min. width rule
min. spacing 3λ
3λ
3λ
3λ
(b) Alignment
min. poly width 2λ poly overlap
of field 2λ
min. contact
size 2λx2λ min. contact
spacing to
poly to gate 2λ
diffusion
spacing 2λ min. contact
overlap λ
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n+ diffusion
D λ x 2λ
2λ λ p-well D
λ x 2λ
2λ λ
λ
5λ
polysilicon λ
6λ
G λ
W=4λ λ
L=2λ
p+ diffusion
G λ
W=2λ λ
L=2λ
λ
2λ λ
Z=2λ contact
λ
5λ λ
6λ
S
S B
n+ diffusion
(this one)
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• First generation
• Hspice Level 1, 2, 3
• “physical” analytical models with geometry in model
equations
• Holding onto hand-calculation...
• Second generation
• Hspice level 13 (Bsim), 28 (“MetaMOS”), 39(Bsim2)
• Shift in emphasis to circuit simulation with lots of
mathematical conditioning
• Quality of outcome is highly dependent on parameter
extraction methodology
• Good luck with hand-calculation
• => BUT served industry well for over 12 years!
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Bsim3 intent was return to simplicity... but... now Bsim3v3 > 100
parameters!
– Vendors have now figured out how to reliably build Bsim3v3
models
– You will be using a Bsim3v3 model (or BSIM4 in the future)
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Linear
Generate IV Characteristics
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VGS
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• May need to bin space of models & stay inside covered space
Wmax
Wmin
Lmin Lmax
Beware of non-physical behavior beyond boundaries! Some model sets
were really just developed with minimum L’s rather than all possible L’s.
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Process Variations
alike 0.6
Prob
Series1
• Parameters of a fabrication 0.4
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Circuit Parameters
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Process Corners
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