8 7 6 5 4 3 2 1

+12V_BUS
PCI-EXPRESS EDGE CONNECTOR
+12V_BUS

C1 +3.3V_BUS

+1
10UF
C928
CD470u16EL11.5 +12V_BUS +12V_BUS +3.3V_BUS

2
No JTAG
+12V_BUS +12V_BUS R2 0R
x16 PCIe
+3.3V
C2 C3 B1 A1 PRESENCE
D
150nF_16V 150nF_16V +12V#B1 PRSNT1#A1 D
B2 +12V#B2 +12V#A2 A2
B3 +12V#B3 +12V#A3 A3
B4 A4 C39
GND#B4 GND#A4 100nF_6.3V
{7} SMBCLK B5 SMCLK JTAG2 A5
B6 A6 JTDI
{7} SMBDATA SMDAT JTAG3
TEST_EN_J B7 A7 JTDO
GND#B7 JTAG4

5
B8 +3.3V#B8 JTAG5 A8
B9 A9 1 NC7SZ08P5X_NL
R1 JTAG1 +3.3V#A9
B10 3.3Vaux +3.3V#A10 A10 4 PERST#_buf {2}
+3.3V 0R B11 A11 PERST# 2
WAKE# PERST# U5
Mechanical Key
B12 A12

3
RSVD#B12 GND#A12
B13 GND#B13 REFCLK+ A13 PCIE_REFCLKP {2}
+1

{2} PETp0_GFXRp0 B14 PETp0 REFCLK- A14 PCIE_REFCLKN {2}

C4 B15 A15
{2} PETn0_GFXRn0 PETn0 GND#A15 PERp0 C7 R_RST
CD470u6.3EL11-RH-1 B16 A16
2

GND#B16 PERp0 PERn0 100nF_6.3V C8 GFXTp0_PERp0 {2} R3 0R

B17 PRSNT2#B17 PERn0 A17 GFXTn0_PERn0 {2}
B18 A18 100nF_6.3V
GND#B18 GND#A18
{2} PETp1_GFXRp1 B19 PETp1 RSVD#A19 A19
{2} PETn1_GFXRn1 B20 PETn1 GND#A20 A20
B21 A21 PERp1 C9 Place R3 in U5
GND#B21 PERp1 PERn1 100nF_6.3V C10 GFXTp1_PERp1 {2}
B22 GND#B22 PERn1 A22 GFXTn1_PERn1 {2}
B23 A23 100nF_6.3V
{2} PETp2_GFXRp2 PETp2 GND#A23
{2} PETn2_GFXRn2 B24 PETn2 GND#A24 A24
B25 A25 PERp2 C11
+3.3V GND#B25 PERp2 PERn2 100nF_6.3V C12 GFXTp2_PERp2 {2}
B26
B27
GND#B26 PERn2 A26
A27 100nF_6.3V GFXTn2_PERn2 {2} Table 1: Connection for JTAG
{2} PETp3_GFXRp3 PETp3 GND#A27
{2} PETn3_GFXRn3 B28 PETn3 GND#A28 A28
B29 A29 PERp3 C13 Production
C5 C6 GND#B29 PERp3 PERn3 100nF_6.3V C14 GFXTp3_PERp3 {2}
B30 RSVD#B30 PERn3 A30 GFXTn3_PERn3 {2} (No JTAG) Install R1 & R2 .Don't Install TSW1
100nF_6.3V 1uF_6.3V B31 A31 100nF_6.3V
PRSNT2#B31 GND#A31
B32 GND#B32 RSVD#A32 A32
{2} PETp4_GFXRp4 B33 PETp4 RSVD#A33 A33
{2} PETn4_GFXRn4 B34 PETn4 GND#A34 A34 Install TSW1 & Don't Install R2
B35 A35 PERp4 C15
GND#B35 PERp4 PERn4 100nF_6.3V C16 GFXTp4_PERp4 {2}
B36 GND#B36 PERn4 A36 GFXTn4_PERn4 {2}
B37 A37 100nF_6.3V JTAG TSW1 Switch #1, 2, 3, 4, 5 and 6 closed (ON)
{2} PETp5_GFXRp5 PETp5 GND#A37
C
{2} PETn5_GFXRn5 B38 PETn5 GND#A38 A38 Internal Use Only #7,8 open C
B39 A39 PERp5 C17
GND#B39 PERp5 PERn5 100nF_6.3V C18 GFXTp5_PERp5 {2}
B40 GND#B40 PERn5 A40 GFXTn5_PERn5 {2}
B41 A41 100nF_6.3V NO JTAG TSW1 Switch #1, 2, 3, 4, 5 and 6 open
{2} PETp6_GFXRp6 PETp6 GND#A41
{2} PETn6_GFXRn6 B42 PETn6 GND#A42 A42 #7,8 closed (ON)
B43 A43 PERp6 C19
GND#B43 PERp6 PERn6 100nF_6.3V C20 GFXTp6_PERp6 {2}
B44 GND#B44 PERn6 A44 GFXTn6_PERn6 {2}
B45 A45 100nF_6.3V TSW1 & R2 are located on the bottom side of the board close to PCIE connector.
{2} PETp7_GFXRp7 PETp7 GND#A45
{2} PETn7_GFXRn7 B46 PETn7 GND#A46 A46
B47 A47 PERp7 C21
GND#B47 PERp7 PERn7 100nF_6.3V C22 GFXTp7_PERp7 {2}
B48 PRSNT2#B48 PERn7 A48 GFXTn7_PERn7 {2}
B49 A49 100nF_6.3V
GND#B49 GND#A49
{2} PETp8_GFXRp8 B50 PETp8 RSVD#A50 A50
{2} PETn8_GFXRn8 B51 PETn8 GND#A51 A51
B52 A52 PERp8 C23
GND#B52 PERp8 PERn8 100nF_6.3V C24 GFXTp8_PERp8 {2}
B53 GND#B53 PERn8 A53 GFXTn8_PERn8 {2}
B54 A54 100nF_6.3V
{2} PETp9_GFXRp9 PETp9 GND#A54
{2} PETn9_GFXRn9 B55 PETn9 GND#A55 A55
B56 A56 PERp9 C25
GND#B56 PERp9 PERn9 100nF_6.3V C26 GFXTp9_PERp9 {2}
B57 GND#B57 PERn9 A57 GFXTn9_PERn9 {2}
B58 A58 100nF_6.3V
{2} PETp10_GFXRp10 PETp10 GND#A58
{2} PETn10_GFXRn10 B59 PETn10 GND#A59 A59
B60 A60 PERp10 C27
GND#B60 PERp10 PERn10 100nF_6.3V C28 GFXTp10_PERp10 {2}
B61 GND#B61 PERn10 A61 GFXTn10_PERn10 {2}
B62 A62 100nF_6.3V
{2} PETp11_GFXRp11 PETp11 GND#A62
{2} PETn11_GFXRn11 B63 PETn11 GND#A63 A63
B64 A64 PERp11 C29
GND#B64 PERp11 PERn11 100nF_6.3V C30 GFXTp11_PERp11 {2}
B65 GND#B65 PERn11 A65 GFXTn11_PERn11 {2}
B66 A66 100nF_6.3V
{2} PETp12_GFXRp12 PETp12 GND#A66
{2} PETn12_GFXRn12 B67 PETn12 GND#A67 A67
B68 A68 PERp12 C31
GND#B68 PERp12 PERn12 100nF_6.3V C32 GFXTp12_PERp12 {2}
B69 GND#B69 PERn12 A69 GFXTn12_PERn12 {2}
B70 A70 100nF_6.3V
{2} PETp13_GFXRp13 PETp13 GND#A70
{2} PETn13_GFXRn13 B71 PETn13 GND#A71 A71
B72 A72 PERp13 C33
GND#B72 PERp13 PERn13 100nF_6.3V C34 GFXTp13_PERp13 {2}
B73 GND#B73 PERn13 A73 GFXTn13_PERn13 {2}
B74 A74 100nF_6.3V
{2} PETp14_GFXRp14 PETp14 GND#A74
B {2} PETn14_GFXRn14 B75 PETn14 GND#A75 A75 B
B76 A76 PERp14 C35
GND#B76 PERp14 PERn14 100nF_6.3V C36 GFXTp14_PERp14 {2}
B77 GND#B77 PERn14 A77 GFXTn14_PERn14 {2}
B78 A78 100nF_6.3V
{2} PETp15_GFXRp15 PETp15 GND#A78
{2} PETn15_GFXRn15 B79 PETn15 GND#A79 A79
B80 A80 PERp15 C37
PRESENCE GND#B80 PERp15 PERn15 100nF_6.3V C38 GFXTp15_PERp15 {2}
B81 PRSNT2#B81 PERn15 A81 GFXTn15_PERn15 {2}
B82 A82 100nF_6.3V
RSVD#B82 GND#A82
MPCIE1

SYMBOL LEGEND

DNI DO NOT
INSTALL

# ACTIVE
LOW

DIGITAL
GROUND

ANALOG
A GROUND A

BUO BRING UP
ONLY

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 1
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - PCI-E Edge Connector 105-B381xx-00A
8 7 6 5 4 3 2 1
 5 4 3 2 1

D D

NOTE: some of the PCIE testpoints will

be available trought via on traces. U1A
PART 1 OF 7
TP7
{1} PETp0_GFXRp0 AK33 PCIE_RX0P PCIE_TX0P AG31 GFXTp0_PERp0 {1}
{1} PETn0_GFXRn0 AJ33 PCIE_RX0N PCIE_TX0N AG30 GFXTn0_PERn0 {1}
TP8
{1} PETp1_GFXRp1 AJ35 PCIE_RX1P P PCIE_TX1P AF31 GFXTp1_PERp1 {1}
{1} PETn1_GFXRn1 AJ34 PCIE_RX1N C PCIE_TX1N AF30 GFXTn1_PERn1 {1}
TP9 I
{1} PETp2_GFXRp2 AH35 PCIE_RX2P - PCIE_TX2P AF28 GFXTp2_PERp2 {1}
{1} PETn2_GFXRn2 AH34 PCIE_RX2N PCIE_TX2N AF27 GFXTn2_PERn2 {1}
E
TP11 TP10 X
{1} PETp3_GFXRp3 AG35 PCIE_RX3P PCIE_TX3P AD31 GFXTp3_PERp3 {1}
AG34 P AD30
{1} PETn3_GFXRn3 PCIE_RX3N PCIE_TX3N GFXTn3_PERn3 {1}
R
TP12
AF33 E AD28
{1} PETp4_GFXRp4 PCIE_RX4P PCIE_TX4P GFXTp4_PERp4 {1}
{1} PETn4_GFXRn4 AE33 PCIE_RX4N S PCIE_TX4N AD27 GFXTn4_PERn4 {1}
TP13 S
{1} PETp5_GFXRp5 AE35 PCIE_RX5P PCIE_TX5P AB31 GFXTp5_PERp5 {1}
{1} PETn5_GFXRn5 AE34 PCIE_RX5N I PCIE_TX5N AB30 GFXTn5_PERn5 {1}
TP14 TP15 N
{1} PETp6_GFXRp6 AD35 PCIE_RX6P T PCIE_TX6P AB28 GFXTp6_PERp6 {1}
{1} PETn6_GFXRn6 AD34 PCIE_RX6N PCIE_TX6N AB27 GFXTn6_PERn6 {1}
E
C TP16 R C

{1} PETp7_GFXRp7 AC35 PCIE_RX7P PCIE_TX7P AA31 GFXTp7_PERp7 {1}

AC34 F AA30
{1} PETn7_GFXRn7 PCIE_RX7N PCIE_TX7N GFXTn7_PERn7 {1}
A
TP17
AB33
C AA28
{1} PETp8_GFXRp8 PCIE_RX8P PCIE_TX8P GFXTp8_PERp8 {1}
{1} PETn8_GFXRn8
AA33 PCIE_RX8N E PCIE_TX8N AA27
GFXTn8_PERn8 {1}
TP19 TP18
AA35 PCIE_RX9P PCIE_TX9P W31
{1} PETp9_GFXRp9 AA34 W30 GFXTp9_PERp9 {1}
{1} PETn9_GFXRn9 PCIE_RX9N PCIE_TX9N GFXTn9_PERn9 {1}
TP20
Y35 PCIE_RX10P PCIE_TX10P W28
{1} PETp10_GFXRp10 Y34 W27 GFXTp10_PERp10 {1}
{1} PETn10_GFXRn10 PCIE_RX10N PCIE_TX10N GFXTn10_PERn10 {1}
TP21
W35 PCIE_RX11P PCIE_TX11P V31
{1} PETp11_GFXRp11 W34 V30 GFXTp11_PERp11 {1}
{1} PETn11_GFXRn11 PCIE_RX11N PCIE_TX11N GFXTn11_PERn11 {1}
TP22 TP23
V33 PCIE_RX12P PCIE_TX12P V28
{1} PETp12_GFXRp12 U33 V27 GFXTp12_PERp12 {1}
{1} PETn12_GFXRn12 PCIE_RX12N PCIE_TX12N GFXTn12_PERn12 {1}
TP24
U35 PCIE_RX13P PCIE_TX13P U31
{1} PETp13_GFXRp13 U34 U30 GFXTp13_PERp13 {1}
{1} PETn13_GFXRn13 PCIE_RX13N PCIE_TX13N GFXTn13_PERn13 {1}
TP25
T35 PCIE_RX14P PCIE_TX14P U28
{1} PETp14_GFXRp14 T34 U27 GFXTp14_PERp14 {1}
{1} PETn14_GFXRn14 PCIE_RX14N PCIE_TX14N GFXTn14_PERn14 {1}
TP27 TP26
R35 PCIE_RX15P PCIE_TX15P R31
{1} PETp15_GFXRp15 R34 R30 GFXTp15_PERp15 {1}
{1} PETn15_GFXRn15 PCIE_RX15N PCIE_TX15N GFXTn15_PERn15 {1}
TP28
Clock Calibration
B B
AJ31 +PCIE_VDDC
{1} PCIE_REFCLKP PCIE_REFCLKP
{1} PCIE_REFCLKN AJ30 PCIE_REFCLKN
AG26 2.0K R8 402
PCIE_CALRN R9 402
PCIE_CALRP AJ27
DNI DNI 1.27K

R13 R14
51R 51R {1} PERST#_buf AM32
402 402 PERSTB

For Tektronix LA only

RV635 XT A11

Place close
to ASIC

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 2
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC PCIE_Interface 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 0402, 6.3V
100nF, X7R, 0402
10nF , X7R, 0402

U1B
PART 2 OF 7
D Integrated Integrated D
R116 182R R120 499R
T2XCM AP22 LVTM/TMDS2 DP/TMDS AN9 DPA_TX0P C1120 180nF_10V
{15} T2XCM T2XCM TXCAM_DPA3N T1XCM {16}
{15} T2XCP T2XCP AR22 AN10 DPA_TX0N C1121 180nF_10V T1XCP {16}
T2XCP TXCAP_DPA3P R110 182R R122 499R R121 499R
{15} T2X0M T2X0M AN22 AR10 DPA_TX1P C1122 180nF_10V T1X0M {16}
T2X0P T2X0M TX0M_DPA2N DPA_TX1N C1123 180nF_10V
{15} T2X0P AN23 T2X0P TX0P_DPA2P AP10 T1X0P {16}
R111 182R R124 499R R123 499R
{15} T2X1M T2X1M AR23 V AR11 DPA_TX2P C1124 180nF_10V T1X1M {16}
T2X1P T2X1M TX1M_DPA1N DPA_TX2N C1125 180nF_10V
{15} T2X1P AP23 AP11 T1X1P {16}
T2X1P I TX1P_DPA1P R112 182R R126 499R R125 499R
{15} T2X2M T2X2M AR24 T2X2M
D TX2M_DPA0N AR12 DPA_TX3P C1126 180nF_10V T1X2M {16}
{15} T2X2P T2X2P AP24 AP12 DPA_TX3N C1127 180nF_10V T1X2P {16}
T2X2P E TX2P_DPA0P R127 499R
{15} T2X3M T2X3M AR25 T2X3M
O
{15} T2X3P T2X3P AP25 AR14
T2X3P TXCBM_DPB3N
TXCBP_DPB3P AP14
{15} T2X4M T2X4M AN26 & R113 182R R132 499R
+1.8V T2X4P T2X4M DPB_TX1P C1132 180nF_10V
{15} T2X4P AN27 T2X4P TX3M_DPB2N AR15 T1X3M {16}
AP15 DPB_TX1N C1133 180nF_10V T1X3P {16}
T2X5M M TX3P_DPB2P R114 182R R134 499R R133 499R
{15} T2X5M AR27 T2X5M
B889 {15} T2X5P T2X5P AP27 U AR16 DPB_TX2P C1134 180nF_10V T1X4M {16}
BLM15BD121SN1 +T2PVDD T2X5P TX4M_DPB1N DPB_TX2N C1135 180nF_10V
AP16 T1X4P {16}
AL22 L TX4P_DPB1P R115 182R R136 499R R135 499R
T2PVDD DPB_TX3P C1136 180nF_10V
AK22 T2PVSS T TX5M_DPB0N AR17 T1X5M {16}
AP17 DPB_TX3N C1137 180nF_10V T1X5P {16}
NS100 MC100 C100 C101 C102 I TX5P_DPB0P R137 499R
NS_VIA 4.7uF_6.3V 10uF_X6S 100nF_6.3V 1uF_6.3V AK27 T2XVDDC_1
M
Q100 1 2 AL27 AG15 DP_CALR R128 150R +1.8V DP_GND
+1.8V SI2304DS T2XVDDC_2 E DP_CALR DNI for RV630 Overlap footprints +DPA_PVDD
GND_T2PVSS D DPA_PVDD AM14 B887 BLM15BD121SN1
Use 0R +LTVDD18
Overlap footprints I DPA_PVSS AL14

3
2 3 B100
AJ26 A AH17 C111 C112 C113 MC113 NS110 Q110
BLM15BD121SN1 T2XVDDR_1 DPB_PVDD 100nF 1uF_6.3V 10uF_X6S 4.7uF_6.3V NS_VIA
AH26 T2XVDDR_2 DPB_PVSS AG17 SI2304DS
MC103 C103 C108 C109 2 1 {13} LVT_EN 1
1

4.7uF_6.3V 10uF_X6S 1uF_6.3V 100nF_6.3V AP19 +1.8V

DPA_VDDR_1 GND_DPAVSS
AR19 Overlap footprints

2
DPA_VDDR_2 +DPB_PVDD B890 BLM15BD121SN1
C AJ22 T2XVSSR_1
C
{13} LVT_EN AN21 T2XVSSR_2 DPA_VSSR_1 AN11
AN24 AN12 C190 C191 C192 MC192 NS190 +1.1V
T2XVSSR_3 DPA_VSSR_2 100nF 1uF_6.3V 10uF_X6S 4.7uF_6.3V NS_VIA
AN25 T2XVSSR_4 DPA_VSSR_3 AN13
R109 AN28 AN14 2 1
T2XVSSR_5 DPA_VSSR_4 B881
0R AP21 AN15 Overlap footprints
T2XVSSR_6 DPA_VSSR_5 GND_DBPVSS +DPA_VDDR
AP26 T2XVSSR_7
+LTVDD33
DNI for RV630 AR21
AR26
T2XVSSR_8 DPB_VDDR_1 AN19
AN20 C115 C116 C117 MC117
T2XVSSR_9 DPB_VDDR_2 100nF 1uF_6.3V 10uF_X6S 4.7uF_6.3V BLM15BD121SN1
AJ24 T2XVSSR_10
C105 AM22 AN16 +1.1V
T2XVSSR_11 DPB_VSSR_1 B892
C107 100nF_6.3V AM24 AN17 Overlap footprints
1uF_6.3V T2XVSSR_12 DPB_VSSR_2 +DPB_VDDR
AM26 T2XVSSR_13 DPB_VSSR_3 AN18
+3.3V AM27 AR18
T2XVSSR_14 DPB_VSSR_4 C193 C194 C195 MC195
DPB_VSSR_5 AP18 BLM15BD121SN1
100nF 1uF_6.3V 10uF_X6S 4.7uF_6.3V

R40 R41 AM29 Monitor DAC / CRT AR31 A_DAC1_R {15}

{15} CRT1DDCDATA DDC1DATA Interface R
+3.3V 4.7K 4.7K {15} CRT1DDCCLK AL29 AP31 A_DAC1_RB {15}
402 402 DDC1CLK RB
DDC2DATA AJ15 AR30 A_DAC1_G {15}
DDC2DATA DDC2DATA G
DDC2CLK DDC2CLK AH15 AP30 A_DAC1_GB {15}
DDC2CLK GB
R80 AJ5 AR29 A_DAC1_B {15}
{16} CRT2DDCDATA DDC3DATA_DP3_AUXN B
R42 4.7K {16} CRT2DDCCLK AJ4 AP29 A_DAC1_BB {15}
4.7K DDC3CLK_DP3_AUXP BB +1.8V
AH14 DDC4DATA_DP4_AUXN HSYNC AN29 HSYNC_DAC1 {7,15}
+3.3V AG14 AN30 VSYNC_DAC1 {7,15}
DDC4CLK_DP4_AUXP VSYNC B882
AG6 AN31 RSET R1030 499R GND_AVSSQ +AVDD BLM15BD121SN1
{16} HPD1 HPD1 RSET
R35 R36 AR32 +1.8V
4.7K 4.7K AVDD C1020 C1021 C1022 NS1020 NS_VIA
SDA AK6 AP32 10nF 100nF_6.3V 1uF_6.3V 2 1
SCL SDA MMI2C AVSSQ B884
AM6 SCL +VDD1DI GND_AVSSQ BLM15BD121SN1
What happens to all the JTAG resistors especially R7 and also the TRs? AR28
I2C DEVICE ADDRESS' ON DDC2 VDD1DI
B DEVICE ADDRESS B
AK4 AP28 C1023 C1024 C1025 NS1021 NS_VIA
LM63 x100 1100 DMINUS Thermal VSS1DI 10nF 100nF_6.3V 1uF_6.3V
AM4 DPLUS 2 1
DP TBD Diode
AG21 TS_FDO DAC2 (TV/CRT2) AM19 GND_VSS1DI
R2 A_DAC2_R {16}
R2B AL19 A_DAC2_RB {16}

G2 AM18 A_DAC2_G {16}

AH19 PLLTEST G2B AL18 A_DAC2_GB {16}
TEST_EN AM30 Test
TESTEN
B2 AM17 A_DAC2_B {16}
B2B AL17 A_DAC2_BB {16}
MR7
1K AM15 HSYNC_DAC2 {7,16}
+1.8V H2SYNC
V2SYNC AL15 VSYNC_DAC2 {7,16}
R43 221R VREFG AD12 VREFG
Y AK18 A_DAC2_Y {17}
R44 110R AK19 A_DAC2_C {17}
C46 C
COMP AK17 A_DAC2_COMP {17}
100nF_6.3V +1.8V

XTALIN AR33 AJ21 R2SET R2030 715R GND_A2VSSQ

XTALOUT XTALIN R2SET B883
AP33 XTALOUT +A2VDDQ BLM15BD121SN1
A2VDDQ AL21

AK21 C2021 C2022 +1.8V

A2VSSQ 100nF_6.3V 1uF_6.3V NS2020 NS_VIA
2 1
AH22 B885
VDD2DI +VDD2DI GND_A2VSSQ BLM15BD121SN1
VSS2DI AG22

C2024 C2025 C2026 NS2021 NS_VIA

Share one pad AM21 10nF 100nF_6.3V 1uF_6.3V 2 1
A2VDD
GND_VSS2DI +A2VDD B2030 26R_600mA +3.3V

A RV635 XT A11 A
C2030 C2031 C2032 C2033 MC2033
10nF 100nF_6.3V 1uF_6.3V 10uF_X6S 4.7uF_6.3V

Overlap footprints
1

C86 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

22pF EY82 R84 ?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
27_MHZ 1M and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
2

is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
C85 regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
22pF any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 3
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC MAIN 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

Recommended caps:
(see BOM for qualified values/vendors)
10uF , X6S, 0805, 6.3V, 1.4MM MAX THICK
1uF, X6S, 0402, 6.3V U1E
100nF, X7R, 0402 PART 5 OF 7 +1.8V
10nF , X7R, 0402 B930
+MVDD +PCIE_PVDD Overlap footprints
A8 VDDR1_1 PCIE_PVDD AM35
H35 VDDR1_2
L22 VDDR1_3
C150 C151 C152 C154 C155 C157 C158 C159 M1 C930 C931 C932 C933 MC933 BLM15BD121SN1
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V VDDR1_4 10nF 100nF_6.3V 1uF_6.3V 10uF_X6S 4.7uF_6.3V
M10 VDDR1_5
M35 NS18 NS_VIA
VDDR1_6
P10 VDDR1_7 2 1
D
T1 VDDR1_8 D
Y1 VDDR1_9
A12 GND_PCIE_PVSS
C156 C130 C131 C132 C133 C134 C135 C136 C137 C138 VDDR1_10
A16 VDDR1_11 PCIE_VDDC_1 R26
100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V 100nF_6.3V A20 W25 Overlap footprints
VDDR1_12 PCIE_VDDC_2 +PCIE_VDDC +1.1V
A24 VDDR1_13 PCIE_VDDC_3 W26
A28 AA25 B920
VDDR1_14 PCIE_VDDC_4 0R
B1 VDDR1_15 PCIE_VDDC_5 AA26

Memory I/O
B35 AB25 C920 C921 C922 C923 C924 C925 C926
VDDR1_16 PCIE_VDDC_6 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 10uF_X6S
D1 VDDR1_17 PCIE_VDDC_7 AB26
C153 C140 C141 C142 C143 C144 C145 C146 C147 C148 D35 AD26
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V VDDR1_18 PCIE_VDDC_8
H1 VDDR1_19 PCIE_VDDC_9 AF26
K10 VDDR1_20 PCIE_VDDC_10 U26
K12 VDDR1_21 PCIE_VDDC_11 V25
K24 VDDR1_22 PCIE_VDDC_12 V26
Overlap cap pair foorprints (0805 with 0603) K26 VDDR1_23
L14 +1.8V
VDDR1_24 +PCIE_VDDR
L15 VDDR1_25
L17 AL33 R900
C124 C125 C126 C127 C128 C129 VDDR1_26 PCIE_VDDR_1 0R
L18 VDDR1_27 PCIE_VDDR_2 AM33
10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S C900 C901 C902 C903 C904 C905 C906 C907

PCI-Express
L19 VDDR1_28 PCIE_VDDR_3 AN33
L21 AN34 10nF 100nF_6.3V 1uF_6.3V 10nF 100nF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
VDDR1_29 PCIE_VDDR_4
PCIE_VDDR_5 AN35
PCIE_VDDR_6 AP34
PCIE_VDDR_7 AP35
MC124 MC125 MC126 MC127 MC128 MC129 AR34
4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V PCIE_VDDR_8
P
+MVDD
O
B120 W +VDDC

Core
A25 N13
A32
VDDRHA_1
VDDRHA_2
E VDDC_1
VDDC_2 R18
BLM15BD121SN1 W11
R VDDC_3
AB19 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C941 C942 C943
B121 C120 VDDC_4 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
VDDC_5 AC23
1uF_6.3V B2 AE18
C121 C122 C123 VDDRHB_1 VDDC_6
L1 VDDRHB_2 VDDC_7 AE19
C BLM15BD121SN1 1uF_6.3V 1uF_6.3V 1uF_6.3V AE21 C
VDDC_8
VDDC_9 AE22
NS120 NS_VIA N15 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180
NS121 NS_VIA VDDC_10 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
1 2 VDDC_11 N18
1 2 VDDC_12 N21
GND_VSSRHA_1 B25 N23
VSSRHA_1 VDDC_13
B32 VSSRHA_2 VDDC_14 P14
GND_VSSRHA_2 P17
NS122 NS_VIA VDDC_15 C160 C184 C185 C186 C944 C945 C946 C947 C948
VDDC_16 P19
B122 1 2 P22 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
VDDC_17
C2 VSSRHB_1 VDDC_18 R13
GND_VSSRHB_1 L2 R15 Overlap cap pair foorprints (0805 with 0603)
BLM15BD121SN1 VSSRHB_2 VDDC_19
VDDC_20 R21
NS123 NS_VIA R23
B123 VDDC_21 C181 C182 C183 C187 C188 C189
1 2 VDDC_22 U14
U17 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S 10uF_X6S
VDDC_23
AE14 VDDR3_1 VDDC_24 U19
BLM15BD121SN1 +3.3V GND_VSSRHB_2 AE15 U22
VDDR3_2 VDDC_25
AE17 VDDR3_3 VDDC_26 V15
AF12 V18 MC181 MC182 MC188 MC189
VDDR3_4 VDDC_27 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V 4.7uF_6.3V
VDDC_28 V21
C90 C91 C92 C93 V23
1uF_6.3V 100nF_6.3V 1uF_6.3V 100nF_6.3V VDDC_29
VDDC_30 W14
VDDC_31 W17
VDDC_32 W19
AP2 VDDR4_1 VDDC_33 W22
+1.8V AR2 AA15
VDDR4_2 VDDC_34
Overlap footprints VDDC_35 AA18
VDDC_36 AA21
C95 C97 AA23
MC94 C94 1uF_6.3V 100nF_6.3V VDDC_37
AN1 VDDR5_1 VDDC_38 AB14
4.7uF_6.3V 10uF_X6S AP1 AB17
VDDR5_2 VDDC_39
VDDC_40 AB22
C96 C98 AC13
1uF_6.3V 100nF_6.3V VDDC_41
VDDC_42 AC15
VDDC_43 AC18
VDDC_44 AC21
B B
+VDDC
BBP_1 U13
+1.8V V13
BBP_2
Overlap footprints +VDDC
B886 Selected PLL's +VDDCI_1
BLM15BD121SN1 +DPLL_PVDD B77 220R_2A
Overlap footprints VDDCI_1 M12
+DPLL_PVDD AR20 M24
DPLL_PVDD VDDCI_2 C74 C75 C77 MC77
VDDCI_3 P11
P25 100nF_6.3V 1uF_6.3V 10uF_X6S 4.7uF_6.3V
MC70 C70 C71 C72 VDDCI_4
B69
NS70 NS_VIA 4.7uF_6.3V 10uF_X6S 100nF_6.3V 1uF_6.3V +VDD_CT +1.8V
1 2 GND_PVSS AP20 R11
DPLL_PVSS VDD_CT_1
VDD_CT_2 R25
+VDDCI_2
Overlap footprints
GND_PVSS U11 C78 C68 C69 BLM15BD121SN1
VDD_CT_3 1uF_6.3V 1uF_6.3V 100nF_6.3V B78 220R_2A
VDD_CT_4 U25
VDD_CT_5 AA11
AB11 C73 C76 C79 MC79
VDD_CT_6 100nF_6.3V 1uF_6.3V 10uF_X6S 4.7uF_6.3V
VDD_CT_7 AD10
VDD_CT_8 AF10

+MPVDD Overlap footprints +VDDC

A14 +MPVDD B67 60R_700mA
MPVDD
C67 MC67
A35 C64 C65 C66 10uF_X6S 4.7uF_6.3V
MECH_1 Mechanical Pins 10nF 100nF_6.3V 1uF_6.3V NS_VIA NS64
AR1 MECH_2
AR35 B15 GND_MPVSS 2 1
MECH_3 MPVSS
Install only one of these two
GND_MPVSS
Overlap footprints +DPLL_VDDC +1.1V
AG19 +DPLL_VDDC B60
DPLL_VDDC BLM15BD121SN1
C61 C62 C63 MC63
RV635 XT A11 100nF_6.3V 1uF_6.3V 10uF_X6S 4.7uF_6.3V +VDDC
MB60 R922
A BLM15BD121SN1 A
1.5R
GND_PVSS

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 4
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC Power 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

{8} DQA_[63..0]
D D

{9} DQB_[63..0]
U1D
U1C
MAB_[12..0] {9}
Part 4 of 7
MAA_[12..0] {8}
Part 3 of 7
H2 MAB_0
DQA_0 MAA_0 MAB_0 MAB_1
P27 DQA_0 MAA_0 C27 MAB_1 H3
DQA_1 P28 B28 MAA_1 DQB_0 H15 J3 MAB_2
DQA_2 DQA_1 MAA_1 MAA_2 DQB_1 DQB_0 MAB_2 MAB_3
P31 DQA_2 MAA_2 B27 G14 DQB_1 MAB_3 J5
DQA_3 P32 G26 MAA_3 DQB_2 E14 J4 MAB_4
DQA_4 DQA_3 MAA_3 MAA_4 DQB_3 DQB_2 MAB_4 MAB_5
M27 DQA_4 MAA_4 F27 D14 DQB_3 MAB_5 J6
DQA_5 K29 E27 MAA_5 DQB_4 H12 G5 MAB_6
DQA_6 DQA_5 MAA_5 MAA_6 DQB_5 DQB_4 MAB_6 MAB_7

MEMORY INTERFACE B
K31 DQA_6 MAA_6 D27 G12 DQB_5 MAB_7 J9
DQA_7 MAA_7 DQB_6 MAB_8

MEMORY INTERFACE A
K32 DQA_7 MAA_7 J27 F12 DQB_6 MAB_8 F3
DQA_8 M33 E29 MAA_8 DQB_7 D10 F4 MAB_9
DQA_9 DQA_8 MAA_8 MAA_9 DQB_8 DQB_7 MAB_9 MAB_10
M34 DQA_9 MAA_9 C30 B13 DQB_8 MAB_10 J1
DQA_10 L34 E26 MAA_10 DQB_9 C12 J2 MAB_11
DQA_10 MAA_10 DQB_9 MAB_11 MAB_BA[2..0] {9}
DQA_11 L35 A27 MAA_11 DQB_10 B12 J7 MAB_12
DQA_11 MAA_11 MAA_BA[2..0] {8} DQB_10 MAB_A12
DQA_12 J33 G27 MAA_12 DQB_11 B11 G2 MAB_BA0
DQA_13 DQA_12 MAA_A12 MAA_BA0 DQB_12 DQB_11 MAB_BA0 MAB_BA1
J34 DQA_13 MAA_BA0 C28 C9 DQB_12 MAB_BA1 G3
DQA_14 H33 B29 MAA_BA1 DQB_13 B9 F1 MAB_BA2
DQA_15 DQA_14 MAA_BA1 MAA_BA2 DQB_14 DQB_13 MAB_BA2
H34 DQA_15 MAA_BA2 D26 A9 DQB_14 DQMBb_[7..0] {9}
DQA_16 K27 DQB_15 B8
DQA_16 DQMAb_[7..0] {8} DQB_15
DQA_17 J29 DQB_16 J10 D12 DQMBb_0
DQA_18 DQA_17 DQMAb_0 DQB_17 DQB_16 DQMBB_0 DQMBb_1
J30 DQA_18 DQMAB_0 M29 H10 DQB_17 DQMBB_1 C10
DQA_19 J31 K33 DQMAb_1 DQB_18 F10 E7 DQMBb_2
DQA_20 DQA_19 DQMAB_1 DQMAb_2 DQB_19 DQB_18 DQMBB_2 DQMBb_3
F29 DQA_20 DQMAB_2 G30 D9 DQB_19 DQMBB_3 C6
DQA_21 F32 E33 DQMAb_3 DQB_20 G7 P3 DQMBb_4
DQA_22 DQA_21 DQMAB_3 DQMAb_4 DQB_21 DQB_20 DQMBB_4 DQMBb_5
D30 DQA_22 DQMAB_4 C22 G6 DQB_21 DQMBB_5 R4
DQA_23 D32 H21 DQMAb_5 DQB_22 F6 W3 DQMBb_6
DQA_24 DQA_23 DQMAB_5 DQMAb_6 DQB_23 DQB_22 DQMBB_6 DQMBb_7
G33 DQA_24 DQMAB_6 C17 D6 DQB_23 DQMBB_7 V8
DQA_25 G34 G17 DQMAb_7 DQB_24 C8
DQA_25 DQMAB_7 DQB_24 QSB_[7..0] {9}
DQA_26 G35 DQB_25 C7
DQA_26 QSA_[7..0] {8} DQB_25
DQA_27 F34 DQB_26 B7
DQA_28 DQA_27 DQB_27 DQB_26 DDR1 DDR2 DDR3 QSB_0
D34 DQA_28 DDR1 DDR2 DDR3 A7 DQB_27 QSB_0 J14
DQA_29 C34 M30 QSA_0 DQB_28 B5 B10 QSB_1
DQA_30 DQA_29 QSA_0 QSA_1 DQB_29 DQB_28 QSB_1 QSB_2
C C35 DQA_30 QSA_1 K34 A5 DQB_29 QSB_2 F9 C
DQA_31 B34 G31 QSA_2 DQB_30 C4 B6 QSB_3
DQA_32 DQA_31 QSA_2 QSA_3 DQB_31 DQB_30 QSB_3 QSB_4
C24 DQA_32 QSA_3 E34 B4 DQB_31 QSB_4 P2
DQA_33 B24 B22 QSA_4 DQB_32 M3 P8 QSB_5
DQA_34 DQA_33 QSA_4 QSA_5 DQB_33 DQB_32 QSB_5 QSB_6
B23 F21 M2 W2
bidir. differential strobe

bidir. differential strobe

DQA_35 DQA_34 QSA_5 QSA_6 DQB_34 DQB_33 QSB_6 QSB_7
A23 DQA_35 QSA_6 B17 N2 DQB_34 QSB_7 V6
DQA_36 C21 D17 QSA_7 DQB_35 N1
DQA_37 DQA_36 QSA_7 DQB_36 DQB_35
B21 DQA_37 R3 DQB_36
DQA_38 C20 DQB_37 R2 H14
DQA_39 DQA_38 DQB_38 DQB_37 QSB_0B
B20 DQA_39 QSA_0B M31 T3 DQB_38 QSB_1B A10
DQA_40 DQB_39

write strobe
J22 DQA_40 QSA_1B K35 T2 DQB_39 QSB_2B E9
DQA_41 DQB_40
write strobe

H22 DQA_41 QSA_2B G32 M8 DQB_40 QSB_3B A6

DQA_42 F22 E35 DQB_41 M7 P1

Not used
DQA_43 DQA_42 QSA_3B DQB_42 DQB_41 QSB_4B
D21 A22 P5 P7
Not used

DQA_44 DQA_43 QSA_4B DQB_43 DQB_42 QSB_5B

J19 DQA_44 QSA_5B E21 P4 DQB_43 QSB_6B W1
DQA_45 G19 A17 DQB_44 R9 V5
DQA_46 DQA_45 QSA_6B DQB_45 DQB_44 QSB_7B
F19 DQA_46 QSA_7B E17 R8 DQB_45
DQA_47 D19 DQB_46 R6 D2 ODTB0 {9}
DQA_48 DQA_47 DQB_47 DQB_46 For DDR2 ODTB0
C19 DQA_48 ODTA0 C31 ODTA0 {8} U4 DQB_47 ODTB1 K5
DQA_49 B19 For DDR2 C25 DQB_48 U3
DQA_50 DQA_49 ODTA1 DQB_49 DQB_48
A19 DQA_50 U2 DQB_49
DQA_51 B18 DQB_50 U1 A3 CLKB0 {9}
DQA_52 DQA_51 DQB_51 DQB_50 CLKB0
C16 DQA_52 CLKA0 A33 CLKA0 {8} V2 DQB_51 CLKB0B B3 CLKB0b {9}
DQA_53 B16 B33 CLKA0b {8} DQB_52 Y3
DQA_54 DQA_53 CLKA0B DQB_53 DQB_52
C15 DQA_54 Y2 DQB_53 CKEB0 E3 CKEB0 {9}
DQA_55 A15 B31 CKEA0 {8} DQB_54 AA2
DQA_56 DQA_55 CKEA0 DQB_55 DQB_54
H18 DQA_56 AA1 DQB_55 RASB0B D3 RASB0b {9}
DQA_57 F18 A31 RASA0b {8} DQB_56 U9
+MVDD DQA_58 DQA_57 RASA0B DQB_57 DQB_56
E18 U7 C1

bidir. strobe

read strobe
DQA_58 DQB_57 CASB0B CASB0b {9}
DQA_59 D18 C32 CASA0b {8} DQB_58 U6
read strobe

DQA_60 DQA_59 CASA0B DQB_59 DQB_58

J17 DQA_60 V4 DQB_59 WEB0B F2 WEB0b {9}
DQA_61 G15 C29 +MVDD DQB_60 W9
bidir. strobe

DQA_61 WEA0B WEA0b {8} DQB_60

DQA_62 E15 DQB_61 W7 E1 CSB0b_0 {9}
DQA_63 DQA_62 DQB_62 DQB_61 CSB0B_0
D15 DQA_63 CSA0B_0 A30 CSA0b_0 {8} W6 DQB_62 CSB0B_1 E2
B30 DQB_63 W4
R291 CSA0B_1 R391 DQB_63
100R 100R K1 CLKB1 {9}
1% 1% CLKB1
B CLKA1 A26 CLKA1 {8} CLKB1B K2 CLKB1b {9} B
MVREFD_0 N35 B26 CLKA1b {8} MVREFD_1 B14
MVREFDA CLKA1B MVREFS_1 MVREFDB
N34 MVREFSA A13 MVREFSB CKEB1 K8 CKEB1 {9}
CKEA1 F24 CKEA1 {8}
R292 R392 C391 C392 K7 RASB1b {9}
100R C291 C292 100R 100nF 10nF RASB1B
RASA1B D24 RASA1b {8}
1% 100nF 10nF 1% AA4 K4
DRAM_RST CASB1B CASB1b {9}
CASA1B H26 CASA1b {8}
AA8 TEST_MCLK WEB1B M6 WEB1b {9}
WEA1B D22 WEA1b {8}
AA7 TEST_YCLK CSB1B_0 L3 CSB1b_0 {9}
G24 CSA1b_0 {8} +MVDD M4
+MVDD CSA1B_0 CSB1B_1
CSA1B_1 H24 AA5 MEMTEST

RV635 XT A11 R393

100R RV635 XT A11
R296 R297 R298
R293 1% 4.7K 4.7K 243R
100R
1%
MVREFS_0 R394 C393 C394
100R 100nF 10nF
1%
R294
100R C293 C294
1% 100nF 10nF

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 5
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC Memory Interface (Channel A & B) 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

U1F
Part 6 of 7
P33 PCIE_VSS_1 VSS_86 AJ14
V29 PCIE_VSS_2 VSS_87 AJ17
AB32 PCIE_VSS_3 VSS_88 AJ18
AG29 PCIE_VSS_4 VSS_89 AJ19
AJ29 PCIE_VSS_5 VSS_90 AK9
AJ32 PCIE_VSS_6 VSS_91 AK10
AK32 PCIE_VSS_7 VSS_92 AK12
D
AL34 PCIE_VSS_8 VSS_93 AK15 D
AL35 PCIE_VSS_9 VSS_94 AK30
P34 PCIE_VSS_10 VSS_95 AM1
P35 PCIE_VSS_11 VSS_96 AN3
R27 PCIE_VSS_12 VSS_97 AN6

PCI-Express GND
R28 PCIE_VSS_13 VSS_98 AN32
R29 PCIE_VSS_14 VSS_99 AR8
R32 PCIE_VSS_15 VSS_100 A11
R33 PCIE_VSS_16 VSS_101 A18
T33 PCIE_VSS_17 VSS_102 A21
U29 PCIE_VSS_18 VSS_103 A29
U32 PCIE_VSS_19 VSS_104 A34
V32 PCIE_VSS_20 VSS_105 C3
V34 PCIE_VSS_21 VSS_106 C5
V35 PCIE_VSS_22 VSS_107 C11
W29 PCIE_VSS_23 VSS_108 C13
W32 PCIE_VSS_24 VSS_109 C14
W33 PCIE_VSS_25 VSS_110 C23
Y33 PCIE_VSS_26 VSS_111 C26
AA29 PCIE_VSS_27 VSS_112 C33
AA32 PCIE_VSS_28 VSS_113 D4
AB29 PCIE_VSS_29 VSS_114 D7
AB34 PCIE_VSS_30 VSS_115 D29
AB35 PCIE_VSS_31 VSS_116 D33
AC33 PCIE_VSS_43 VSS_117 E10
AD29 PCIE_VSS_32 VSS_118 E12
AD32 PCIE_VSS_33 VSS_119 E19
AD33 PCIE_VSS_34 VSS_120 E24
AF29 PCIE_VSS_35 VSS_121 F7
AF32 PCIE_VSS_36 VSS_122 F14
AF34 PCIE_VSS_37 VSS_123 F15
AF35 PCIE_VSS_38 VSS_124 F17
AG27 PCIE_VSS_39 VSS_125 F26
AG32 PCIE_VSS_40 VSS_126 F30
AG33 PCIE_VSS_41 VSS_127 F33
AH33 PCIE_VSS_42 VSS_128 F35
VSS_129 G1
VSS_130 G9
C
VSS_131 G10 C
A2 VSS_1 VSS_132 G18
P15 VSS_2 VSS_133 G21
R14 VSS_3 VSS_134 G22
V1 VSS_4 VSS_135 G29
W8 VSS_5 VSS_136 H17
AA19 VSS_6 VSS_137 H19
AC17 VSS_7 VSS_138 J12
AF19 VSS_8 VSS_139 J15
AK3 VSS_9 VSS_140 J21
A4 VSS_10 VSS_141 J24
C18 VSS_11 VSS_142 J26
E22 VSS_12 VSS_143 J32
G4 VSS_13 VSS_144 J35
J18 VSS_14 VSS_145 K3
K17 VSS_15 VSS_146 K6
M28 VSS_16 VSS_147 K9
P6 VSS_17 VSS_148 K14
P9 VSS_18 VSS_149 K15
P13 VSS_19 VSS_150 K18
P18 VSS_20 VSS_151 K19
P21 VSS_21 VSS_152 K21
P23 VSS_22 VSS_153 K22
P26 VSS_23 VSS_154 K28
P29 K30
P30
R1
VSS_24
VSS_25
VSS_26
CORE GND VSS_155
VSS_156
VSS_157
L33
M5
R5 VSS_27 VSS_158 M9
R7 VSS_28 VSS_159 M26
R10 VSS_29 VSS_160 M32
R17 VSS_30 VSS_161 N3
R19 VSS_31 VSS_162 N14
R22 VSS_32 VSS_163 N17
U5 VSS_33 VSS_164 N19
U8 VSS_34 VSS_165 N22
U10 VSS_35 VSS_166 N33
U15 VSS_36
B
U18 VSS_37 B
U21 VSS_38
U23 VSS_39
V3 VSS_40
V7 VSS_41
V9 VSS_42
V10 VSS_43
V11 VSS_44
V14 VSS_45
V17 VSS_46
V19 VSS_47
V22 VSS_48
W5 VSS_49
W10 VSS_50
W15 VSS_51
W18 VSS_52
W21 VSS_53
W23 VSS_54
AA3 VSS_55
AA6 VSS_56
AA10 VSS_57
AA14 VSS_58
AA17 VSS_59
AA22 VSS_60
AB5 VSS_61
AB8 VSS_62
AB10 VSS_63
AB13 VSS_64
AB15 VSS_65
AB18 VSS_66
AB21 VSS_67
AB23 VSS_68
AC14 VSS_69
AC19 VSS_70
AC22 VSS_71
AD6 VSS_72
AD24 VSS_73
AF6 VSS_74
A AF9 VSS_75
A
AF14 VSS_76
AF15 VSS_77
AF17 VSS_78 BBN_1 W13
AF18 VSS_79 BBN_2 AA13
AF21 VSS_80
AF22 VSS_81
AF24 CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
VSS_82 ?2007 Advanced Micro Devices Advanced Micro Devices Inc.
AG10 VSS_83 This AMD Board schematic and design is the exclusive property of AMD,
AG12 VSS_84 and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
AH21 VSS_85
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
RV635 XT A11 any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 6
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC Grounds 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

U1G +3.3V
PIN BASED STRAPS GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable) ATI PCIE FEATURE I
PART 7 OF 7
R50 10K GPIO_0 0: 50% Tx output swing for mobile mode
AG2 GPIO_0 DNI MR50 10K 1: full Tx output swing (Default setting for Desktop)
GPIO_0 GPIO_1
VID_0 GPIO_1 AF2
GPIO_2
CrossFire GPIO_1 GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable) ATI PCIE FEATURE II
AM12 AF1 R51 10K
VID_1 VIP_0 GPIO_2 GPIO_3 FLOW_CONTROL_1 - Lower Cable DNI MR51 10K 0: Tx de-emphasis disabled for mobile mode
AL12 VIP_1 GPIO_3 AE3
VID_2 AJ12 VIP General AE2 GPIO_4 FLOW_CONTROL_2 - Upper Cable 1: Tx de-emphasis enabled (Default setting for Desktop)
VID_3 VIP_2 Capture Purpose GPIO_4 GPIO_5 SWAP_LOCK_1 - Lower Cable DNI R52 10K GPIO_2
AH12 VIP_3 GPIO_5 AE1
VID_4 AM10 I/O AD3 GPIO_6 SWAP_LOCK_2 - Upper Cable MR52 10K
VID_5 VIP_4 GPIO_6 GPIO_7 DNI R53 10K GPIO_3 AMD Internal Use Only - Reserved (Default: 00)
AL10 VIP_5 GPIO_7_BLON AD2
VID_6 AJ10 AD1 GPIO_8 MR53 10K
VID_7 VIP_6 GPIO_8_ROMSO GPIO_9
AH10 VIP_7 GPIO_9_ROMSI AD5
AD4 GPIO_10 DNI R54 1K GPIO_4 DEBUG_ACCESS
GPIO_10_ROMSCK GPIO_11 MR54 10K AMD Internal Use Only - Reserved (Default: 0)
GPIO_11 AC3
AL7 AC2 GPIO_12
VPCLK0 GPIO_12 GPIO_13 R55 10K GPIO_5
GPIO_13 AC1
AB3 HPD2
D GPIO_14_HPD2 HPD2 {15} AMD Internal Use Only - Reserved (Default: G1=0, G2=1) D
AM9 VHAD_0 GPIO_15_PWRCNTL_0 AB2
AL9 AB1 GPIO_16 MR55 10K
VHAD_1 GPIO_16_SSIN
GPIO_17_THERMAL_INT AF5
VIP AF4 GPIO_18_HPD3 +3.3V DNI R56 1K GPIO_6 AMD Internal Use Only - Reserved (Default: 0)
GPIO_18_HPD3 GPIO_18_HPD3
AJ9 Host AG4 MR56 10K
VPHCTL GPIO_19_CTF TV OUT STANDARD (Jumper position overwrite resistor settings)
GPIO_20_PWRCNTL_1 AG3
AK7 AD9 GPIO21_BB_EN BUO TR50 NTSC R57 10K GPIO_7 0 - PAL TVO (Jumper is closed)
VIPCLK GPIO_21_BB_EN TP50
AD8 GPIO_22 10K MR57 10K 1 - NTSC TVO (Jumper is open)
GPIO_22_ROMCSB PCIE_CLK_REQb
GPIO_23_CLKREQB AD7
AB4 JTAG_MODE DNI R58 10K GPIO_8_R AMD Internal Use Only - Reserved (Default: 0)
GPIO_24_TRST MR58 10K
AH1 DVPCLK GPIO_25_TDI AB6
AG1 AB7 MR5 R59 10K GPIO_9_R CONFIG[3] GPIO(9,13:11) - CONFIG[3..0]
DVPCNTL_0 GPIO_26_TCK 1K MR59 10K 0010 - 512Kbit AT25F512A (Atmel)
AH3 DVPCNTL_1 GPIO_27_TMS AB9
AH2 AA9 R63 10K GPIO_13 CONFIG[2] 0011 - 1Mbit AT25F1024A (Atmel)
DVPCNTL_2 GPIO_28_TDO MR63 10K 0100 - 512Kbit M25P05A (ST)
AN8 DVPCNTL_MVP_0 GENERICA R62 10K GPIO_12 0101 - 1Mbit M25P10A (ST)
AP8 DVPCNTL_MVP_1 GEN_A AF8 GENERICA {17} CONFIG[1] 0101 - 2Mbit M25P20 (ST)
AF7 GENERICB MR62 10K
GEN_B GENERICC R61 10K GPIO_11
0100 - 512Kbit Pm25LV512 (Chingis)
GEN_C AG5 CONFIG[0] 0101 - 1Mbit Pm25LV010 (Chingis)
AP9 MR61 10K
GEN_D_HPD4
GEN_E AR9
AJ3 AP13 DNI R65 10K GENERICC AMD Internal Use Only - Reserved (Default: 0)
DVPDATA_0 GEN_F MR65 10K
AJ2 DVPDATA_1 GEN_G AR13
AJ1 DNI R64 10K GENERICB
DVPDATA_2 DVALID DNI MR64 10K
AK2 DVPDATA_3 DVALID AJ7
AK1 AM7 PSYNC VIP_DEVICE_STRAP_EN
DVPDATA_4 PSYNC R66 10K VSYNC_DAC1 VSYNC_DAC1 {3,15} 0: Slave VIP host port devices present (use if Theater is populated)
AL3 DVPDATA_5
AL2 AG24 MR66 10K 1: No slave VIP host port devices reporting presence during reset (use for
DVPDATA_6 RSVD_1 configurations without video-in)
AL1 DVPDATA_7 RSVD_2 AH24
AM3 AK24 R67 10K HSYNC_DAC1 HSYNC_DAC1 {3,15} AMD Internal Use Only - Reserved (HDMI_EN =1 )
DVPDATA_8 RSVD_3 MR67 10K
AM2 DVPDATA_9 RSVD_4 AK26
AN2 DVPDATA_10 RSVD_5 AL24
AP3 RESERVED AL26 DNI R68 10K PSYNC VGA DISABLE : 1 for disable (set to 0 for normal operation)
DVPDATA_11 RSVD_6 MR68 10K
AR3 DVPDATA_12 RSVD_7 AG7
AN4 AJ6 +3.3V
DVPDATA_13 RSVD_8
AR4 DVPDATA_14
AP4 AG18 DNI R69 10K GPIO21_BB_EN AMD Internal Use Only - Reserved (Default: 0)
DVPDATA_15 NC_1 MR69 10K
AN5 DVPDATA_16 NC_2 AH18
C AR5 No Connect AM34 C
DVPDATA_17 NC_3 DNI R70 10K VID_0 AMD Internal Use Only - Reserved (Default: 0)
AP5 DVPDATA_18 NC_DRM_0 AF3
AP6 AG9 R38 R39 MR70 10K
DVPDATA_19 NC_DRM_1 GND_PCIE_PVSS 4.7K 4.7K
AR6 DVPDATA_20 NC_FAN_TACH AK14
AN7 AK29 DNI R71 10K VID_1 MSI_DIS (Default: 0)
DVPDATA_21 NC_AC_BATT MR71 10K
AP7 DVPDATA_22 NC_SMBCLK AK34 SMBCLK {1}
AR7 DVPDATA_23 NC_SMBDATA AK35 SMBDATA {1} DNI R72 10K VID_2 AMD Internal Use Only - Reserved (Default: 0)
MR72 10K
RV635 XT A11
BUO R73 10K VID_3 BIF_AUDIO_EN
MR73 10K 0 - Disable HD Audio 1- Enable HD Audio (Default 1 for RV635)

DNI R74 10K VID_4 AMD Internal Use Only - Reserved (Default: 0)
MR74 10K

DNI R75 10K VID_5 64BAR_EN_A (Default: 0)

MR75 10K

DNI R76 10K VID_6 AMD Internal Use Only - Reserved (Default: 0)
MR76 10K

DNI R77 10K VID_7 AMD Internal Use Only - Reserved (Default: 0)
MR77 10K

R78 10K VSYNC_DAC2 VSYNC_DAC2 {3,16} MEMORY CONFIG ATI Board Feature I
MR78 10K [V2SYNC: GPIO_18_HDP3]
Quimonda [0:0]
R88 10K GPIO_18_HPD3 Hynix [0:1]
MR88 10K Samsung [1:0]

DNI R79 10K HSYNC_DAC2 HSYNC_DAC2 {3,16}

MR79 10K AMD Internal Use Only - Reserved Default: 0

BIF_CLK_PM_EN
DNI R60 10K DVALID 0 - Disable CLKREQ# power management capability
MR60 10K 1 - Enable CLKREQ# power management capability
B B
R87 10K GPIO_16
DNI MR87 10K

+3.3V

R46
Place close to ASIC 10K

GPIO_8 R37 33R GPIO_8_R

U2
GPIO_9 R47 33R GPIO_9_R 5 2 BIOS1
D Q
GPIO_10 R48 33R GPIO_10_R 6 C BIOS
GPIO_22 R49 33R GPIO_22_R 1
+3.3V S
+3.3V 7 113-B381XX-XXX
HOLD
3 VIDEO BIOS
R45 W FIRMWARE
10K 8 4
VCC VSS
M25P05-AVNM6P
C47
A MR45 100nF_6.3V A
10K

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 7
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - ASIC DVO & GPIOs 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

CHANNEL A: 128MB/256MB DDR2

{5} DQA_[63..0]

D D

{5} MAA_BA[2..0]
U201 U202 U203 U204
MAA_BA0 L2 B9 DQA_3 MAA_BA0 L2 B9 DQA_18 MAA_BA0 L2 B9 DQA_34 MAA_BA0 L2 B9 DQA_61
MAA_BA1 BA0 DQ15 DQA_5 MAA_BA1 BA0 DQ15 DQA_23 MAA_BA1 BA0 DQ15 DQA_38 MAA_BA1 BA0 DQ15 DQA_57
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
MAA_BA2 L1 D9 DQA_0 MAA_BA2 L1 D9 DQA_16 MAA_BA2 L1 D9 DQA_33 MAA_BA2 L1 D9 DQA_60
{5} MAA_[12..0] BA2 DQ13 BA2 DQ13 BA2 DQ13 BA2 DQ13
D1 DQA_4 D1 DQA_19 D1 DQA_37 D1 DQA_59
MAA_12 DQ12 DQA_7 MAA_12 DQ12 DQA_22 MAA_12 DQ12 DQA_39 MAA_12 DQ12 DQA_56
R2 A12 DQ11 D3 R2 A12 DQ11 D3 R2 A12 DQ11 D3 R2 A12 DQ11 D3
MAA_11 P7 D7 DQA_1 MAA_11 P7 D7 DQA_17 MAA_11 P7 D7 DQA_32 MAA_11 P7 D7 DQA_63
MAA_10 A11 DQ10 DQA_6 MAA_10 A11 DQ10 DQA_21 MAA_10 A11 DQ10 DQA_36 MAA_10 A11 DQ10 DQA_58
M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2
MAA_9 P3 C8 DQA_2 MAA_9 P3 C8 DQA_20 MAA_9 P3 C8 DQA_35 MAA_9 P3 C8 DQA_62
MAA_8 A9 DQ8 DQA_27 MAA_8 A9 DQ8 DQA_12 MAA_8 A9 DQ8 DQA_43 MAA_8 A9 DQ8 DQA_52
P8 A8 DQ7 F9 P8 A8 DQ7 F9 P8 A8 DQ7 F9 P8 A8 DQ7 F9
MAA_7 P2 F1 DQA_28 MAA_7 P2 F1 DQA_11 MAA_7 P2 F1 DQA_45 MAA_7 P2 F1 DQA_51
MAA_6 A7 DQ6 DQA_26 MAA_6 A7 DQ6 DQA_15 MAA_6 A7 DQ6 DQA_41 MAA_6 A7 DQ6 DQA_55
N7 A6 DQ5 H9 N7 A6 DQ5 H9 N7 A6 DQ5 H9 N7 A6 DQ5 H9
MAA_5 N3 H1 DQA_31 MAA_5 N3 H1 DQA_9 MAA_5 N3 H1 DQA_47 MAA_5 N3 H1 DQA_50
MAA_4 A5 DQ4 DQA_30 MAA_4 A5 DQ4 DQA_8 MAA_4 A5 DQ4 DQA_46 MAA_4 A5 DQ4 DQA_48
N8 A4 DQ3 H3 N8 A4 DQ3 H3 N8 A4 DQ3 H3 N8 A4 DQ3 H3
MAA_3 N2 H7 DQA_24 MAA_3 N2 H7 DQA_14 MAA_3 N2 H7 DQA_42 MAA_3 N2 H7 DQA_54
MAA_2 A3 DQ2 DQA_29 MAA_2 A3 DQ2 DQA_10 MAA_2 A3 DQ2 DQA_44 MAA_2 A3 DQ2 DQA_49
M7 A2 DQ1 G2 M7 A2 DQ1 G2 M7 A2 DQ1 G2 M7 A2 DQ1 G2
MAA_1 M3 G8 DQA_25 MAA_1 M3 G8 DQA_13 MAA_1 M3 G8 DQA_40 MAA_1 M3 G8 DQA_53
MAA_0 A1 DQ0 MAA_0 A1 DQ0 MAA_0 A1 DQ0 MAA_0 A1 DQ0
M8 A0 M8 A0 M8 A0 M8 A0

VDDQ1 A9 +MVDD VDDQ1 A9 +MVDD VDDQ1 A9 +MVDD VDDQ1 A9

{5} CLKA0b K8 CK VDDQ2 C1 {5} CLKA0b K8 CK VDDQ2 C1 {5} CLKA1b K8 CK VDDQ2 C1 {5} CLKA1b K8 CK VDDQ2 C1
{5} CLKA0 J8 CK VDDQ3 C3 {5} CLKA0 J8 CK VDDQ3 C3 {5} CLKA1 J8 CK VDDQ3 C3 {5} CLKA1 J8 CK VDDQ3 C3
VDDQ4 C7 VDDQ4 C7 VDDQ4 C7 VDDQ4 C7
{5} CKEA0 K2 CKE VDDQ5 C9 {5} CKEA0 K2 CKE VDDQ5 C9 {5} CKEA1 K2 CKE VDDQ5 C9 {5} CKEA1 K2 CKE VDDQ5 C9
VDDQ6 E9 VDDQ6 E9 VDDQ6 E9 VDDQ6 E9
VDDQ7 G1 VDDQ7 G1 VDDQ7 G1 VDDQ7 G1
{5} CSA0b_0 L8 CS VDDQ8 G3 {5} CSA0b_0 L8 CS VDDQ8 G3 {5} CSA1b_0 L8 CS VDDQ8 G3 {5} CSA1b_0 L8 CS VDDQ8 G3
VDDQ9 G7 VDDQ9 G7 VDDQ9 G7 VDDQ9 G7
{5} WEA0b K3 WE VDDQ10 G9 {5} WEA0b K3 WE VDDQ10 G9 {5} WEA1b K3 WE VDDQ10 G9 {5} WEA1b K3 WE VDDQ10 G9

{5} RASA0b K7 RAS VDD1 A1 +MVDD {5} RASA0b K7 RAS VDD1 A1 +MVDD {5} RASA1b K7 RAS VDD1 A1 +MVDD {5} RASA1b K7 RAS VDD1 A1
VDD2 E1 VDD2 E1 VDD2 E1 VDD2 E1
{5} CASA0b L7 CAS VDD3 J9 {5} CASA0b L7 CAS VDD3 J9 {5} CASA1b L7 CAS VDD3 J9 {5} CASA1b L7 CAS VDD3 J9
M9 B201 M9 B202 M9 B203 M9 B204
DQMAb_3 VDD4 220R_200mA DQMAb_1 VDD4 220R_200mA DQMAb_5 VDD4 220R_200mA DQMAb_6 VDD4 220R_200mA
F3 LDM VDD5 R1 F3 LDM VDD5 R1 F3 LDM VDD5 R1 F3 LDM VDD5 R1
C DQMAb_0 B3 DQMAb_2 B3 DQMAb_4 B3 DQMAb_7 B3 C
UDM UDM UDM UDM
VDDL J1 VDDL J1 VDDL J1 VDDL J1
VSSDL J7 VSSDL J7 VSSDL J7 VSSDL J7
{5} ODTA0 K9 ODT {5} ODTA0 K9 ODT {5} ODTA0 K9 ODT {5} ODTA0 K9 ODT
C200 C201 C203 C204 C206 C207 C209 C210
100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V
QSA_3 F7 QSA_1 F7 QSA_5 F7 QSA_6 F7 +MVDD
VREF_A0 LDQS VREF_A0 LDQS VREF_A1 LDQS VREF_A1 LDQS
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
+MVDD B2 +MVDD B2 +MVDD B2 +MVDD B2
VSSQ2 VSSQ2 VSSQ2 VSSQ2
VSSQ3 B8 VSSQ3 B8 VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2 VSSQ4 D2 VSSQ4 D2
QSA_0 B7 D8 QSA_2 B7 D8 QSA_4 B7 D8 QSA_7 B7 D8
R201 VREF_A0 UDQS VSSQ5 R203 VREF_A0 UDQS VSSQ5 R205 VREF_A1 UDQS VSSQ5 R207 VREF_A1 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
4.99K F2 4.99K F2 4.99K F2 4.99K F2
VSSQ7 VSSQ7 VSSQ7 VSSQ7
VSSQ8 F8 VSSQ8 F8 VSSQ8 F8 VSSQ8 F8
VREF_U201 J2 H2 VREF_U202 J2 H2 VREF_U203 J2 H2 VREF_U204 J2 H2
VREF VSSQ9 VREF VSSQ9 VREF VSSQ9 VREF VSSQ9
VSSQ10 H8 VSSQ10 H8 VSSQ10 H8 VSSQ10 H8
+MVDD
R202 C202 A2 A3 R204 C205 A2 A3 R206 C208 A2 A3 R208 C211 A2 A3
4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1
E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

23BC2347SC25 23BC2347SC25 23BC2347SC25 23BC2347SC25

{5} DQMAb_[7..0] {5} QSA_[7..0]

DQMAb_0 QSA_0
DQMAb_1 QSA_1
B B
DQMAb_2 QSA_2
DQMAb_3 QSA_3
DQMAb_4 QSA_4
DQMAb_5 QSA_5
DQMAb_6 QSA_6
DQMAb_7 QSA_7

+MVDD +MVDD

C239 C240 C241 C242 C243 C236 C237 C238

1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V

+MVDD +MVDD
+MVDD {5} CLKA0
R221
A C228 C229 C230 C220 C221 C222 56R A
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V C212 C213 C214 C244 10nF +MVDD +MVDD
1uF_6.3V 1uF_6.3V 1uF_6.3V
R222
56R
{5} CLKA0b R209 R219
+MVDD +MVDD 4.99K 4.99K
+MVDD CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
VREF_A0 VREF_A1 ?2007 Advanced Micro Devices Advanced Micro Devices Inc.
{5} CLKA1 This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
C231 C232 C233 C234 C235 C223 C224 C225 C226 C227 R223 with AMD for evaluation purposes. Further distribution or disclosure
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V C215 C216 C217 C218 C219 56R R210 R220 is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V C245 10nF 4.99K 4.99K other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
R224 any implied warranty of merchantibility or fitness for a particular
0
56R purpose, and disclaims responsibility forany consequences resulting Sheet 8
from use of the information included herein. of 21
{5} CLKA1b
Title Doc No.
RV635 DDR2 - MEM CH A 105-B381xx-00A
5 4 3 2 1
 5 4 3 2 1

CHANNEL B: 128MB/256MB DDR2

{5} DQB_[63..0]

{5} MAB_BA[2..0]
U301 U302 U303 U304
MAB_BA0 L2 B9 DQB_3 MAB_BA0 L2 B9 DQB_23 MAB_BA0 L2 B9 DQB_34 MAB_BA0 L2 B9 DQB_60
MAB_BA1 BA0 DQ15 DQB_5 MAB_BA1 BA0 DQ15 DQB_17 MAB_BA1 BA0 DQ15 DQB_38 MAB_BA1 BA0 DQ15 DQB_57
D
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 D
MAB_BA2 L1 D9 DQB_0 MAB_BA2 L1 D9 DQB_21 MAB_BA2 L1 D9 DQB_33 MAB_BA2 L1 D9 DQB_61
{5} MAB_[12..0] BA2 DQ13 BA2 DQ13 BA2 DQ13 BA2 DQ13
D1 DQB_4 D1 DQB_16 D1 DQB_37 D1 DQB_59
MAB_12 DQ12 DQB_7 MAB_12 DQ12 DQB_18 MAB_12 DQ12 DQB_39 MAB_12 DQ12 DQB_56
R2 A12 DQ11 D3 R2 A12 DQ11 D3 R2 A12 DQ11 D3 R2 A12 DQ11 D3
MAB_11 P7 D7 DQB_1 MAB_11 P7 D7 DQB_22 MAB_11 P7 D7 DQB_32 MAB_11 P7 D7 DQB_62
MAB_10 A11 DQ10 DQB_6 MAB_10 A11 DQ10 DQB_19 MAB_10 A11 DQ10 DQB_36 MAB_10 A11 DQ10 DQB_58
M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2 M2 A10/AP DQ9 C2
MAB_9 P3 C8 DQB_2 MAB_9 P3 C8 DQB_20 MAB_9 P3 C8 DQB_35 MAB_9 P3 C8 DQB_63
MAB_8 A9 DQ8 DQB_27 MAB_8 A9 DQ8 DQB_12 MAB_8 A9 DQ8 DQB_43 MAB_8 A9 DQ8 DQB_53
P8 A8 DQ7 F9 P8 A8 DQ7 F9 P8 A8 DQ7 F9 P8 A8 DQ7 F9
MAB_7 P2 F1 DQB_28 MAB_7 P2 F1 DQB_11 MAB_7 P2 F1 DQB_46 MAB_7 P2 F1 DQB_51
MAB_6 A7 DQ6 DQB_26 MAB_6 A7 DQ6 DQB_15 MAB_6 A7 DQ6 DQB_40 MAB_6 A7 DQ6 DQB_54
N7 A6 DQ5 H9 N7 A6 DQ5 H9 N7 A6 DQ5 H9 N7 A6 DQ5 H9
MAB_5 N3 H1 DQB_31 MAB_5 N3 H1 DQB_9 MAB_5 N3 H1 DQB_47 MAB_5 N3 H1 DQB_50
MAB_4 A5 DQ4 DQB_30 MAB_4 A5 DQ4 DQB_8 MAB_4 A5 DQ4 DQB_44 MAB_4 A5 DQ4 DQB_48
N8 A4 DQ3 H3 N8 A4 DQ3 H3 N8 A4 DQ3 H3 N8 A4 DQ3 H3
MAB_3 N2 H7 DQB_24 MAB_3 N2 H7 DQB_13 MAB_3 N2 H7 DQB_41 MAB_3 N2 H7 DQB_55
MAB_2 A3 DQ2 DQB_29 MAB_2 A3 DQ2 DQB_10 MAB_2 A3 DQ2 DQB_45 MAB_2 A3 DQ2 DQB_49
M7 A2 DQ1 G2 M7 A2 DQ1 G2 M7 A2 DQ1 G2 M7 A2 DQ1 G2
MAB_1 M3 G8 DQB_25 MAB_1 M3 G8 DQB_14 MAB_1 M3 G8 DQB_42 MAB_1 M3 G8 DQB_52
MAB_0 A1 DQ0 MAB_0 A1 DQ0 MAB_0 A1 DQ0 MAB_0 A1 DQ0
M8 A0 M8 A0 M8 A0 M8 A0

VDDQ1 A9 +MVDD VDDQ1 A9 +MVDD VDDQ1 A9 +MVDD VDDQ1 A9 +MVDD

{5} CLKB0b K8 CK VDDQ2 C1 {5} CLKB0b K8 CK VDDQ2 C1 {5} CLKB1b K8 CK VDDQ2 C1 {5} CLKB1b K8 CK VDDQ2 C1
{5} CLKB0 J8 CK VDDQ3 C3 {5} CLKB0 J8 CK VDDQ3 C3 {5} CLKB1 J8 CK VDDQ3 C3 {5} CLKB1 J8 CK VDDQ3 C3
VDDQ4 C7 VDDQ4 C7 VDDQ4 C7 VDDQ4 C7
{5} CKEB0 K2 CKE VDDQ5 C9 {5} CKEB0 K2 CKE VDDQ5 C9 {5} CKEB1 K2 CKE VDDQ5 C9 {5} CKEB1 K2 CKE VDDQ5 C9
VDDQ6 E9 VDDQ6 E9 VDDQ6 E9 VDDQ6 E9
VDDQ7 G1 VDDQ7 G1 VDDQ7 G1 VDDQ7 G1
{5} CSB0b_0 L8 CS VDDQ8 G3 {5} CSB0b_0 L8 CS VDDQ8 G3 {5} CSB1b_0 L8 CS VDDQ8 G3 {5} CSB1b_0 L8 CS VDDQ8 G3
VDDQ9 G7 VDDQ9 G7 VDDQ9 G7 VDDQ9 G7
{5} WEB0b K3 WE VDDQ10 G9 {5} WEB0b K3 WE VDDQ10 G9 {5} WEB1b K3 WE VDDQ10 G9 {5} WEB1b K3 WE VDDQ10 G9

{5} RASB0b K7 RAS VDD1 A1 +MVDD {5} RASB0b K7 RAS VDD1 A1 +MVDD {5} RASB1b K7 RAS VDD1 A1 +MVDD {5} RASB1b K7 RAS VDD1 A1 +MVDD
VDD2 E1 VDD2 E1 VDD2 E1 VDD2 E1
{5} CASB0b L7 CAS VDD3 J9 {5} CASB0b L7 CAS VDD3 J9 {5} CASB1b L7 CAS VDD3 J9 {5} CASB1b L7 CAS VDD3 J9
M9 B301 M9 B302 M9 B303 M9 B304
DQMBb_3 VDD4 220R_200mA DQMBb_1 VDD4 220R_200mA DQMBb_5 VDD4 220R_200mA DQMBb_6 VDD4 220R_200mA
F3 LDM VDD5 R1 F3 LDM VDD5 R1 F3 LDM VDD5 R1 F3 LDM VDD5 R1
DQMBb_0 B3 DQMBb_2 B3 DQMBb_4 B3 DQMBb_7 B3
UDM UDM UDM UDM
VDDL J1 VDDL J1 VDDL J1 VDDL J1
VSSDL J7 VSSDL J7 VSSDL J7 VSSDL J7
{5} ODTB0 K9 ODT {5} ODTB0 K9 ODT {5} ODTB0 K9 ODT {5} ODTB0 K9 ODT
C300 C301 C303 C304 C306 C307 C309 C310
C 100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V 100nF_6.3V 1uF_6.3V C
QSB_3 F7 QSB_1 F7 QSB_5 F7 QSB_6 F7
VREF_B0 LDQS VREF_B0 LDQS VREF_B1 LDQS VREF_B1 LDQS
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
+MVDD B2 +MVDD B2 +MVDD B2 +MVDD B2
VSSQ2 VSSQ2 VSSQ2 VSSQ2
VSSQ3 B8 VSSQ3 B8 VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2 VSSQ4 D2 VSSQ4 D2
QSB_0 B7 D8 QSB_2 B7 D8 QSB_4 B7 D8 QSB_7 B7 D8
R301 VREF_B0 UDQS VSSQ5 R303 VREF_B0 UDQS VSSQ5 R305 VREF_B1 UDQS VSSQ5 R307 VREF_B1 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
4.99K F2 4.99K F2 4.99K F2 4.99K F2
VSSQ7 VSSQ7 VSSQ7 VSSQ7
VSSQ8 F8 VSSQ8 F8 VSSQ8 F8 VSSQ8 F8
VREF_U301 J2 H2 VREF_U302 J2 H2 VREF_U303 J2 H2 VREF_U304 J2 H2
VREF VSSQ9 VREF VSSQ9 VREF VSSQ9 VREF VSSQ9
VSSQ10 H8 VSSQ10 H8 VSSQ10 H8 VSSQ10 H8

R302 C302 A2 A3 R304 C305 A2 A3 R306 C308 A2 A3 R308 C587 A2 A3

4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1 4.99K 100nF_6.3V NC#A2 VSS1
E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3 E2 NC#E2 VSS2 E3
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

23BC2347SC25 23BC2347SC25 23BC2347SC25 23BC2347SC25

{5} DQMBb_[7..0] {5} QSB_[7..0]

B B
DQMBb_0 QSB_0
DQMBb_1 QSB_1
DQMBb_2 QSB_2
DQMBb_3 QSB_3
DQMBb_4 QSB_4
DQMBb_5 QSB_5
DQMBb_6 QSB_6
DQMBb_7 QSB_7

+MVDD +MVDD

C339 C340 C341 C342 C343 C336 C337 C338

1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V

+MVDD
+MVDD +MVDD {5} CLKB0
R321
A C312 C313 C314 56R A
1uF_6.3V 1uF_6.3V 1uF_6.3V C320 C321 C322 C328 C329 C330 C344 10nF +MVDD +MVDD
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V
R322
56R
{5} CLKB0b R309 R319
4.99K 4.99K
+MVDD +MVDD +MVDD CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.
VREF_B0 VREF_B1 ?2007 Advanced Micro Devices Advanced Micro Devices Inc.
{5} CLKB1 This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
R323 with AMD for evaluation purposes. Further distribution or disclosure
C315 C316 C317 C318 C319 C323 C324 C325 C326 C327 C331 C332 C333 C334 C335 56R R310 R320 is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V 1uF_6.3V C345 10nF 4.99K 4.99K other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
R324 any implied warranty of merchantibility or fitness for a particular
0
56R purpose, and disclaims responsibility forany consequences resulting Sheet 9
from use of the information included herein. of 21
{5} CLKB1b
Title Doc No.
RV635 DDR2 - MEM CH B 105-B381xx-00A
5 4 3 2 1
 8 7 6 5 4 3 2 1

CORE REGULATOR VDDC

+12V_BUS +12V_BUS
D D

EB1 EB2
Chock 1.2u Chock 1.2u

1
+

+
+12V_BUS EC1706 EC1151 EC1150 EC1148 EC1147 EC1705
CD680u16EL12.5-RH 10uF 10uF 10uF 10uF CD680u16EL12.5-RH

2
ER1600
2R2
ER1603 ER1602
+PW_VDDC3 +PW_VDDC3

3K 3K

ED28
BAT54SLT1 ER1688
EC1688 100nF

D
EQ28 EQ30 +VDDC +1.1V
G G
0R
APM2512 TO-252 APM2512 TO-252

S
BOOT_VDDC3
U-Gate EB61
60R
C C

EL63

1
Dip 1.6u

+
EC1532 EC1149 EC1146 EC1153 EC1154 EC1155
L-Gate

2
1.0uF 10uF 10uF C820u2.5SO-RH C820u2.5SO-RH C820u2.5SO-RH

EC1158
1nf

D
EC1692 EQ29 EQ31 EQ32 DNI
+12V_BUS +3.3V_BUS G G G ER1592
1uF 348R
APM2512 TO-252 APM2512 TO-252 APM2512 TO-252 ER1617 1%

S
1.5K
DNI
ER1599 ER1686
1M Fb_VDDC3
1K
EMU43
ER1598 51K 1 14
+PW_VDDC3 RT VCC ER1597
2 OCSET PVCC 13
SS_VDDC3 3 12 1K
COMP_VDDC3 SS LGATE 1%
4 COMP PGND 11
Fb_VDDC3 5 10 BOOT_VDDC3 ER1618 EC1159
FB BOOT 2.2R 1nF
6 EN UGATE 9
7 GND PHASE 8

9232
EC1157
22nf

B B

+VDDC=0.8*( 1+( ER1592 / ER1597 ))

Compensation Circuit
COMP_VDDC3

EC1163
33pF
EC1161
10nF

Fb_VDDC3
ER1580
15K

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 10 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - VDDC SMPS 01 105-B381xx-00A
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D
+3.3V
+3.3V

C1011 C1012 C1013 C1015 C1026

100pF 100pF 100pF 100pF 100pF
C995 C996 C997 C999 C1000
10uf 10uf 10uf 10uf 10uf

+3.3V
+3.3V

C1016 C1017 C1018 C1033 C1028

C1029 C1030 C1031 C1032 C1027 10nF 10nF 10nF 10nF 10nF
1000 pF 1000 pF 1000 pF 1000 pF 1000 pF

C C

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 11 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - VDDC SMPS 02 105-B381xx-00A
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

+12V_BUS

D D

ER1595
+12V_BUS
2R2

ED2 ER1801
BAT54SLT1
DNI EB16
Chock 1.2u

EC1801

+1
DNI
EC108 +MVDDC=0.8*( 1+( ER12 / ER13))
CD470u16EL11.5 EC182 EC181

2
EC124 ER1596 10uF 10uF

0.1uF 0R

D
EQ36
ER307 G

0R APM2512 TO-252

S
EMU42 +MVDD
1 BOOT PHASE 8
2 7 EL64
UGATE OPS ER10 Dip 1.6uH
3 GND FB 6
4 LGATE VCC 5

APW7120 19K

1
ER308 EQ37 C1034 C1035 C1036 C1037

+
G EC164 EC159 EC169 EC346 EC347 EC348 EC349 EC350 EC184 100pF 100pF 100pF 100pF
10uF 10uF 10uF 10uf 10uf 10uf 10uf 10uf CD1000u63EL11.5-RH-1

2
0R APM2512 TO-252

S
ER20
DNI
ER12
C C
+12V_BUS
1.87K C1038 C1039 C1040 C1041
ER13 1000pF 1000pF 1000pF 1000pF
EC7 ER11
EC168 1.2K
0.1uF
0.1uF 200RF
ER21
DNI
C1042 C1043 C1044 C1045
10nF 10nF 10nF 10nF
EC1693
DNI
EC1694
DNI
+VDDC +12V_BUS

ER15 ER14
1K 10K
D

EQ106
G

2N7002
S
3

1 Q992
MMBT3904
2

Memory Power Delay

B ER16 B
2K

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 12 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - MVDD SMPS 01 105-B381xx-00A
8 7 6 5 4 3 2 1
 5 4 3 2 1

Power up Sequencing

D D

+5V

+VDDC +12V_BUS
30ohm
R845
LDO_EN LDO_EN {14}
R843
3

C 5.1K C
R841 5% R844 5.1K 1 Q841
1K 5% MMBT3904
2
3

1 Q840
MMBT3904
2

C841
1uF_6.3V

+3.3V_BUS +3.3V
Q995
4

APM2054NVC
+12V_BUS 2 3
1

C842 R840
+

10uF_1206 100K_1206 C994 C993

R848 0.1uf C47u6.3TN3216
2

100K R849
510K

LVT_EN {3}
3

B B

1 Q844
+1.8V
3

MMBT3904
2

R847 10K 1 Q843 C843

MMBT3904 100NF
C844 402
2

1uF_6.3V X5R
16V

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 13
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - Power Management 105-B381xx-00A
5 4 3 2 1
 8 7 6 5 4 3 2 1

+3.3V_BUS +2.5V_REF

ER124
15R

Optional regulator for +1.1V

Vout = 1.1V
Y
D EC109 D
X EREG9 10uF_6.3V
DNI
.APL431BAC-TRL_SOT23-3-RH +MVDD +1.1V
Z

U951_VIN U951_VOUT U951

U951_VIN 1 8
+2.5V_REF VIN NC#8
2 GND NC#7 7
U951_REFEN 3 6 U951_VCNTL
VREF VCNTL LDO_EN {13}
U951_VOUT 4 5
R951 VOUT NC
THM 9
1.27K
C958 C957 C956 U951_REFEN R953 C953 C952 C951 APL5331
1uF_6.3V 10uF 10uF 1K 22uF 10uF 10uF
R952
1K C954
1uF_6.3V

+MVDD

C
Optional regulator for +1.8V C
+1.8V
Vout = 1.8V
EB62
60R

+3.3V_BUS

U952_VIN U952_VOUT U952

U952_VIN 1 8
+2.5V_REF VIN NC#8
2 GND NC#7 7
U952_REFEN 3 6 U952_VCNTL
VREF VCNTL LDO_EN {13}
U952_VOUT 4 5
R956 VOUT NC
THM 9
383R
C962 C964 C963 U952_REFEN R955 C959 C955 C961 C965 APL5331
1uF 10uF 10uF 1K 22uF_6.3V 10uF 10uF 10uF
R954
1K C960
1uF_6.3V

B B

+12V_BUS +5V
4

U4
4
ADJ/GND

3 VIN VOUT 2

RC1117S_SOT223 ER304
1

121 EC135 EC134

EC133 I31-01117F9-A30 10uF 10uF
10uF R11-1210T13-W08

ER305
365

R11-3650T13-Y01

Vout=1.25V* [1+(ER305/ER304) ]

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

8 7
?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 14 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - Linear Regulators 105-B381xx-00A
6 5 4 3 2 1
 8 7 6 5 4 3 2 1

+5V
See BOM for qualified filters
L1001 A_R_DAC1_M L1004 +3.3V +3.3V +3.3V
{3} A_DAC1_R 47nH 36NH
R1001 C1004 BAT54SLT1 BAT54SLT1 BAT54SLT1
75R 8.0pF C1001 ED62 ED63 ED64 EF1
12pF_50V
R1027 37.4R +5V_VESA 1.5A
{3} A_DAC1_RB

L1002 A_G_DAC1_M L1005

{3} A_DAC1_G 47nH 36NH
R1002 C1005
75R 8.0pF C1002 MJ1001
12pF_50V A_R_DAC1_F 1
D R1028 37.4R A_G_DAC1_F R D
{3} A_DAC1_GB 2 G
A_B_DAC1_F 3 B
11 MS0
DDCDATA_DAC1_R 12 DDC2_MONID0
L1003 A_B_DAC1_M L1006 MS1 DDC2_MONID1(SDA)
{3} A_DAC1_B 4 MS2
47nH 36NH DDCCLK_DAC1_R 15 DDC2_MONID2
R1003 C1006 MS3
9 DDC2_MONID3(SCL)
8.0pF C1003 HSYNC_DAC1_R NC
75R 13 HS
12pF_50V VSYNC_DAC1_R 14
R1029 37.4R VS
{3} A_DAC1_BB 5 VSS
6 VSS#6
7 VSS#7
C1010 8
Pseudo differential RGB should be routed from the ASIC to the display 104pF VSS#8
10 VSS#10
connector without switching reference plane or running over split plane. +5V +5V +5V +5V 16 CASE
17 CASE#17
G3179C219-005

ED71 ED70 ED69 ED68

BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1

+3.3V +5V
1

R1004 R1005 DB15 pin Standard VGA DDC1 Host DDC2B or DDC2AB Host DDC1/2 Display
10K 2.2K DDC2B+ Host
2 3 DDCDATA_DAC1_5V R1006 33R DDCDATA_DAC1_R 11 Monitor ID bit 0
Monitor ID bit 0 Monitor ID bit 0 Monitor ID bit 0 Optional
{3} CRT1DDCDATA Monitor ID bit 1
BSH111 12 Data from display SDA SDA SDA
Q1001 4 Monitor ID bit 2
Monitor ID bit 2 Monitor ID bit 2 Monitor ID bit 2 Optional
C +3.3V +5V 15 Monitor ID bit 3
Open SCL SCL SCL C
+5V +5V +5V
9 N/C 50mA min 50mA min 300mA min Optional
1

R1007 R1008 Mechanical Key 1A max 1A max 1A max

10K 2.2K Hardware
2 3 DDCCLK_DAC1_5V R1009 33R DDCCLK_DAC1_R Support No Yes Yes No Yes
{3} CRT1DDCCLK
BSH111
Q1002
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

+5V
C1999
14

100nF_6.3V

2 3 HSYNC_DAC1_B R1010 10R HSYNC_DAC1_R

{3,7} HSYNC_DAC1
U1999A
SN74HCT125D
7
1 4

SN74HCT125D +5V_VESA
U1999B
5 6 VSYNC_DAC1_B R1011 10R VSYNC_DAC1_R
{3,7} VSYNC_DAC1
J1001
25 CASE
R102 100R
R1012 0R 1
{3} T2X2M TMDS Data2-
R1013 0R 2
{3} T2X2P TMDS Data2+
R104 100R 3
0R TMDS Data2/4 Shield
{3} T2X4M R1014 4
0R TMDS Data4-
{3} T2X4P R1015 5
DDCCLK_DAC1_R TMDS Data4+
6 DDC Clock
DDCDATA_DAC1_R 7
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane VSYNC_DAC1_R DDC Data
8 Analog VSYNC
R1016 0R 9
{3} T2X1M TMDS Data1-
R1017 0R 10
+3.3V {3} T2X1P TMDS Data1+
R101 100R 11
B 0R TMDS Data1/3 Shield B
{3} T2X3M R1018 12
0R TMDS Data3-
{3} T2X3P R1019 13
R103 100R TMDS Data3+
14 +5V Power

3
15 GND (for +5V)
Q1021 1 R1022 10K HPD_DVI2 16
MMBT3904 0R Hot Plug Detect
{3} T2X0M R1020 17
0R TMDS Data0-
{3} T2X0P R1021 18

2
R100 100R TMDS Data0+
{7} HPD2 19 TMDS Data0/5 Shield
R1024 0R 20
{3} T2X5M TMDS Data5-
R1025 0R 21
{3} T2X5P TMDS Data5+
R1023 R105 100R 22
10K 0R TMDS Clock Shield
{3} T2XCP R1026 23
0R TMDS Clock+
{3} T2XCM R1031 24
R106 100R TMDS Clock-
A_R_DAC1_F C1
A_G_DAC1_F Analog Red
C2 Analog Green
A_B_DAC1_F C3
HSYNC_DAC1_R Analog Blue
C4 Analog HYNC
C5 Analog GND
C6 Analog GND#C6
26 CASE#26
27 CASE#27
28 CASE#28
29 CASE#29
30 CASE#30
DVI_CONNECTOR

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 15 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - DAC1&TMDS2 105-B381xx-00A
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

See BOM for qualified filters

+5V_VESA
L2001 A_R_DAC2_M L2004 +3.3V +3.3V +3.3V
{3} A_DAC2_R 47nH 36NH
R2001 C2004 BAT54SLT1 BAT54SLT1 BAT54SLT1
75R 8.0pF C2001 ED67 ED66 ED65
402 402 402 12pF_50V
R2027
{3} A_DAC2_RB
37.4R

L2002 A_G_DAC2_M L2005

{3} A_DAC2_G 47nH 36NH
R2002 C2005
75R 8.0pF C2002 MJ2001
D 402 402 402 12pF_50V A_R_DAC2_F D
1 R
R2028 A_G_DAC2_F 2
{3} A_DAC2_GB G
37.4R A_B_DAC2_F 3 B DDC2_MONID0
11 MS0
DDCDATA_DAC2_R 12 DDC2_MONID1(SDA)
L2003 A_B_DAC2_M L2006 MS1 DDC2_MONID2
{3} A_DAC2_B 4 MS2
47nH 36NH DDCCLK_DAC2_R 15 DDC2_MONID3(SCL)
R2003 C2006 MS3
9 NC
75R 8.0pF C2003 HSYNC_DAC2_R 13
402 402 402 12pF_50V VSYNC_DAC2_R HS
14 VS
R2029 5
{3} A_DAC2_BB VSS
37.4R 6 VSS#6
7 VSS#7
8 VSS#8
Pseudo differential RGB should be routed from the ASIC to the display 10
+5V +5V +5V +5V VSS#10
connector without switching reference plane or running over split plane. 16 CASE
17 CASE#17
G3179C219-005

+3.3V +5V ED75 ED74 ED73 ED72

BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1

1
DNI for RV635 R2004 R2005
24.3K 2.2K
2 3 402 DDCDATA_DAC2_5V R2006 33R 402 DDCDATA_DAC2_R
{3} CRT2DDCDATA
BSH111
Q2001 DB15 pin Standard VGA DDC1 Host DDC2B or DDC2AB Host DDC1/2 Display
DDC2B+ Host
R2012 Monitor ID bit 0
11 Monitor ID bit 0 Monitor ID bit 0 Monitor ID bit 0 Optional
12 Monitor ID bit 1
Data from display SDA SDA SDA
RV635: no pull up on 3.3V, 2.2K pull up on 5V 4 Monitor ID bit 2
Monitor ID bit 2 Monitor ID bit 2 Monitor ID bit 2 Optional
C 15 Monitor ID bit 3
Open SCL SCL SCL C
RV630: 24.3K pull up on 3.3V, 19.1K on 5V 0ohm
+3.3V +5V +5V +5V +5V
9 N/C 50mA min 50mA min 300mA min Optional
Mechanical Key 1A max 1A max 1A max
1

DNI for RV635 R2007 R2008 Hardware

24.3K 2.2K Support No Yes Yes No Yes
2 3 402 DDCCLK_DAC2_5V R2009 33R 402 DDCCLK_DAC2_R
{3} CRT2DDCCLK
BSH111
Q2002 Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
R2013

0ohm

9 8 HSYNC_DAC2_B R2010 10R 402 HSYNC_DAC2_R

{3,7} HSYNC_DAC2
U1999C
SN74HCT125D
13 10

SN74HCT125D
U1999D
12 11 VSYNC_DAC2_B R2011 10R 402 VSYNC_DAC2_R
{3,7} VSYNC_DAC2

+5V_VESA
J2001
25 CASE
B B
{3} T1X2M 1 TMDS Data2-
{3} T1X2P 2 TMDS Data2+
SYNC and DDC should be routed from the ASIC to the display connector without switching reference plane or running over split plane 3 TMDS Data2/4 Shield
{3} T1X4M 4 TMDS Data4-
{3} T1X4P 5 TMDS Data4+
DDCCLK_DAC2_R 6
DDCDATA_DAC2_R DDC Clock
7 DDC Data
VSYNC_DAC2_R 8 Analog VSYNC
{3} T1X1M 9 TMDS Data1-
{3} T1X1P 10 TMDS Data1+
11 TMDS Data1/3 Shield
+3.3V 12
{3} T1X3M TMDS Data3-
{3} T1X3P 13 TMDS Data3+
14 +5V Power

3
15 GND (for +5V)
Q2021 1 R2022 10K HPD_DVI1 16
MMBT3904 Hot Plug Detect
{3} T1X0M 17 TMDS Data0-
{3} T1X0P 18

2
TMDS Data0+
{3} HPD1 19 TMDS Data0/5 Shield
{3} T1X5M 20 TMDS Data5-
{3} T1X5P 21 TMDS Data5+
R2023 22
10K TMDS Clock Shield
{3} T1XCP 23 TMDS Clock+
{3} T1XCM 24 TMDS Clock-
A_R_DAC2_F C1
A_G_DAC2_F Analog Red
C2 Analog Green
A_B_DAC2_F C3
HSYNC_DAC2_R Analog Blue
C4 Analog HYNC
C5 Analog GND
C6 Analog GND#C6
26 CASE#26
27 CASE#27
28 CASE#28
29 CASE#29
30 CASE#30
A DVI_CONNECTOR A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
0
any implied warranty of merchantibility or fitness for a particular
purpose, and disclaims responsibility forany consequences resulting Sheet 16 of 21
from use of the information included herein.
Title Doc No.
RV635 DDR2 - DAC2/TMDS1 105-B381xx-00A
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

L3001 470nH_250mA
{3} A_DAC2_Y DAC2_Y_F

R3001 C3001 C3004

75R 47pF_50V 47pF_50V

L3002 470nH_250mA
{3} A_DAC2_C DAC2_C_F

R3002 C3002 C3005

75R 47pF_50V 47pF_50V

L3003 470nH_250mA
{3} A_DAC2_COMP DAC2_COMP_F

R3003 C3003 C3006

75R 47pF_50V 47pF_50V

C C

+3.3V
Place near connector TV Out
0R leaves footprint for Ferrite R3008
Beads if req'd for EMI 10K J3001
{7} GENERICA STV/HDTV#_DET R3009 0R PIN6 6 HDTV_OUT_DET#
DAC2_Y_F 3
DAC2_C_F Y-OUT
4 C-OUT
DAC2_COMP_F 7 Comp_out
5 SYNC
1 GND
2 GND#2
Rpin5 8 CASE
9 CASE#9
10 CASE#10
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

+3.3V +3.3V +3.3V

B B

ED78 ED77 ED76

BAT54SLT1 BAT54SLT1 BAT54SLT1

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 17
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - TVO 105-B381xx-00A
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

+12V_BUS
B4001

26R_600mA

D D
C4008
1uF
0805
16V

MJ4030

1
2

Header_1X3
3
2
1

MJU4003

C C

B B

H2A
H2B H2C H2D
9
10
11
12
13
14
15
16

17
18
19
20
21
22
23

25
26
27
28
29
30
31
32

RV630_FANSINK
1

3
4
5
6
7
8

RV630_FANSINK RV630_FANSINK RV630_FANSINK See BOM for qualified option.

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 18
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - Thermal Management 105-B381xx-00A
8 7 6 5 4 3 2 1
 5 4 3 2 1

DVI/DVI SCREWS with top tab

ASSY-SCREW2

SCREW
ASSY-SCREW1 JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>
SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>

ASSY-SCREW4

SCREW
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
ASSY-SCREW3 <3rd part field> DNI
D D
SCREW SK1 PCB1
JACKPOST, HEX, 3/16 AF, 4-40 INT/EXT
<3rd part field>
PCB

ASSY1 BKT1 ASSY-SCREW5 109-GN982-00A

BRACKET SCREW SOCKET_880

ANTISTATIC
SCREW, PAN HD, PHILLIPS, 4-40 X 3/16L
BAG
RV635 Socket
6_X_11 8020046100G

Need New Bracket

MT1
MT_Hole_0.136_in.

FM8
FM1 FM4 1 SW_FB
1 SW_FB 1 SW_FB

FM2 FM5
1 SW_FB 1 SW_FB

FM7
FM3 FM6 1 SW_FB
1 SW_FB 1 SW_FB

C C

J1 +MVDD J4

X_PIN1*2 X_PIN1*2

J2
+MVDD +MVDD
3 1
J5
4 2
3 1
impedence
4 2
impedence

B B

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 19
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - Mechanical 105-B381xx-00A
5 4 3 2 1
 <Variant Name> 5 4 3 2 1

Title Schematic No. Date:

RH PCIE RV635 2x256MB DDR2 DUAL DL-DVI-I DL-DVI-I VO FH 105-B381xx-00A Monday, March 24, 2008

NOTE: This schematic represents the PCB, it does not represent any specific SKU.
Rev
REVISION HISTORY For Stuffing options (component values, DNI, ? please consult the product specific BOM.
Please contact AMD representative to obtain latest BOM closest to the application desired.
0
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A ??/??/07 Initial design for RV635 GDDR3

C C

B B

A A

5 4 3 2 1
 5 4 3 2 1

MEMORY CHANNEL A & B - RANK0 MEMORY CHANNEL A & B - RANK1

DDR2 4pcs 16Mx32 (256MB) DDR2 4pcs 16Mx32 (256MB)

D D

RANK0 RANK1

TMDP
DPA AC Coupling Caps DisplayPort
Debug
Connector HPD1
Connector
POWER REGULATORS CrossFire
CrossFire DVOCLK DAC2
Interlink DVPCNTL_[0..2]
From +12V DVPDATA[23:0] CRT2 RBG Filters
Header DVP_MVP_CNTL[1:0] Slim-VGA
+VDDC (MPVDD, VDDCI), GPIO[6:3]
GENERICB, DVALID H/V2Sync Connector
+MVDD
AUX_DDC3

From +12V LINEAR:

+5V, +5V_VESA, Straps
GPIO
C
TMDP C

From +12V DIRECT: DPA AC Coupling Caps DisplayPort

FAN Connector
BIOS HPD3
ROM
From +MVDD Linear (1.1V): AUX_DDC4

PCIE_VDDC, DPLL_VDDC Thermal

DDC2
From +3.3V: XTALIN Oscillator
Direct or Linear (1.8V) Speed control
GPIO17
& temperature INTERRUPT
VDD_CT, DPLL_PVDD, XTALOUT
sense Temp. Sensing D+/D- XTAL
DPA_PVDD, DPB_PVDD, FAN
PVDD, DPA_VDDR, TS_FDO
Built-in PWM
DPB_VDDR,
T2XVDDR(LTVDD33),
VDDC(LTVDD18), AVDD,
A2VDD, A2VDDQ, VDD1DI,
VDD2DI, PCIE_VDDR, Dynamic VDDC GPIO20
TMDS2
PCIE_PVDD, VDDR3, VDDR4,
VDDR5
POWER DELIVERY DL TMDS2 Shunt Resistors
HPD2
+PCIE_SOURCE (GPIO14)
HPD2
+3.3V +12V_BUS
DAC1
B B
RV635 DVI-I &
CRT1 RBG Filters
Slim-VGA
H/VSync Connector
3.3V_BUS DDC1
5V_VESA
delayed circuit Temperature Critical
CTF

PCI-Express
SMPS Enable
Circuit

+3.3V_BUS
RH PCIE RV635 2x256MB DDR2
PCI-Express Bus
+12V_BUS
DL-DVI-I DP DP FH
REV 0

A A

CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.

?2007 Advanced Micro Devices Advanced Micro Devices Inc.
This AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement 1 Commerce Valley Drive East
with AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose Markham, Ontario
other than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
regarding this schematic and design, including, not limited to, Date: Monday, March 24, 2008 Rev
any implied warranty of merchantibility or fitness for a particular
0
purpose, and disclaims responsibility forany consequences resulting Sheet 21
from use of the information included herein. of 21
Title Doc No.
RV635 DDR2 - BLOCK DIAGRAM 105-B381xx-00A
5 4 3 2 1