Professional Documents
Culture Documents
A PROJECT REPORT
submitted by
AJITH BALAKRISHNAN
AWH15EEPE01
to
the APJ Abdul Kalam Technological University
in partial fulfillment of the requirements for the award of the Degree
of
Master of Technology
In
Power Electronics
First and foremost, I would like to invoke the grace of the Almighty, without which no fruitful
event occurs in this world.
I wish to express my sincere gratitude and thanks to Mr. Subhash Joshi T.G., Senior Engineer,
Power Electronics Group, CDAC, (TVM) for his guidance, encouragement and support during
this project.
I am grateful to my Honourable Principal Prof. Shahir V.K., for providing me with all facilities
and help for the successful completion of this project.
I owe a whole hearted sense of reverence and gratitude to Mrs. FATHIMA SAPNA P.,
Associate Professor & Head of the Department, EEE, for her constant support and
encouragement rendered to me.
I also convey my immense gratitude to my guide, Ms. MERCY THOMAS, Assistant
Professor, EEE, for her efficient and excellent guidance.
I also convey my sincere gratitude to Mr. MURALI KRISHNAN K., Assistant Professor, EEE,
for his guidance and support.
I also extend my heartfelt thanks to all the faculty members of EEE Department who have
rendered their valuable help.
Last but not the least, I thank my family and friends for their encouragement and prayers.
i
ABSTRACT
This paper presents a new single-stage single-phase solar PV based, grid connected dc-
ac boost converter with an active power injection and reactive power compensation scheme.
The single stage topology is based on a full-bridge DC-AC inverter, which uses a single circuit
for DC-DC boost conversion and DC-AC conversion. The proposed converter not only acts as
inverter, but also boosts the output voltage with respect to input. Two additional diodes and
one input inductor implement the two boost converters that share the same input inductor.
Switching strategy for this topology is similar to a conventional inverter, and in each half
cycle, boost operation is done by one of the two boost converter. For generating the sinusoidal
output voltage, a variable duty cycle is applied to the switches. A current based perturb and
observe control algorithm is used for tracking the maximum power point of the solar panel.
The active power is injected from the PV panel and the reactive power is compensated by
extracting the load current.
ii
CONTENTS
Contents Page No.
ACKNOWLEDGEMENT i
ABSTRACT ii
LIST OF TABLES iii
LIST OF FIGURES iv
ABBREVIATIONS v
Chapter 1. INTRODUCTION 1
1.1 General 1
1.2 Project Objective 2
1.3 Scope of the project work 2
1.4 Scheme of the project work 3
1.5 Conclusion 4
Chapter 2. LITERATURE SURVEY 5
2.1 Introduction 5
2.2 Literature review 5
2.2 Conclusion 12
Chapter 3. MODELING OF SOLAR PV SYSTEM 13
3.1 Introduction 13
3.2 Modeling of a solar pv module 13
3.3 Solar cell characteristics 13
3.1 Introduction 13
3.2 Modeling of a solar pv module 13
3.3 Solar cell characteristics 13
3.3.1 Effect of variation of solar irradiation 16
3.3.2 Effect of variation of temperature 17
3.4 Maximum power point tracking 18
3.4.1 Perturb and observe method 18
3.3.2 Flowchart of perturb and observe method 19
3.5 Conclusion 19
iii
Chapter 4. SINGLE STAGE DC-AC BOOST CONVERTER 20
4.1 Introduction 20
4.2 Single stage dc-ac boost converter 20
4.3Modes of operation of the proposed converter 21
4.3.1 State I [0<t<T/2] 21
4.3.2 State II [T/2<t<T] 22
4.4 Steady state analysis of the converter 23
4.5 Switching strategy 24
4.6 Design of the dc-ac boost converter 25
4.6.1 DC capacitor voltage 25
4.6.2 DC capacitor 26
4.6.3 Boost inductor 26
4.7 Conclusion 26
Chapter 5. CONTROL SCHEME FOR THE GRID CONNECTED
DC-AC BOOST CONVERTER 27
5.1 Introduction 27
5.2 Control block diagram 27
5.3 Unit vector for single-phase grid 28
5.4 Scheme for active current extraction 29
5.4.1 Expression for active current extraction 29
5.5 Scheme for reactive current extraction 30
5.5.1 Expression for active current extraction 30
5.6 Control law for the current controller 32
5.7 Scheme for duty cycle generation 33
5.8 Conclusion 33
Chapter 6. SIMULATION OF THE PROPOSED SINGLE-STAGE
GRID CONNECTED BOOST CONVERTER 34
6.1 Introduction 34
6.2 Simulation parameters 34
6.3 Simulation diagram 34
6.4 Simulation results 38
iv
6.5 Conclusion 49
Chapter 7 . HARDWARE IMPLEMENTATION 50
7.1 Introduction 50
7.2 Design of the dc-dc boost converter 50
7.3.1 Design of the boost inductor 50
7.3.2 Design of the output capacitor 51
7.3 Hardware parameters 51
7.4 Circuit diagram 52
7.5 Hardware set up 54
7.6 Description of circuit 55
7.6.1 Power supply unit 55
7.6.2 Control unit 56
7.6.3 M-board unit 58
7.6.4 DC-DC converter unit 59
7.6.5 Inverter unit 60
7.7 Working 61
7.8 Hardware results 61
7.9 Conclusion 62
Chapter 8. CONCLUSION 63
8.1 General 63
8.2 Future Works 64
REFERENCES 65
v
LIST OF TABLES
No Title Page No
vi
LIST OF FIGURES
No Title Page No
vii
6.7 Simulation diagram showing variation of with time 40
6.8 Simulation diagram showing current command generation 40
6.9 Simulation diagram showing the variation of inductor current 41
6.10 Simulation diagram showing the variation of capacitor voltage 42
6.11 Simulation diagram showing the variation of duty cycle in one
period, for T1 and T3 43
6.12 Simulation diagram showing the variation of duty cycle in one
period, for T2 and T4 43
6.13 Simulation diagram showing the variation of active current 44
6.14 Simulation diagram showing the variation of reactive current 44
6.15 Simulation diagram showing the variation of reference current 45
6.16 Simulation diagram showing the variation of converter current 45
6.17 Simulation diagram showing the variation of grid current 46
6.18 Simulation diagram showing the variation of active current and
grid current 47
6.19 Simulation diagram showing the variation of load current 47
6.20 Simulation diagram showing the converter voltage 48
6.21 Simulation diagram showing the grid voltage 48
7.1 Circuit diagram of the hardware prototype 53
7.2 Hardware prototype of the PV based multi-stage dc-ac converter 54
7.3 Solar module used at the input of dc-dc converter 55
7.4 Power supply unit (a) circuit diagram (b) Hardware prototype 56
7.5 Control unit (a) circuit diagram (b) Hardware prototype 57
7.6 M-board unit (a) circuit diagram (b) Hardware prototype 58
7.7 Converter unit (a) circuit diagram (b) Hardware prototype 59
7.8 Inverter unit (a) circuit diagram (b) Hardware prototype 60
7.7 Gate pulses of dc-dc boost converter MOSFET 61
7.8 Gate pulses of inverter MOSFET 62
viii
ABBREVIATIONS
AC Alternating Current
DC Direct Current
LCD Liquid Crystal Display
LED Light Emitting Diode
MPPT Maximum Power Point Tracking
MW Mega Watt
MOSFET Metal Oxide Semiconductor Field Effect Transistor
PLL Phase Locked Loop
PV Photo Voltaic
PWM Pulse Width Modulation
THD Total Harmonic Distortion
TTL Transistor Transistor Logic
USART Universal Synchronous Asynchronous Receiver Transmitter
NOTATIONS
I Current, A
D Duty Cycle
Fs Switching Frequency, kHz
L Inductance, mH
C Capacitance, F
V Voltage, V
ix
CHAPTER 1
INTRODUCTION
1
1.2 PROJECT OBJECTIVE
To model a new single-phase single-stage dc-ac boost converter with lesser
number of switches.
To implement control scheme for active power injection for grid interfacing of
boost converter and dc-ac inverter feeding a single phase induction motor.
2
system, a prototype single-phase single-stage grid connected solar converter with active
power injection and reactive power compensation is simulated using PSIM software.
Simulation results are presented to demonstrate the effectiveness of the proposed grid
connected system. The results validate the theoretical analyses and the practicability of the
proposed single-phase single-stage grid connected converter.
A hardware prototype with multi-stage topology using a dc-dc boost converter and a
dc-ac inverter feeding a single phase induction motor is also implemented. In the hardware
prototype, speed control of the single phase induction motor is implemented using
microcontroller based control.
3
1.5 CONCLUSION
The chapter dealt with a brief introduction of the single-stage system and its
advantages over the multi-stage system. A new single-phase single-stage dc-ac boost
converter with lesser number of switches was proposed. A control scheme for the active
power injection and reactive power compensation was also presented. The scope of the thesis
was presented and the overview of various chapters included in this thesis was also presented.
4
CHAPTER 2
LITERATURE SURVEY
2.1 INTRODUCTION
This chapter reviews the papers based on different topologies of single-stage grid
connected boost converters, solar photovoltaic (PV) systems with maximum power point
tracking (MPPT), various previous studies done on the active power injection and reactive
power compensation.
5
followed by full-bridge inverter feeding transformer with three secondary windings. It was
envisioned that a large PV field is divided into many zones, each comprising of two PV
arrays. The number of zones depended on the voltage of the grid with which it is interfaced.
The power conversion architecture consisted of an IGBT based full-bridge inverter feeding
the medium frequency transformer. The voltage at the transformer secondary was then
converted to three phase line frequency ac by full-bridge ac-ac converters. This also
eliminated the second harmonic power from the DC bus, thereby reducing the capacitor size.
A new control method was also proposed for the series connected modules during partial
shading while minimizing the switch ratings.
S. Pouresmaeil, B. Eskandari, and M. T. Bina [4], introduced an efficient modulation
technique for a conventional six pulse, three-phase dc-ac boost converter. This paper
suggested a simple formulation of pulse widths for generation of sinusoidal waveform for
boost inverter. It was observed that, despite waveform improvement, still the output was
distorted. It was also noted that even the use of PI controllers still lead to distorted output
voltage because of the non-linear structure of the converter. An optimized offset modulation
technique was defined to overcome the issues. The proposed technique led to a lower dc link
current oscillation, reduction in the dc offset produced, lower component counts and less
losses in converter. The three phase sinusoidal voltage with bigger amplitude compared to the
source voltage at different levels with different desired frequency could be produced.
Soeren Baekhoej Kjaer, John K. Pedersen, and Frede Blaabjerg [5], explained about
some of the standards that inverters for PV and grid applications must fulfil, which focused on
power quality, injection of dc currents into the grid, detection of islanding operation, and
system grounding. The role of power decoupling between the modules and the grid was also
investigated and concluded that the ripple amplitude across a PV module should never exceed
3V in order to have a utilization efficiency of 98% at full generation. A historical summary of
the string inverters was done. Also, PV module interfaced to the grid with its own dcac
inverter was investigated. It was followed with a classification of the inverters. It was
concluded that the multi string grid connected concept was a better choice. Also, it was
concluded that the preferable location for the capacitor was in the dc link, where the voltage
was high and a large fluctuation could be allowed, with the use of film capacitors instead of
electrolytic capacitors. Inverter topology with dual grounding was found suitable to mitigate
the resonance between the PV modules and inductances in the current paths.
6
T. Kerekes, R. Teodorescu and U. Borup [6], analysed and compared the most
common single-stage transformer-less PV inverter topologies for single-phase with respect to
the leakage current generation. It was found that the best results were obtained when the
middle point of the input capacitors was connected to the neutral point, thereby minimizing
the voltage fluctuations present at the terminals of the PV panel. By experimental results, it
was concluded that the single phase full-bridge topology with bipolar switching was suitable
for transformer less PV inverters, because the leakage current was much lower than in case of
the unipolar switching. The NPC was also found to be a good, due to its grounded middle
point, which minimized the voltage fluctuations present at PV panel terminals that would
generate high leakage currents through the parasitic capacitance of the PV panel.
H. Ribeiro, A. Pinto, and B. Borges [7], introduced a new dc-ac converter, merging a
dc-dc converter and an inverter in a single-stage topology. It was based on a full bridge
converter with three levels of output voltage, where two diodes and one inductor were added
in order to create a boost converter. The control system was based on a digital variable for the
voltage polarity and two hysteretic controllers: one for the grid injected current, and the other
for controlling the PV panel current. The topology was found suitable to be operated with low
PV voltages, due to high voltage gain given by the two input boosts. Also, a reduction in the
leakage inductance resulted in reduction of the dissipated power, with an increase in the
efficiency.
Hiren Patel and Vivek Agarwal [8], introduced a single-phase single-stage
transformer-less doubly grounded, PV-fed buckboost grid connected inverter. Only one,
undivided PV source and one buckboost inductor and a decoupling capacitor was used and
shared between the two half cycles, which prevented asymmetrical operation and parameter
mismatch problems. It was demonstrated that, as compared to the split PV source topology,
the proposed double grounding configuration was more effective in MPPT and array
utilization. It was observed that in the proposed topology, the maximum voltage that could be
developed on the ungrounded conductor was limited to the PV array output voltage, and
hence, not only the topology exhibited a good safety feature but also eliminated the problems
arising out of asymmetrical operation and mismatch in the components. Thus the THD and
the dc component of the injected grid current were much lower. Also, due to its inherent
nature, it could work over a wide input voltage range. The effectiveness of the proposed
inverter configuration to operate in non-uniform insolation conditions was also demonstrated.
7
Mihai Ciobotaru, Remus Teodorescu and Frede Blaabjergis [9], aimed at presenting a
single-stage converter for single-phase PV systems. Two different current controllers using PI
and PR were implemented and experimental comparison between them was made. A
complete control structure for the single-phase PV system was also presented. An incremental
conductance method was used to track the MPPT of the PV system. For grid synchronization,
a PLL based on delay structure was used. The PLL provided a unity power factor operation,
which involved synchronization of the inverter output current with the grid voltage to give a
clean sinusoidal current reference. It was demonstrated that the PR+HC controller gave better
performances then the classical PI controller for the grid current loop. The main drawbacks of
a PI controller are the steady-state error and poor harmonics rejection capability. The former
could be overcome by the PR controller itself, and the latter could be addressed by adding
selective harmonic compensator to the PR controller, which gave a very good rejection of the
dominant harmonics.
S. Ozdemir, N. Altin and I. Sefa [10], designed a single stage, three-phase, three level
neutral point clamped inverter is for grid connected solar supplied systems. The proposed
voltage source inverter was operated in current controlled mode and a PI current controller
was used for the production of switching. The inverter was operated in parallel with public
grid by using phase locked loop method. MPPT algorithm was used to generate the current
reference for the current controller. Experimental results showed that the inverter output
current was in phase with line current, and unity power factor operation was also obtained. a
very good rejection of the dominant harmonics.
Yuansheng XiongSuxiang Qian and Jianming Xu [11], designed a grid connected
inverter consisting of two boost converters for single-phase grid connected PV system. A
double loop control structure was included with an outer current loop and inner voltage loop.
The phase error between grid current and grid voltage was computed whenever the negative
zero-crossing of grid voltage was detected. Two PI controllers were used in the outer current
loop to regulate the phase of the grid reference current and to compute the reference voltage
of inner loop. The amplitude and phase of the grid connected reference current was adjusted
when the positive zero crossing of grid voltage was detected. The error between the reference
current and actual current was the input of the PI controller, and the output added to grid
voltage was used as the given voltage for the inner voltage loop. The sliding mode controller
was designed for the inner voltage loop of boost inverter. The simulated results showed that
8
the system could be realized under the condition that the PV array voltage was lower than the
amplitude of the grid voltage. Also, the grid current had good sine degree, and was also
synchronous with grid voltage. The amplitude of reference grid current was tracked with no
error.
T.I. Marisa, St. Kourtesib, L. Ekonomouc, G.P. Fotisd [12], designed a model of a
single-phase grid connected PV voltage inverter. The simulation was done using
PSCAD/EMTDC simulation package. This inverter model was used to show real and reactive
power flow. The satisfactory operation of the inverter circuit was ensured obtaining a square
wave as the output. With the introduction of a relative phase shift between the two output
voltages, it was proved that the real power was a function of the power angle d. It was also
found that the inverters performance could be improved using faster switching devices. The
operation of the inverter in this work showed the models ability to both absorb and generate
reactive power. It was shown that increasing the supply voltage at the input of the inverter,
resulted in exporting reactive power from the inverter, and the vice versa. Also, when the dc
supply was increased, the magnitude of the fundamental of the inverter output was increased
with respect to the grid voltage magnitude. The difference in voltage magnitudes lead to the
injection of reactive power by the inverter and vice versa. This ability proved to be useful if
such models were installed in houses fed from the main distribution grid, as the inverter could
compensate for some of the power needed to supply such loads at good sine degree,
synchronous with grid voltage. The amplitude of reference grid current was tracked with no
error.
P. Liengpradis and V. Kinnares [13], proposed the active power control of a single-
phase grid connected system supplying nonlinear load. The main objective was to employ the
converter acting as multifunction for single-phase grid connection. The control method
employed reference current calculation combining the required real component of the grid
current derived from required active power transfer to the grid and required harmonic current
for harmonic elimination associated with the nonlinear load. With this method, power of any
type of renewable energy could be transferred to the nonlinear load and the grid. Also, the
grid current obtained was nearly sinusoidal, the reactive power of the nonlinear load was also
compensated and the power factor was always nearly unity. The simulation results using
MATLAB/Simulink verified the correctness of operation for the proposed functions. The
9
achievement of control of active power delivery, current harmonic distortion and power factor
improvements were efficiently obtained.
Martin Gahid and Pavol Spanik [14], proposed a model of PV solar cell and module.
The model was verified by the simulation using Matlab. The influence of temperature and
solar irradiation on the PV module was investigated. A mathematical model for the PV
module was proposed to simulate this dependence on the environmental conditions. The
model was based on fundamental circuit equations of PV solar cell. The accuracy of the
model was confirmed by comparison between the Sharp NU-245(J5) 245Wp datasheet and
the simulated I-V characteristics. The influence of the temperature and the solar irradiation
was investigated. The solar irradiation influence was found to be bigger than temperature
especially when the decrease of the solar irradiation was focussed upon. The impact on the
output power was much heavier. The proposed simple model of the PV solar module was
found enough accurate and could be used for the development and simulation of a stand-alone
power system.
Sachin Jain and Vivek Agarwal [15], presented a new MPPT algorithm based on
current control for a single-stage grid connected PV system. This algorithm could predict the
approximate amplitude of the reference current waveform or power that could be derived
from the PV array with the help of an intermediate variable. A variable step size for the
change in reference amplitude during initial tracking helped in faster tracking. With variable,
large step changes in reference current, an approximate MPP was reached within a few
iteration steps, drastically reducing the tracking time as compared to conventional techniques.
It was also observed that if the reference current amplitude was greater than the array
capacity, the system got unstable. The proposed algorithm prevented that. It was also capable
of restoring stability if the system got unstable due to a sudden environmental change. The
proposed algorithm was tested on a new single-stage grid connected PV configuration. The
system was operated in a CCM to realize advantages such as low device current stress, lower
losses high efficiency and low EMI. Specific cases of the system, operating in just DCM and
DCM and their relative merits and demerits were also discussed.
Yang Jun, Lian Xiaoqin, Zhang Xiaol, Duan Zhengang and Wang Min [16], proposed
a versatile simulation model for PV array based on the DC physical model of PV module
under PSIM environment. The I-V, P-V characteristics of the PV array with different
combinations were simulated by the model, using PSIM. In addition, the model included the
10
function of MPPT using the Perturb and Observe method. It was concluded from the analysis
of simulation results that high accuracy of the model simulation could accurately reflect the
physical characteristics of the PV array, which would provide a basis for the simulation of the
power generation systems.
M. El-Habrouk, M. K. Darwish and P. Mehta [17], proposed an overview of the state
of the art techniques in reactive power compensation and active power filters. The
presentation and the subdivisions of the power system conditioners presented showed the
merits and drawbacks of each type and the technique used. The results would enable design
engineers and researchers in power quality to enable them to select the correct system for their
specific applications.
Leonardo B. G. Campanhol, Srgio A. Oliveira da Silva, Leonardo P. Sampaio and
Azauri A. O. Junior [18], proposed a single-phase, single-stage solar PV system, connected to
the utility grid by using a full bridge dc-ac converter. The proposed system had active power
injection ability from the PV panels. Simultaneously, it performed reactive power
compensation and harmonic current suppression generated by nonlinear loads. For the PV
system, MPP tracking using P&O algorithm, was implemented utilizing an equivalent electric
model proposed in the literature. The algorithm adopted to obtain the current reference of the
converter was based on the synchronous reference frame. The dynamic behaviour of the PV-
active filter system for different levels of solar radiation was also verified. The fast response
at the inverter side was also verified by means of load transients. Simulation results using
Matlab were presented to validate the proposed control strategy for active power injection,
reactive power compensation and harmonic current suppression as well as to verify the system
feasibility.
Woo-Jun Cha, Yong-Won Cho, Jung-Min Kwon [19], proposed a novel highly
efficient micro-inverter with a soft-switching step-up dcdc converter using an active clamp
circuit with a series resonant voltage doubler and a high-efficiency inverter with single-
switch-modulation inverter for single-phase grid-connected PV system. The active-clamp
circuit provided ZVS turn on, recycled the energy stored in the leakage inductance of the
transformer, and also limited the switch voltage stress by clamping the voltage stress across it.
The series resonant voltage doubler removed the reverse-recovery problem of the rectifier
diodes. To improve efficiency and reliability, only a single switch was modulated at the
switching frequency without a shoot-through problem. A modified controller was also
11
adopted to achieve fast output control. Thus, the proposed PV micro-inverter has the structure
to minimize power losses. The experimental results showed a maximum efficiency of 96.2%
for a 400-W hardware prototype.
2.3 CONCLUSION
The literature review on the single-phase grid connected solar PV systems, maximum
power point tracking for PV panel, active power injection and reactive power compensation
was presented. Also, the literatures dealing with the various control algorithms were
presented.
12
CHAPTER 3
MODELING OF SOLAR PV SYSTEM
3.1 INTRODUCTION
The most readily available renewable source of energy is the solar energy. Solar
energy can be converted into electrical energy by means of a solar cell. A single cell produces
a very small voltage. Therefore, many cells need to be connected in series or parallel
combinations to achieve the desired dc voltage or current. A group of solar cells connected in
series is called a solar module. A series and/or parallel combinations of modules form a solar
panel, and a combination of group of such panels form a solar array. Because of the non-
linear iv characteristics of the solar array, the power extracted from a PV source depends on
its operating point. For a given insolation and temperature, there exists a unique operating
point corresponding to the maximum power point of the PV array. Therefore, to extract
maximum power from the PV array, it is necessary to operate at the corresponding MPP as
insolation and temperature. This is called the electrical tracking of the maximum power point
or simply maximum power point tracking [16]. The modelling of a solar cell, solar cell
characteristics and maximum power point tracking are discussed in this chapter.
13
Fig. 3.1 Single diode model of a solar cell
The solar module characteristic equation is dependent on the number of cells in series
and number of cells in parallel. Also, it has been observed from the experimental results that
the solar cell output current variation is more dependent on the series resistance. The cell
output current is given as,
I=NpIlg-NpIos[exp{qVNs+IRsNp/AkT}-1]-V(Np/Ns)+IRs/Rsh (3.4)
14
The equivalent circuit of a solar module, with Ns number of series cells and Np number
of cells in parallel, is as shown in Fig. 3.2
.
Fig. 3.3 I-V, P-V curve of a solar cell at a given temperature and solar irradiation
15
3.3.1 Effect of variation of solar irradiation
The I-V and P-V characteristics of a solar cell are dependent on the incident solar
irradiation. As the solar irradiation increases, the solar input also increases. Both the open
circuit voltage and the short circuit current of the cell also increases as, now the electrons are
supplied with higher excitation energy, thereby increasing the electron mobility, which in turn
leads to more power being generated. Hence, for an increase in the solar irradiation level, the
power magnitude increases for the same voltage value. The I-V and P-V characteristics of a
solar cell, with the variation of irradiation, are as shown in the Fig. 3.4 and Fig. 3.5.
16
3.3.2 Effect of variation of temperature
Solar cell performance decreases with an increase in the ambient temperature. This
negative impact on the power generation capability is because of an increase in the internal
carrier recombination rates caused by an increase in carrier concentration. An increase in
temperature causes the band gap of the material to increase. Hence, more energy is required to
cross the energy barrier, which in turn causes a decrease in the open circuit voltage value and
a decrease in the efficiency of solar cell. The I-V and P-V characteristics of a solar cell, with
the variation of temperature, are as shown in the Fig. 3.6 and Fig. 3.7.
17
3.4 MAXIMUM POWER POINT TRACKING
As discussed earlier, for a given insolation and temperature, there exists a unique
operating point corresponding to the maximum power point of the PV array. Therefore, to
extract maximum power from the PV array, it is necessary to operate at the corresponding
MPP as insolation and temperature varies. Also, the I-V curve being non-linear, methods are
to be undertaken to increase the efficiency. One such method is the Maximum Power Point
Tracking, MPPT, used to obtain the maximum power from a varying source. It is done by
varying the duty cycle of a boost converter by using an algorithm. There are several methods
for the MPPT, like the perturbation and observation method, incremental conductance
method, fractional short circuit current method, fractional open circuit voltage method, etc. In
the proposed work, the perturb and observe, or hill climbing method using a current control
algorithm is used for tracking the maximum power point.
Perturb and observe is the most widely used algorithm in MPPT because of its simple
structure and the few measured parameters which are required. In the proposed scheme, the
MPPT operates by periodically measuring the voltage and current of the panel so as to get the
PV output power and then perturbing (i.e. incrementing or decrementing) the array current
and comparing the PV output power with that of the previous perturbation cycle. If the power
is increasing, the perturbation will continue in the same direction in the next cycle, otherwise
the perturbation direction will be reversed. This process is repeated until the maximum power
point is reached. Thus, the proposed algorithm compares the current power reading with the
previous one. If the power has increased, it keeps the same direction (increases current),
otherwise it changes direction (decreases current). This process is repeated at each maximum
power point step until the MPP is reached. After reaching the MPP, the algorithm oscillates
around the correct value. The basic algorithm uses a fixed step to increase or decrease current.
The size of the step determines the size of the deviation while oscillating about the MPP.
Having a smaller step will help reduce the oscillation, but will slow down tracking, while
having a bigger step will help reach MPP faster, but will increase power loss when it
oscillates. The proposed algorithm uses a fixed step of 0.5 to increment or decrement the
current.
18
3.4.2 Flowchart of perturb and observe method
3.5 CONCLUSION
The modelling of a solar cell, solar cell characteristics and maximum power point
tracking using perturb and observe method were discussed in this chapter.
19
CHAPTER 4
SINGLE-STAGE DC-AC BOOST CONVERTER
4.1. GENERAL
Conventionally, PV based grid connected systems use a multi-stage topology,
with a dc-dc boost converter and a dc-ac inverter. But depending on the output power and
voltage levels needed, such a system can result in higher volume, cost and a reduced
efficiency and compactness of the system. In order to overcome the above said drawbacks, it
is preferable to use single-stage system, with as many features of a multi-stage system, as
possible. Such systems have advantages of compactness, modularity and higher efficiency.
This chapter introduces a new single-stage DC-AC boost converter topology [20]. The
different modes of operation are also discussed. The design of the converter is also presented.
20
4.3 MODES OF OPERATION OF THE PROPOSED CONVERTER
There are two states for the converter operation, and in each state, two stages for the
boost operation are defined. For obtaining the sinusoidal output voltage, the duty cycle to the
switches in this structure should be variable. The ac output frequency is taken to be 50Hz and
the switching frequency is taken as 10 kHz. The modes of operation are also discussed.
21
In stage 1 of state I, inductor current increases linearly. This current is alternative and
has tiny fluctuations of switching. At the same time, the capacitor which has a stored energy
from the source and the inductor, discharges through load. As inductor current as well as the
duty cycle is variable, capacitor voltage is also variable. As the load voltage is same as the
capacitor voltage, the positive half cycle of the load voltage is thus obtained. In stage 2, the
inductor discharges, and capacitor gets charged by the source voltage and the inductor current.
22
As the duty cycle for both states is similar, the inductor current and the capacitor
voltage in state 2 are similar to state 1. But, the output voltage in state 2 is negative, as the
switches T2, T4 changes the path of the circuit. Thus, an ac voltage with a higher amplitude is
obtained.
KVL ( )
( ) ( )
( ) }
KVL ( )
( )
KVL ( )
} ( )
( )
Differentiating,
( )
where,
( )
} ( )
( )
23
Solving,
( ) ( )
( )
( ) ( ) ( )
( ) ( ) ( )
24
Duty cycle of T1 and T3 during the positive half cycle and the duty cycle of T2 and T4
in the negative half cycle is as shown in Fig. 4.7 and Fig. 4.8.
25
where, m is the modulation index and is taken as 1, and is the ac line output voltage of the
converter, which is 48V.
For of 48 V, is obtained as 71.287 V and is selected as 72 V.
4.6.2 DC capacitor
The value of dc capacitor ( ), of the converter depends upon the instantaneous
energy available to the converter during transients. Using the energy conservation principle,
[ ] ( ) ( )
where, is the reference dc voltage and is the minimum voltage level of dc bus, a is
the overloading factor, Vis the phase voltage, I is the phase current, and t is the time by which
the dc bus voltage is to be recovered.
Taking the minimum voltage level of the dc bus, = 71.5V, = 72 V, V = 33.95 V,
I= 3.39 A, t = 100 s, a = 1.2, the value of is 385 F and is selected as 400 F.
where, is the switching frequency, and is the ripple current of the inductor. to be 20
Taking output voltage, = 72 V, input voltage, = 12 V, maximum value of output
current = 3.4 A, and the value of ripple current of inductor to be 20 of maximum value of
output current, the value of is 9 mH and is selected as 10 .
4.7 CONCLUSION
A new single-stage dc-ac boost converter topology has been discussed in this chapter.
The different modes of operation along with the steady state analysis and the working
principle were also dealt with. A switching strategy with variable duty cycle so as to achieve a
sinusoidal voltage waveform was also introduced. The design of the proposed single-stage
converter was also done.
26
CHAPTER 5
CONTROL SCHEME FOR THE GRID CONNECTED
DC-AC BOOST CONVERTER
5.1 INTRODUCTION
This chapter discusses the control scheme for active power injection and reactive
power compensation for the proposed grid connected dc-ac boost converter. The reference
current generation algorithm and the scheme for duty cycle generation are also discussed.
27
active power injection and that for the reactive power compensation and a control scheme for
the duty ratio generation with variable pulse width modulation scheme for the dc-ac boost
converter topology.
The unit vector can be used for the calculation of current reference and also for
extracting the active power component and the reactive power component separately. The in
phase unit vector component is used in extracting the active component of the power, while
the 90 displaced unit vector component is used in extracting the reactive component of the
power.
28
5.4 SCHEME FOR ACTIVE CURRENT EXTRACTION
For the proposed grid connected system, the active current command is obtained from
the MPPT by using the current controlled P&O algorithm. The active current command so
obtained is then multiplied with the in phase component of the unit vector. The resultant so
obtained will give the fundamental active component of the load current.
where,
I0 is the dc component in the load current.
IP is the peak of the active current
IQ is the peak of the reactive current
IP sinSt is the active current present in the load current
IQ cosSt is the reactive current present in the load current
I2h is the peak of even harmonics in the load current
I2h+1 is the peak of odd harmonics in the load current
Let the active current command obtained from MPPT by using the current controlled
P&O algorithm be IP. Multiplying this active current command with cos will result in,
I cos I sin t I sin t (5.3)
P P s P s
which is the same as the active current present in the generalized form of load current,
given in equation (5.3).
29
5.5 SCHEME FOR REACTIVE CURRENT EXTRACTION
For reactive current extraction, the actual load current is first sensed. The sensed load
current is then multiplied with the component of unit vector, which is 90 displaced with
respect to the grid voltage. The resultant fundamental reactive term thus becomes a dc
quantity. Now, using a low pass filter of corner frequency, 1Hz, this dc quantity can be
extracted. This extracted dc quantity is again multiplied with the same 90 displaced
component of the unit vector. The resultant so obtained will give the fundamental reactive
component of the load current.
(5.5)
I sin 2h t I sin 2h 1 t
2h s 2h 2h 1 s 2h 1
h 1
30
I I
Q
I sin I cos t P sin 2 t 1 cos 2 t
load 0 s 2 s 2 s
2
I 2h
sin 2 h 1
s
t
2h
sin 2 h 1
s
t
2h
h 1 I 2h 1
2
sin 2h 2 t
s 2 h 1
sin 2h t
s 2 h 1
(5.8)
I I I
Q Q
I cos t P sin 2 t cos 2 t
2 0 s 2 s 2 s
I 2h
2
sin 2h 1 t
s 2h
sin 2h 1 t
s 2h
h 1 I 2h 1
2
sin 2h 2 t
s 2h 1
sin 2h t
s
2h 1
(5.9)
To get the reactive component peak present in the load current given in the above
equation (5.9), the above result is passed through a low pass filter of corner frequency, 1Hz.
Increasing the corner frequency will pass the 50Hz component present in the equation (5.9),
which is the dc quantity present in the load current, practically which will be absent. The next
frequency will be 100Hz, which is the reflection of fundamental present in the load current.
To avoid this 100Hz component in the output of the low pass filter, the corner frequency is
chosen as 1Hz. The resultant will be,
I
Q (5.10)
2
which is the negative of the half of reactive component peak present in the load
current, given in equation (5.5). Multiplying equation (5.10) with 2sin, results in load current
reference as,
I I
2 sin t 90 I cos t (5.11)
Q Q
I 2 sin
load Re f 2 2 s Q s
which is the same as the reactive current present in the generalized form of load
current, given in equation (5.5).
31
5.6 CONTROL LAW FOR THE CURRENT CONTROLLER
The response of the inverter current can be considered as first order, and its response
can be written as,
dI
conv I I (5.12)
i dt conv conv Re f
where,
Iconv is the inverter current
IconvRef is the converter current reference
i is the time constant chosen for the converter current controller
The voltage equation can be written as,
dI
V L conv V (5.13)
conv dt grid
Combining equation (5.12) and (5.13), the control law can be written as,
I conv Re f I conv
V V L
(5.14)
conv Re f grid
i
where,
dI
1 1 T
I
conv conv
dIconv Ts I
conv Re f
I
conv s
(5.15)
i i
where,
Ts is the sampling time
Rewriting equation (5.14),
V k I I (5.16)
conv
V
conv Re f grid P conv Re f
where,
L
k = Proportional controller constant for the current controller
P
i
For the switching frequency of 10kHz, the sampling time will be 100s. The time
constant of the current controller is taken as 70% of the sampling time. Hence, is chosen to
i
be 70s.
32
5.7 SCHEME FOR DUTY CYCLE GENERATION
The difference between the reference current and the inverter current is taken and is
fed to a proportional current controller. The proportional controller is used so that the make
the grid current track its current reference For obtaining the modulating signal and to scale it
to the carrier signal, the grid voltage, Vg is added to the output from the proportional current
controller, and the resultant signal is divided with the dc bus voltage across the capacitor. A
limiter is used so that the peak magnitude of the modulating signal remains limited to the peak
magnitude of the carrier signal. The high frequency carrier waveform (10kHZ) is then
compared with the modulating signal using comparators. The comparator output is further
used to control the high and low level switches of the proposed single-stage dc-ac converter.
5.8 CONCLUSION
The scheme for active power injection and reactive power compensation for the
proposed grid connected single-stage boost converter has been discussed in this chapter. The
current control scheme with reference current generation algorithm was also discussed. The
scheme for duty cycle generation was also discussed.
33
CHAPTER 6
SIMULATION OF THE PROPOSED SINGLE-STAGE
GRID CONNECTED BOOST CONVERTER
6.1 INTRODUCTION
The simulation of the proposed single-phase single-stage grid connected dc-ac boost
converter with active power injection and reactive power compensation is discussed in this
chapter. The simulation is done using PSIM software. The results obtained are also discussed.
PARAMETER VALUE
DC capacitor 4400 F
Load resistor 55
Load inductor 140 mH
34
35
Fig. 6.2 shows the simulation diagram of MPPT using current controlled P&O
method, and the generation of active current command. The instantaneous value of power is
first calculated using the and values, and is then compared with the previous value of
power using a comparator. A time delay using trigger is used to make the comparator output
high. The output of the comparator is then given to a multiplex, where the increment or
decrement to be done in PV current value is decided. This scheme is as shown in first figure.
The second figure shows the generation of the active current command. Here, the feedback
command is first added to a constant. The resultant is then added to the output from multiplex,
thus providing the increment or decrement to be provided in the value of current command, in
accordance with the maximum power point. The resultant magnitude is then limited by using
a limiter. The output from the limiter is fed to a circular buffer consisting of a comparator and
two sample and hold. The current command is held before being fed back in the next instant,
at the rising edge of the trigger point, by using the first sample and hold,. It is then sent at the
falling edge of the trigger point, by using the second sample and hold. A sine wave is used at
the first comparator input for the zero crossing detection of the generated current command.
Fig. 6.2 Simulation diagram of MPPT using current controlled P&O method and
the generation of active current command
36
Fig. 6.3 shows the simulation diagram for the generation of the active and reactive
components of the load current and the generation of reference current. The active current
command from MPPT is first limited by using a limiter and then, multiplied with a unity
magnitude in phase template, to obtain the fundamental active component of the load current.
For obtaining the reactive component, the grid current is multiplied with a unity magnitude
90 lagging template. The resultant fundamental term is a dc quantity. This dc quantity is then
extracted using a low pass filter of corner frequency, 1Hz. The extracted dc quantity is limited
by using a limiter and is then multiplied with the same unity magnitude 90 lagging template.
The resultant so obtained gives the fundamental reactive component of the load current. The
sum of the active and the reactive components of the load current will give the reference
current.
Fig. 6.3 Simulation diagram for reference current generation using the active current
command and the reactive current command
Fig. 6.4 shows the simulation diagram for obtaining the variable duty cycle for the
switches of the proposed dc-ac converter. The difference between the reference current and
the inverter current is taken and is given to the proportional current controller. To get the
modulating signal, and to scale it to the carrier signal, the grid voltage is added to the
controller output, and the resultant signal is divided with the dc bus voltage. Peak magnitude
of the modulating signal is limited by limiter. The 10kHz frequency carrier waveform is then
compared with modulating signal using two comparators, to get a variable duty cycle, which
37
is further given for controlling the switches of the proposed dc-ac boost converter.
Fig. 6.4 Simulation diagram for variable duty cycle generation for the switches
38
Fig. 6.6 shows the variation of photovoltaic voltage, with the variation in solar
irradiation. It can be seen that after the initial transient phase, the is constant at 145V for
the irradiation of 800W/m2 till time, t= 2sec. then increases with an increase in irradiation,
and then starts decreasing, as the irradiation reaches 1000W/m2 and finally reaches a steady
state value. The decrease in , with an increase in irradiance and a corresponding increase
in current, is in accordance with the I-V characteristics of the solar cell.
Fig. 6.7 shows the variation of photovoltaic current, with the variation in solar
irradiation. It can be seen that after the initial transient phase, is constant at 4A for the
irradiation of 800W/m2 till time, t= 2sec. then increases with an increase in irradiation, as
the irradiation reaches 1000W/m2, and finally reaches a steady state value. The increase in
, with an increase in solar irradiance, is in accordance with the I-V characteristics of the
solar cell.
39
Fig 6.7 Simulation diagram showing variation of with time
Fig 6.8 Simulation diagram showing current command generation using P&O method
40
Fig 6.8 shows the maximum power point tracking, using the current controlled P&O
method. The current command increases from zero, and reaches a steady state value of 2.5A,
for the irradiation of 800W/m2, corresponding to the maximum power point, for this value of
irradiation. As the irradiation increases, current command also increases, and reaches a steady
state value of 3.25A, for the irradiation of 1000W/m2, corresponding to maximum power
point, for this irradiation value.
Fig 6.9 shows the current waveform of the input boost inductor of the dc-ac boost converter.
As the inductor current is equal to the sum of the two boost converter currents, the inductor
current is alternating, which has tiny fluctuations of switching with the frequency of 10kHz.
The ripple of this voltage is depended on inductor value and the switching frequency.The
inductor current magnitude is constant for a given value of irradiance, and increases with an
increase in the irradiance value.
41
Fig. 6.10 shows the voltage waveform of the capacitor of the dc-ac boost converter. As the
stored energy in inductor in each stage is given to the capacitor and as the duty cycle is
variable, like the inductor current, this voltage is also variable and has tiny fluctuation of
switching. The ripple of this voltage is depended on capacitor value and switching frequency.
The capacitor voltage is constant for a given value of irradiance.
Fig. 6.11 shows the waveform of the duty cycle in one period, for the upper level
switches, T1 and T3. Fig. 6.12 shows the waveform of the duty cycle in one period, for the
lower level switches, T2 and T4. It can be seen that the duty cycle in both the periods, for both
set of switches, is variable.
42
Fig 6.11 Simulation diagram showing the variation of duty cycle in one period, for T1 and T3
Fig 6.12 Simulation diagram showing the variation of duty cycle in one period, for T2 and T4
Fig. 6.13 shows the waveform of the active current component. As the active current
command is constant for a given value of irradiance, and increases with an increase in the
irradiance value, so does the active current component. Fig. 6.14 shows the waveform of the
reactive current component. This current is always constant for a given value of load.
Fig. 6.15 shows the waveform of reference current, which is the sum of the active and reactive
current components. The reference current is constant for a given value of irradiance, and
increases with an increase in the irradiance, as, the active current increases with an increase in
the irradiance. Fig. 6.16 shows the waveform of converter current. It can be seen that the
converter current tracks its grid current reference at every instant.
43
Fig 6.13 Simulation diagram showing the variation of active current
44
Fig 6.15 Simulation diagram showing the variation of reference current
45
Fig. 6.17 shows the waveform of the grid current. Initially, as the active current
component of load current is less, the current drawn from the grid is higher. But, as the active
current value increases, with an increase in the value of irradiance, the grid current demand
starts decreasing. Also, the grid current is constant for a given value of irradiance, as the
active current component is a constant. As the irradiance increases further, the active current
component of load current also increases, and the current drawn from the grid reduces to a
low value. Fig. 6.18 shows the combined waveform of the grid current and the active current
component of the load current, which shows a proportional variation in the value of the grid
current, with an increase in the value of the active current.
Fig. 6.19 shows the waveform of the net load current. As the load current is the sum
of the active component of load current and the grid current, it is always seen as a constant,
irrespective of the variation in the value of irradiance.
46
Fig 6.18 Simulation diagram showing the variation of active current and grid current
47
Fig. 6.20 shows the waveform of the proposed single-stage dc-ac converter voltage.
Fig. 6.21 shows the waveform of the grid voltage. Both voltages have the same value.
48
6.5 CONCLUSION
The chapter discussed the simulation of the proposed single-phase single-stage grid
connected dc-ac boost converter with active power injection and reactive power compensation
using the PSIM software. The simulated waveforms along with the results obtained were also
discussed.
49
CHAPTER 7
HARDWARE IMPLEMENTATION
7.1 INTRODUCTION
This chapter describes the hardware implementation of a single-phase, solar PV based
multi-stage dc-ac converter configuration, with a speed control scheme for a single-phase
induction motor. The results obtained are also discussed.
( )
where,
D is the duty ratio
Substituting the value in equation (7.1)
( )
or,
Input current of the panel,
( )
( )
50
Output current of the panel,
( ) ( )
( ) )
Choosing the ripple current of inductor to be 20 of input current,
where,
is the switching frequency = 10kHz
( )
( )
Capacitor value,
51
Table 7.1 Table of hardware parameter values
PARAMETER VALUE
Output voltage 60 V
Transformer 230/15V
Microcontroller PIC16F877A
DC capacitor 10 F
Optocoupler K1010
Switching frequency 50 Hz
Trimming potentiometer 10 k
52
Fig 7.1 Circuit diagram of the hardware prototype
53
7.5 HARDWARE SET UP
The hardware set up of the single-phase, solar PV based multi-stage dc-ac converter
configuration, with a speed control scheme for a single-phase induction motor, is as shown in
Fig.7.2. The proposed prototype consists of a power supply unit, a controller unit, an M-board
unit, a dc-dc boost converter, a dc-ac inverter and a single-phase induction motor with a
proximity sensor. The solar module used at the input of the dc-dc boost converter unit is as
shown in Fig.7.3.
Fig 7.2 Hardware prototype of the solar based multi-stage dc-ac converter
54
Fig 7.3 Solar module used at the input of dc-dc converter
55
(a)
DIODE RECTIFIER VOLTAGE REGULATOR GLASS PASSIVATED RECTIFIER
(b)
Fig 7.4 Power supply unit (a) circuit diagram (b) Hardware prototype
56
(a)
RESET CRYSTAL OSCILLATOR PIC16F877A MICROCONTROLLER 1602A LCD
(b)
Fig 7.5 Control unit (a) circuit diagram (b) Hardware prototype
57
7.6.3 M-board unit
The M-board unit is used for controlling the gate of dc-dc converter. The unit
consists of a 6N137 high speed TTL optocoupler, which has a GaAsP LED with an integrated
high gain photo detector for providing isolation, an ICL7667 dual monolithic high speed
MOSFET driver, to convert TTL level signals into outputs with an output voltage swing only
millivolts less than the supply voltage, and a 12V power supply unit for driving the gate driver
IC. The circuit diagram and the hardware set up of the M-board unit are as shown in Fig. 7.6.
(a)
6N137 OPTOCOUPLER ICL7667 MOSFET DRIVER BC547 TRANSISTOR
(b)
Fig 7.6 M-board unit (a) circuit diagram (b) Hardware prototype
58
7.6.4 DC-DC converter unit
The dc-dc converter unit consists of a 3.3mH inductor being supplied from a solar
PV source, an IRF250 n-channel MOSFET, a diode, a 1000F capacitor and a trimming
potentiometer for the output voltage measurement. The circuit diagram and the hardware set
up of the dc-dc converter unit are as shown in Fig. 7.7.
(a)
12mH INDUCTOR IRF250 MOSFET DIODE CAPACITOR TRIMMING POT
(b)
Fig 7.7 Converter unit (a) circuit diagram (b) Hardware prototype
59
7.6.5 Inverter unit
The inverter unit consists of four IRF840 power MOSFETs, four COSMO K1010
optocoupler with infrared emitting diodes, which are optically coupled to phototransistor
detectors, two IR2110 high speed power MOSFET gate drivers, and related circuit elements.
The circuit diagram and the hardware set up of the inverter unit are as shown in Fig. 7.8.
(a)
K1010 OPTOCOUPLER IR2110 MOSFET DRIVER IRF840 MOSFET
(b)
Fig 7.8 Inverter unit (a) circuit diagram (b) Hardware prototype
60
7.7 WORKING
The solar PV panel dc voltage is fed to the dc-dc boost converter. The switching
frequency of the converter MOSFET is 10kHz. The boosted output voltage is fed to the dc-ac
inverter, where, the input dc voltage is inverted to ac voltage with a switching frequency of
50Hz. The output voltage from the inverter is used to drive a single-phase induction motor.
The speed of rotation of the motor is measured using a proximity sensor. The speed of the
motor can be changed by varying the trimming potentiometer. The desired speed at which the
motor is to be rotated can thus be set. PIC16F877A microcontroller is programmed in such a
way, as to generate the PWM signals for both, the dc-dc boost converter MOSFET as well as
the inverter MOSFETs and also, for sensing the speed from the proximity sensor, and for
sensing the set speed using the trimming potentiometer. The microcontroller is also
programmed to displaying readings of the speed of the motor, the desired speed at which the
motor should rotate, and also, the voltage of the dc-dc boost converter output, in the LCD.
When the trimming potentiometer is varied, the width of the pulses to the boost converter
MOSFET varies, and the motor rotates at the desired speed.
61
The PWM signals obtained at the gate of the inverter MOSFET is as shown in Fig.
7.10.
The initial speed of the motor was nearly 1400 rpm. By varying the trimming
potentiometer, the desired speed of the motor was set at 900 rpm. The motor speed reduced
correspondingly, and the motor started running at 900 rpm, the set value of speed.
7.9 CONCLUSION
The hardware prototype of a single-phase, solar PV based multi-stage dc-ac converter
configuration, with a speed control scheme for a single-phase induction motor was
implemented. The speed control scheme was also realized.
62
CHAPTER 8
CONCLUSION
8.1 GENERAL
In this project, a new single-phase single-stage dc-ac boost converter, with lesser
number of switches is modelled. An MPPT algorithm for the solar PV system is developed
using a current control scheme. The concept of unit vector is introduced. A control scheme for
active power injection, and for reactive power compensation, for the grid interfacing of the
proposed single-stage dc-ac boost converter is developed using the unit vector.
To ascertain the effectiveness of the single-stage dc-ac converter, the solar MPPT
algorithm, and the power control scheme, the proposed grid connected system is simulated
using the PSIM. The simulation results show that, for the single stage dc-ac converter, from a
low voltage dc input, an ac voltage with higher amplitude and desired frequency is achieved,
by using a variable duty cycle and by changing the path of capacitor discharge. The
performance of the solar PV system is validated for varying irradiance levels. The simulation
results show that the maximum power point is extracted from the PV array, for each of the
irradiance levels. Also, the active current command is generated by the MPPT algorithm in
accordance with the input irradiance value. The simulation results also validate that, the
fundamental active component of the load current can be obtained by utilizing the in-phase
component of the unit vector and the fundamental reactive component of the load current can
be obtained by utilizing the 90 displaced component of the unit vector. The grid current
reference is also obtained. It is found that the converter current tracks its grid current
reference at every instant. It is also seen from the simulation results, that the grid interfaced
solar PV based single-stage system is capable of injecting active power into the grid and is
also able to compensate for the load reactive power. Thus, the performance of the power
controller is found satisfactory.
A hardware prototype with multi-stage topology, with a dc-dc boost converter, and a
dc-ac inverter, with a speed control scheme for a single-phase induction motor is also
implemented and tested. The experimental results demonstrate the validity of the proposed
system.
63
8.2 FUTURE WORKS
For the proposed single-stage dc-ac converter, a separate control scheme for the dc
capacitor can be implemented for regulating its voltage level. The proposed system is
designed for a fixed load. The same can be extended for an instantaneously varying load.
Also, further studies can be carried on total harmonic distortion of grid power quality.
Another area of interest is islanding, a condition in which a distributed generator (solar panel
or wind turbine) continues to generate power and feed the grid, even though the power from
the electrical utility is no longer present. A scheme for islanding detection and protection can
be implemented.
64
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67
5 4 3 2 1
C7
0.1/400V
R1
1K R2
VCC 1K R31 C25 D11 D12
R3 1000MFD/200V
47K Q1 D2 100K 6A10 6A10
IRF840 BY399 R7
U1 100H/1W
10 7
HIN HO
12 1
LIN LO C30 J2
4
15V 11 0.1/400V
ISO1 SHDN 1
FOD817 GND 2 2
COM
6
3
15V VB L3-300V
3
15V VCC CON2
9 RED
GND C3 C4 VDD C8
5
PIC MICRO CONTROLLER D1
1N4007 C5 C6
13
VS
VSS
0.1/400V
C26
D LCD CONNECTOR 10MFD 0.1MFD 10MFD 0.1MFD 1000MFD/200V D
R5
GND IR2110 47K Q2 D3 D14 D15
5V IRF840 BY399 R8 6A10 6A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
100H/1W
15V 15V
GND
820H
5V
GND
RC4
RC5
5V
5V
R9
1K R10
32
11
120H VCC 1K
GND
VCC
VCC
2 30 RD7
RA0 RD7 RD6
3 29
RA1 RD6 RD5
4 28
4
RA2 RD5 RD4
5 27
RA3 RD4 RD3 ISO2
6 22
RA4 RD3 RD2 FOD817
7 21
RA5 RD2 RD0
19
3
RD0 RD1
20
RD1
8
RE0 GND
9
RE1
10
RE2
40
PIC16F877 RB7
39
RB6
15 38
RCO RB5 15V
16 37
RC1 RB4
17 36
RC2 RB3
18 35
RC4 RC3 RB2 C15
23 34
RC5 RC4 RB1 0.1/400V
24 33 R11
RXD RC5 RB0 1K R12
26
RC7 VCC 1K
R13
RESET CIRCUIT TXD 25
RC6 13
13
27PF
47K Q3
IRF840
D5
BY399 R17
14 U2 100H/1W
14
1
5V 1
12MHZ GND 10 7
TO LOAD
GND
GND
HIN HO
12 1
LIN LO
1
4
15V 11 2
10K 27PF
31
12
ISO3 SHDN
FOD817 GND 2
GND 6
COM CON2
3
15V VB
3
15V VCC
1 2 3 4 9
GND C11 C12 VDD C16
5
D4 VS 0.1/400V
13
1N4007 C13 C14 VSS
7414 7414 10MFD 0.1MFD 10MFD 0.1MFD
R15
GND IR2110 47K Q4 D6
BY399 R18
IRF840 100H/1W
15V 15V
0.1MF
GND
R19
1K R20
VCC 1K
4
ISO4
FOD817
3
C C
GND
BOOST CONVERTER
L1 D7
12MH
UF5408 R14
10K
TO LOAD
VARIABLE
Q5
DC C18
SOURCE IRF250
10MFD R16
10K
GND
VOLTAGE
MMT
M DRIVE
15V
7 1 8
6 2 7
3 GND 3 6 15V
4 5
R21
7667 47K/1W
5
R26 10K R25
Q6 470H A
BC547
R27 R22
10K 10K
B GND B
GND
POWERSUPPLY 7815
CON3
1
2
3
15V
Transformer Rectifier 7805
1 3 5V D16 D17
1
AC-18V
230V
1 3 4 - + 3 C27 C28
1 1000MFD/35V 10MFD/25V
AC
2 4
1000mfd 10mfd CON2
2
D18 D19
1N4007 1N4007
GND
GND
A A
5 4 3 2 1
INCHANGE Semiconductor
FEATURES
Output current in excess of 1.5A
Output voltage of 12V
Internal thermal overload protection
Output transition Safe-Area compensation
Minimum Lot-to-Lot variations for robust device
performance and reliable operation
Vi DC input voltage 35 V
THERMAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Tj=25 (Vi= 19V, IO=0.5A, Ci= 0.33F, CO= 0.1F unless otherwise specified)
FEATURES
* High reverse voltage to 1000V
* Surge overload ratings to 50 amperes peak
* Good for printed circuit board assembly
* Mounting position: Any
* Weight: 1.20 grams
WOM
MECHANICAL DATA
* UL listed the recognized component directory, file #E94233 .360 (9.1)
* Epoxy: Device has UL flammability classification 94V-O .340 (8.6)
.217 (5.5)
.197 (5.0)
1.2 1.0
(30.5) (25.4)
MIN. MIN.
.032 (0.8)
POS. .028 (0.7)
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS LEAD
RATINGS SYMBOL W005M W01M W02M W04M W06M W08M W10M UNITS
Maximum Recurrent Peak Reverse Voltage VRRM 50 100 200 400 600 800 1000 Volts
Maximum RMS Bridge Input Voltage VRMS 35 70 140 280 420 560 700 Volts
Maximum DC Blocking Voltage VDC 50 100 200 400 600 800 1000 Volts
Maximum Average Forward Rectified Output Current at T A = 25oC IO 1.5 Amps
Peak Forward Surge Current 8.3 ms single half sine-wave
I FSM 50 Amps
superimposed on rated load (JEDEC method)
CHARACTERISTICS SYMBOL W005M W01M W02M W04M W06M W08M W10M UNITS
Maximum Forward Voltage Drop per element at 1.0A DC VF 1.0 Volts
2002-8
1.4
40 8.3ms Single Half Sine-Wave
(JEDED Method) 1.2
1.0
30
.8
20
.6
60 Hz RESISTIVE OR
.4 INDUCTIVE LOAD
10
.2
0 0
1 2 4 6 8 10 20 40 60 100 20 50 80 110 140 170 200
NUMBER OF CYCLES AT 60Hz AMBIENT TEMPERATURE, ( )
10
TJ = 25
Pulse Width = 300us
1% Duty Cycle
1.0
1.0
TJ = 25
0.1
.1
.01 .01
.2 .4 .6 .8 1.0 1.2 1.4 1.6 0 20 40 60 80 100 120 140
INSTANTANEOUS FORWARD VOLTAGE, (V)
PERCENT OF RATED PEAK
REVERSE VOLTAGE, (%)
RECTRON
PIC16F87XA
28/40/44-Pin Enhanced Flash Microcontrollers
Devices Included in this Data Sheet: Analog Features:
PIC16F873A PIC16F876A 10-bit, up to 8-channel Analog-to-Digital
PIC16F874A PIC16F877A Converter (A/D)
Brown-out Reset (BOR)
High-Performance RISC CPU: Analog Comparator module with:
- Two analog comparators
Only 35 single-word instructions to learn
- Programmable on-chip voltage reference
All single-cycle instructions except for program (VREF) module
branches, which are two-cycle
- Programmable input multiplexing from device
Operating speed: DC 20 MHz clock input inputs and internal voltage reference
DC 200 ns instruction cycle
- Comparator outputs are externally accessible
Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Special Microcontroller Features:
Up to 256 x 8 bytes of EEPROM Data Memory
Pinout compatible to other 28-pin or 40/44-pin 100,000 erase/write cycle Enhanced Flash
PIC16CXXX and PIC16FXXX microcontrollers program memory typical
1,000,000 erase/write cycle Data EEPROM
Peripheral Features: memory typical
Data EEPROM Retention > 40 years
Timer0: 8-bit timer/counter with 8-bit prescaler
Self-reprogrammable under software control
Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via external In-Circuit Serial Programming (ICSP)
crystal/clock via two pins
Timer2: 8-bit timer/counter with 8-bit period Single-supply 5V In-Circuit Serial Programming
register, prescaler and postscaler Watchdog Timer (WDT) with its own on-chip RC
Two Capture, Compare, PWM modules oscillator for reliable operation
- Capture is 16-bit, max. resolution is 12.5 ns Programmable code protection
- Compare is 16-bit, max. resolution is 200 ns Power saving Sleep mode
- PWM max. resolution is 10-bit Selectable oscillator options
Synchronous Serial Port (SSP) with SPI In-Circuit Debug (ICD) via two pins
(Master mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous Receiver CMOS Technology:
Transmitter (USART/SCI) with 9-bit address Low-power, high-speed Flash/EEPROM
detection technology
Parallel Slave Port (PSP) 8 bits wide with Fully static design
external RD, WR and CS controls (40/44-pin only)
Wide operating voltage range (2.0V to 5.5V)
Brown-out detection circuitry for
Commercial and Industrial temperature ranges
Brown-out Reset (BOR)
Low-power consumption
MCLR/VPP 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5
PIC16F873A/876A
RA2/AN2/VREF-/CVREF 4 25 RB4
RA3/AN3/VREF+ 5 24 RB3/PGM
RA4/T0CKI/C1OUT 6 23 RB2
RA5/AN4/SS/C2OUT 7 22 RB1
VSS 8 21 RB0/INT
OSC1/CLKI 9 20 VDD
OSC2/CLKO 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
MCLR/VPP
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
28-Pin QFN
RB5
RB4
28
27
26
25
24
23
22
RA2/AN2/VREF-/CVREF 1 21 RB3/PGM
RA3/AN3/VREF+ 2 20 RB2
RA4/T0CKI/C1OUT 3 19 RB1
PIC16F873A
RA5/AN4/SS/C2OUT 4 18 RB0/INT
VSS 5 PIC16F876A 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO 7 10 15 RC7/RX/DT
12
13
14
11
8
9
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RC3/SCK/SCL
RC5/SDO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
44-Pin QFN
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 OSC2/CLKO
RD4/PSP4 2 32 OSC1/CLKI
RD5/PSP5 3 31 VSS
RD6/PSP6 4 30 VSS
RD7/PSP7 5 29 VDD
VSS
PIC16F874A VDD
6 28
VDD 7 PIC16F877A 27 RE2/CS/AN7
VDD 8 26 RE1/WR/AN6
RB0/INT 9 25 RE0/RD/AN5
RB1 10 24 RA5/AN4/SS/C2OUT
RB2 11 23 RA4/T0CKI/C1OUT
22
12
13
14
15
16
17
18
19
20
21
RA2/AN2/VREF-/CVREF
NC
RB6/PGC
RB7/PGD
RA3/AN3/VREF+
MCLR/VPP
RB3/PGM
RB4
RB5
RA0/AN0
RA1/AN1
40-Pin PDIP
MCLR/VPP 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5
RA2/AN2/VREF-/CVREF 4 37 RB4
RA3/AN3/VREF+ 5 36 RB3/PGM
RA4/T0CKI/C1OUT 6 35 RB2
PIC16F874A/877A
RA5/AN4/SS/C2OUT 7 34 RB1
RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
OSC1/CLKI 13 28 RD5/PSP5
RA2/AN2/VREF-/CVREF
OSC2/CLKO 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RA3/AN3/VREF+
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
MCLR/VPP
RB7/PGD
RB6/PGC
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RA1/AN1
RA0/AN0
RD0/PSP0 19 22 RD3/PSP3
RB5
RB4
RD1/PSP1 20 21 RD2/PSP2
NC
NC
44-Pin PLCC
6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI/C1OUT 39 RB3/PGM
7
RA5/AN4/SS/C2OUT 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F874A 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F877A 33 RD7/PSP7
OSC1/CLKI 14 32 RD6/PSP6
OSC2/CLKO 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
282
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC5/SDO
NC
RC4/SDI/SDA
RC6/TX/CK
NC
44-Pin TQFP
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKO
RD6/PSP6 4 30 OSC1/CLKI
RD7/PSP7 5 PIC16F874A 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F877A 27 RE2/CS/AN7
RB0/INT 8 26 RE1/WR/AN6
RB1 9 25 RE0/RD/AN5
RB2 10 24 RA5/AN4/SS/C2OUT
RB3/PGM 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22
RB4
RB5
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
NC
NC
RB6/PGC
RB7/PGD
RA3/AN3/VREF+
MCLR/VPP
PORTE
RE1/WR/AN6
RE2/CS/AN7
Timer2 Parallel
Timer0 Timer1 10-bit A/D Slave Port
Synchronous Voltage
Data EEPROM CCP1,2 USART Comparator Reference
Serial Port
*Add -T suffix for tape and reel. Please refer to TB347 for details IN A 2 7 OUT A
on reel specifications.
V- 3 6 V+
**Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder IN B 4 5 OUT B
processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination Functional Diagram (Each Driver)
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed V+
the Pb-free requirements of IPC/JEDEC J STD-020.
2mA
OUT
IN
V-
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 1999, 2006, 2010, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL7667
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on an evaluation PC board in free air.
2. For JC, the case temp location is the center of the exposed metal pad on the package underside.
Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25C, V+ = 0V unless otherwise specified.
Temperature limits established by characterization and are not production tested.
ICL7667C, M ICL7667M
TA = +25C 0C TA +70C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
DC SPECIFICATIONS
SWITCHING SPECIFICATIONS
2 FN2853.7
September 4, 2015
ICL7667
Test Circuits
V+ = 15V
+5V
90%
INPUT
+
4.7F 0.1F
10%
0.4V
INPUT OUTPUT TD1 TD2
ICL7667 CL = 1000pF tf tr
15V
INPUT RISE AND 90% 90%
FALL TIMES 10ns
OUTPUT
10% 10%
0V
1s 100
V+ = 15V
90
CL = 1nF
80
V+ = 15V
70
tRISE TD2
50
40
10 TD1
30
tFALL 20
10
1 0
10 100 1000 10k 100k
-55 0 25 70 125
CL (pF) TEMPERATURE (C)
50 30
CL = 1nF V+ = 15V
V+ = 15V
40 200kHz
tr AND tf
10
tr AND tf (ns)
30
IV+ (mA)
20kHz
20
3.0
10
0
1.0
-55 0 25 70 125 10 100 1k 10k 100k
TEMPERATURE (C) CL (pF)
3 FN2853.7
September 4, 2015
ICL7667
100 100
V+ = 15V
IV+ (mA)
IV+ (mA)
10 10 V+ = 15V
V+ = 5V
1
1
V+ = 5V
CL = 1nF
CL = 10pF
100A 100mA
10k 100k 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
50 50
40 40
tr AND tD2 (ns)
30
tD1 AND tf (ns)
30 tr = TD2
tf
20 20
tD1
10
10
CL = 1nF CL = 10pF
0 0
5 10 15 5 10 15
V+ (V) V+ (V)
4 FN2853.7
September 4, 2015
ICL7667
current capability of the ICL7667 enables it to drive a 2. Output stage crossover current loss
1000pF load with a rise time of only 40ns. Because the 3. Output stage I2R power loss
output stage impedance is very low, up to 300mA will flow The sum of the above must stay within the specified limits for
through the series N-Channel and P-Channel output devices reliable operation.
(from V+ to V-) during output transitions. This crossover current
is responsible for a significant portion of the internal power As noted above, the input inverter current is input voltage
dissipation of the ICL7667 at high frequencies. It can be dependent, with an IV+ of 0.1mA maximum with a logic 0
minimized by keeping the rise and fall times of the input to the input and 6mA maximum with a logic 1 input.
ICL7667 below 1s. The output stage crowbar current is the current that flows
through the series N-Channel and P-Channel devices that
Application Notes form the output. This current, about 300mA, occurs only
Although the ICL7667 is simply a dual level-shifting inverter, during output transitions. Caution: The inputs should never
there are several areas to which careful attention must be be allowed to remain between VIL and VIH since this could
paid. leave the output stage in a high current mode, rapidly
leading to destruction of the device. If only one of the drivers
Grounding
is being used, be sure to tie the unused input to V- or
Since the input and the high current output current paths
ground. NEVER leave an input floating. The average supply
both include the V- pin, it is very important to minimize and
current drawn by the output stage is frequency dependent,
common impedance in the ground return. Since the ICL7667
as can be seen in Figure 5 (IV+ vs Frequency graph in the
is an inverter, any common impedance will generate
Typical Characteristics Graphs).
negative feedback, and will degrade the delay, rise and fall
times. Use a ground plane if possible, or use separate The output stage I2R power dissipation is nothing more than
ground returns for the input and output circuits. To minimize the product of the output current times the voltage drop
any common inductance in the ground return, separate the across the output device. In addition to the current drawn by
input and output circuit ground returns as close to the any resistive load, there will be an output current due to the
ICL7667 as is possible. charging and discharging of the load capacitance. In most
high frequency circuits the current used to charge and
Bypassing discharge capacitance dominates, and the power dissipation
The rapid charging and discharging of the load capacitance is approximately:
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance P AC = CV V 2 f (EQ. 1)
over a wide frequency range should be used. A 4.7F
tantalum capacitor in parallel with a low inductance 0.1F where C = Load Capacitance, f = Frequency
capacitor is usually sufficient bypassing. In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
Output Damping ICL7667 power dissipation will be:
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long P AC = QGV V f (EQ. 2)
inductive lines with capacitive loads. Techniques to reduce
where QG = Charge required to switch the gate, in
ringing include:
Coulombs, f = Frequency.
Reduce inductance by making printed circuit board traces
as short as possible. Power MOS Driver Circuits
Reduce inductance by using a ground plane or by closely Power MOS Driver Requirements
coupling the output lines to their return paths.
Because it has a very high peak current output, the ICL7667
Use a 10 to 30 resistor in series with the output of the the at driving the gate of power MOS devices. The high
ICL7667. Although this reduces ringing, it will also slightly current output is important since it minimizes the time the
increase the rise and fall times. power MOS device is in the linear region. Figure 9 is a
Use good by-passing techniques to prevent supply typical curve of Charge vs Gate voltage for a power
voltage ringing. MOSFET. The flat region is caused by the Miller
capacitance, where the drain-to-gate capacitance is
Power Dissipation
multiplied by the voltage gain of the FET. This increase in
The power dissipation of the ICL7667 has three main capacitance occurs while the power MOSFET is in the linear
components: region and is dissipating significant amounts of power. The
1. Input inverter current loss very high current output of the ICL7667 is able to rapidly
5 FN2853.7
September 4, 2015
ICL7667
overcome this high capacitance and quickly turns the SG1525 IC, except that the outputs are inverted. This
MOSFET fully on or off. inversion is needed since ICL7667 is an inverting buffer.
IRF730
+VC V+
SG1527 ICL7667
IRF730
B
GND V-
FIGURE 10A.
6 FN2853.7
September 4, 2015
6N137, HCNW137, HCNW2601, HCNW2611, HCPL-0600,
HCPL-0601, HCPL-0611, HCPL-0630, HCPL-0631, HCPL-0661,
HCPL-2601, HCPL-2611, HCPL-2630, HCPL-2631, HCPL-4661
High CMR, High Speed TTL Compatible Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description Features
The 6N137, HCPL-26xx/06xx/4661, HCNW137/26x1 are 15 kV/s minimum Common Mode Rejection (CMR)
optically coupled gates that combine a GaAsP light emit- at VCM= 1 kV for HCNW2611, HCPL-2611, HCPL-4661,
ting diode and an integrated high gain photo detector. HCPL-0611, HCPL-0661
An enable input allows the detector to be strobed. The High speed: 10 MBd typical
output of the detector IC is an open collector Schottky- LSTTL/TTL compatible
clamped transistor. The internal shield provides a guar- Low input current capability: 5 mA
anteed common mode transient immunity specification Guaranteed AC and DC performance over temper
up to 15,000 V/s at Vcm = 1000 V. ature: -40 C to +85 C
This unique design provides maximum AC and DC circuit Available in 8-Pin DIP, SOIC-8, widebody packages
isolation while achieving TTL compatibility. The optocou- Strobable output (single channel products only)
pler AC and DC operational parameters are guaranteed
Safety approval
from -40 C to +85 C allowing troublefree system per-
UL recognized - 3750 Vrms for 1 minute and 5000 Vrms*
formance.
for 1 minute per UL1577 CSA approved
Functional Diagram IEC/EN/DIN EN 60747-5-5 approved with
6N137, HCPL-2601/2611 HCPL-2630/2631/4661 VIORM= 567 Vpeak for 06xx Option 060
HCPL-0600/0601/0611 HCPL-0630/0631/0661
VIORM= 630 Vpeak for 6N137/26xx Option 060
NC 1 8 V CC ANODE 1 1 8 V CC
VIORM=1414 Vpeak for HCNW137/26x1
ANODE 2 7 VE CATHODE 1 2 7 V O1
MIL-PRF-38534 hermetic version available
CATHODE 3 6 VO CATHODE 2 3 6 V O2 (HCPL-56xx/66xx)
NC 4 5 GND ANODE 2 4 5 GND
SHIELD SHIELD Applications
Isolated line receiver
TRUTH TABLE TRUTH TABLE
(POSITIVE LOGIC) (POSITIVE LOGIC) Computer-peripheral interfaces
LED ENABLE OUTPUT LED OUTPUT
ON H L ON L Microprocessor system interfaces
OFF H H OFF H
ON L H Digital isolation for A/D, D/A conversion
OFF L H Switching power supply
ON NC L
OFF NC H Instrument input/output isolation
Ground loop elimination
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
Pulse transformer replacement
Power transistor isolation in motor drives
Isolation of high speed logic systems
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
The 6N137, HCPL-26xx, HCPL-06xx, HCPL-4661, HCNW137,
and HCNW26x1 are suitable for high speed logic interfac-
ing, input/output buffering, as line receivers in environ-
ments that conventional line receivers cannot tolerate
and are recommended for use in extremely high ground
or induced noise environments.
Selection Guide
Widebody
Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic
Input Single
On- Single Dual Single Dual Single and Dual
dV/dt VCM Current
Output Channel Channel Channel Channel Channel Channel
(V/s) (V) (mA) Enable Package Package Package Package Package Packages
1000 10 5 YES 6N137
5,000 1,000 5 YES HCPL-0600 HCNW137
NO HCPL-2630 HCPL-0630
10,000
1,000 YES HCPL-2601 HCPL-0601 HCNW2601
NO HCPL-2631 HCPL-0631
15,000
1,000 YES HCPL-2611 HCPL-0611 HCNW2611
NO HCPL-4661 HCPL-0661
1,000 50 YES HCPL-2602 [1]
Notes:
1. Technical data are on separate Avago publications.
2. 15 kV/s with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193x devices.
2
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
YYWW RU
UL
1 2 3 4 RECOGNITION
8-pin DIP Package with Gull Wing Surface Mount Option 300
(6N137, HCPL-2601/11/30/31, HCPL-4661)
LAND PATTERN RECOMMENDATION
9.65 0.25 1.016 (0.040)
(0.380 0.010)
8 7 6 5
1 2 3 4
2.0 (0.080)
1.27 (0.050)
1.080 0.320
(0.043 0.013) 0.635 0.25
(0.025 0.010)
0.635 0.130 12 NOM.
2.54
(0.100) (0.025 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
5
IRF840, SiHF840
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
Dynamic dV/dt rating
VDS (V) 500 Available
RDS(on) () VGS = 10 V 0.85 Repetitive avalanche rated
Qg max. (nC) 63 Fast switching Available
ORDERING INFORMATION
Package TO-220AB
IRF840PbF
Lead (Pb)-free
SiHF840-E3
IRF840
SnPb
SiHF840
3.0
7.0 V
101 6.0 V
2.0
(Normalized)
5.5 V
5.0 V
Bottom 4.5 V
1.5
1.0
4.5 V
0.5
100 20 s Pulse Width
TC = 25 C
0.0
100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91070_01 VDS, Drain-to-Source Voltage (V) 91070_04 TJ, Junction Temperature (C)
VGS 2500
VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
101 10 V Crss = Cgd
2000
8.0 V Coss = Cds + Cgd
ID, Drain Current (A)
7.0 V
Capacitance (pF)
6.0 V
5.5 V 1500 Ciss
4.5 V
5.0 V
Bottom 4.5 V
1000
Coss
500
100 Crss
20 s Pulse Width
TC = 150 C
0
100 101 100 101
91070_02 VDS, Drain-to-Source Voltage (V) 91070_05 VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
ID = 8.0 A
VGS, Gate-to-Source Voltage (V)
VDS = 250 V
25 C VDS = 100 V
12
8
100
4
20 s Pulse Width
For test circuit
VDS = 50 V
see figure 13
0
4 5 6 7 8 9 10 0 15 30 45 60 75
91070_03 VGS, Gate-to-Source Voltage (V) 91070_06 QG, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage
8.0
ISD, Reverse Drain Current (A)
150 C
25 C
4.0
2.0
VGS = 0 V
100 0.0
0.4 0.6 0.8 1.0 1.2 1.4 25 50 75 100 125 150
91070_07 VSD, Source-to-Drain Voltage (V) 91070_09 TC, Case Temperature (C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
102 VDS
Operation in this area limited
5 by RDS(on)
VGS
10 s D.U.T.
2
ID, Drain Current (A)
RG
+
10 - VDD
100 s
5
10 V
2 1 ms Pulse width 1 s
Duty factor 0.1 %
1
10 ms
5 Fig. 10a - Switching Time Test Circuit
TC = 25 C
2 TJ = 150 C VDS
Single Pulse
0.1 90 %
2 5 2 5 2 5 2 5 2 5
0.1 1 10 102 103 104
10
Thermal Response (ZthJC)
1
0 - 0.5
0.2
0.1 0.1 PDM
0.05
0.02 Single Pulse
0.01 t1
(Thermal Response)
10-2 t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10 102
DWG: 6031
Note
M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM
C
b
e
J(1)
e(1)
Package Picture
ASE Xian
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features Product Summary
Floating channel designed for bootstrap operation
Fully operational to +500V or +600V VOFFSET (IR2110) 500V max.
Tolerant to negative transient voltage (IR2113) 600V max.
dV/dt immune
Gate drive supply range from 10 to 20V IO+/- 2A / 2A
Undervoltage lockout for both channels
3.3V logic compatible VOUT 10 - 20V
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset ton/off (typ.) 120 & 94 ns
CMOS Schmitt-triggered inputs with pull-down
Delay Matching (IR2110) 10 ns max.
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels (IR2113) 20ns max.
Outputs in phase with inputs
Packages
Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output chan-
nels. Proprietary HVIC and latch immune CMOS technologies enable 16-Lead SOIC
14-Lead PDIP IR2110S/IR2113S
ruggedized monolithic construction. Logic inputs are compatible with IR2110/IR2113
standard CMOS or LSTTL output, down to 3.3V logic. The output
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 500 or 600 volts.
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com 1
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
2 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
www.irf.com 3
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Lead Definitions
Symbol Description
VDD Logic supply
HIN Logic input for high side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low side gate driver output (LO), in phase
VSS Logic ground
VB High side floating supply
HO High side gate drive output
VS High side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return
4 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
250 250
200 200
Max.
Turn-On Delay Time (ns)
Max.
50 50
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (C) VCC/VBS Supply Voltage (V)
Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage
250 250
Max.
200 200
Turn-On Delay Time (ns)
Typ.
Turn-Off Delay Time (ns)
150 150
100 100
Max.
Typ.
50 50
0 0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Supply Voltage (V) Temperature (C)
Figure 7C. Turn-On Time vs. VDD Supply Voltage Figure 8A. Turn-Off Time vs. Temperature
250 250
200 200
Max.
Turn-Off Delay Time (ns)
Turn-Off Delay Time (ns)
150
Max.
150
Typ.
100
100
Typ
50
50
0
0
10 12 14 16 18 20
0 2 4 6 8 10 12 14 16 18 20
VDD Supply Voltage (V)
VCC/VBS Supply Voltage (V)
Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage Figure 8C. Turn-Off Time vs. VDD Supply Voltage
www.irf.com 7
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
250 250
200 200
Max.
Shutdown Delay Time (ns)
Max.
100 100
Typ.
50 50
0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (C) VCC/VBS Supply Voltage (V)
Figure 9A. Shutdown Time vs. Temperature Figure 9B. Shutdown Time vs. VCC/VBS Supply Voltage
250 100
Shutdown Delay Time (ns)
200 80
Max .
Turn-On Rise Time (ns)
150 60
100
Typ 40
M ax.
50 Typ.
20
0
0
0 2 4 6 8 10 12 14 16 18 20
-50 -25 0 25 50 75 100 125
VDD Supply Voltage (V) Temperature (C)
Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 10A. Turn-On Rise Time vs. Temperature
100 50
80 40
Turn-On Rise Time (ns)
60 30
Max.
Max.
40 20
Typ. Typ.
20 10
0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)
Figure 10B. Turn-On Rise Time vs. Voltage Figure 11A. Turn-Off Fall Time vs. Temperature
8 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
50
15.0
40
12.0
Max
Min.
30
9.0
20
6.0
Max.
Typ.
10
3.0
0
0.0
10 12 14 16 18 20
-50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V)
Temperature (C)
Figure 11B. Turn-Off Fall Time vs. Voltage Figure 12A. Logic 1 Input Threshold vs. Tempera-
ture
15 15.0
12
Logic " 1" Input Threshold (V)
12.0
Max.
Logic "0" Input Threshold (V)
9 9.0
6 6.0
Max.
Min.
3
3.0
0
0.0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)
Figure 12B. Logic 1 Input Threshold vs. Voltage Figure 13A. Logic 0 Input Threshold vs. Tempera-
ture
15 5.00
12 4.00
Logic "0" Input Threshold (V)
9 3.00
Min.
6
2.00
Max.
3
1.00
0
0.00
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)
Figure 13B. Logic 0 Input Threshold vs. Voltage Figure 14A. High Level Output vs. Temperature
www.irf.com 9
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
5.00 1.00
4.00 0.80
High Level Output Voltage (V)
2.00 0.40
M ax.
1.00 0.20
Max.
0.00 0.00
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)
Figure 14B. High Level Output vs. Voltage Figure 15A. Low Level Output vs. Temperature
1.00 500
0.80 400
Offset Supply Leakage Current (A)
Low Level Output Voltage (V)
0.60 300
0.40 200
0.20 100
M ax.
Max.
0.00 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)
Figure 15B. Low Level Output vs. Voltage Figure 16A. Offset Supply Current vs. Temperature
500 500
400
Offset Supply Leakage Current (A)
400
VBS Supply Current (A)
300 300
Max.
200 200
Typ.
100 Max. 100
0 0
0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125
IR2110 IR2113
V B Boost Voltage (V) Temperature (C)
Figure 16B. Offset Supply Current vs. Voltage Figure 17A. VBS Supply Current vs. Temperature
10 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
500 625
400 500
300 375
Max.
200 250
Max.
Typ.
100 125
Typ.
0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBS Floating Supply Voltage (V) Temperature (C)
Figure 17B. VBS Supply Current vs. Voltage Figure 18A. VCC Supply Current vs. Temperature
625 100
500 80
VCC Supply Current (A)
375 60
250 40
Max.
Max.
125 20
Typ.
Typ.
0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VCC Fixed Supply Voltage (V) Temperature (C)
Figure 18B. VCC Supply Current vs. Voltage Figure 19A. VDD Supply Current vs. Temperature
60 100
50
80
Logic "1" Input Bias Current (A)
VDD Supply Current (A)
40
60
30
40
20
Max.
10 20
Typ.
0
0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)
Figure 19B. VDD Supply Current vs. VDD Voltage Figure 20A. Logic 1 Input Current vs. Temperature
www.irf.com 11
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
60 5.00
Logic 1 Input Bias Current (A)
50
4.00
10 1.00
Max.
0
0.00
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)
Figure 20B. Logic 1 Input Current vs. VDD Voltage Figure 21A. Logic 0 Input Current vs. Temperature
5 11.0
Logic 0 Input Bias Current (A)
4 10.0
VBS Undervoltage Lockout + (V)
Max.
3
9.0
Typ.
2
8.0
1 Min.
7.0
0
0 2 4 6 8 10 12 14 16 18 20 6.0
-50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V)
Temperature (C)
Figure 21B. Logic 0 Input Current vs. VDD Voltage Figure 22. VBS Undervoltage (+) vs. Temperature
11.0 11.0
10.0 10.0
VCC Undervoltage Lockout + (V)
VBS Undervoltage Lockout - (V)
Max.
Max.
9.0 9.0
Typ.
Typ.
8.0 8.0
Min.
7.0 Min.
7.0
6.0 6.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Figure 23. VBS Undervoltage (-) vs. Temperature Figure 24. VCC Undervoltage (+) vs. Temperature
12 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
11.0 5.00
10.0 4.00
VCC Undervoltage Lockout - (V)
Typ.
9.0 3.00
Min.
Typ.
8.0 2.00
6.0 0.00
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (C) Temperature (C)
Figure 25. VCC Undervoltage (-) vs. Temperature Figure 26A. Output Source Current vs. Temperature
5.00 5.00
4.00 4.00
Output Source Current (A)
Min.
2.00 2.00
Typ.
1.00 1.00
Min.
0.00 0.00
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)
Figure 26B. Output Source Current vs. Voltage Figure 27A. Output Sink Current vs. Temperature
320V
5.00 150
125
4.00
Junction Temperature (C)
140V
Output Sink Current (A)
100
3.00
75
2.00
10V
Typ. 50
1.00 Min.
25
0.00 0
10 12 14 16 18 20 1E+2 1E+3 1E+4 1E+5 1E+6
VBIAS Supply Voltage (V) Frequency (Hz)
Figure 27B. Output Sink Current vs. Voltage Figure 28. IR2110/IR2113 TJ vs. Frequency
(IRFBC20) RGATE = 33 , VCC = 15V
www.irf.com 13
K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER
Description Schematic
The K1010 series consist of an infrared emitting
diode, optically coupled to a phototransistor detector.
They are packaged in a 4-pin DIP package and available
in wide-lead spacing and SMD option.
1. Anode
2. Cathode
3. Emitter
4. Collector
Features
1. Current transfer ratio
( CTRMin. 50% at IF=5mA VCE=5V )
2. High isolation voltage between input and output
( Viso5000Vrms )
3. Pb free and RoHS compliant
4. MSL class 1
5. Agency Approvals
UL Approved (No. E169586): UL1577
c-UL Approved (No. E169586)
VDE Approved (No. 101347): DIN EN60747-5-5
FIMKO Approved: EN60065, EN60950, EN60335
SEMKO Approved: EN60065, EN60950, EN60335
CQC Approved: GB8898-2011, GB4943.1-2011
Applications
System appliances
Measuring instruments
Computer terminals
Programmable controllers
Medical instruments
Physical and chemical equipment
Signal transmission between circuits of different potentials and impedances
K10101X K10104X
7.62
4.60 7.62
6.50
6.50 4.60
3.50
3.50
0~10
0.40
3.00
2.70
0.100.1
0.25
1.20
1.00
10.000.4 2.54
0.25 0.50
1.20
2.54
13.00 13.00
K10103X K10106X
10.16
7.62 4.60 7.62
6.50 4.60
6.50
3.50
3.50
0.30
0~10
0.900.25 0.900.25
1.20
0.25
11.80+0.2
3.00
2.70
-0.5
0.25
0.25 2.54
10.160.50
1.20 0.50
2.54
TOLERANCE0.2mm
Device Marking
Notes:
cosmo
1010 cosmo
817 1010
YWW 817
YWW Y: Year code / WW: Week code
: CTR rank
CTR ( % )
300
K1010 A 80 ~ 160 A 250
K1010 B 130 ~ 260 B 200
K1010 C 200 ~ 400 C
150
K1010 D 300 ~ 600 D
100
K1010 E 50 ~ 600 Blank,A,B,C,D,E
50
0
0 0.5 1 2 5 10 20 50
10-6
Collector Dark Current
200
-7
10
PC ( mW )
150
ICEO ( A )
-8
10
100 -9
10
-10
50 10
-11
0 10
-55 0 25 50 75 115 125 -55 0 25 50 75 115
Ta=75C
Forward Current IF ( mA )
Forward Current IF ( mA )
50 200
50C 25C
40 100
50
30 0C
20
-25C
20 10
5
10
2
0 1
-55 0 25 50 75 115 125 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
25 VCE=5V
20 100
Ratio ( % )
15 10mA
10 50
5mA
5
0 0
0 1 2 3 4 5 6 7 8 9 -55 -25 0 25 50 75 115
Collector-Emitter Voltage VCE (V) Ambient Temperature Ta ()
Collector-Emitter Saturation
0.14
Ic=1mA 6
Ic=0.5mA
0.12
Voltage VCE ( V )
Voltage VCE ( V )
5
Ic=1mA
0.10
4
0.08 Ic=3mA
3
0.06
Ic=5mA
2
0.04
Ic=7mA
0.02 1
0 0
-55 0 25 50 75 115 0 5 10
50 50 Ic=2mA
Ta=25C Ta=25C
tr
20 20 tf
10 10
5 5
2 2
1 1
0.5 0.5
0.2 0.2
0.1 0.1
0.1 1 10 0.1 1 10
1 2.54
5.23 (.100)
Features (.206)
BL S NT
n Multiturn / Cermet / Industrial / Sealed n Mounting hardware available
LA N IA
AI SIO PL
2.54 2.41
(H-117P)
AV R M n 5 terminal styles
VE S CO (.100) (.095)
E
n RoHS compliant* version available
3
oH
TN
(.100)
IA
PL
3
OM
oH
C
S 3296 - 3/8 Square Trimpot Trimming Potentiometer
2
1 2.54
*R
(.100) 2.41
(.095)
E
RE
(.100)
(see standard resistance table) (.252 .052) (.395) 3
F
AD
Resistance Tolerance............ 10 % std. 1.52 4.83 .13
2
LE
.38
MIN. 1
(tighter tolerance available) (.015) (.060) (.190 .005)
2.54 2.54
1.27 0.1
Absolute Minimum Resistance (.050 .004) 9.53
(.100) (.100)
............................ 1 % or 2 ohms max. (.375)
(whichever is greater) 2.54 3296Z
Contact Resistance Variation (.100)
ADJ. SLOT
1.27 0.1 1.14
(.050 .004) 2.54 (.045)
......................... 1.0 % or 3 ohms max. 2.54
2.19 DIA.
PL AR
(.100)
IA E
OM S E
*
(.100) 3
C ION FRE
NT
(whichever is greater) (.086)
HS RS D 2
.51 .03 DIA. .56
Adjustability
Ro VE LEA
X WIDE
(.020 .001) (.022) 1
2.54
Voltage................................... 0.01 % X
.76
DEEP (.100)
2.54
(.100)
Resistance............................. 0.05 % (.030)
2.41 .25
(.095 .010)
REV. 05/16
Trimpot is a registered trademark of Bourns, Inc.
Specifications are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specific applications.