A Seminar Report on FPGA Based Design and Development of

Distributed Arithmetic Control System.

Submitted by: Abdul Hafeez Sajid

Guide: Prof. D.G. Chougule

 Certificate

This is to certify that Mr. ABDUL HAFEEZ SAJID has satisfactorily

presented a seminar on the topic “FPGA BASED DESIGN AND
DEVELOPMENT OF DISTRIBUTED ARTHIMETIC CONTROL
SYSTEM” in partial fulfillment of the requirements of M.Tech-II Sem-III
(Electronics Technology) of Electronics Technology Department of Shivaji
University Kolhapur, during academic year 2008-2009.

Seminar Guide Head of Department

Prof. D.G. Chougule Prof. S.R. Sawant

 Acknowledgement

I wish to express my thanks to Prof. S.R. Sawant Head, Department of

Electronics Technology, Shivaji University, Kolhapur for giving me an opportunity to

present a seminar on “FPGA Based Design and Development of

Distributed Arithmetic Control System”.

I am thankful to Prof. D. G. Chougule for guiding and helping me in

preparation of seminar.

Last but not least I am thankful to Mr. M Sultan M Siddiqui, Research Scholar

IIT Delhi, for guiding me to present the seminar.

At last I am thankful to everyone who directly or indirectly helped me in making

my efforts successful.

A.H.Sajid
Contents

1. Abstract
2. Introduction
3. Importance of PID & its Application
4. Digital Implementation of PID
5. Advantages of Using FPGA over other Digital Techniques
6. PID Implementation using DA Algorithm
7. FPGA Architecture
8. FPGA Design Flow
9. Proposed Experimental Setup
10. Advantages of the Approach
11. Conclusion
12. References
Abstract
Introduction
A control system seeks to make a physical system output track a desired reference
input by setting physical system input. Designing a control system in not easy. The
objective of a control system design is to make a physical system behave in a useful
fashion, in particular, by causing its output to track a desired reference input even in
the presence of measurement noise, model error and disturbances.

e(t) u(t)
þ Physical
Controller
System
y(t)

Measurement
System
Figure: Block Diagram of a Control System.

Controller
In a control system, one of the main components is the controller (control element). It
is the component required to generate the appropriate control signal applied to the
physical system. It measures the error or difference between the output and the
desired output. The output signal of controller regulates the system performance.
Many a times the function of a controller is to obtain the desirable characteristics
avoiding undesired characteristics.

Controller Types
1. Continuous Controller
The most common controller action used in process control is one or a
combination of contino
i. Proportional Controller
ii. Integral Controller
iii. Derivative Controller
2. Discontinuous Controller
i. Two-Position Controller
ii. Multi-position Controller
 3. Composite Controllers
i. Proportional-Integral Controller
ii. Proportional-Derivative Controller
iii. Proportional-Integral-Derivative Controller

 PID- (Proportional- Integral- Derivative )

It is one of the most commonly used type of controller in dynamic control systems, which
provides proportional, integral, and derivative compensation to an existing system.

P Control– Increases gain margin & stabilizes the unstable system.

I Control– Minimizes Steady State error.
D Control– Increases System Speed by increasing system Bandwidth.

It does not need a precise analytical model of the system that is being controlled.
Used in many different areas, such as aerospace, process control, manufacturing,
robotics, automation, and transportation system.

Drawback– Overall System Complexity increases.

Digital Implementation of PID

Two approaches for implementing control systems using digital technology.

1. Based on software which implies a memory-processor interaction.
Ex: PLCs, microcontrollers, microprocessors, DSPs, and general purpose
computers are tools for software implementation.
2. Based on Hardware.
Ex: Digital Logic & MSI Components, ASIC & FPGA.
FPGA Implementation of PID
1. Conventional Approach–
Use of Multipliers & Adders.
Requires large area on chip
Consumes more power.
2. Use of DA Algorithm—
Is an efficient LUT design method
Uses only 13% of logic devices on
FPGA
Power consumption is reduced by 40%
Advantages of Using FPGA over other Digital Techniques
1. They ensure ease of design.
2. Lower development costs.
3. More product revenue, and the opportunity to speed products to market.
4. Real time processing Capability.
5. They are superior to software-based controllers as they are
 6. More compact,
7. Power-efficient, while adding high speed capabilities.
8. Another advantage of FPGA-based platforms is their capability to execute
concurrent operations, allowing parallel architectural design of digital controllers.
Distributed Arithmetic Algorithm
Distributed arithmetic is a bit level rearrangement of a multiply accumulate to hide the
multiplications.
Basically it is a bit serial computation operation that forms an inner product of a
pair of vectors in a single direct step
Arithmetic operations are not lumped but are distributed in an often
unrecognizable fashion.
Advantages of DA
• It is a powerful technique for reducing the size of a parallel hardware multiply-
accumulate that is well suited to FPGA designs.
• DA Algorithm uses only 13% of logic devices of FPGA to implement PID
functionality compared to the design using multiplier.
• With DA power consumption is reduced by 40%(for PID).

Concept of DA

 In this case we feed four parallel scaling accumulators with unique serialized data.
 Each multiplies that data by a possibly unique constant, and the resulting products
are summed in an adder tree.

Fig: Parallel multiply-accumulate based on Scaling Accumulator

Fig: Rearranged circuit
• Here, the adder tree combines the 1 bit partial products before they are
accumulated by the scaling accumulator.
• Rearranged the order in which the 1xN partial products are summed.
• Instead of individually accumulating each partial product and then summing the
results, first we sum all the 1xN partials & then accumulate at a particular bit
time.
• Effectively replaces N multiplies followed by an N input add with a series of N
input adds followed by a multiply.
• This arithmetic manipulation directly eliminates N-1 multipliers in an N product
term multiply-accumulate function. For larger numbers of product terms, the
savings becomes significant.
• If the coefficient Cn is a constant, then the adder tree becomes a Boolean logic
function of the 4 serial inputs.
• The combined 1xN products and adder tree is reduced to a four input look up
table, which further reduces hardware resource.
• Drawback of DA—
• Slowness as it is a bit-serial nature.
• Remedy—
• Use of bit paring technique
• Partitioning the input word into Half MSB & Half LSB i.e.
introducing the parallelism.

 Consider

1.

Where Ak = Fixed coefficients

Xk = Input data

If each Xk is a 2’s compliment binary number such that Xk is less than 1 then
 2.

Where the bkn are the bits, 0 or 1, bk0 is the sign bit, bk N-1 is the LSB.

Combining equation 1 & 2 we get

3.
Equation 3 defines Lumped Arithmetic Computation
Let change the order of Summation we get

4.

Equation 4 defines Distributed Arithmetic Computation.

Consider the bracketed term in Equation 4

5.

Since bkn can take 0 & 1 only therefore Equation 5 have 2k possible values
Rather than computing these values online, we pre-compute them & store in ROM. The
I/P data can be used directly address the memory & the result of equation 5 can be
dropped directly into an accumulator.
After N cycles the memory contains the result y.

Consider an example with K=4, A1= 0.72, A2 = -0.3,A3= 0.95, A4= 0.11.
The memory must contains all possible 24 combinations. As a consequence we need to
use 2* 24 word ROM.
PID Implementation Using DA Algorithm

The simplest form of the PIDcontrol algorithm is given by

u(t) = KP e + KI Int(0-t) e(τ )dτ + KD ė + offset 1

Problems with this implementation are

1. Sluggish transient response. (coz of I)

2. Detoriation of Command signal due to noise. (coz of D).
3. Spikes in Command signal (coz of D)

Therefore we use a modified PIDcontrol algorithm that overcomes the above problems &
is given in laplace domain as
U(s) = K(bUc(s)−Y(s)+(1/sTi)(Uc(s)−Y(s))−(sTd/1+sTd/N)Y(s)) 2

Where K, b, Ti , Td , and N are controller parameters, and

U (s), Uc (s), and Y (s) denote the Laplace transforms of u, uc ,& y, respectively.

To implement the control algorithm using digital technology, equation (2) has to be
discretized.

Let T be the sampling period, and using backward differences to discretize the derivative
term and forward differences for the integral term, we get
u(kT ) = P (kT ) + I(kT ) + D(kT ) 3

where k denotes the k-th sampling instant

P (kT ) = K(bu(kT ) − y(kT ))

I(kT)=I((k−1)T)+(KT/Ti)(u((k−1)T)−y((k− )T))

D(kT)=(Td/Td+NT)D((k−1))−(KTdN/Td+NT)(y(kT)−y((k−1)T)) 4

where,
y(kT) is the output of the system at the current instant,
y((k −1)T) is the output of the system at the previous instant,
uc (kT ) is the desired output of the system,
I((k − 1)T ) is the integral term at the previous instant,
D((k − 1)T ) is the derivative term at the previous instant, and
K, b, Ti , Td , N are controller parameters,
The direct(Multiplier & Adder/Substractor) Implementation of above algorithm us
5 Multipliers 5 Adders/Substractors 4 Delay blocks
i.e.
P(kT) uses 2 Multipliers & 1 Adder/Substractor
I(kT) uses 1 Multipliers & 2 Adder/Substractor
D(kT) uses 2 Multipliers & 2 Adder/Substractor

Since Multiplier -Based Design uses many Multipliers & Adders, in order to reduce the
number of Multipliers & Adders we use DA Algorithm for PID Implementation.
Let us consider the controller terms given in Equation 4.
Assume that u(kT), u((k-1)T), y(kT) & y((k-1)T) are M-bit numbers & [j] represents the
jth bit of number then

We have
m−1
P(kT) = Ʃ (Kb×u(kT)[ j]−K × y(kT)[ j]) × 2j 5
j=0

m−1
I(kT) = Ʃ (I((k−1)T)[ j] + (KT/Ti)(u((k−1)T)[ j] − y((k−1)T)[ j])) × 2j 6
j=0

m−1
D(kT ) = Ʃ ((Td/Td+NT)D((k−1)T)[ j] −(KTd N/Td + NT)((y(kT )[ j] −y ((k−1) T )
j=0 [ j]) × 2 j)) 7

The results of
(Kb×u(kT)[ j]−K × y(kT)[ j]),
I((k−1)T)[ j] + (KT/Ti)(u((k−1)T)[ j] − y((k−1)T)[ j]))((Td/Td+NT)
D((k−1)T)[ j] −(KTdN/Td + NT)((y(kT )[ j]−y((k−1)T)[ j]) × 2 j)) can be pre-computed
& the result can be stored in 3 LUT's namely LUTp, LUTi, & LUTd.
Using the 3 LUTs and the corresponding shift-add accumulators (ACCs), the P (kT),
I(kT), and D(kT) terms can be obtained in m clock cycles.
Main advantage of the DA expression given by (5), (6) and (7) lies in its capability to
compute the PID function utilizing the LUT-rich FPGA.

Based on the above Equations the DA Implementation of PID Controller is shown in Fig
It consists of 4 delay blocks, 3 LUT's, 3 ACC's & 2 Adders.
i.e.
3 LUTS's & 3 ACC's for P(kT),I(kT) & D(kT).
ACC consists of shift register & adder
2 Adders to produce sum of P(kT),I(kT) & D(kT).

Speed of this PID is M+1 clock cycles i.e. M clock cycles to generate the result & 1 clock
cycle to update the I((k−1)T) and D((k−1)T) terms.

FPGA Architecture
The typical FPGA consists of the following components:
1. Programmable Logic blocks
2. Interconnection Resources
3. Input output blocks

The general schematic of an FPGA is as shown in the figure :

Programmable Logic Block

The programmable logic block in a typical FPGA consists of Configurable

Logic Blocks (CLB).

The CLB can be realized in many ways; one of them being the Look Up Table (LUT)
based CLB.
The LUT is a one bit wide memory location . The memory address lines are the inputs to
the LUT and the one bit output is the LUT output. Thus the LUT with K-inputs acts as a
2k by 1 bit memory and the user can directly implement any k input function by
programming the functions truth table into the LUT
Fig: Xilinx FPGA CLB Schematic

Interconnect Resources

The interconnect resources in an typical FPGA can be classified as :

1. General Purpose Interconnects
2. Direct Interconnects
3. Long Lines

Input Output Blocks (IOB)

The IOB provides the interface between the FPGA and the real world signals.

The IOB consists broadly of I/O pads.

DA-based PID controller is to be implemented using the Xilinx Inc. FPGA technology.
ie. SPARTAN IIE Xc2s200e-FT256

The FPGA design flow is as follows:

1. Controller is implemented using pico blaze a soft processor developed by xilinx.

2. Simulation at RTL level to verify the correctness of design.

3. Place & route is done automatically to generate FPGA implementation file.
4. Finally the generated implementation file was downloaded to the FPGA development
board for testing.

Proposed Experimental Setup

• The FPGA-based temperature control system that is shown in Fig.

1) A tube with a fan, a light bulb, and a thermistor;

2) An I/O panel
3) An ADC chip (Maxim MAX189 12-bit ADC)
4) FPGA development board consisting a Xilinx Spartan-2E FPGA

Conclusion
 The proposed PID controller reduces the cost of the FPGA design.
 Due to the flexibility of the LUT in the FPGA, this FPGA-based PID controller
can be easily extended to incorporate other algorithms,
 This design approach would specifically be suitable for the next generation of
FPGA chips, in which ADC and D/A converter are built inside the chip.
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 www.google.com