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1.

Data-flow models can be implemented as:

Select one:
a. Hardware only
b. Software only
c. Hardware and Software
d. Neither Hardware nor Software
e. Firmware only

2. Cycle based Hardware modeling is called register-transfer-level modeling. This modeling


is done through Hardware Description Languages (HDL's). Tick the HDLs.

Select one or more:


a. C and C++
b. VHDL
c. SystemC
d. Pascal, Fortran
e. Verilog, SystemVerilog

3. Basic goals of Hardware / Software co-design are:

Select one or more:


a. Performance goals
b. Area goals
c. Power goals
d. People goals
e. Business Goals -- Time to Market and Cost

In HSCD, we are interested in programmable components. Some examples of Programmable


components are:-

Select one or more:


a. Graphics Processor (GPU)
b. RISC or CISC microprocessor
c. Application Specific Instruction Set Processor (ASIP)
d. Field Programmable Gate Array (FPGA)
e. Digital Signal Processor (DSP)

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space
A Hardware Designer solves problems by decomposition in . (Hardware Gogles)
time
A Software Designer solves problems by decomposition in mposition in .
(Software Gogles)

flexibility
Software excels over Hardware in support of

Question text

The control flow graph as above represents:

Select one:
a. CFG of a while loop
b. CFG of a case statement
c. CFG of a do-while loop
d. CFG of a for loop
e. CFG of a if-then-else
Select one:
a. CFG of for loop
b. CFG of if-then-else
c. CFG of do-while loop
d. CFG of while loop
e. CFG of counter

A Control Flow Graph (CFG) as below represents:


Select one:
a. CFG of do-while
b. CFG of 4bit Multiplier
c. CFG of if-then-else
d. CFG of for loop
e. CFG of while loop
Select one:

a. An if-then-else
b. CFG of 4bit Multiplier
c. A do-while loop
d. A while loop
e. A for loop

A typical 5 stage RISC pipeline has the ordering as:

Select one:
a. Instruction fetch, Instruction decode, Execute, Buffer, Write-back
b. Instruction fetch, Buffer, Instruction decode, Execute, Write-back
c. Buffer, Execute, Instruction fetch, Buffer, Execute
d. Execute, Write-back, Instruction decode, Instruction fetch, Buffer
e. Write-back, Execute, Instruction decode, Buffer, Instruction fetch

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If there are 'm' programming languages and 'n' different processor architectures, the minimum
number of programs needed are 'm+n'.

Select one:
True
False

Different front-end phases in a compiler are:

Select one or more:


a. Optimization of IRs
b. Parsing
c. Scanning
d. Semantic Analysis
e. code emission

The back-end phases in a compiler are:

Select one or more:


a. Loading
b. Code Emission
c. Instruction Selection from IR to assembly
d. Code optimization
e. Linking

Tools used by the Architecture Team are:-

Select one or more:


a. Processor related compilers
b. Editors, Word processors
c. SystemVerilog, SystemC compiler & simulator
d. Tools for Partitioning HW/SW
e. Design Rule Checkers

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Tools used by Logic Designer are:

Select one or more:


a. Design rule checkers
b. Gate level simulation tool
c. Logic Synthesis tool
d. Floorplanning tools
e. System Simulator (System C, System Verilog)

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Tools used by Backend (Circuit Designer, Physical Designer, Mask Designer) Team are:

Select one or more:


a. Design Rule Checkers
b. Floorplanning Tools
c. SystemC simulator
d. Timing Analyzers
e. Place and Route Tools

Which of these is a computation optimization problem:

Select one or more:


a. Selecting communication modes and interconnect mechanisms
b. Allocating Tasks to processors
c. Tuning instruction sets of processors, and processor memories
d. Measuring traffic and optimizing communication mechanisms
e. Parallelizing tasks across processors

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The digital abstraction converted an analog voltage to one of two discrete values. The cycle
abstraction does the same for time. We throw away analog time (usually measured in
nanoseconds), and instead count time in terms of cycles of a clock.

Select one:
True
False

For a real time clock, typically the oscillator's frequency is 32.768 kHz because:-

Select one:
a. frequency is exactly 215 cycles per second
b. clock based counters wont work at other frequencies
c. oscillators cannot be produced below 32.768kHz
d. oscillator is unstable at other frequencies
e. the oscillator at 32.768kHz can be produced in any technology node from 250nm to 28nm
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