Code: R7220404 R07

B.Tech II Year II Semester (R07) Supplementary Examinations May/June 2015

SWITCHING THEORY & LOGIC DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 80

Answer any FIVE questions

All questions carry equal marks
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1 Construct a 7 - bit single error correcting code to represent the decimal digits by using excess - 3 code
word using even parity checks. Using an example explain the process of error detection and correction.

2 (a) Realize the function F = A(B+CD) + BC using minimum number of NAND gates only.
(b) Simplify the following expression using Boolean theorems:
(A+B+C) (B+C) + (A+D) (A+C).

3 (a) Minimize the following function F(A,B,C,D) = m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14)

(b) Simplify the Boolean expression F = M(0, 1, 3, 5, 6, 7, 10, 14, 15).

4 (a) Design an excess-3 to binary decoder using the unused combinations of the code as dont care
condition.
(b) Draw the logic diagram of a 2 x 4 line decoder using NOR gates only.

5 (a) Draw the internal construction of PLA having three inputs, three product terms and two outputs.
(b) Derive the PLA programming table for the combinational circuit that squares a 3-bit number and also
minimize the number of product terms.

6 (a) Design a modulo-32 ripple counter using JK flip-flops.

(b) Draw the circuit of a decade ripple counter using four flip-flops and explain it working with a table
showing the counting sequences.

7 (a) State the capabilities and limitations of finite state machine.

(b) For a machine given below find the equivalence partition and a corresponding reduces in standard form.
N.S
P.S
X=0 X=1
A D,0 H,1
B F,1 C,1
C D,0 F,1
D C,0 E,1
E C,1 D,1
F D,1 D,1
G D,1 C,1
H B,1 A,1

8 (a) Obtain the ASM chart for the following state transition: if x = 0, control goes from state T1 to T2 ; if x = 1,
generate a conditional output F and go from T1 to T2.
(b) Explain the data path subsystem implementation for weighing machine using ASM chart.

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