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Functional Description
PART NUMBER TYPE rON
HI-5042 SPDT 50
HI-5047 4PST 50
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-5042 thru HI-5051
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. #
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts (SWITCHES SHOWN FOR LOGIC 0 INPUT) Pinouts (SWITCHES SHOWN FOR LOGIC 0 INPUT)
D1 1 16 S1 D2 1 16 S2 D1 1 16 S1 D1 1 16 S1
2 15 A 2 15 A 2 15 A1 2 15 A1
D2 3 14 V- D1 3 14 V- D3 3 14 V- D3 3 14 V-
S2 4 13 VR S1 4 13 VR S3 4 13 VR S3 4 13 VR
5 12 VL S4 5 12 VL S4 5 12 VL S4 5 12 VL
6 11 V+ D4 6 11 V+ D4 6 11 V+ D4 6 11 V+
7 10 7 10 7 10 A2 7 10 A2
8 9 D3 8 9 S3 D2 8 9 S2 D2 8 9 S2
NOTE: Unused pins may be internally connected. Ground all NOTE: Unused pins may be internally connected. Ground all
unused pins. unused pins.
2
HI-5042 thru HI-5051
3
HI-5042 thru HI-5051
Schematic Diagrams
V+
P15 P16
VL
P14
35A
R3 QN1
R6
N13 QP1
QP3 QP4
100A
25A
25A
25A
R4
QP5 QP6
P13
QP8 V+
25A
TO VR
16A
R5
25A
R2
QP7 QN2 R7
VR
QP2
V-
N14 N15
N16
to VL
NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT (NOTE)
A1 (A2)
N1
V+
IN N3 OUT
P2
N2
V-
P1
A1 (A2)
SWITCH CELL
V+
P3
P5
V+ P1
P4
N1
P8 P9 P10 P11 P12
P6 P7
D1 A1
R4 VR' A1
A
200 VL' A2
D2 A2
N6 N7 N8 N9 N10 N11 N12
P2
V-
N4
N2
N5
N3
V-
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
4
HI-5042 thru HI-5051
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL = 5V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded
-2 -5, -9
TEST TEMP
PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS
Switch ON Time, tON (Note 5) 25 - 370 500 - 370 500 ns
Switch OFF Time, tOFF (Note 5) 25 - 280 500 - 280 500 ns
Charge Injection, Q (Note 3) 25 - 5 20 - 5 - mV
OFF Isolation (Note 4) 25 75 80 - - 80 - dB
Crosstalk (Note 4) 25 -80 -88 - - -88 - dB
Input Switch Capacitance, CS(OFF) 25 - 11 - - 11 - pF
Output Switch Capacitance, CD(OFF) 25 - 11 - - 11 - pF
Output Switch Capacitance, CD(ON) 25 - 22 - - 22 - pF
Digital Input Capacitance, CA 25 - 5 - - 5 - pF
Drain To Source Capacitance, CDS(OFF) 25 - 0.5 - - 0.5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL Full - - 0.8 - - 0.8 V
Input High Threshold, VAH Full 2.4 - - 2.4 - - V
Input Leakage Current (High or Low), IA Full - 0.01 1.0 - 0.01 1.0 A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range Full -15 - +15 -15 - +15 V
ON Resistance, rON
HI-5042 to HI-5047 (Note 2) 25 - 50 75 - 50 75
Full - - 150 - - 150
HI-5049, HI-5051 (Note 2) 25 - 25 45 - 25 45
Full - - 50 - - 50
Channel-to-Channel Match, rON
HI-5042 to HI-5047 25 - 2 10 - 2 10
HI-5049, HI-5051 25 - 1 5 - 1 5
5
HI-5042 thru HI-5051
Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL = 5V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
Unused Pins are Grounded (Continued)
-2 -5, -9
TEST TEMP
PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS
OFF Input or Output Leakage Current, 25 - 0.8 2 - 0.8 2 nA
IS(OFF) = ID(OFF)
Full - 100 200 - 100 200 nA
ON Leakage Current, ID(ON) 25 - 0.01 2 - 0.01 2 nA
Full - 2 200 - 2 200 nA
POWER REQUIREMENTS
Quiescent Power Dissipation, PD 25 - 1.5 - - 1.5 - mW
I+, I-, IL , IR 25 - - 0.2 - - 0.3 mA
I+, +15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
I-, -15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IL , +5V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
IR , Ground Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA
NOTES:
2. VOUT = 10V, IOUT = 1mA.
3. VIN = 0V, CL = 10nF.
4. RL = 100, f = 100kHz, VIN = 2.0VP-P , CL = 5pF.
5. VAL = 0V, VAH = 5V.
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified
1mA
V2
rON = V2
1mA
IN OUT
VIN
80
1.2
NORMALIZED ON RESISTANCE
60 1.1 VIN = 0V
(REFERRED TO 25oC)
ON RESISTANCE ()
V+ = +12V
V- = -12V 1.0
V+ = +10V
40 V- = -10V
0.9
0.8
20 V+ = +15V
V- = -15V
0.7
0 0.6
-15 -10 -5 0 5 10 15 -50 -25 0 25 50 75 100 125
ANALOG SIGNAL LEVEL (V) TEMPERATURE (oC)
FIGURE 1B. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 1C. NORMALIZED ON RESISTANCE vs TEMPERATURE
FIGURE 1. ON RESISTANCE
6
HI-5042 thru HI-5051
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
100nA OFF LEAKAGE CURRENT
IS(OFF) ID(OFF)
IN OUT
A A
10nA IS(OFF) = ID(OFF)
LEAKAGE CURRENT
10V 10V
ON LEAKAGE CURRENT
1nA
IN OUT
ID(ON)
100pA
A ID(ON)
10pA 10V
25 50 75 100 125
TEMPERATURE (oC)
1.4
NORMALIZED ON RESISTANCE
1.3
(REFERRED TO 1mA)
1.2
IN OUT
I
VIN
1.1
V IN
r ON = ---------
I
1.0
0 20 40 60 80
ANALOG CURRENT (mA)
200
IN
OFF ISOLATION (dB)
OUT
160 VOUT
VIN
50
RL = 100 2VP-P RL
120
80
V IN
RL = 10k OFF ISOLATION = 20 Log ----------------
40 V OUT
7
HI-5042 thru HI-5051
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
-200
SWITCHED
CHANNEL
CROSSTALK (dB)
-160
VIN
50 VOUT RL
-120 2VP-P
RL = 100
RL
-80
RL = 10k RL = 1k
-40
V OUT
CROSSTALK = 20 Log ----------------
0 V IN
1 10 100 1K 10K 100K 1M
FREQUENCY (Hz)
200
POWER CONSUMPTION (mW)
160 +10V
-10V
A
120 TOGGLE
AT 50%
DUTY VL VR V+ V-
80
IL I+ I-
40
+5V +15V -15V
0
1K 10K 100K 1M
TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz)
VAH
VA
VA
tON
tOFF
8
HI-5042 thru HI-5051
Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH = 3V and VAL = 0.8V
Unless Otherwise Specified (Continued)
VA
VA
OUTPUT OUTPUT
VA = 0V to 5V VA = 0V to 10V
Vertical: 2V/Div. Vertical: 5V/Div.
Horizontal: 200ns/Div. Horizontal: 200ns/Div.
FIGURE 7C. WAVEFORMS WITH TTL COMPATIBLE LOGIC FIGURE 7D. WAVEFORMS WITH CMOS COMPATIBLE LOGIC
INPUT INPUT
720 720
660 660
600 600
540 540
INPUT)
INPUT)
480 480
420 420
(NEED
tON
(NEED
FIGURE 7E. SWITCHING TIMES vs POSITIVE DIGITAL VOLTAGE FIGURE 7F. SWITCHING TIMES vs NEGATIVE DIGITAL VOLTAGE
FIGURE 7. SWITCH tON AND tOFF
9
HI-5042 thru HI-5051
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
10
HI-5042 thru HI-5051
11
HI-5042 thru HI-5051
12
HI-5042 thru HI-5051
SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE L c1 0.008 0.015 0.20 0.38 3
S1 D - 0.840 - 21.34 5
A A eA
b2 E 0.220 0.310 5.59 7.87 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A-B S D S aaa M C A - B S D S eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 -
ed adjacent to pin one and shall be located within the shaded Q 0.015 0.060 0.38 1.52 6
area shown. The manufacturers identification shall not be used
S1 0.005 - 0.13 - 7
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be 90o 105o 90o 105o -
measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 -
solder dip or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3
partial lead paddle. For this configuration dimension b3 replaces N 16 16 8
dimension b2.
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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