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ISL98604 Features
The ISL98604 is a high power, fully programmable 6-Channel 8V to 16.5V input supply
output control IC targeted at large panel LCD displays. The AVDD boost up to 19.0V, with integrated 4.0APEAK FET
ISL98604 integrates a high power, boost converter and delay
HAVDD synchronous buck for 8V with 1APEAK FET
switch for AVDD generation, one VIO asynchronous buck
regulator, two synchronous buck regulators for HAVDD and Overvoltage protection (OVP)
VCORE supply generation, and linear regulator controllers for VON Internal AVDD delay FET
and VOFF charge pumps. Dual linear regulator controllers for VON and VOFF
Operating at 750kHz, the AVDD boost converter features a 4.0A VON temperature compensation
boost FET and 6-bit resolution programmable from 12.7V to VIO buck with integrated 2APEAK FET
19.0V. The delay switch is also integrated for power sequence.
VCORE synchronous buck with integrated 1APEAK FET
The asynchronous buck converter for VIO supply features an Internal feedback and compensation
integrated 2A FET. It also operates at 750kHz internal clock and
compensation features. Programmable output control with IIC
Programmable sequencing with IIC
The two synchronous bucks are integrated with controller,
upper, and lower side switches for HAVDD and VCORE UVLO and OTP protection
generation with internal compensation. The HAVDD and Thermally enhanced 5x5 Thin QFN package
VCORE outputs are both programmable ranging from 6.4V to Pb-free (RoHS compliant)
9.55V and 0.9V to 2.4V, respectively.
Dual linear regulator controllers are provided to allow generation Applications
of accurate VON and VOFF voltages in conjunction with external LCD TV
charge pumps and bipolar power transistors. VON output voltage
can be compensated adoptively by temperature sensing.
All output voltages are programmed through IIC and stored in
EEPROM. Alternative factory set voltages are available for
ISL98604; please contact Consumer Product Marketing via email
at Consumer-All@intersil.com.
Pin Configuration
ISL98604
(40 LD 5x5 TQFN)
TOP VIEW
PHASE2
PGND4
PVIN1
PVIN2
SWB2
SWB1
VIO
NC
NC
NC
40 39 38 37 36 35 34 33 32 31
EN 1 30 VCORE
TCOMP 2 29 SDA
VDC 3 28 SCL
AGND 4 27 A0
AVIN 5 THERMAL 26 PG
PVIN3 6 PAD 25 NC
NC 7 24 DRVN
PHASE1 8 23 NC
HAVDD 9 22 FBN
PGND3 10 21 FBP
11 12 13 14 15 16 17 18 19 20
SS
COMP
SWO
DRVP
SWIN
NC
SW2
SW1
PGND2
PGND1
December 17, 2012 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN7687.0 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL98604
Typical Application Circuit
VIN: 12V L1 SS34 AVDD: 16V
4.7H LX D1 12.7V~19.0V
8V~16.5V
PVIN1 SW1
PVIN2 SW2
SWIN
VIO: 3.3V L2 SWB1
6.8H SWO
3.0V~3.7V
SWB2 R01
COMP AVDD
C11 5.6k
D11 C01
20F PGND1 BAT54S
SS33 15nF LX
D61 0
VIO C63
PGND2 R64
1F
C64
SS 0.1F
C05
47nF
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ISL98604
Block Diagram
AGND VIO COMP
SWO
SW1
FOSC SW2
PVIN1 750kHz
S
Q
REF R
PVIN2
FOSC
PGND1
750kHz SLOPE
S COMPENSATION
Q PGND2
SWB1 R
SWIN
SWB2
DELAY
FET
PGOOD SWO
PG
MONITORING
VON
LINEAR DRVP
EN REGULATOR
CONTROL FBP
SS
2
I C INTERFACE EEPROM
AND
SCL TCOMP
SEQUENCE
CONTROL 4.5V REF
SCA REGULATOR
A0 VOFF
DRVN
LINEAR
REGULATOR FBN
VDC CONTROL
AVIN
VCORE HAVDD
PVIN3
VIO
FOSC FOSC
3MHz REF REF 1MHz
S S
Q Q
Q R R Q
PHASE2 PHASE1
AVIN AVIN
PGND4 PGND3
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ISL98604
Pin Descriptions
PIN # SYMBOL DESCRIPTION
2 TCOMP Temperature compensation input, connect NTC resistor in the resistor ladder from VDC to GND to set the curve of VON vs
temperature.
3 VDC Internal linear regulator output, connected to external 1F capacitor close to the pin.
5 AVIN Internal regulator supply pin; connect to external 10F capacitor close to the pin.
6 PVIN3 HAVDD buck power input pin; connect to external 10F capacitor close to the pin.
7, 19, NC Not connected.
23, 25,
34, 37,
40
8 PHASE1 HAVDD buck switch node; connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
9 HAVDD HAVDD buck output feedback input pin.
11 SS AVDD boost and HAVDD buck soft-start timing capacitor connection for step-up.
12 COMP AVDD boost compensation pin; connect a 5.6k resistor and 15nF capacitor in series to the pin.
17 SWIN AVDD delay FET input, connect a 10F capacitor close to the pin.
18 SWO AVDD delay FET output, connect a 22F capacitors close to the pin.
20 DRVP Positive charge pump LDO transistor driver, connect the base of an external PNP bipolar to the pin.
24 DRVN Negative charge pump LDO transistor driver, connect the base of an external NPN bipolar to the pin.
32 PHASE2 VCORE buck switch node, connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
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ISL98604
Ordering Information (Note 1)
NOTES:
1. For availability and lead time of devices with voltage and power-on timing combinations not listed in the table, please contact Intersil Marketing via
email at Consumer-All@intersil.com.
2. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL98604. For more information on MSL please see techbrief TB363.
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ISL98604
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HAVDD Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VIO Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCORE Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VON Linear-Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VOFF Linear-Regulator Controller and Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Calculation of the Linear Regulator Base-Emitter Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VON/VOFF Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VON Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Start-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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ISL98604
Absolute Maximum Ratings (TA = +25C) Thermal Information
DRVP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +45V Thermal Resistance (Typical) JA (C/W) JC (C/W)
FBP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V 5x5 TQFN Package (Notes 5, 6) . . . . . . . . . 32 2.4
FBN to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -10V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150C
SW1, SW2, SWI, and SWO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
PVIN1, PVIN2, AVIN, SWB1, SWB2, PHASE1, PHASE2, HAVDD, and EN to Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18.6V http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DRVN, VDC, VCORE, SS, PGOOD, SCL, SDA, and A0
to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Voltage between AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Recommended Operating Conditions
All other pins to GND, AGND and PGND . . . . . . . . . . . . . . . . -0.5V to +5.5V Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
ESD Rating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 16.5V
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . 750V
Latch Up (Tested per JESD-78B; Class II, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech
Brief TB379.
6. For JC, the case temp location is the center of the exposed metal pad on the package underside.
Electrical Specifications VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40C to +85C, unless otherwise noted.
MIN MAX
SYMBOL PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
SUPPLY PINS
PVIN +SUP Supply Voltage 8 12 16.5 V
IVIN +SUP Supply Current when Enabled EN = VDC, no loading on all channels 8 mA
IEN Enable Input Bias Current EN = 0 0.01 0.1 A
EN = VDC 10 15 A
ISWPL_AVDD Switch Peak Current Limit Boost Peak Current limit 3.5 4 4.5 A
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Electrical Specifications VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40C to +85C, unless otherwise noted. (Continued)
MIN MAX
SYMBOL PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
ISWLK_ DLY Leakage Current When Disabled VIN = 16.5V, VSWIN = 19V, VSWO = 0V, 5 20 A
EN = 0V
DVHAVDD/DVIN Line Regulation 9.5V < PVIN < 13.5V, ILOAD = 200mA 0.3 %
VIO BUCK
DVVIO/DVIN Line Regulation 9.5V < PVIN < 13.5V, ILOAD = 200mA 0.3 %
VCORE BUCK
VCORE Output Voltage Range Internal feedback 0.9 1.0 2.4 V
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Electrical Specifications VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40C to +85C, unless otherwise noted. (Continued)
MIN MAX
SYMBOL PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
DVVCORE/DVIN Line Regulation of VCORE Buck 9.5V < PVIN < 13.5V, ILOAD = 200mA 0.1 %
DVVCORE/DIOUT Load Regulation of VCORE Buck 200mA < ILOAD < 500mA 0.3 %
High temperature 17 26 32 V
ACCVON Output Voltage Accuracy VON = 28V -2.1 2.1 %
VOFF LDO
ILEAK_DRVN DRVN Off Leakage Current VFBN = 0.5V, VDRVN = -6V 0.1 10 A
LOGIC INPUTS
EN 1.6 V
EN 0.675 V
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ISL98604
Electrical Specifications VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40C to +85C, unless otherwise noted. (Continued)
MIN MAX
SYMBOL PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
I2C
tiN (Note 8) Pulse Width Suppression Time at SDA and SCL Any pulse narrower than max spec is 50 ns
Inputs suppressed
tAA (Note 8) SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VO_LDO, 900 ns
until SDA exits the 30% to 70% of VO_LDO
window
tBUF (Note 8) Time the Bus Must Be Free before the Start of a New SDA crossing 70% of VO_LDO during a STOP 1300 ns
Transmission condition, to SDA crossing 70% of VO_LDO
during the following START condition
tLOW (Note 8) Clock LOW Time Measured at the 30% of VO_LDO crossing 1300 ns
tHIGH (Note 8) Clock HIGH Time Measured at the 70% of VO_LDO crossing 600 ns
tSU:STA (Note 8) START Condition Setup Time SCL rising edge to SDA falling edge. Both 600 ns
crossing 70% of VO_LDO
tHD:STA (Note 8) START Condition Hold Time SDA falling edge crossing 30% of VO_LDO to 600 ns
SCL falling edge crossing 70% of VO_LDO
tSU:DAT (Note 8) Input Data Setup Time From SDA exiting the 30% to 70% of VCC 100 ns
window, to SCL rising edge cross 30% of VCC
tHD:DAT (Note 8) Input Data Hold Time From SCL falling edge crossing 70% of VCC 0 900 ns
to SDA entering the 30% to 70% of VCC
window
tSU:STO (Note 8) Stop Condition Setup Time From SCL rising edge crossing 70% of VCC, 600 ns
to SDA rising edge cross 30% of VCC
tHD:ST0 (Note 8) Stop Condition Hold Time From SDA rising edge to SCL falling edge. 600 ns
Both crossing 70% of VCC
tDH (Note 8) Output Data Hold Time From SCL falling edge crossing 30% of VCC, 0 ns
until SDA enters the 30% to 70% of VCC
window
tR (Note 8) SDA and SCL Rise Time Depend on Load 1000 ns
tSU:A (Note 8) nWR Condition Setup Time From nWR rising/falling edge crossing 600 ns
70/30% of VCC, to SDA falling edge cross
30% of VCC (START)
tHD:A (Note 8) nWR Data Hold Time From SDA rising edge crossing 70% of VCC 800 ns
(STOP) to nWR rising/falling edge crossing
70/30% of VCC window
nWR = 1 5 pF
tWP (Note 8) Non-volatile Write Cycle Time 12 20 ms
EEPROM
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Electrical Specifications VIN = 12V, EN = VDC, AVDD = 16V, VON = 28V, VOFF = -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply over the operating temperature range, TA = -40C to +85C, unless otherwise noted. (Continued)
MIN MAX
SYMBOL PARAMETER TEST CONDITIONS (Note 7) TYP (Note 7) UNITS
VUVLO Undervoltage Lock Out Threshold PVIN rising 7.2 7.5 7.9 V
tDLY2 Delay Time from VOFF to AVDD Start From 90% of VOFF 0 30 ms
tDLY3 Delay Time from AVDD to VON Start From 90% of AVDD 0 30 ms
POWER GOOD BLOCK
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Typical Performance Curves
95 0.04
94 VIN = 12V
0.02
93
91
90 -0.02
89
-0.04
88
87 -0.06
VIN = 12V
86 L = RLF7030T-4R7M3R4 -0.08
85 D = SS34
84 -0.10
0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 0.3 0.5 0.7 0.9 1.1
I_AVDD (A) I_AVDD (A)
0.01
IAVDD = 200mA AVDD RIPPLE (500mV/DIV)
0.01
LINE REGULATION (%)
0.00
-0.01
-0.01
IAVDD (100mA/DIV)
-0.02
-0.02
-0.03
9 10 11 12 13 14
VIN (V) VIN = 12V
FIGURE 3. AVDD BOOST LINE REGULATION FIGURE 4. AVDD BOOST TRANSIENT RESPONSE
100 0.04
VIN = 12V
90
0.02
80
LOAD REGULATION (%)
70 0.00
EFFICIENCY (%)
60 -0.02
50
-0.04
40
30 -0.06
20 VIN = 12V -0.08
10 L = RLF7030T-6R8M2R8
0 -0.10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.2 0.4 0.6 0.8
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Typical Performance Curves (Continued)
0.10
HAVDD RIPPLE (50mV/DIV)
IHAVDD = 200mA
LINE REGULATION (%)
0.05
0.00
IHAVDD (100mA/DIV)
-0.05
-0.10
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5
VIN (V)
FIGURE 7. HAVDD BUCK LINE REGULATION FIGURE 8. HAVDD BUCK TRANSIENT RESPONSE
90 0.05
VIN = 12V
85
LOAD REGULATION (%)
0.00
EFFICIENCY (%)
80
75 -0.05
70
VIN = 12V -0.10
65 L = RLF7030T-6R8M2R8
D = SS33
60 -0.15
0 0.5 1.0 1.5 2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
I_VIO (A) I_VIO (A)
FIGURE 9. VIO BUCK EFFICIENCY FIGURE 10. VIO BUCK LOAD REGULATION
0.04
IVIO = 200mA
0.03 VIO RIPPLE (50mV/DIV)
LINE REGULATION (%)
0.03
0.02
0.01
0.01
0.00
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 VIN = 12V
VIN (V)
FIGURE 11. VIO BUCK LINE REGULATION FIGURE 12. VIO BUCK TRANSIENT RESPONSE
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Test Circuits and Waveforms
95 0.04
93 VIN = 12V
0.02
91
87
-0.02
85
83 -0.04
81 -0.06
79
VIN = 12V -0.08
77
L = RLF7030T-2R2M5R4
75 -0.10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.2 0.3 0.4 0.5 0.6 0.7 0.8
I_VCORE (A) I_VCORE (A)
FIGURE 13. VCORE BUCK EFFICIENCY FIGURE 14. VCORE BUCK LOAD REGULATION
0.01
IVCORE = 200mA
0.01
VCORE RIPPLE (50mV/DIV)
LINE REGULATION (%)
0.01
0.01
0.00
IVCORE (100mA/DIV)
0.00
0.00
0.00
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 VIN = 12V
VIN (V)
FIGURE 15. VCORE BUCK LINE REGULATION FIGURE 16. VCORE BUCK TRANSIENT RESPONSE
0.10 0.04
VIN = 12V IVON = 20mA
0.05 0.02
LOAD REGULATION (%)
0.00
0.00
-0.05
-0.02
-0.10
-0.04
-0.15
-0.06
-0.20
-0.25 -0.08
-0.30 -0.10
0 0.01 0.02 0.03 0.04 0.05 9.5 10.5 11.5 12.5 13.5
I_VON (A) VIN (V)
FIGURE 17. VON LOAD REGULATION FIGURE 18. VON LINE REGULATION
14 FN7687.0
December 17, 2012
ISL98604
Test Circuits and Waveforms (Continued)
0.10 0.18
VIN = 12V IVOFF = 20mA
0.16
0.00
LOAD REGULATION (%)
0.14
0.10
-0.20
0.08
-0.30 0.06
0.04
-0.40
0.02
-0.50 0.00
0 0.01 0.02 0.03 0.04 0.05 9.5 10.5 11.5 12.5 13.5
I_VOFF (A) VIN (V)
FIGURE 19. VOFF LOAD REGULATION FIGURE 20. VOFF LINE REGULATION
Applications Information V IN D
I L = --------- ----- (EQ. 3)
L fS
The ISL98604 provides a complete power solution for TFT LCD
applications. The system consists of one boost converter to ISL98604 uses internal feedback resistor divider to divide the
generate AVDD voltage for column drivers, one asynchronous output voltage down to the nominal reference voltage. The boost
buck converter to provide voltage to logic circuit in the LCD panel, converter output voltage is programmable through I2C control,
two synchronous bucks for core voltage and HAVDD, LDO which will be described in more detail in section I2C Control on
controllers for VON and VOFF charge pump outputs, and AVDD page 20.
delay FET. With the high output current capability, this part is
ideal for LCD TV and monitor panel application. INPUT CAPACITOR
An input capacitor is used to suppress the voltage ripple injected
Boost Converter into the boost converter. A ceramic capacitor with low ESR should be
OPERATION chosen to minimize the ripple. The voltage rating of input capacitor
should be larger than the maximum input voltage. Some capacitors
The AVDD boost converter is a current mode PWM converter are recommended in Table 1.
operating at a fixed switching frequency (750kHz). It can operate
in both discontinuous conduction mode (DCM) at light loads and TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION
continuous mode (CCM). In continuous current mode, current CAPACITOR SIZE VENDOR PART NUMBER
flows continuously in the inductor during the entire switching
cycle in steady state operation. The voltage conversion ratio in 10F/25V 1206 TDK C3216X7R1E106K
continuous current mode is given by Equation 1: 22F/25V 1206 Murata GRM31CR61E226KE15L
V boost 1
------------------ = ------------- (EQ. 1)
V IN 1D BOOST INDUCTOR
where D is the duty cycle of the switching MOSFET. The boost inductor is a critical part which influences the output
voltage ripple, transient response, and efficiency. The selection
The boost converter uses a summing amplifier architecture for of inductor should be based on its maximum current (ISAT)
voltage feedback, current feedback, and slope compensation. A characteristics, power dissipation (DCR) and size. Values of
comparator looks at the peak inductor current cycle-by-cycle and 3.3H to 10H are recommended to match the internal slope
terminates the PWM cycle if the current limit is triggered. Since compensation as well as to maintain a good transient response
this comparison is cycle based, the PWM output will be released performance. The inductor must be able to handle the average
after the peak current goes below the current limit threshold. and peak currents shown in Equations 4 and 5:
The current through the MOSFET is limited to 4A peak. This restricts IO
(EQ. 4)
I LAVG = ------------------------------
the maximum output current (average) based on Equation 2: ( 1 D )xEff
I L V IN I L (EQ. 5)
I OMAX = I LMT -------- --------- (EQ. 2) I LPK = I LAVG + --------
2 VO 2
Where Eff is the efficiency of the boost converter; 90% can be used
Where DIL is peak to peak inductor ripple current, and is set by
in calculation as approximation.
Equation 3. fs is the switching frequency (750kHz).
15 FN7687.0
December 17, 2012
ISL98604
Some inductors are recommended in Table 2. COMPENSATION
TABLE 2. BOOST INDUCTOR RECOMMENDATION The boost converter of ISL98604 can be compensated by a RC
network connected from the COMP pin to ground. The resistance
DIMENSIONS sets the high -frequency integrator gain for fast transient
INDUCTANCE DCR (m) (mm) VENDOR PART NUMBER
response and the capacitance sets the integrator zero to ensure
4.7H/ 31 7.3x6.8x3.2 TDK RLF7030T-4R7M3R4 loop stability. On the demo board 5.6k and 15nF RC network is
3.4APEAK used. Stability can be examined by repeatedly changing the load
4.7H/ 44.1 4.0x4.0x3.1 Coilcraft XAL4030-472MEB
between 100mA and a max level that is likely to be used in the
4.5APEAK application. The AVDD voltage should be examined with an
oscilloscope set to AC and observe the amount of ringing when
4.3H/ 11.2 12.9x12.9x4 SUMIDA CDEP12D38NP-4R3M the load current changes.
6.4APEAK
SOFT-START
RECTIFIER DIODE The soft-start is provided by an internal current source to charge
A high-speed diode is necessary due to the high switching the external soft-start capacitor. The ISL98604 ramps up the
frequency. Schottky diodes are recommended because of their current limit from 0A up to the full value, as the voltage at the SS
fast recovery time and low forward voltage. The reverse voltage pin ramps up from 0.8V. Hence, the soft-start time is 2.9ms
rating of this diode must be higher than the maximum output when the soft-start capacitor is 22nF, 6.3ms for 47nF and
voltage. Also the average/peak current rating of the selected 13.3ms for 100nF.
Schottky diode must meet the output current and peak inductor
AVDD DELAY SWITCH
current requirements. Table 3 shows some recommendations for
boost converter diodes. ISL98604 integrates a disconnect switch for the AVDD boost
output to disconnect VIN from AVDD when the EN input is low or
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION when DLY2 is not completed. When EN is taken high and DLY2
VR/IAVG timing is finished, the integrated FET is turned on to connect
DIODE RATING PACKAGE VENDOR power to the display. The AVDD delay switch circuitry constantly
monitors both the current flowing through the switch and the
SS34 40V/3A DO-214 Fairchild
voltage at SWOUT. The delay switch has two current limits: a low
PMEG3030 30V/3A SOD128 NXP current limit and a high current limit. If the current flowing
through delay switch is higher than the delay switch low current
limit, the IC faults out after 1ms; if the delay switch high current
OUTPUT CAPACITOR
limit is reached, the IC faults out immediately.
The output capacitors smooths the output voltage and supplies
load current directly during the conduction phase of the power HAVDD Synchronous Buck Converter
switch. Output ripple voltage consists of two components: the
voltage drop due to the inductor ripple current flowing through OPERATION
the ESR of output capacitor, and the charging and discharging of HAVDD synchronous buck converter is a step down converter with
the output capacitor. a fixed switching frequency (750kHz) supplying voltage bias for
V O V IN IO 1 gamma buffer in the LCD system. The ISL98604 integrates two
V RIPPLE = I LPK ESR + ------------------------ ---------------- ---- (EQ. 6)
VO C OUT f s MOSFETs to reduce external component count, save cost, and
improve efficiency. In continuous current mode, the relationship
The conservation of charge principle also indicates that, during between input voltage and output voltage is as shown in Equation 7:
the boost switch Off period, the output capacitor is charged with HVDD
------------------ = D (EQ. 7)
the inductor ripple current, minus a relatively small output V IN
current in boost topology. As a result, the user must select an
output capacitor with low ESR and adequate input ripple current where D is the duty cycle of the upper switching MOSFET.
capability. Because D is always less than 1, the output voltage of the HAVDD
Table 4 shows some recommendations of output capacitors. buck converter is lower than the input voltage.
Note: Capacitors have a voltage coefficient that makes their effective The peak current limit of HAVDD buck converter is set to 0.9A,
capacitance drop as the voltage across them increases. COUT in which restricts the maximum output current based on
Equation 6 assumes the effective value of the capacitor at a Equation 8:
I P-P
particular voltage and not the manufacturer's stated value, I HAVDDMAX = 0.9 --------------- (EQ. 8)
2
measured at 0V.
Where IP-P is the ripple current in the buck inductor as shown in
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION Equation 9:
CAPACITOR SIZE VENDOR PART NUMBER HAVDD
I P-P = ---------------------- ( 1 D ) (EQ. 9)
10F/50V 1206 TDK C3216X5R1H106K L fs
16 FN7687.0
December 17, 2012
ISL98604
Where L is the buck inductance, fs is the switching frequency of capacitor is recommended (see Table 7).
HADD buck inductor (750kHz).
TABLE 7. HAVDD BUCK OUTPUT CAPACITOR RECOMMENDATION
ISL98604 uses internal feedback resistor divider to divide the
CAPACITOR SIZE VENDOR PART NUMBER
output HAVDD voltage down to the nominal reference voltage. The
HAVDD voltage is programmable through I2C control, which will be 22F/16V 0805 TDK C2012X5R1C226K
described in more detail in section I2C Control on page 20. 10F/25V 0805 TDK C2012X5R1E106M
INPUT CAPACITOR
Selection of input capacitance is important for input voltage VIO Buck Converter
ripple. A ceramic capacitor should be used because of its small
ESR. Another important criteria when selecting input capacitor is OPERATION
that it should be able to support the maximum AC RMS current VIO buck converter is an asynchronous step down converter with
which occurs at D = 0.5 and maximum output current. a fixed switching frequency (750kHz) supplying power to the logic
circuit of the LCD system. In continuous current mode, the
I ACRMS = D ( 1 D ) I HAVDD (EQ. 10) relationship between input voltage and output voltage, is as shown
in Equation 11.
Where IHAVDD is the output current of the buck converter. Table 5 VIO
----------- = D (EQ. 11)
shows recommendations for input capacitors. V IN
TABLE 5. HAVDD BUCK CONVERTER INPUT CAPACITOR
RECOMMENDATION where D is the duty cycle of the switching MOSFET.
CAPACITOR SIZE VENDOR PART NUMBER The peak current limit of VIO buck converter is set to 2A, which
restricts the maximum output current based on Equation 12:
10F/25V 1206 TDK C3216X7R1E106K I P-P
I VIOMAX = 2 --------------- (EQ. 12)
22F/25V 1206 Murata GRM31CR61E226KE15L 2
Where IP-P is the ripple current in the buck inductor as shown in
HAVDD BUCK INDUCTOR Equation 13:
The inductance is selected to meet the output voltage ripple VIO
I P-P = ------------ ( 1 D ) (EQ. 13)
requirements and minimize the converters response time to the L fs
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce Where L is the buck inductance, fs is the switching frequency of VIO
the converters response time to load transients. Taking all the buck inductor.
factors into consideration, a 3.3H to 10H inductor range is ISL98604 uses internal feedback resistor divider to divide the
recommended for the HAVDD buck converter. Besides the output VIO voltage down to the nominal reference voltage. The VIO
inductance, the DC resistance and the saturation current are also voltage is programmable through I2C control, which will be
factors that need to be considered when choosing a buck described in more detail in section I2C Control on page 20.
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor INPUT CAPACITOR
current in the application. Table 5 shows some
Selection of input capacitance is important for input voltage ripple.
recommendations for the HAVDD buck inductor.
A ceramic capacitor should be used because of its small ESR.
TABLE 6. HAVDD BUCK INDUCTOR RECOMMENDATION Another important criteria when selecting input capacitor is that it
should be able to support the maximum AC RMS current, which
DCR DIMENSIONS PART
occurs at D = 0.5 and maximum output current.
INDUCTANCE (m) (mm) VENDOR NUMBER
I ACRMS = D ( 1 D ) I VIO (EQ. 14)
6.8H/ 74.1 4.0x4.0x3.1 Coilcraft XAL4030-
3.6APEAK 682MEB
6.8H/ 45 7.3x6.8x3.2 TDK RLF7030T- Where IVIO is the output current of the VIO buck converter. Table 8
2.8APEAK 6R8M2R8 shows recommendations for input capacitors.
TABLE 8. VIO BUCK CONVERTER INPUT CAPACITOR RECOMMENDATION
OUTPUT CAPACITOR
The output ripple and transient response typically drives the CAPACITOR SIZE VENDOR PART NUMBER
selection of an output capacitor. A 10F or a 22F ceramic 10F/25V 1206 TDK C3216X7R1E106K
17 FN7687.0
December 17, 2012
ISL98604
load transient. Increasing the inductance reduces the ripple current mode, the relationship between input voltage and output
current and voltage. However, the large inductance values reduce voltage is as shown in Equation 16.
the converters response time to load transients. Taking all the
VCORE (EQ. 16)
factors into consideration, a 3.3H to 10H inductor range is ----------------------- = D
V IN
recommended for the VIO buck converter. Besides the
inductance, the DC resistance and the saturation current are also
where D is the duty cycle of the upper MOSFET and VIN of the
factors that need to be considered when choosing a buck
VCORE buck converter is the output voltage of the VIO buck
inductor. Low DC resistance can help maintain high efficiency.
converter.
Saturation current rating should be higher than the peak inductor
current in the application. Table 9 shows some The peak current limit of the VCORE buck converter is set to 1A,
recommendations for the VIO buck inductor. which restricts the maximum output current based on
Equation 17:
TABLE 9. VIO BUCK INDUCTOR RECOMMENDATION
I P-P
I VCOREMAX = 1 --------------- (EQ. 17)
DCR DIMENSIONS PART 2
INDUCTANCE (m) (mm) VENDOR NUMBER
6.8H/ 74.1 4.0x4.0x3.1 Coilcraft XAL4030- Where IP-P is the ripple current in the buck inductor, as shown in
3.6APEAK 682MEB Equation 18:
TABLE 11. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION Saturation current rating should be higher than the peak inductor
current in the application. Taking all the factors into
CAPACITOR SIZE VENDOR PART NUMBER consideration, 2.2H inductors as shown in Table 12 are
10F/10V 0805 TDK C2012X7R1A106K recommended for the VCORE buck inductor.
10F/10V 0805 Murata GRM21BR71A106KE51L TABLE 12. VCORE BUCK INDUCTOR RECOMMENDATION
18 FN7687.0
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ISL98604
TABLE 12. VCORE BUCK INDUCTOR RECOMMENDATION frequency, low gain switching transistor. Further improvement can
DCR DIMENSIONS PART
be obtained by adding a base-emitter resistor RBE, which increases
INDUCTANCE (m) (mm) VENDOR NUMBER the pole frequency to: fp = fT * (1 + Hfe * re/RBE)/Hfe, where
re = KT/qIc. Therefore, choose the lowest value RBE in the design as
2.2H/ 12 7.3x6.8x3.2 TDK RLF7030T- long as there is still enough base current (IB) to support the
5.5APEAK 2R2M5R4 maximum output current (IC).
OUTPUT CAPACITOR For example, the VON linear regulator. If a Fairchild MMBT3906 PNP
transistor is used as the external pass transistor (Q7 in the
The output ripple and transient response typically drives the application diagram), then for a maximum VON operating
selection of output capacitor. 10F or 22F ceramic capacitors requirement of 50mA, the data sheet indicates Hfe_min = 60. The
(Table 13) are recommended. base-emitter saturation voltage is: Vbe_max = 0.7V.
TABLE 13. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION For the ISL98604, the minimum drive current is:
CAPACITOR SIZE VENDOR PART NUMBER I_DRVP_min = 3mA.
10F/6.3V 0603 MURATA GRM188R60J106ME47D The minimum base-emitter resistor, RBP, can now be calculated as
Equation 19:
10F/6.3V 0402 TDK C1005X5R0J106M
RBP_min = VBE_max (I_DRVP_min - Ic/Hfe_min =
22F/6.3V 0603 TDK C1608X5R0J226M (EQ. 19)
( ( 0.7V ) ( 3mA ( 50mA ) 60 ) ) = 325
19 FN7687.0
December 17, 2012
ISL98604
CHARGE PUMP OUTPUT CAPACITORS All communication over the I2C interface is conducted by sending
A ceramic capacitor with low ESR is recommended. With ceramic the MSB of each byte of data first.
capacitors, the output ripple voltage is dominated by the TABLE 14. I2C INTERFACE SPECIFICATION
capacitance value. The capacitance value can be chosen by
PARAMETER MIN TYP MAX UNITS
Equation 24:
I OUT SDA and SCL Rise Time 1000 ns
C OUT ------------------------------------------------------ (EQ. 24)
2 V RIPPLE f OSC
SDA and SCL Fall Time 300 ns
For VON charge pump, fOSC is the switching frequency of boost I2C Bus Capacitive Load 400 pF
converter; for VOFF charge pump, fOSC is the switching frequency of
VIO buck converter. PROTOCOL CONVENTIONS
VON Temperature Compensation Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
The ISL98604 can output two levels of VON voltages depending indicating START and STOP conditions (see Figure 22). On
on the temperature. A voltage divider which consists of two power-up, the SDA pin is in the input mode.
resistors (R61 and R62) and a thermistor, as shown in the
application diagram connected to TCOMP pin is used to All I2C interface operations must begin with a START condition,
determine the VON voltage. which is a HIGH to LOW transition of SDA while SCL is HIGH.
ISL98604 continuously monitors the SDA and SCL lines for the
Figure 21 shows that the VON voltage will be VON_LT when the START condition and does not respond to any command until this
TCOMP voltage is above the compensation threshold voltage. If condition is met (see Figure 22). All I2C interface must be
the TCOMP voltage is below the compensation threshold voltage, terminated by a STOP condition, which is a LOW to HIGH
the VON voltage will be VON_HT. There is a 20mV hysteresis transition of SDA while SCL is high (see Figure 22). An ACK
between the threshold when TCOMP voltage rises and the (Acknowledge) is a software convention used to indicate a
threshold when TCOMP voltage falls. R61, R62, and thermistor successful data transfer. The transmitting device, either master or
values are selected to set the VON voltage at desired slave, releases the SDA bus after transmitting eight bits. During the
temperature. VON_LT and VON_HT are programmable through ninth clock cycle, the receiver pulls the SDA line LOW to
I2C control, which will be described in more detail in section I2C acknowledge the reception of the eight bits of data (see Figure 23).
Control on page 20.
WRITE OPERATION
FBP
VDC
To write into a DAC register (DR), it requires a START condition
from the Master, followed by 7-bit device address (010000A0),
VON_LT R61 R/W bit (=0 when writing), a valid DAC register address Byte
TCOMP (01h-09h), a data byte, and a STOP condition. After each of the
VON (V)
NTC
R62 three bytes, the ISL98604 responds with an ACK. At this time, if
the data byte is to be written only to volatile registers, the device
enters its standby state.
VON_HT
Example: Writing 21h to register address 01h (HAVDD)
TEMPERATURE WHEN TCOMP VOLTAGE
> VTCOMP_TH = 1.265V To write data in the DAC registers into EEPROM, it requires a
TEMPERATURE (C) START condition from the Master, followed by 7-bit device
TEMPERATURE HYSTERESIS RESULTED FROM VTCOMP_HYST = 20mV address, R/W bit (=0 when writing), Control Register (CR)
address byte (FFh), a data byte of 80h to write data in DRs to
EEPROM and a STOP condition. After each of the three bytes,
FIGURE 21. VON TEMPERATURE COMPENSATION
ISL98604 responds with an ACK. If the Data Byte is to be written
to EEPROM, ISL98604 begins its internal write cycle, which takes
I2C Control 25ms to finish. During the internal EEPROM write cycle, the
The ISL98604 supports all rail outputs with fully programmable I2C device ignores transitions at the SDA and SCL pins and the SDA
control. The programmed output values can be stored into EEPROM output is at high impedance state. When the internal EEPROM
during the operation and read out. write cycle is completed, the ISL98604 enters its standby state.
The I2C protocol defines any device that sends data on to the bus Example: Writing current data in DRs into EEPROM.
as a transmitter and the receiving device as the receiver. The
READ OPERATION
device controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers To read from the DAC register (DR), it first requires to write 00
and provides the clock for both transmit and receive operations. into the Control Register (CR) (FFh) to specify that the data is
Therefore, ISL98604 operates as a slave device in all read from DR. Then it sends desired DR address to be read
applications. The fall and rise time of SDA and SCL signal should (00h-09h). Finally, it reads data from DR, which requires a START
be in the range listed in Table 14. The capacitive load on the I2C condition from Master, followed by 7-bit device address
bus is also specified in Table 14. (010000A0), R/W bit (= 1 when reading); the second byte
20 FN7687.0
December 17, 2012
ISL98604
contains the data read from the specified DR. Note that the (00h-09h). Finally, it reads data from DR, which requires a START
Master will not acknowledge this byte. Finally, the last Master condition from Master, followed by 7-bit device address
sends STOP condition. (010000A0), R/W bit (=1 when reading); the second byte
contains the data read from EEPROM. Note that the Master will
Example: Reading data from DR address 06h (VOFF).
not acknowledge this byte. Finally, the last Master sends STOP
To read from EEPROM first, it first requires to write 01 into the condition.
Control Register (CR) (FFh) to specify that the data is read from
Example: Reading data from EEPROM address 06h (VOFF).
EEPROM. Then it sends the desired DR address to be read
SCL
SDA
SCL FROM
MASTER 1 8 9
START ACK
FIGURE 23. ACKNOWLEDGE RESPONSE FROM RECEIVER
21 FN7687.0
December 17, 2012
ISL98604
REGISTER MAP AND REGISTER VALUES TABLE 16. DATA FORMAT OF DAC REGISTER AND EEPROM
Table 15 shows the address of the DAC registers and their default AVDD (Default Data: 21h)
values. Table 16 shows the data format of each register. Table 17 MSB LSB
shows the parameters corresponding to different register values. R R 1 0 0 0 0 1
TABLE 15. MEMORY MAP OF DAC REGISTER AND EEPROM
HAVDD (Default Data: 20h)
DATA
MSB LSB
(VOLATILE/ FACTORY DEFAULT
REGISTER ADDRESS NON-VOLATILE) (POWER-UP) R R 1 0 0 0 0 0
22 FN7687.0
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ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
AVDD HAVDD VIO VCORE VON_LT VON_HT VOFF DLY1 DLY2 DLY3
STEP HEX (V) (V) (V) (V) (V) (V) (V) (ms) (ms) (ms)
23 FN7687.0
December 17, 2012
ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES (Continued)
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
AVDD HAVDD VIO VCORE VON_LT VON_HT VOFF DLY1 DLY2 DLY3
STEP HEX (V) (V) (V) (V) (V) (V) (V) (ms) (ms) (ms)
PROTECTIONS
The ISL98604 integrates overcurrent protection (OCP), overvoltage
protection (OVP), and over-temperature protection (OTP). The
protection threshold and the reaction of the chip are listed in
Table 18.
24 FN7687.0
December 17, 2012
ISL98604
TABLE 18. ISL98604 PROTECTION TABLE
AVDD delay FET IDS current higher than 1ms Shut down whole IC Power Cycle
3.1A during operation
IDS current higher than Immediately Shut down whole IC Power Cycle
6A at start-up and
normal operation
OVP AVDD Higher than 20.5V on Immediately Shut down whole IC Power Cycle
SWI pin
OTP Junction Temp Temperature higher Immediately Shut down whole IC Power Cycle
than +140C
Start-Up Sequence 6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
When VIN rising exceeds UVLO and EN is high, VIO and VCORE
This contact area should have multiple via connections to the
start-up. When VIO and VCORE reach 90% of the their target
back of the PCB as well as connections to intermediate PCB
values, after a delay time of DLY1, PGOOD rises up and VOFF
layers, if available, to maximize thermal dissipation away
soft-starts; when VOFF reaches 90% of its target value, after a
from the IC.
delay time of DLY2, AVDD and HAVDD start to rise up. The
soft-start time of AVDD and HAVDD depends on the capacitance 7. To minimize the thermal resistance of the package when
on the soft-start pin. When AVDD and HAVDD reach 90% of their soldered to a multi-layer PCB, the amount of copper track and
target values, after a delay time of DLY3, VON starts to rise up. ground plane area connected to the exposed die plate should
DLY1, DLY2 and DLY3 are programmable through I2C control, be maximized and spread out as far as possible from the IC.
which is described in section I2C Control on page 20. The detailed The bottom and top PCB areas especially should be
start-up sequence is shown in Figure 24. maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
Layout Recommendation noise pick-up.
PCB layout is critical especially at high switching frequency. The A demo board is available to illustrate the proper layout
device's performance, including efficiency, output noise, implementation.
transient response and control loop stability is dramatically
affected by the PCB layout.
There are some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2. Place VDC and VREF bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from the LX
node as possible.
5. The power ground (PGND) and signal ground (SGND) pins
should be connected at the ISL98604 exposed die plate area.
25 FN7687.0
December 17, 2012
ISL98604
U V LO UVLO
V IN
VHI VLO
VDC
EN
V IO
90%
VCORE
DLY1
PGOOD
VOFF
90%
90%
50%
DLY2
AVDD
50%
HAVDD
DLY3
VON
NOTES:
9. VIO and VCORE start when EN is enabled and 90% rising point will occur at the same time.
The timing gap between VIO and VCORE at 90% rising point will be less than 3ms.
10. PGOOD and VOFF will be triggered after VIO and VCORE rise and not before delay time DLY1.
11. AVDD and HAVDD start-up after delay time DLY2. Both are synchronized at 50% rising point.
12. VON will be triggered after AVDD and HAVDD rise and not before delay time DLY3.
26 FN7687.0
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ISL98604
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL98604
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
27 FN7687.0
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ISL98604
Package Outline Drawing
L40.5x5D
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/10
4X 3.60
6
6
PIN #1 INDEX AREA
PIN 1
INDEX AREA
3.65
5.00
(4X) 0.15
PACKAGE OUTLINE
0.40
0.750 SEE DETAIL "X"
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.050 0.08 C
SIDE VIEW
5.00
3.65
(36X 0.40)
(40X 0.20) 5
C 0.2 REF
(40X 0.60) 0.00 MIN
0.05 MAX
NOTES:
28 FN7687.0
December 17, 2012