AN ANT COLONY OPTIMIZATION OF FAULT TOLERANT ROUTER

ON NETWORK ON CHIP

1
T.Madhavkumar, 2P.Bharathi M.E, 3R.Ganesan M.E PhD
1
PG scholar, 2Asst.professor, 3Programme Head
1,3
M.E VLSI Design
2
Department of Electronics and Communication Engineering
1, 2, 3
Sethu Institute of Technology, Kariyapatti

Abstract -This project proposes a 6.4 tools has been used to demonstrate
fault-tolerant solution for a buffer-less existing and proposed results.
network-on-chip, including an on-line
fault-diagnosis mechanism to detect Keywords - FIFO, Shared buffer,
both transient and permanent fault. Network on chip, ACO
This brief proposes an on-line I. INTRODUCTION
transparent test technique for
detection of latent hard faults which The design of a chip is based on four
develop in first input first output distinct aspects: computation,
buffers of routers during field memory, communication and I/O
operation of NoC and also propose (Fig.1). The increase of the processing
fault tolerant solution by introducing power and the emergence of data
shared buffer in router. It provides intensive applications has attracted
alternative way in case of detection of major attention on the challenge of
faults otherwise used to improve the communication aspect in single-
efficiency. The technique involves chip systems (SoC).
repeating tests periodically to prevent
accumulation of faults. A prototype
implementation of the proposed test
algorithm has been integrated into the
router-channel interface and on-line
test has been performed with synthetic
self-similar data traffic. The Ant
Colony Optimization (ACO)
Algorithm is used to find the
minimum distance between senders to
receiver. xilinx 12.1and Model sim
Fig 1 NoC Architecture
 Fault-tolerance or graceful
degradation is the property that
enables a system to continue
operating properly in the event of the
failure of (or one or more faults
within) some of its components. If its
operating quality decreases at all, the
decrease is proportional to the
severity of the failure, as compared to
a naively-designed system in which
even a small failure can cause total
breakdown.
Fault-tolerance is not just a
property of individual machines; it
may also characterize the rules by
which they interact. For example, the
Transmission Control Protocol (TCP)
is designed to support reliable two-
way communication in a packet-
switched network, even in the
presence of communications links
which are imperfect or overloaded.
Within the scope of an individual
system, fault-tolerance can be
achieved by anticipating exceptional
conditions and building the system to
cope with them, and, in general,
aiming for self-stabilization so that
the system converges towards an
error-free state. The SoC design
challenges concern at first the design
complexity; the goals are the
separation of computation from
communication, and the use of
structured communication means. It is
also important to achieve design
reliability in order to cope with
process variability, and to guarantee
resilience against soft and hard errors.
Fault-Tolerant Routing
Algorithms to Handle Permanent
Faults for NoC Two kinds of fault-
tolerant routing, which are known as
stochastic and deterministic, have
been proposed for NoC to handle
permanent faults. Stochastic
communication transfers redundant
packets through different paths to
avoid faults Depending on the shape
of the fault region, deterministic fault-
tolerant routing algorithms can be
categorized into two classes: one can
handle regular fault regions (e.g.,
convex and concave shapes) and the
other, which is also known as
topology-agnostic, can handle
irregular fault regions.
II. FAULTS IN FIFO BUFFERS OF NOC
ROUTERS
On-line transparent test technique
for detection of latent hard faults
which develop in first input first
output buffers of routers during field
operation of NoC. The technique
involves repeating tests periodically
to prevent accumulation of faults. A
prototype implementation of the test
algorithm has been integrated into the
router-channel interface and on-line
test has been performed with synthetic
self-similar data traffic. The
performance of the NoC after addition
of the test circuit has been
investigated in terms of throughput
while the area overhead has been
studied by synthesizing the test
hardware.
 The algorithmic interpretation of
the transparent SOA-MATS++ test is
presented in below (fig.2). It describes
the step-by-step procedure to perform
the three phases of the transparent
SOA MATS++ test for each location
of the FIFO memory. we present the
technique used for implementing the
proposed transparent SOA-MATS++
test on a mesh-type NoC. Data
packets are divided into flow control
units (flits) and are transmitted in
pipeline fashion.
Fig.2 SOA-MATS++
The flit movement in a mesh-type
NoC infrastructure considered for this
work is assumed to require buffering
only at the input channels of routers.
Thus, for a data traffic movement
from one core to another, the online
test is performed only on the input
channel FIFO buffers, which lie along
the path. The buffers operate in two
modes, the normal mode and the test
mode. The normal mode and test
mode of operation of a FIFO buffer
are synchronized with two different
clocks. The clock used for test
purpose (referred as test_clk in this
brief) is a faster clock compared with
the clock required for normal mode
(router clock).
III .EXISTING SCHEME
a. Shared Buffer
A new error mitigation
mechanism suitable for dynamic
NoCs, where the number and position
of processor elements or faulty blocks
vary during runtime. Indeed, online
detection of data packet and adaptive
routing algorithm errors.
Fig.3 shared routing
Both presented mechanisms are
able to distinguish permanent and
transient errors and localize
accurately the position of the faulty
blocks (data bus, input port, output
port) in the NoC routers, while
preserving the throughput, the
network load, and the data packet
latency. We provide alternate by-
passing capacity in the case of
detection of faults.
IV. PROPOSED SCHEME
a. Ant Colony Optimization
The ant colony optimization
algorithm (ACO) is a probabilistic
technique for solving computational
problems which can be reduced to
finding good paths through graphs.
This algorithm is a member of the ant
colony algorithms family, in swarm
intelligence methods, and it
constitutes some met heuristic
optimizations. The first algorithm was
aiming to search for an optimal path
in a graph, based on the behavior of
an ants seeking path between their
colony and a source of food. The
original idea has since diversified to
solve a wider class of numerical
problems, and as a result, several
problems have emerged, drawing on
various aspects of the behavior of
ants. ACS was the first algorithm
inspired by real ants behavior.
Fig.4 Minimal path searching and
selection mechanism
The merit is used to introduce the
ACO algorithms and to show the
potentiality of using artificial
pheromone and artificial ants to drive
the search of always better solutions
for complex optimization problems.
In ACS once all ants have computed
their tour (i.e. at the end of each
iteration) AS updates the pheromone
trail using all the solutions produced
by the ant colony. Each edge
belonging to one of the computed
solutions is modified by an amount of
pheromone proportional to its solution
value.
At the end of this phase the
pheromone of the entire system
evaporates and the process of
construction and update is iterated.
On the contrary, in ACS only the best
solution computed since the
beginning of the computation is used
to globally update the pheromone. As
was the case in AS, global updating is
intended to increase the attractiveness
of promising route but ACS
mechanism is more effective since it
avoids long convergence time by
directly concentrate the search in a
neighborhoods of the best tour found
up to the current iteration of the
algorithm.
V.EXPERIMENTAL RESULTS
The proposed route system, with
ANT COLONY algorithm are
simulated by using Xilinx ISE 12.1i
and implemented in Spartan FPGA
processor.
s.no Parameter existing Proposed
1 Number
32 28
of Slices
2 Number
of 4 input 60 50
LUTs
3 Number
of bonded 15 10
IOBs
Table1comparsionb/w existing and propose
VI. RTL SCHEMATIC
After performing the synthesize
process, the RTL schematic has been
created automatically based on the
functionality. The routing between the
different cells can be viewed clearly
by this schematic
Fig 3 Schematic Diagram
Fig 4 Technical schematic diagram
Fig 4 Simulation result from model
sim 6.4
VII.CONCLUSION
In this paper, we provided a fault-
tolerant solution for a buffer-less NoC
to protect it from both transient and
permanent faults on the links based on
Ant Colony Optimization based
routing algorithm was implemented
The experimental results showed that
FTDR and FTDR-H routers are high-
reliability buffer-less routers, which
can protect against any fault
distribution pattern, as long as the
network is not cut into two or more
disconnected sub-networks
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Dr.R.Ganesan received his B.E in
Instrumentation &
Control engineering
from Arulmigu
Kalasalingam college
of engineering and
M.E Instrumentation
from madras institute
of technology in the year of 1991 and
1999 respectively. He has completed
his Ph.D from Anna University,
Chennai, India in 2010. He is
presently working as professor and
head of the department of M.E VLSI
Design at Sethu Institute of
Technology, India. He has published
more than 25 research papers in the
national and international Journals/
conferences. His research interests are
VLSI Design, Image Processing, and
Neural Networks and genetic
algorithms.