EXPERIMENT NO.

7
Aim: - To design a NOT gate using MENTOR GRAPHICS and compute the delay between
input and output waveforms.

EDA Tool Used: - MENTOR GRAPHICS.

Methodology: - A CMOS(Complementary metaloxidesemiconductor) circuit is composed

of two MOSFETs. The top FET is a PMOS type device while the bottom FET is an NMOS
type. The body effect is not present in either device since the body of each device is directly
connected to the devices source. Both gates are connected to the input line. The output line
connects to the drains of both FETs.

CMOS is a technology for constructing integrated circuits. CMOS technology is used in

microprocessors, microcontrollers, static RAM, and other digital logic circuits.

Circuit Schematic: -

Fig 7.1 circuit diagram of CMOS Inverter

TRUTH TABLE:
Table 7.1 NOT gate truth table

A B

0 1

1 0
GIVEN SPECIFICATIONS:
Table 7.2 Specification for NMOS and PMOS

NMOS PMOS

Length Width Length Width

0.18u 0.36u 0.18u 0.72u

Table 7.3 Input to NOT Gate

Signal Pulse Pulse Time Rise time Fall time

Amplitude width period
(in ns) (in ns)
(in volts) (in ns) (in ms)

A 1.8 20 50 1 1

SYMBOLIC DIAGRAM:

Fig 7.2 Symbolic diagram of NOT gate

WAVEFORMS:

Fig 7.3 Waveforms of CMOS Inverter

DC ANALYSIS:

Fig 7.4 DC analysis of CMOS Inverter

DELAY AND DC ANALYSIS:

Table 7.4 Delay and DC analysis

TPHL[in ns] TPLH[in ps] TP[in ns]
50.002 78.329 25.05

VIL[in V] VIH[in V] VOL[in V] VOH[in V]

0.647 0.907 0.108 1.71

RISE TIME[in ps] FALL TIME[in ps]

179.57 112.64

SLEW RATE [FALLING]

12.782G

Result:
CMOS inverter was designed and its DC and transient analysis were done on MENTOR Graphic
and VOH, VOL, VIH, VIL were calculated.