Fast 64-points FFT / IFFT
1 Features
• 64-Point complex FFT or IFFT algorithm
• Configurable word width (10- to 32-bit words)
• Dynamic selection between FFT and IFFT
• Dynamic normalization selection
• Split-radix FFT algorithm for enhanced
performance
• New FFT transform result is available after a
maximum of 69 clock cycles resulting in 1.38us
@ 50 MHz per FFT operation
• Synthesizable and configurable RTL (VHDL)
netlist
• Support for ASIC and FPGA technology
• Validated on FPGA @ 16 MHz
• Provided with test bench and test vectors
• Implemented in standard logic gates only (no
RAM)
2 General Description
The Fast Fourier Transform (FFT) core computes a
64-point complex forward FFT or inverse FFT (IFFT).
Direction of Transform can be selected dynamically.
3 Block Diagram
Figure 1: Functional Block Diagram
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The input data is a vector of 64 complex elements.
Real and imaginary parts of each complex element
are represented as 10- to 32-bit 2’s complement
numbers.
The output data as well is a vector of 64 complex
elements each of which is represented by two 10- to
32-bit 2’s complement numbers.
Normalization (division by 64) is selectable
dynamically.
The applied algorithms enable the block to compute
one FFT / IFFT transform within 64 to 69 clock
cycles, depending on the selected word width.
Selecting the word width (prior to synthesis) is
basically a tradeoff between accuracy, transform time
and gate count / power consumption and needs to be
done according to system application.
A number of selected test vectors are provided as
test bench. The solution vectors calculated by the
FFT block can be compared to solution vectors
calculated by specialized standard software such as
MATLAB.
4 Signal Description

Signal Name Direction Size Activ Description

e
masterclk Input 1 N.A. Master clock.
Note: maximal allowable clock frequency is technology dependent.
(Example: With TSMC 0.18 um at 3.3 V, typical process, max frequency is 75
MHz)
reset_n Input 1 low Global asynchronous reset.
If this signal is set to low an asynchronous global reset is performed.
All registers and all output signals are set to zero.
start_fft Input 1 high Start of conversion.
If this signal is set to high for at least one clock cycle FFT / IFFT
operation will be started. Once start has occurred, this signal
becomes redundant and can be either high or low.

Note: Before start_fft is latched high by a rising edge of masterclk valid data
must be presented to the data inputs. Once start of operation has occurred,
input data must remain valid for at least nine clock cycles. After that, input
data becomes redundant and new data may be presented to the data inputs.
Note: If this signal is set to high continuously (see Figure 3 “restart condition”)
and input data is presented right in time a continuous conversion mode is
reached. In this mode output data will be available after every {64 to 69} + 1
clock cycles.
Note: To avoid continuous mode operation (see Figure 3 “Stop condition”)
this signal must be set to low before the trailing edge of signal fft_done.
ifft_mode Input 1 N.A. Operation mode selection.
If this signal is set to low FFT operation is performed, if it is set to
high IFFT operation is performed.
ifft_norm Input 1 high Normalization mode for IFFT.
If this signal is set to high normalization is performed on the output
data. That is to say, all output values are divided by a factor of 64.

Note: When the block performs an FFT conversion (ifft_mode = low) this
signal is redundant and does not affect the operation.
x_in[63:0] Input 64 N.A. Real part of complex input vector.
Note: Complex input vector's element n is equal to x_in[n] + j y_in[n].
y_in[63:0] Input 64 N.A. Imaginary part of complex input vector.
fft_done Output 1 high FFT / IFFT operation completed.
Once the selected operation (FFT / IFFT) is finished, this signal will
become high for one clock cycle.
x_out[63:0] Output 64 N.A. Real part of complex output vector.
Note: Complex output vector's element n is equal to x_out[n] + j y_out[n].
y_out[63:0] Output 64 N.A. Imaginary part of complex output vector.

Table 1: Signal Description

5 Symbol
masterclk
reset_n fft_done
FFT
start_fft
ifft_mode
ifft_norm

x_in [63:0] Generics: x_out [63:0]

Figure 2: Block Symbol
data_size_g
y_in [63:0] y_out [63:0]

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 6 Computation Timing
Figure 3 shows the computation timing conditions, which need to be respected in any circumstances.

Transform time 64 to 69 cycles

masterclk

> 1 Cycle Restart condition

start_fft

fft_done Stop condition

Valid data required ≥ 9 Cycles In case of restart

data

Figure 3: Computation Timing

7 Theory of Operation 9 Accuracy

The Discrete Fourier Transform (DFT) formula is: Computation accuracy increases with increasing
N −1 word width and so does gate count and transform
X k = ∑ xnW nk
− j 2Nπ n
with WNn = e time. So basically it is a trade off between accuracy,
n=0 gate count and transform time.
The inverse DFT operation is defined as:
10 Transform Time
N −1
1
xk =
N
∑X W
k =0
k
−nk As shown in Table 2 transform time depends on the
word width used to represent real and imaginary
parts of the elements of input and output vectors.

8 Data Format Transform Transform

Word
Input and output data vectors consist of 64 fixed- time in time @
width in
point complex vector elements, each represented by clock 20MHz in
bits
a real part and an imaginary part. The word width of cycles us
10 to 12 64 3.20
each of the two values of each vector element can 13 to 16 65 3.25
be configured prior to synthesis using the generics 17 to 20 66 3.30
data_size_g. Word width may be between 10 and 21 to 24 67 3.35
32 bits. Input and output values are represented as 25 to 28 68 3.40
2’s complement numbers. 29 to 32 69 3.45

Note: It is a matter of interpretation, where to put the Table 2: Transform Time

decimal point within the 10- to 32-bit fixed point
input values.

However, the position of the decimal point in the

output values is shifted to the right by 6 digits
referring to the position of the decimal point in the
input values.

This measure does increase accuracy without

affecting gate count and transform time.

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 11 Gate Count
As shown in Figure 4 the number of standard logic
gates consumed by the block is highly dependent
on the word width used to represent input and
output data.
15 References
[1] A. V. Oppenheim and R. W. Schafer, “Discrete-
time signal processing”, Prentice-Hall, pp. 514–661.

16 0
16 Contact
15 0

14 0
For more details about our products and services,
Gate count in K-Gates

13 0

12 0 please visit us at www.newlogic.com or

110

10 0
www.wipro.com or contact us at:
90

80

70
United States
60 Wipro Technologies
1300, Crittenden Lane
50

40

30

10 12 14 16 18 20 22 24 26 28 30 32
2nd Floor, Mountain View
CA 94043
Wo rd widt h in bit s
USA
Tel.: +1-650-316 3555
Figure 4: Gate Count vs. Word Width Fax: +1-650-316 3468

Europe
12 Power Consumption NewLogic Technologies
(a Wipro Company)
An increasing number of standard logic cells will Millennium Park 6
result in increasing power consumption. Hence, as A 6890 Lustenau
gate count is dependent on word width power Austria
consumption is too. Tel.: +43-5577 995-0
Fax: +43-5577 995-988
Furthermore, power consumption depends on the
clock frequency and on the applied technology. The Japan
provider of the standard cell library and the foundry Wipro Technologies
will provide numbers for the term Power/Gate/MHz. #911A, Landmark Towers
2-1-1, Minatomirai 2-Chome
Nishi-Ku, Yokohama 220-8109
Japan
13 Test Bench Tel.: +81-45-650 3950
A number of carefully selected test vectors are Fax: +81-45-650 3951
provided as test bench. The solution vectors
calculated by this FFT block can be compared to India
solution vectors calculated by specialized standard Wipro Technologies
software such as MATLAB. Ganappa Towers
53/1, Hosur Main Road
Madiwala, Bangalore 560 068 Karnataka
14 Deliverables India
Tel.: +91-80-550 2001
As part of the License Agreement the components
listed below will be delivered:
• VHDL Netlist (Verilog TBD)
• Test Bench
• Datasheet
• Synthesis Scripts (Ambit + Synopsys)

Information furnished is believed to be accurate and reliable. However, Wipro-NewLogic assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Wipro-NewLogic. All information is
subject to change without notice, © 2006 NewLogic, a Wipro Company. Version 1.1, January 2006. All Trademarks are the
property of their respective owners.

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