A 2.

4 GHz Low Power Folded Down-conversion

Quadrature Mixer in 0.18-m CMOS*
Dongjun SHEN1, 2, Zhiqun LI1, 2**
1
Institute of RF- & OE-ICs, Southeast University, 210096 Nanjing, China;
2
Research Center of Sensor Network, Southeast University, 214135 Wuxi, China

AbstractThis paper describes a 1.8-V I/Q down mixer operating

in 2.4GHz band for the Wireless Sensor Network (WSN)
application using TSMC 0.18-m RF CMOS process. The
double-balanced mixer is modified based on the conventional
Gilbert cell. It is composed of I/Q shared transconductance stage,
folded switching stage, nMOS load stage, and common-mode
feedback (CMFB) circuits. The mixer achieves a conversion gain
of 13.84 dB with an input 1-dB compression point (IP1dB) of -3.66
dBm. It also achieves a single side band (SSB) noise figure (NF)
of 11.55 dB. The mixer acquires the third order input referred
intercept point (IIP3) of 2.16 dBm. It consumes 1.96 mA of
current from a 1.8-V power supply.

Keywords-WSN application, low power, folded mixer, CMFB,

nMOS load, 0.18-m CMOS
I. INTRODUCTION
Wireless Sensor Network (WSN), is a self-organizing
Network system deployed in monitoring areas by large
amounts of cheap miniature sensor nodes. These nodes are
designed for data collecting, processing and transmitting in
applications such as home automation, industrial control,
public security, environmental monitoring and so on. WSN is
based on IEEE 802.15.4/ZigBee standard which operates in the
ISM radio bands. In this case of application it operates in the
2.4 GHz band which has gained much interest for its potential
low cost and system level integration. To further the market,
low voltage WSN nodes with less power consumption and
higher performance/price ratio are required.
The down mixer is set up directly after the low noise
amplifier (LNA) as shown in Fig. 1. It receives RF signals
amplified by the LNA and translates to intermediate frequency
(IF) signals. Mixers can be passive or active. The former
category provides good linearity but brings a typical
conversion gain (CG) loss of 6-7 dB which sacrifices NF. The
latter, especially the well-known Gilbert cell [1], has prevailed
for its high conversion gain, high port-to-port isolation and low
noise figure. The compromise is linearity which is an
irreconcilable conflict with conversion gain. Several different
works have been published in past years: a modified Gilbert
cell mixer without current tail transistor [2] [3], a low voltage
high gain CMOS mixer [4], a folded switching mixer with
current reuse [5], and a single balanced mixer with current
reuse [6].
In a radio frequency wireless communication system, the
mixer is a crucial building block in the front-end of receiver.
Figure 1. Front-end block of a WSN receiver
Passive mixers can reach very high IIP3 with high NF. Such a
high NF limits the signal to noise ratio of a front-end. A very
high gain LNA is required to suppress the effect of noise
degeneration in the whole frond-end. A high gain LNA
requires a higher current which is not hoped in the low power
system design. Compared to a RF front-end using high gain
LNA and passive down mixer, a proper gain LNA consuming
much less current and a high gain active down mixer seems a
more reasonable and effective combination.
This paper presents a low power I/Q active down mixer
which consumes less than 2 mA from a 1.8-V supply voltage.
The I/Q down mixer consists of two identical mixers which
share the same transconductance stage. It means that each
mixer in the I/Q mixer consumes less than 1mA current, yet
achieves a conversion gain of 13.84dB without deteriorating
the linearity evidently.
The rest of the paper is organized as follows. The circuit
designs of the mixer core and CMFB are included in section II.
The simulation results are in section III. In section IV the paper
draws some conclusions.
II. CIRCIUT DESIGN
A. Conventional Gilbert Cell Mixer
A conventional double balanced Gilbert mixer, as shown in
Fig. 2, provides good port-to-port isolation as a consequence of
its full differential topology which cancels LO-IF and RF-IF
feed through. Moreover, it is easy to achieve a high gain using
high impedance loads. But high impedance loads result in
degeneration in both voltage headroom and linearity.

* Project supported by the National High Technology Research and

Development Program (No. 2007AA01Z2A7) and the Special Fund of Jiangsu
Province for the Transformation of Scientific and Technological
Achievements (No. BA2010073).
** Corresponding Author: zhiqunli@seu.edu.cn

978-1-4577-1010-0/11/$26.00 2011 IEEE

 VDD
RL RL
IF+ IF-
LO+ M1 M2 M3 M4
LO-
RF+ M5 M6
Figure 2. Conventional double balanced Gilbert mixer
Assume that the LO signal is an ideal periodical square
wave, and transistors work without channel length modulation
effect. The conversion gain is as follow [7]:
2 mixer on the right. This design considers the symmetry and
CG gm RL
where gm is the transconductance of M5 and M6. RL stands for
the load resistance.
There are two factors determining the conversion gain. To
obtain a high conversion gain, high dc bias current of the
transconductance is required to increase gm. The other way is to
use high RL. Now that the low power consumption is of first
priority in the WSN application, the latter is preferred in the
circuit design.
Higher current of the transconductance stage improves the
gain and the linearity of the mixer but forces more current
flowing through LO switches. The latter effect aggravates the
non-ideal switching, which means that both switching
transistors are turned on simultaneously for a longer time. Thus
more RF current is lost as a common-mode signal. For a given
LO amplitude, the switching time of the transistors can be
reduced by reducing the drain current flowing through them [8].
At a given current there is a limitation for increasing the
load resistors RL because of the voltage drop on these resistors.
The drain-source voltage of the transistors M5 and M6 is not
enough to keep them work linearly especially when the input
RF signal gets large. So there is not much headroom for the
receiver system to function well.
Besides, the three stacked transistors and resistor RL imply
pretty high voltage supplies in the order of 2.4 V [9].
Downscaling of the supply voltage meets the need of low
power consumption but worsens linearity performances due to
the same reason of headroom requirements. The dc voltage of
1.8 V is applied by the WSN receiver system design which
does not reserve much headroom for the conventional Gilbert
cell. So improvements of the conventional Gilbert current
commutating mixer must be made to resolve these problems.
B. Proposed Mixer Design
Fig. 3 shows the proposed mixer topology based on the
conventional Gilbert cell aiming at reducing the power
consumption without weakening other performances.
RF-
Figure 3. Folded Gilbert cell I/Q mixer
Main parts of the conventional Gilbert cell are the
transconductance stage, the switching stage and the load stage.
M1 and M2 are the transconductance stage. Notice that M1
and M2 are shared by both the I-mixer on the left and the Q-
(1) balance of the two mixers. If the transconductance stage is
separated, it would be difficult to provide the same
transconductance for the I and Q mixers and lead to a
mismatch of the output amplitude which is not wanted. In order
to use the maximum of the voltage headroom and improve the
linearity of the mixer, M1 and M2 are grounded without a
common current tail.
M5 to M8 consist of the load stages. The nMOS transistors
are used instead of resistance loads. Assume Id of M5 is 0.3
mA, the Rds of M5 can be easily designed over 10 k. If
traditional loads of the same resistance are used, the voltage
drop could be more than 3V while the supply voltage provides
merely 1.8-V. This design increases the load resistance without
reducing much headroom. Thus it improves linearity
performances and retains high conversion gain.
M9 to M16 are four switch pairs. The channel length of
them is designed to the minimum scale of 0.18-m for fast
switching. Wider gates show a lower resistance when the
switches are on, which improves linearity. But the parasitic
capacitances get larger and worsen the noise performance. So
the dimension of the switching transistors must be carefully
chosen. Their gates are biased through high resistance. Because
the VG and VS of the switch transistors drift with each other in
this folded structure, the bias voltage is not strictly confined.
But VG needs to be carefully adjusted to allow adequate output
headroom and keep all transistors work in saturation region.
Besides good headroom and linearity performance, the
folded structure has its inherent advantages in controlling the
transconductance stage and the switch stage independently
because the two stages are on different current paths, which is
very much unlike the conventional Gilbert cell. So reducing the
current of the switch stage would not deteriorate the gain and
linearity while increasing the switching speed.
As in (2), the RF signal multiplies the LO signal:
1 1
cos(RFt )cos(LOt ) = cos(RF LO)t + cos(RF + LO)t (2)
2 2
 There are two parts produced. One is the difference
frequency or the intermediate frequency (IF) fIF and the other is
the sum frequency. In the WSN application, presume fRF is
2.402 GHz and fLO is 2.4 GHz. Then fIF is 2 MHz and fIF+fLO is
4.802 GHz. The intermediate frequency is the useful
component while the sum frequency is not wanted. Two small
capacitances C1 and C2 are implanted in the I/Q mixers. The
capacitance is calculated to introduce a proper low-pass pole.
This slight change proves to be very effective in simulation
verification.

C. CMFB Design
For this case of current source loads implemented by M5 to
M8 the common-mode level is not well defined. The fully
differential circuit needs CMFB to operate properly and to fix
the DC of the output nodes. The CMFB circuit is shown in Fig.
4.
VCM1, VCM2 is connected to the same nodes in Fig. 3. The
reference voltage Vref is generated by IrefRref. Vout is connected
to the gates of M1 and M2 through high resistance in Fig. 3 and
provides the bias voltage.
D. Other Details
The bias circuits of the mixer core are not elaborated in this
article for clarity.
At last the output of the quadrature mixer is buffered with
four source followers in order to realize 50 output
impedances. These buffers are not required later on for the
front-end receiver and only for measurement reasons. The
supply voltage for them is separated from the mixer core and
the bias circuits in order not to bring in additional power to the
actual power consumption of the front-end receiver.
III.POST-SIMULATION RESULTS
The mixer is designed in TSMC 0.18 m RF CMOS
technology. Layout of the mixer in Cadence Virtuoso
environment is shown in Fig. 5. The area of the mixer core is
Figure5. Layout of the mixer
The following simulation are all performed at a LO power
level of 0 dBm.
The NF is dependent on the RF port source impedance. The
authors are concerned about the actual noise performance in
the front-end receiver. The source impedance is set to be 1 k
which is very close to the LNA output impedance. Fig. 7
depicts the simulated SSB NF versus the IF frequency. Notice
that a single point at the IF 2MHz is of concern. The SSB NF is
11.55 dB @ 2 MHz.
The IP1dB and IIP3 are -3.66 dBm and 2.16 dBm as shown
in Fig. 8 and Fig. 9 respectively.
Some of the most significant works are shown in Table 1
for comparison. The power consumption is remarkably reduced
compared to the other works. The quadrature mixer contains
two identical mixers, which are the I-mixer and the Q-mixer.
Under a 1.8 V voltage supply, each mixer consumes less than
1mA.
15
14
13
12
CG (dB)

11
0.40.44 mm2 and the whole chip size is 0.830.95 mm2 with 10
pads. 9
8
7
Post-simulation is under the temperature of 27 degrees -4 -2 0 2 4 6
Celsius with Spectre RF tools in Cadence. Plo (dBm)
Figure 6. Simulated CG with LO power as parameter
Fig 6 shows the simulated dependence of CG versus the LO fRF = 2.402GHz; fLO = 2.4GHz
power. The optimal LO power is 0dBm which is an amplitude
of 316 mV on 50 . The corresponding CG is 13.84 dB with a
load of 126 k, which is the input impedance of the Band Pass
Filter (BPF) after the mixer.
NF

Figure 4. CMFB circuit Figure 7. Simulated NF versus IF frequency

 IV. CONCLUSIONS
WSN is an application of extreme low power consumption.
The front-end of WSN receiver is composed of a LNA and a
mixer. The presented design uses an active mixer with gain co-
working with the LNA in order to reduce the total power
consumption of the front-end.
With the transistors and voltage downscaling, the
conventional Gilbert cell mixer is of low conversion gain and
low linearity performances. The presented folded Gilbert cell
mixer is a solution for low voltage and low power consumption
design. It greatly reduces power consumption while keeping
good performances.
The drawbacks of conventional Gilbert cell mixers are Figure 9. Simulated IIP3
discussed and some improving principles are raised. The
proposed circuit design is developed accordingly. Simulations
prove the design to be a satisfaction. REFERENCES
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Figure 8. Simulated IP1dB