IEEE ELECTRON DEVICE LETTERS, VOL. 15, NO. 4.

APRIL 1994 129

An Analytic Polysilicon Depletion

Effect Model for MOSFET’s
Rafael Rios, Member IEEE, Narain D. Arora, Senior Member IEEE, and Cheng-Liang Huang, Member IEEE

Abshct- A novel polysilicon depletion model for MOSFET where

devices is presented. It is shown that only simple modifications to
standard analytical MOSFET models used for circuit simulations
are required to account for the polysilicon depletion effect. The
accuracy of the model is validated by comparing results to both
simulated and measured device characteristics. It is also shown Here, q is the electronic charge, t,i is the dielectric constant of
that neglecting the polysilicon depletion effect for devices with silicon, Np is the active donor concentration in the polysilicon
non-degenerate polysilicon gates may lead to non-physical model region, CO, is the gate oxide capacitance per unit area, V,, is
parameter values and large errors in the calculated intrinsic the applied gate to source bias, Vfb is the flat-band voltage,
device capacitances. and is the bulk Fermi potential. V is the channel voltage,
varying from 0 at the source end to the applied drain to source
I. INTRODUCTION bias, Vd,, at the drain end. As expected, the potential drop
given by (1) goes to zero for large Np values, corresponding
T HE process requirements of current N + / P + dual-gate
CMOS technologies result in a compromise in the achiev-
able electrically active impurity concentration in the polysil-
to the degenerate polysilicon case.
To include the polydepletion effect in the standard strong-
icon gate [l]. The implant and annealing conditions for the inversion drain current expression, the extra voltage drop in
polysilicon doping must be carefully selected to avoid impurity the polysilicon region, as given by (l), must be accounted
penetration through the gate oxide, while maintaining the re- for. Thus, the standard inversion layer charge expression [3]
quired source/drain junction depth and lateral diffusion length is modified to read
dictated by scaling rules. The reduced active dopant levels in
the polysilicon gate give rise to the formation of a depletion
Qi = -Coz(Vgs - #Jp - K h - a v ) , (2)
layer near the polysilicon/oxide interface when the device is
biased in strong inversion, which in turn results in degraded where &h is the threshold voltage, and a is the bulk charge
device characteristics (the so-called polysilicon depletion or factor. Assuming that the polysilicon doping N p remains high
polydepletion effect). The achievable concentration of active enough to make the relation a, >> V valid, the square root
dopants in the polysilicon gate is expected to decrease for term in (1) can be approximated by the first two terms of the
future scaled-down devices, due to more stringent process Taylor series expansion in V . Thus, substitution of (1) in (2)
requirements. In addition, a reduction in gate oxide thickness results in
will accentuate the polydepletion effect [2].
An analytic polydepletion effect model suitable for cir- Qi -Coz(Vga -Khp - NpV), (34
cuit simulations may become essential for the design of ad-
vanced dual-gate CMOS circuits with non-degenerate polysil-
icon gates. Without such a model, accurate representation of
both DC and AC device characteristics may not be possible. As
Khp=Kh+av --h
(“l ),
a result, the accuracy of circuit simulations may be seriously
affected.
ap = a + ($ - 1)
11. POLYDEPLETIONMODEL
Using (3a) for the inversion layer charge and employing the
The potential drop $ p in the polysilicon depletion region gradual channel approximation (GCA) [3], the drain current
can be readily found from a solution of the Poisson equation, expression with polydepletion effect becomes
using the depletion approximation. For an n-channel MOSFET
(nMOST), this results in (4)

Where is the gain factor. Comparison of (4) with the standard

strong-inversion current equation shows that inclusion of the
polysilicon depletion effect amounts to replacing the standard
Manuscript received October 29, 1993: revised January 14, 1994.
The authors are with Digital Equipment Corporation, Hudson, MA 01749. threshold voltage v t h and bulk charge factor (Y by the expres-
IEEE Log Number 9400183. sions given in (3b) and (3c), respectively. It should be stressed,
0741-3106/94$04.00 0 1994 IEEE
130
however, that Vthp is not the device threshold voltage, as is
normally defined, since it has a gate bias dependency through
parameter b. The new threshold voltage b$, is found by forcing
V,, = qhin (3b), resulting in
where y is the body factor. As expected, ( 5 ) shows that
the magnitude of the device threshold voltage will increase
as Np (or a,) decreases and it will revert to the standard
expression for large Np. The increase in threshold voltage with
reduced polysilicon doping results in degraded drain current
characteristics.
It should also be noted that the standard drain current
equations used for circuit simulation are in general more
involved than the simple form shown in (4),and include
short and narrow channel effects, field dependent mobilities,
sourcddrain resistance effects, etc. However, all these higher
order corrections can be lumped in the expressions for the
pre-factor /3, threshold voltage Vth and bulk charge factor a ,
resulting in a final general form similar to (4).
Derivations of the device terminal charges and capacitances
proceed in a similar manner (see, for example, [ 3 ] ) .Again, it
can be shown that inclusion of the polydepletion effect into
the device AC model amounts to simple modifications to the
threshold voltage and bulk charge factor.
111. &SULTS AND DISCUSSION
The polydepletion effect model described above has been
implemented in a physically based analytical MOSFET model
[4] in the circuit simulator SPICE. The model has been vali-
dated by comparison to both simulated and measured device
characteristics. Drain characteristics were generated using a 2-
D numerical simulator with three different polysilicon doping
concentrations, N p = 5 x 1018,10'9, and 5 x 1019 c r r 3 ,
with all other simulated conditions remaining the same. The
polysilicon gate was treated as single crystal silicon, and
the possible effect of trap levels in the polysilicon depletion
region was ignored. The analytical MOSFET model was then
employed to fit all three drain characteristics with the same set
of fitting parameters, using a nonlinear parameter extraction
program [ 5 ] . Note also that N p was not considered a fitting
parameter, but for each case was set to the above specified
values. Very good fits with average errors below 1% and
maximum errors below 5% were obtained, as illustrated in
Fig. 1 for nMOST devices. Similar results were also obtained
for p-channel devices (pMOST).
Without including the polydepletion effect, good fits to
measured or simulated I-V characteristics of devices with non-
degenerate polysilicon are still possible, by allowing some of
the fitting parameters outside their normal physical values.
However, this may result in significant over-prediction of
device capacitances, as illustrated below. Furthermore, since
the model parameters are usually extracted from drain current
characteristics, the errors in the calculated capacitances would
be undetected.
Fig. 2 shows the measured drain characteristics (circles)
of a test pMOST device with an active polysilicon doping
IEEE ELECTRON DEVICE LETTERS, VOL. 15, NO. 4, APRIL 1994
t.. = 7 nrn
T
E
-0
(II
.-c
ne
0 i 2 3
Draln Voltage, Vda (VI
Fig. I . New model fit to simulated nMOST drain characteristics with
different plysilicon dopings: ,VP = 5 x 1019 (circles, simulated: solid
line, model), .VP = 1019 (squares, simulated; dashed line, model), and
= 5 x 10'' (triangles, simulated; dotted line, model).
I
0
0 1 2 3
-
Draln Voltage, Vdr (V)
Fig. 2. Drain characteristics for a test pMOST device with A'p = 5.5 X 10IR
C I I - ~ , showing that misleading good fits are still possible without the
polydepletion effect (see text). Solid line: with polydepletion model; dashed
line: without polydepletion model; circles: measured data.
concentration of Np = 5.5 x 1OI8 C I I - ~ (value obtained from
C-V profiles). Details on the device structure can be found
in [2] and [ 6 ] .The L , f j value noted on Fig. 2 was obtained
with the least resistance variation method [7]. The solid and
dashed curves are the analytic model fits with and without the
polydepletion effect, respectively. Both drain characteristics
fits are very good, with average errors below 2%. Table I
shows the extracted model parameters for the two cases (only
those parameters that are different arc shown in the table). In
order to fit the degraded linear region characteristics with the
standard model (no polydepletion effect), significantly reduced
low field mobility po and flat-band voltage Vjb are obtained.
An increased drain induced barrier lowering (DIBL) parameter
U and a non-physical carrier saturation velocity usat [8] are
then required to match the saturation drain current.
Fig. 3 shows the corresponding gate to drain capacitance
characteristics for the same device used in Fig. 2. The circles
represent the measured data while the solid and dashed lines
RIOS er al.: AN ANALYTIC POLYSILICON DEPLETION EFFECT MODEL FOR MOSFET'S 131

TABLE I capacitance are incurred when the polydepletion effect is

MODELPARAMETER COMPARISON FOR THE EXTRACTION ignored.
WITH AND WITHOUT THE POLYDEPLETIOKMODEL
Parameter Description With Without
Polvdeoletion Polvdeoletion IV. CONCLUSION
Effict Model Effect Model An analytical polydepletion effect model suitable for cir-
Vrh ,-(v) Flat-hand voltage 0.885 0.808
cuit simulations has been presented. It was shown that the
CbUle( a ~ - ~Bulk ) doping 2.951 x 10'' 3.066 x 10"
j r , (cm2 / V.s) Low-field 110.1 91.71
necessary modifications to a standard MOSFET model to
mobility account for the polydepletion effect are straightforward. The
~ ' ( c ~d s ) ~ t Saturation 7.i89 X loG 1.339 x 10' model results have been validated with experimental and
velocity simulated DC and AC characteristics of dual-gate devices.
U DIBL parameter 0.0963 0. I387
It was shown that neglecting the polydepletion effect may
lead to non-physical model parameter values and significant
over-prediction of intrinsic device capacitances.

Fig. 3. Gate to drain capacitance CSd for the same device of Fig. 2, illus-
trating the large errors in gate capacitances incurred when the polydepletion
effect is ignored. Solid line: with polydepletion model; dashed line: without
polydepletion model; circles: measured data.
are the modeled results with and without the polydepletion
effect, respectively. Note that severe errors in the calculated
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