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Entit et architecture
(1.0.0..0)
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8
Entit et architecture
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8
Programme en VHDL
E<=(A2 AND A3) OR(NOT A0 AND NOT A2) OR(A1 AND A3) OR
(NOT A0 AND A1);
end vhdl;
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8
COD SORTIE
A2 A1 A0 S1 S2 S3 S4 S5 S6 S7 S8
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 00
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
S1=** S5=**A2
S3=*A1* S7=*A1*A2
PROGRAMM EN VHDL
Transcodeur binaire 7 segments+ Mux 8x1+ decodeur 3x8