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4.

5 Unit V ACTIVE FILTERS

4.5.1 Syllabus

Introduction, Butter worth filters 1st order, 2nd order LPF, HPF filters. Band pass, Band reject
and All pass filters. Four Quadrant multiplier, balanced modulator, IC1496,Applications of analog
switches and MultipSample & Hold amplifiers

4.5.2 Unit Objectives:


After reading this Unit, you should be able to understand:

- Types of filters
- Difference between active & passive filters
- Design of filters using op-amps

4.5.3 Unit Outcomes:


Student designing gets knowledge on different types of filters.

4.5.4 Unit Lecture Plan:

Lecture Topic Methodology Quick reference


no.
1. Butter worth filters Chalk & Board T2: Ch-7
1st order, 2nd order Pg. No. 264-268
LPF
2. HPF, Band pass Chalk & Board T2: Ch-7
Filters Pg. No. 271-276
3. Band reject and All Chalk & Board T2: Ch-7
pass filters Pg. No. 277-281
4. TUTORIAL
5. Four Quadrant Chalk & Board T2: Ch-4
multiplier Pg. No. 159-161
6. Balanced modulator, Chalk & Board www.onsemi.com/pub/Collate
IC1496 ral/MC1496-D.PDF
7. Applications of Chalk & Board www.analog.com/media/en/tr
analog switches and aining-seminars/tutorials/MT-
Multiplexers 088.pdf

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8. Sample & Hold Chalk & Board T2: Ch-4
amplifiers Pg. No. 153
9. TUTORIAL

4.5.5 Teaching Material / Teaching Aids as per above lecture plan


4.5.5.1 Lecture-1

First Order Low Pass Filter:

Fig.5.1 1st Order LPF

This first-order low pass active filter consists simply of a passive RC filter stage
providing a low frequency path to the input of a non-inverting operational amplifier.
The amplifier is configured as a voltage-follower (Buffer) giving it a DC gain of one,
Av = +1 or unity gain as opposed to the previous passive RC filter which has a DC gain
of less than unity.

The advantage of this configuration is that the op-amps high input impedance prevents
excessive loading on the filters output while its low output impedance prevents the
filters cut-off frequency point from being affected by changes in the impedance of the
load.

While this configuration provides good stability to the filter, its main disadvantage is
that it has no voltage gain above one. However, although the voltage gain is unity the
power gain is very high as its output impedance is much lower than its input impedance.
If a voltage gain greater than one is required we can use the following filter circuit.

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Active Low Pass Filter with Amplification

Fig.5.2 Active LPF with Amplifier

The frequency response of the circuit will be the same as that for the passive RC filter,
except that the amplitude of the output is increased by the pass band gain, AF of the
amplifier. For a non-inverting amplifier circuit, the magnitude of the voltage gain for
the filter is given as a function of the feedback resistor ( R2 ) divided by its
corresponding input resistor ( R1 ) value and is given as:

2
DC gain = (1 + )
1
Therefore, the gain of an active low pass filter as a function of frequency will be: Gain
of a first-order low pass filter


() =
2
1 + ( )

Where:

AF = the pass band gain of the filter, (1 + R2/R1) = the frequency of the input signal
in Hertz, (Hz)
c = the cut-off frequency in Hertz, (Hz)

Thus, the operation of a low pass active filter can be verified from the frequency gain
equation above as:

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3

1. At very low frequencies, <


2. At the cut-off frequency, = c = 0.707
2


3. At very high frequencies, > <

Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high
frequency cut-off point,C. At C the gain is 0.707AF, and after C it decreases at a
constant rate as the frequency increases. That is, when the frequency is increased
tenfold (one decade), the voltage gain is divided by 10.

In other words, the gain decreases 20dB (= 20log 10) each time the frequency is
increased by 10. When dealing with filter circuits the magnitude of the pass band gain
of the circuit is generally expressed indecibels or dB as a function of the voltage gain,
and this is defined as:

Magnitude of Voltage Gain in (dB)


() = 2010 ( )


3 = 2010 (0.707 )

Second-order Low Pass Active Filter

As with the passive filter, a first-order low-pass active filter can be converted into a
second-order low pass filter simply by using an additional RC network in the input
path. The frequency response of the second-order low pass filter is identical to that of
the first-order type except that the stop band roll-off will be twice the first-order filters
at 40dB/decade (12dB/octave). Therefore, the design steps required of the second-order
active low pass filter are the same.

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Second-order Active Low Pass Filter Circuit

Fig.5.3 2nd Order Active LPF

When cascading together filter circuits to form higher-order filters, the overall gain of
the filter is equal to the product of each stage. For example, the gain of one stage may
be 10 and the gain of the second stage may be 32 and the gain of a third stage may be
100. Then the overall gain will be 32,000, (10 x 32 x 100) as shown below.

4.5.5.2 Lecture-2

First Order High Pass Filter

Fig.5.4 1st Order HPF

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Technically, there is no such thing as an active high pass filter. Unlike Filters which
have an infinite frequency response, the maximum pass band frequency response of
an active high pass filter is limited by the open-loop characteristics or bandwidth of the
operational amplifier being used, making them appear as if they are band pass filters
with a high frequency cut-off determined by the selection of op-amp and gain.

In the Operational Amplifier tutorial we saw that the maximum frequency response of
an op-amp is limited to the Gain/Bandwidth product or open loop voltage gain ( A V )
of the operational amplifier being used giving it a bandwidth limitation, where the
closed loop response of the op amp intersects the open loop response.
A commonly available operational amplifier such as the uA741 has a typical open-
loop (without any feedback) DC voltage gain of about 100dB maximum reducing at a
roll off rate of -20dB/Decade (-6db/Octave) as the input frequency increases. The gain
of the uA741 reduces until it reaches unity gain, (0dB) or its transition frequency (
t ) which is about 1MHz. This causes the op-amp to have a frequency response curve
very similar to that of a first-order low pass filter and this is shown below.

Fig.5.5 Frequency response curve of a typical Operational Amplifier

Then the performance of a high pass filter at high frequencies is limited by this unity
gain crossover frequency which determines the overall bandwidth of the open- loop
amplifier. The gain-bandwidth product of the op-amp starts from around 100kHz for
small signal amplifiers up to about 1GHz for high-speed digital video amplifiers and
op-amp based active filters can achieve very good accuracy and performance provided
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that low tolerance resistors and capacitors are used.

Under normal circumstances the maximum pass band required for a closed loop active
high pass or band pass filter is well below that of the maximum open-loop transition
frequency. However, when designing active filter circuits it is important to choose the
correct op-amp for the circuit as the loss of high frequency signals may result in signal
distortion.

Active High Pass Filter

A first-order (single-pole) Active High Pass Filter as its name implies, attenuates low
frequencies and passes high frequency signals. It consists simply of a passive filter
section followed by a non-inverting operational amplifier. The frequency response of
the circuit is the same as that of the passive filter, except that the amplitude of the signal
is increased by the gain of the amplifier and for a non- inverting amplifier the value of
the pass band voltage gain is given as 1 + R2/R1, the same as for the low pass filter
circuit.

Active High Pass Filter with Amplification

Fig.5.6 Active HPF with Amplifier

This first-order high pass filter consists simply of a passive filter followed by a non-
inverting amplifier. The frequency response of the circuit is the same as that of the
passive filter, except that the amplitude of the signal is increased by the gain of the
amplifier.

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For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is
given as a function of the feedback resistor ( R2 ) divided by its corresponding input
resistor ( R1 ) value and is given as:
Gain for an Active High Pass Filter


( )

() =
2
1 + ( )

Where:


AF = the Pass band Gain of the filter, ( 1 + 2 )
1

= the Frequency of the Input Signal in Hertz, (Hz) c = the Cut-off Frequency in
Hertz, (Hz)

Just like the low pass filter, the operation of a high pass active filter can be verified
from the frequency gain equation above as:


1. At very low frequencies, < <


2. At the cut-off frequency, = c = = 0.707
2


3. At very high frequencies, >

Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the low
frequency cut-off point, C at 20dB/decade as the frequency increases. At C the gain
is 0.707AF, and after C all frequencies are pass band frequencies so the filter has a
constant gain AF with the highest frequency being determined by the closed loop

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bandwidth of the op-amp.

When dealing with filter circuits the magnitude of the pass band gain of the circuit is
generally expressed in decibels or dB as a function of the voltage gain, and this is
defined as:

Magnitude of Voltage Gain in (dB)


() = 2010 ( )


3 = 2010 (0.707 )

For a first-order filter the frequency response curve of the filter increases by
20dB/decade or 6dB/octave up to the determined cut-off frequency point which is
always at -3dB below the maximum gain value. As with the previous filter circuits, the
lower cut-off or corner frequency ( c ) can be found by using the same formula:

1
=
2

The corresponding phase angle or phase shift of the output signal is the same as that
given for the passive RC filter and leads that of the input signal. It is equal to +45o at
the cut-off frequency c value and is given as:

1
= 1 ( )
2

A simple first-order active high pass filter can also be made using an inverting
operational amplifier configuration as well, and an example of this circuit design is
given along with its corresponding frequency response curve. A gain of 40dB has been
assumed for the circuit.

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Inverting Operational Amplifier Circuit

Fig.5.7 Inverting Op-amp

Frequency Response Curve

Fig.5.8 Frequency Response Curve

Second-order High Pass Active Filter

As with the passive filter, a first-order high pass active filter can be converted into a
second-order high pass filter simply by using an additional RC network in the input
path. The frequency response of the second-order high pass filter is identical to that of
the first-order type except that the stop band roll-off will be twice the first-order filters
at 40dB/decade (12dB/octave). Therefore, the design steps required of the second-order
active high pass filter are the same.

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Second-order Active High Pass Filter Circuit

Fig.5.9 2nd Order Active HPF

Active Band Pass Filter Circuit

Fig.5.10 Active BPF

This cascading together of the individual low and high pass passive filters produces a
low Q-factor type filter circuit which has a wide pass band. The first stage of the
filter will be the high pass stage that uses the capacitor to block any DC biasing from
the source. This design has the advantage of producing a relatively flat asymmetrical

pass band frequency response with one half representing the low pass response and the

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other half representing high pass response as shown.

Fig.5.11 Frequency Response of BPF

The higher corner point ( H ) as well as the lower corner frequency cut-off point( L
) are calculated the same as before in the standard first-order low and high pass filter
circuits. Obviously, a reasonable separation is required between the two cut-off points
to prevent any interaction between the low pass and high pass stages. The amplifier
also provides isolation between the two stages and defines the overall voltage gain of
the circuit.

The bandwidth of the filter is therefore the difference between these upper and lower-
3dB points. For example, suppose we have a band pass filter whose -3dB cut-off points
are set at 200Hz and 600Hz. Then the bandwidth of the filter would be given as:
Bandwidth (BW) = 600 200 = 400Hz.

The normalized frequency response and phase shift for an active band pass filter will
be as follows.

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Fig.5.12 Active Band Pass Frequency Response

While the above passive tuned filter circuit will work as a band pass filter, the pass
band (bandwidth) can be quite wide and this may be a problem if we want to isolate a
small band of frequencies. Active band pass filter can also be made using inverting
operational amplifier.
So by rearranging the positions of the resistors and capacitors within the filter we can
produce a much better filter circuit as shown below. For an active band pass filter, the
lower cut-off -3dB point is given by C1 while the upper cut-off -3dB point is given by
C2.

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Inverting Band Pass Filter Circuit

Fig.5.13 Inverting BPF


= , = , =

This type of band pass filter is designed to have a much narrower pass band. The centre
frequency and bandwidth of the filter is related to the values of R1, R2, C1 and
C2. The output of the filter is again taken from the output of the op-amp.

4.5.5.3 Lecture-3

Band Reject filters:

The band pass filter passes one set of frequencies while rejecting all others. The band-
stop filter does just the opposite. It rejects a band of frequencies, while passing all
others. This is also called a band-reject or band-elimination filter. Like band pass filters,
band-stop filters may also be classified as (i) wide-band and (ii) narrow band reject
filters. The narrow band reject filter is also called a notch filter. Because of its higher
Q, which exceeds 10, the bandwidth of the narrow band reject filter is much smaller
than that of a wide band reject filter.

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Wide Band-Stop (or Reject) Filter

Fig.5.14 Wide band stop filter

A wide band-stop filter using a low-pass filter, a high-pass filter and a summing
amplifier is shown in figure. For a proper band reject response, the low cut-off
frequency fL of high-pass filter must be larger than the high cut-off frequency fH of
the low-pass filter. In addition, the pass band gain of both the high-pass and low-pass
sections must be equal.

Narrow Band-Stop Filter

Fig.5.15 Narrow Band-Stop Filter


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Fig.5.16 Narrow Band-Stop Filter Response

network illustrated in Fig.5.16 . This is a passive filter composed of two T-shaped


networks. One T-network is made up of two resistors and a capacitor, while the other
is made of two capacitors and a resistor. One drawback of above notch filter (passive
twin-T network) is that it has relatively low figure of merit Q. However, Q of the
network can be increased significantly if it is used with the voltage follower, as
illustrated in fig. (a). Here the output of the voltage follower is supplied back to the
junction of R/2 and 2 C. The frequency response of the active notch filter is shown in
fig (b).

Fig.5.17 Frequency Response of Narrow Band-Stop Filter

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Notch filters are most commonly used in communications and biomedical instruments
for eliminating the undesired frequencies.
A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a
phase angle, shown in fig. (b). Again, there is a frequency fc at which the phase shift
is equal to 0. In fig. (c), the voltage gain is equal to 1 at low and high frequencies. In
between, there is a frequency fc at which voltage gain drops to zero. Thus such a filter
notches out, or blocks frequencies near fc. The frequency at which maximum
attenuation occurs is called the notch-out frequency given by

= = 2

Notice that two upper capacitors are C while the capacitor in the centre of the network
is 2 C. Similarly, the two lower resistors are R but the resistor in the centre of the
network is 1/2 R. This relationship must always be maintained.

All pass filters:

An all-pass filter is that which passes all frequency components of the input signal
without attenuation but provides predictable phase shifts for different frequencies of
the input signals. The all-pass filters are also called delay equalizers or phase
correctors. An all-pass filter with the output lagging behind the input is illustrated in
figure.

Fig. 5.18 All Pass Filter

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The output voltage Vout of the filter circuit shown in Fig .5.18 can be obtained by
using the superposition theorem.


= + [ ]

Where f is the frequency of the input signal in Hz.

From equations given above it is obvious that the amplitude of vout / vin is unity, that is
|Vout | = |Vin| throughout the useful frequency range and the phase shift between the
input and output voltages is a function of frequency

By interchanging the positions of R and C in the circuit shown in fig. (a), the output
can be made leading the input. These filters are most commonly used in
communications. For instance, when signals are transmitted over transmission lines
(such as telephone wires) from one point to another point, they undergo change in
phase. To compensate for such phase changes, all-pass filters are employed

4.5.6 Test Questions

a) Fill in the blanks type of questions

1) This circuit is known as a ________ filter, and the fc is ________( high-


pass, 15.9 kHz)

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2) Filters with the ________ characteristic are used for filtering pulse
waveforms.( Bessel)
3) Which filter exhibits a linear phase characteristic(Bessel)
4) The critical frequency is defined as the point at which the response drops
________ from the passband(3 dB)
5) Filters with the ________ characteristic provide a very flat amplitude in
the passband and a roll-off rate of 20 dB/decade/pole.( Butterworth)
6) Which filter exhibits the most rapid roll-off rate(Chebyshev)
7) Which filter has a maximally flat response(Butterworth)
8) Identify the frequency response curve for a high-pass filter (b)

9) A ________ filter rejects all frequencies within a specified band and


passes all those outside this band.( band-stop)
10) A ________ filter significantly attenuates all frequencies below fc and
passes all frequencies above fc(high-pass)

b) True or False questions


1) A band-pass filter can be created by cascading a high-pass filter and a low-
pass filter(T).
2) The bandwidth of a band-pass filter is the sum of the two cutoff
frequencies(F).
3) A Sallen-Key filter is a second-order filter(T).
4) Filters with Bessel characteristics are used for filtering pulse
waveforms(T).
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5) Filters with Bessel characteristics are used for filtering pulse waveforms(F).
6) Filters with Bessel characteristics are used for filtering pulse
waveforms(T).
7) A band-pass filter passes all frequencies within a band between a lower and
an upper cut-off frequency(T)
8) An active filter uses capacitors and inductors in the feedback network(F).
9) A second-order filter has a roll-off of 20 dB/decade(F)
c) Multiple choice questions
1) Which filter performs exactly the opposite to the band-pass filter?

a) Band-reject filter
b) Band-stop filter
c) Band-elimination filter
d) All of the mentioned

2) Given the lower and higher cut-off frequency of a band-pass filter are
2.5kHz and 10kHz. Determine its bandwidth.

a) 750 Hz
b) 7500 Hz
c) 75000 Hz
d) None of the mentioned
3) In which filter the output and input voltages are equal in amplitude for all
frequencies?
a) All-pass filter
b) High pass filter
c) Low pass filter
d) All of the mentioned
4) The gain of the first order low pass filter
a) Increases at the rate 20dB/decade
b) Increases at the rate 40dB/decade
c) Decreases at the rate 20dB/decade
d) Decreases at the rate 40dB/decade
5) Which among the following has the best stop band response?
a) Butterworth filter
b) Chebyshev filter
c) Cauer filter
d) All of the mentioned
6) the order of filter used, when the gain increases at the rate of 60dB/decade
on the stop band.
a) Second-order low pass filter
b) Third-order High pass filter
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c) First-order low pass filter
d) None of the mentioned
7) Name the filter that has two stop bands?
a) Band-pass filter
b) Low pass filter
c) High pass filter
d) Band-reject filter
8) The frequency response of the filter in the stop band.
i. Decreases with increase in frequency
ii. Increase with increase in frequency
iii. Decreases with decrease in frequency
iv. Increases with decrease in frequency
a) i and iv
b) ii and iii
c) i and ii
d) ii and iv

4.5.7 Review Questions

a. Objective type of questions


1) Define the term roll of rate?
2) What is the gain of 1st order Butterworth low pass filter?
3) Draw the frequency response of 3rd order Butterworth low pass
filter?

b. Analytical type questions


1) This filter has a roll-off rate of

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2) This is a ________ filter, and it has a cutoff frequency of ________

3) A low-pass filter has a cutoff frequency of 1.23 kHz. Determine the


bandwidth of the filter ?

C) Essay type Questions


1) Derive the gain for 1st order butterworth low pass filter?
2) Derive the gain and magnitude for all pass filter?
3) Draw and explain the expression for sallen and key high
pass filter?
D) Problems
1) Form the the given figure. RA = 2.2 k and RB = 1.2 k . This
filter is probably a

E) Case study
NA

4.5.8 Skill Building Exercises/Assignments

Eg:- -Prepare a model of something


-Trace something

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-Prepare a report on something etc.,
1. Draw the functional diagram of monostable multivibrator using 555 timer. Explain the
operation using relevant waveforms.
2. Discuss the application of PLL as (a)Frequency Translator
(b) AM demodulator

3. Draw the diagram of Schmitt trigger using 555 timer. Explain the operation using relevant
waveforms.
4. Explain the operation of PLL using a block schematic. Also explain the terms Lock-in
range, capture range, pull-in time.

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5 Give the block diagram of IC566 VCO and explain the operation.

6 Discuss the applications of VCO in detail.

7 Applying 555 timer explain PWM generation using relevant block diagrams and
waveforms.
8 Explain Astable multivibrator circuit using 555. Also derive expression for time
period.
9 List the applications of PLL. Explain any two applications of PLL in detail.

10 Draw the diagram of Schmitt trigger using 555 timer. Explain the operation using
relevant waveforms.

4.5.9 Previous Questions (Asked by JNTUK from the concerned Unit)

1. a) Draw the functional diagram of monostable multi vibrator using 555 timer. Explain the
operation using relevant waveforms.

b) Discuss the application of PLL as a frequency translator.

2. (a) Draw the block diagram of a 565 PLL and explain its salient features. Derive the
expression for capture range.
(b) Explain the application of PLL as a frequency translator.

3. (a)Design an astable multivibrator using 555 Timer to operate at 10 KHz with 40% duty
cycle.

(b)With a suitable circuit diagram using NE 565 PLL IC, explain the implementation of a
frequency translation.

4.5.10 GATE Questions (Where relevant)

NA

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4.5.11 Interview questions (which are frequently asked in a Technical round -
Placements)

NA

4.5.12 Real-Word (Live) Examples / Case studies wherever applicable

NA

4.5.13 Suggested Expert Guest Lectures (both from in and outside of the campus)
NA

4.5.14 Literature references of Relevant NPTEL Videos/Web/You Tube videos etc.

NA

4.5.15 Any Lab requirements; if so link it to Lab Lesson Plan.

NA

4.5.16 Reference Text Books / with Journals Chapters etc.

T1. Op-amps and Linear Integrated Circuits --- Ramakant A Gaykwad


T2. Linear Integrated Circuits --- D.Roy Choudhury & Shail B.Jain

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4.6 Unit VI DIGITAL TO ANALOG & ANALOG TO DIGITAL CONVERTERS
4.6.1 Syllabus

Introduction, basic DAC techniques, weighted resistor DAC, R-2R ladder DAC, inverted R-2R
DAC, and IC 1408 DAC, Different types of ADCs parallel Comparator type ADC, counter type
ADC, successive approximation ADC and dual slope ADC.DAC and ADC Specifications,
Specifications AD 574 (12 bit ADC)

4.6.2 Unit Objectives:


After reading this Unit, you should be able to understand:

- Purpose of DACs and ADCs


- Design of different types of DACs
- Design of different types of ADCs
4.6.3 Unit Outcomes

- Student will understand the purpose of ADCs and DACs.


- Student will be able to analyze different types of DACs and ADCs.

4.6.4 Unit Lecture Plan

Lecture no. Topic Methodology Quick reference


54. Introduction, DAC and ADC Presentation T2: Ch-10
Specifications Pg.No.348, 366
55. Weighted resistor DAC Presentation T2: Ch-10
Pg.No.349-351
56. R-2R ladder DAC Presentation T2: Ch-10
Pg.No.352-353
57. Inverted R-2R DAC, and IC Presentation T2: Ch-10
1408 DAC Pg.No.353-354
58. TUTORIAL

161
59. Counter type ADC Presentation T2: Ch-10
Pg.No.360-361
60. Successive approximation Presentation T2: Ch-10
ADC Pg.No.361-363
61. Parallel Comparator type Presentation T2: Ch-10
ADC Pg.No.358-359
62. Dual slope ADC Presentation T2: Ch-10
Pg.No.363-365
63. Specifications AD 574 (12 Presentation T2: Ch-10
bit ADC) Pg.No.367
64. TUTORIAL

4.6.5 Teaching Material / Teaching Aids as per above lecture plan


4.6.5.1 Lecture-1

DAC.ppt

4.6.5.2 Lecture-2

DAC.ppt

Binary-Weighted Resistor DAC


The binary-weighted-resistor DAC employs the characteristics of the inverting summer
Op Amp circuit. In this type of DAC, the output voltage is the inverted sum of all the
input voltages. If the input resistor values are set to multiples of two: 1R, 2R and 4R, the
output voltage would be equal to the sum of V1, V2/2 and V3/4. V1 corresponds to

Fig.6.1 Binary weighted resistor network

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the most significant bit (MSB) while V3 corresponds to the least significant bit (LSB).The
circuit for a 4-bit DAC using binary weighted resistor network is shown below

Fig.6.2 4-bit DAC using binary weighted resistor network


The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The value, 0,
represents an open switch while 1 represents a closed switch. The operational amplifier
is used as a summing amplifier, which gives a weighted sum of the binary input based on
the voltage, Vref. For a 4-bit DAC, the relationship between Vout and the binary input is
as follows:

1 2 3 4
= ( + + + )
2 4 8 16
1 2 3 4
= ( + + + )
2 4 8 16
1 2 3 4
= (+ + + )
21 21 23 24
The negative sign associated with the analog output is due to the connection to a summing
amplifier, which is a polarity-inverting amplifier. When a signal is applied to the latter
type of amplifier, the polarity of the signal is reversed (i.e. a + input becomes -, or vice
versa). For a n-bit DAC, the relationship between Vout and the binary input is as follows:


=
2
=1

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4.6.5.3 Lecture-3

DAC.ppt

Fig.6.3: R-2R ladder network


Vref is nothing but the input binary value reference voltage, that is for binary
1, Vref=5V and for binary 0, Vref=0V.
For 0001 only D0=Vref, all other inputs are at 0V and can be treated as ground. So
finally Vref/16 volt is appearing as the input to op amp. This value gets multiplied
by the gain of op amp circuit (Rf/Ri).
If we proceed in this manner (Thevenin equivalent reduction), we will get
0 1 2 3
= [ + + + ]
16 8 4 2

Note that you can build a DAC with any number of bits you want, by simply
enlarging the resistor network, by adding more R-2R resistor branches.

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In this circuit the 7493 IC simply provides digital inputs to DAC. It is a counter
IC and not an integral part of the DAC circuit. You can apply any combinations
of binary inputs to D3D2D1D0

4.6.5.4 Lecture-4

Inverted R-2R ladder DAC

Fig.6.4: Inverted R-2R ladder DAC

4.6.5.5 Lecture-5

ADC.ppt

Counter Type ADC (Analog to Digital Converter)


The Counter type ADC is the basic type of ADC which is also called as digital ramp
type ADC or stair case approximation ADC. This circuit consists of N bit counter, DAC
and Op-amp comparator as shown in below figure.

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Operation of counter type ADC

The N bit counter generates an n bit digital output which is applied as an input to the
DAC. The analog output corresponding to the digital input from DAC is compared with
the input analog voltage using an opamp comparator. The opamp compares the two
voltages and if the generated DAC voltage is less, it generates a high pulse to the N bit
counter as a clock pulse to increment the counter. The same process will be repeated until
the DAC output equals to the input analog voltage.

If the DAC output voltage is equal to the input analog voltage, then it generates low clock
pulse and it also generates a clear signal to the counter and load signal to the storage
resistor to store the corresponding digital bits. These digital values are closely matched
with the input analog values with small quantization error.

For every sampling interval the DAC output follows a ramp fashion so that it is called as
Digital ramp type ADC. And this ramp looks like stair cases for every sampling time so
that it is also called as staircase approximation type ADC.

Fig.6.5: Counter type ADC

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Conversion time of Counter type ADC
Conversion time of ADC is the time taken by the ADC to convert the input sampled
analog value to digital value. Here the maximum conversion of high input voltage for a
N bit ADC is the clock pulses required to the counter to count its maximum count value.
So The maximum conversion of Counter type ADC is = (2N-1) T Where, T is the time
period of clock pulse.
If N=2 bit then the Tmax = 3T.

By observing the above conversion time of Counter type ADC it is illustrated that the
sampling period of Counter type ADC should be as shown below.
Ts >= (2N-1) T

Advantages of Counter type ADC

Simple to understand and operate.

Cost is less because of less complexity in design.

Disadvantages or limitations of Counter type of ADC

Speed is less because every time the counter has to start from ZERO.

There may be clash or aliasing effect if the next input is sampled before
completion of one operation.

4.6.5.6 Lecture 6

TUTORIAL

4.6.5.7 Lecture 7

ADC.ppt

167
Successive Approximation ADC

method of addressing the digital ramp ADCs shortcomings is the so- called
successive-approximation ADC. The only change in this design is a very special counter
circuit known as a successive-approximation register. Instead of counting up in binary
sequence, this register counts by trying all values of bits starting with the most-significant
bit One and finishing at the least-significant bit. Throughout the count process, the register
monitors the comparators output to see if the binary count is less than or greater than the

analog signal input, adjusting the bit values accordingly. The way the register counts is
identical to the trial-and-fit method of decimal-to-binary conversion, whereby different
values of bits are tried from MSB to LSB to get a binary number that equals the original
decimal number. The advantage to this counting strategy is much faster results: the DAC
output converges on the analog signal input in much larger steps than with the 0-to-full
count sequence of a regular counter.

Fig.6.6: Successive Approximation ADC


Without showing the inner workings of the successive-approximation register (SAR), the
circuit looks like this:

It should be noted that the SAR is generally capable of outputting the binary number in
serial (one bit at a time) format, thus eliminating the need for a shift register. Plotted over
time, the operation of a successive-approximation ADC looks like this:

168
Note how the updates for this ADC occur at regular intervals, unlike the digital ramp
ADC circuit

4.6.5.8 Lecture 8

ADC.ppt

Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique
reference voltage. The comparator outputs connect to the inputs of a priority encoder
circuit, which then produces a binary output. The following illustration shows a 3-bit

Fig.6.7: Flash ADC

169
ADC circuit:
Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds
the reference voltage at each comparator, the comparator outputs will sequentially
saturate to a high state. The priority encoder generates a binary number based on the
highest-order active input, ignoring all other active inputs.

When operated, the flash ADC produces an output that looks something like this:

For this particular application, a regular priority encoder with all its inherent complexity
isnt necessary. Due to the nature of the sequential comparator output states (each
comparator saturating high in sequence from lowest to highest), the same highest-
order-input selection effect may be realized through a set of Exclusive-OR gates,
allowing the use of a simpler, non-priority encoder:

170
And, of can be made from a matrix of diodes, demonstrating just how simply this
converter design may be constructed course, the encoder circuit itself:

Not only is the flash converter the simplest in terms of operational theory, but it is the
most efficient of the ADC technologies in terms of speed, being limited only in
comparator and gate propagation delays. Unfortunately, it is the most component-
intensive for any given number of output bits. This three-bit flash ADC requires seven
comparators. A four-bit version would require 15 comparators. With each additional
171
output bit, the number of required comparators doubles. Considering that eight bits is
generally considered the minimum necessary for any practical ADC (255 comparators
needed), the flash methodology quickly shows its weakness.
An additional advantage of the flash converter, often overlooked, is the ability for it to
produce a non-linear output. With equal-value resistors in the reference voltage divider
network, each successive binary count represents the same amount of analog signal
increase, providing a proportional response. For special applications, however, the
resistor values in the divider network may be made non-equal. This gives the ADC a
custom, nonlinear response to the analog input signal. No other ADC design is able to
grant this signal-conditioning behavior with just a few component value changes.

4.6.5.9 Lecture 9

ADC.ppt

Slope (integrating) ADC

So far, weve only been able to escape the sheer volume of components in the flash
converter by using a DAC as part of our ADC circuitry. However, this is not our only
option. It is possible to avoid using a DAC if we substitute an analog ramping circuit and
a digital counter with precise timing. The is the basic idea behind the so-called single-
slope, or integrating ADC. Instead of using a DAC with a ramped output, we use
an op-amp circuit called an integrator to generate a sawtooth waveform which is then
compared against the analog input by a comparator. The time it takes for the sawtooth
waveform to exceed the input signal voltage level is measured by means of a digital
counter clocked with a precise-frequency square wave (usually from a crystal oscillator).
The basic schematic diagram is shown here:
The IGFET capacitor-discharging transistor scheme shown here is a bit oversimplified.
In reality, a latching circuit timed with the clock signal would most likely have to be
connected to the IGFET gate to ensure full discharge of the capacitor when the

172
comparators output goes high. The basic idea, however, is evident in this diagram. When
the comparator output is low (input voltage greater than integrator output), the integrator
is allowed to charge the capacitor in a linear fashion. Meanwhile, the counter is counting
up at a rate fixed by the precision clock frequency. The time it takes for the capacitor to
charge up to the same voltage level as the input depends on the input signal level and the
combination of - Vref, R, and C. When the capacitor reaches that voltage level, the
comparator output goes high, loading the counters output into the shift register for a final
output. The IGFET is triggered on by the comparators high output, discharging the
capacitor back to zero volts. When the integrator output voltage falls to zero, the
comparator output switches back to a low state, clearing the counter and enabling the
integrator to ramp up voltage again.

This ADC circuit behaves very much like the digital ramp ADC, except that the
comparator reference voltage is a smooth sawtooth waveform rather than a stairstep:

The single-slope ADC suffers all the disadvantages of the digital ramp ADC, with the
added drawback of calibration drift. The accurate correspondence of this ADCs output
with its input is dependent on the voltage slope of the integrator being matched to the
counting rate of the counter (the clock frequency). With the digital ramp ADC, the clock
frequency had no effect on conversion accuracy, only on update time. In this circuit, since
the rate of integration and the rate of count are independent of each other, variation
173
between the two is inevitable as it ages, and will result in a loss of accuracy. The only
good thing to say about this circuit is that it avoids the use of a DAC, which reduces
circuit complexity.

An answer to this calibration drift dilemma is found in a design variation called the dual-
slope converter. In the dual-slope converter, an integrator circuit is driven positive and
negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts
at the end of every cycle. In one direction of ramping, the integrator is driven by the
positive analog input signal (producing a negative, variable rate of output voltage change,
or output slope) for a fixed amount of time, as measured by a counter with a precision
frequency clock. Then, in the other direction, with a fixed reference voltage (producing a
fixed rate of output voltage change) with time measured by the same counter. The counter
stops counting when the integrators output reaches the same voltage as it was when it
started the fixed- time portion of the cycle. The amount of time it takes for the integrators
capacitor to discharge back to its original output voltage, as measured by the magnitude
accrued by the counter, becomes the digital output of the ADC circuit.

The dual-slope method can be thought of analogously in terms of a rotary spring such
as that used in a mechanical clock mechanism. Imagine we were building a mechanism
to measure the rotary speed of a shaft. Thus, shaft speed is our input signal to be
measured by this device. The measurement cycle begins with the spring in a relaxed
state. The spring is then turned, or wound up, by the rotating shaft (input signal) for
a fixed amount of time. This places the spring in a certain amount of tension
proportional to the shaft speed: a greater shaft speed corresponds to a faster rate of
winding. and a greater amount of spring tension accumulated over that period of time.
After that, the spring is uncoupled from the shaft and allowed to unwind at a fixed rate,
the time for it to unwind back to a relaxed state measured by a timer device. The amount
of time it takes for the spring to unwind at that fixed rate will be directly proportional
to the speed at which it was wound (input signal magnitude) during the fixed-time
portion of the cycle.
This technique of analog-to-digital conversion escapes the calibration drift problem of
the single-slope ADC because both the integrators integration coefficient (or gain)

174
and the counters rate of speed are in effect during the entire winding and
unwinding cycle portions. If the counters clock speed were to suddenly increase,
this would shorten the fixed time period where the integrator winds up (resulting in
a lesser voltage accumulated by the integrator), but it would also mean that it would
count faster during the period of time when the integrator was allowed to unwind at
a fixed rate. The proportion that the counter is counting faster will be the same
proportion as the integrators accumulated voltage is diminished from before the clock
speed change. Thus, the clock speed error would cancel itself out and the digital output
would be exactly what it should be.

Another important advantage of this method is that the input signal becomes averaged as
it drives the integrator during the fixed-time portion of the cycle. Any changes in the
analog signal during that period of time have a cumulative effect on the digital output at
the end of that cycle. Other ADC strategies merely capture the analog signal level at a
single point in time every cycle. If the analog signal is noisy (contains significant levels
of spurious voltage spikes/dips), one of the other ADC converter technologies may
occasionally convert a spike or dip because it captures the signal repeatedly at a single
point in time. A dual-slope ADC, on the other hand, averages together all the spikes and
dips within the integration period, thus providing an output with greater noise immunity.
Dual-slope ADCs are used in applications demanding high accuracy.

4.6.5.10 Lecture 10

ADC.ppt
4.6.5.11

TUTORIAL

4.6.6
a. Multiple choice questions

1.Find out the resolution of 8 bit DAC/ADC?


a) 562
175
b) 625
c) 256

d) 265

2.Non-linearity in the output of converter is expressed in


a) none of the mentioned
b) Percentage of reference voltage

c) Percentage of resolution

d) Percentage of full scale voltage

3. A binary input 000 is fed to a 3bit DAC/ADC. The resultant output is 101.
Find the type of error?
a) Settling error
b) Gain error
c) Offset error
d) Linearity error

4.How many equal intervals are present in a 14-bit D-A


converter?
a) 16383
b) 4095
c) 65535
d) 1023

5. Resolution of a 6 bit DAC can be stated as


a) All of the mentioned
b) 6-bit resolution
c) Resolution of 1.568% of full scale d)
Resolution of 1 part in 63
6. Find the resolution of a 10-bit AD converter for an input range of 10v?

a) 97.7mv
b)9.77mv
c) 0.977mv
d) 977mv

7. A good converter exhibits a linearity error a) Less than or equal to (1/2) LSB

b) Greater than equal to (1/2) LSB


c)Greater than or equal to (1/2) LSB
176
b) none of the mentioned

8. The maximum deviation between actual and ideal converter output after the removal of
error is
a)Absolute accuracy
b)Relativeaccuray
c) Relative /absolute accuracy
d) Linearity

9. A monotonic DAC is one whose analog output increases for

a) Decreases in digital input


b) An increases in analog input

c) An increases in digital input

d) Decreases in analog input

10.Ina flash analog-to-digital converter, the output of each comparator is connected


to an input of a:
a) Decoder
b) Priority encoder
c) Multiplixer
d) demultiplixer

11. Which is not an analog-to-digital (ADC) conversion error?


a) Differential nonlinearity
b) Missing code
c) Incorrect code
d) Offset

12. Sample-and-hold circuits in analog-to digital converters (ADCs)

a) Sample and hold output off the binary counter during the conversion process
b) Stabilize the comparators threshold voltage during the conversion process
c) Stabilize the input analog signal during the conversion process
d) Sample and hold the D/A converter staircase waveform during the conversion process

177
b) True Or False

1)A sample-and-hold circuit samples an analog value and holds it long enough for the
analog-to-digital conversion to occur.(T)

2)Incorrect codes are a form of output error for a digital-to-analog converter (DAC).(F)

3)A digital-to-analog converter (DAC) is said to be nonmonotonic if the magnitude of the


output voltage increases every time the input code increases(F)

4)The relative accuracy of a digital-to-analog converter (DAC) is determined by settling


time.(F)

5)The key advantage of the successive approximation analog-to-digital converter (ADC)


is its conversion speed(T)

6)One way to determine the resolution of a digital-to-analog converter (DAC) is to


compare the ratio of one step voltage to the maximum output voltage(T)

7)In a binary-weighted digital-to-analog converter (DAC), the values of the input resistors
are chosen to be proportional to the binary weights of the corresponding input bits(F)

8)An 8-bit digital-to-analog converter (DAC) has a resolution of 0.125 V(F)

c) Fill in the Blanks

1) _______ analog-to-digital converters (ADCs) use no clock signal, because there is no


timing or sequencing required.(FLASH)

2) ______ analog-to-digital converters (ADCs) have a fixed value of conversion time that
is not dependent on the value of the analog input(Successive approximation)

3) The problems of the binary-weighted resistor digital-to-analog converter (DAC) can


be overcome by using ___________(an R/2R ladder DAC)

4) The number of binary bits at the input of a digital-to-analog converter (DAC) is known
as ________(resolution)

178
5) A(n) ________ converts an analog input to a digital output.( ADC)

6) The characteristic that a change of one binary step on the input of a digital-to-analog
converter (DAC) should cause exactly one step change on the output is called
________.(monotonicity)

7) Inaccurate analog-to-digital conversion may be due to ____________. (faulty sample-


and-hold circuitry)

8) A binary-weighted resistor used in a digital-to-analog converter (DAC) is only


practical up to a resolution of ________(4 bits)

4.6.7 Review Questions


a) Objective type of questions
1) Draw the block diagram of DAC?
2) Classifications of DAC?
3) Explain types of ADC?
b) Analytical type questions
1) Explain the limitation of binary-weighted digital-to-analog converters?
2) A binary-weighted digital-to-analog converter has an input resistor of 100 k
. If the resistor is connected to a 5 V source, the current through the resistor
is ?
3) A binary-weighted digital-to-analog converter has a feedback resistor, Rf, of
12 k. If 50 A of current is through the resistor, the voltage out of the circuit
is
c) Essay type Questions
1) Explain 3-bit binary weighted Resistor
2) Explain the classification of DAC and explain inverted R-2R ladder circuit?
d) Problems
1) A given 4-bit digital to analog converter has a reference voltage of 15 volts
and a binary inout of 0101. What is the proportionality factor?

2) Consider the following 3-bit ADC. Draw the conversion transfer function
(binary output vs input voltage) on the top graph. Draw the quantization error
transfer function (error voltage vs input voltage) on the bottom graph. Make
sure the transition points are clear. Assume Vref is 5V

179
3) Assume you have a 3-bit SAR ADC. The analog input is 0.65 V and the Vref
is 1V. Show how the SAR would approximate the analog input over three
cycles. Label the cycles on the x-axis and show the approximation as a
meandering stair-step line on the graph.

e) Case study NA
4.6.8 Skill Building Exercises/Assignments

Eg:- -Prepare a model of something


-Trace something
-Prepare a report on something etc.,
Assignment-6
1. Explain the operation of Flash ADC using relevant diagrams.
2. Compare and contrast Flash, dual slope, SAR type of ADCs.
3. Explain the operation of weighted resistor DAC with the help of relevant diagrams
and sketches.
4. Explain the operation of dual slope ADC.
5. Explain the various sources of errors in DAC.
6. Explain the counter type A/D converter in detail.
7. Discuss various DAC/ADC specifications.
8. Describe the operation of SAR type ADC.
9. Explain in detail with a neat circuit diagram the operation of a parallel comparator
type analog to digital converter.
10. Explain the following characteristics of ADC: resolution, accuracy, settling time,
linearity, conversion time.

4.6.9 Previous Questions (Asked by JNTUK from the concerned Unit)

1. a) Explain the operation of Flash ADC using relevant diagrams.


a) A dual slope ADC uses a 18-bit counter with a 5mHz clock. The maximum input voltage
is+12 V and the maximum integrator output voltage at 2N count is -10 V. If R= 100K_, find
the size of the capacitor to be used for integrator.

2(a) A dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The maximum input
voltage is +10V. The maximum integrator output voltage should be -8 V when the counter
180
has cycled through 2n counts. The capacitor used in the integrator is 0.1F. Find the value
of the resistor R of the integrator. If the analog signal voltage is +4.129 V, find the equivalent
digital number.
(b)Explain the working of successive approximation type converter and compare the
conversion times of tracking and successive approximation type ADCs.
3. a) List and compare different types of analog to digital converters.
(b) Explain the operation of successive approximation type ADC with neat circuit
diagram.
4.6.10 GATE Questions (Where relevant)

NA

4.6.11 Interview questions (which are frequently asked in a Technical round -


Placements)

NA

4.6.12 Real-Word (Live) Examples / Case studies wherever applicable

NA

4.6.13 Suggested Expert Guest Lectures (both from in and outside of the campus)

NA

4.6.14 Literature references of Relevant NPTEL Videos/Web/You Tube videos etc.

NA

4.6.15 Any Lab requirements; if so link it to Lab Lesson Plan.

NA

4.6.16 Reference Text Books / with Journals Chapters etc.

T1. Op-amps and Linear Integrated Circuits --- Ramakant A Gaykwad


T2. Linear Integrated Circuits --- D.Roy Choudhury & Shail B.Jain

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