Instrumentation Anthology Circuits From The Lab

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Instrumentation Anthology
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Instrumentation Anthology
Circuits from the Lab
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Anthology | Page 2 of 215

Instrumentation Anthology Circuits from the Lab Reference Designs
TABLE OF CONTENTS
Introduction ...................................................................................... 2 CN-0102: Precision Weigh Scale Design Using the AD7190
Revision History ............................................................................... 4 24-Bit Sigma-Delta ADC with Internal PGA ............................. 49
CN-0006: High Accuracy, Bipolar Data Conversion CN-0107: Weigh Scale Design Using the AD7780
(AD5764, ADR02) ............................................................................ 5 24-Bit Sigma-Delta ADC with Internal PGA ............................. 53
CN-0016: Interface Between I/Q Modulator and High Speed CN-0108: Weigh Scale Design Using the AD7781
DAC (AD9779A, ADL5370) ........................................................... 7 20-Bit Sigma-Delta ADC with Internal PGA ............................. 57
CN-0021: Interfacing the ADL5375 I/Q Modulator to the CN-0109: Low Jitter Sampling Clock Generator for High
AD9779A Dual-Channel, 1 GSPS High Speed DAC ................... 9 Performance ADCs Using the AD9958/AD9858
CN-0026: Precision, Unipolar, Inverting Conversion Using the 500 MSPS/1 GSPS DDS and AD9515 Clock Distribution IC .. 61
AD5547/AD5557 DAC .................................................................. 12 CN-0112: Variable Gain Noninverting Amplifier Using the
CN-0027: Precision, Unipolar, Noninverting Configuration for AD5292 Digital Potentiometer and the OP184 Op Amp ......... 64
the AD5547/AD5557 DAC ............................................................ 14 CN-0114: Low Cost, High Voltage, Programmable Gain
CN-0028: Precision, Bipolar, Configuration for the Instrumentation Amplifier Using the AD5292 Digital
AD5547/AD5557 DAC .................................................................. 16 Potentiometer and the AD8221 In-Amp ..................................... 67
CN-0030: AD5390/AD5391/AD5392 Channel Monitor CN-0118: Precision Weigh Scale Design Using the AD7191
Function ........................................................................................... 18 24-Bit Sigma-Delta ADC with Internal PGA ............................. 70
CN-0032: Converting a Single-Ended Signal with the AD7982 CN-0119: Precision WEigh Scale Design Using the AD7192
Differential PulSAR ADC .............................................................. 20 24-Bit Sigma-Delta ADC with Internal PGA ............................. 73
CN-0041: DC-Coupled, Single-Ended-to-Differential
CN-0123: Automated Calibration Technique that Reduces the
Conversion Using the AD8138 Low Distortion Differential
AD5360 16-Channel, 16-Bit DAC Offset Voltage to
ADC Driver and the AD7356 5 MSPS, 12-Bit SAR ADC ......... 22
Less Than 1 mV .............................................................................. 77
CN-0042: Driving the AD7366/AD7367 Bipolar SAR ADC in
CN-0131: 16 Channels of Programmable Output Span Using
Low Distortion, DC-Coupled Applications ................................ 24
the AD5360 16-Bit Voltage Output DAC ....................................79
CN-0046: Using the AD8352 as an Ultralow Distortion
Differential RF/IF Front End for High Speed ADCs ................. 26 CN-0133: Sensing Low-g Acceleration Using the ADXL345
Digital Accelerometer Connected to the ADuC7024 Precision
CN-0050: Stable, Closed-Loop Automatic Power Control for RF Analog Microcontroller ................................................................. 81
Applicatons ...................................................................................... 29
CN-0140: High Performance, Dual Channel IF Sampling
CN-0051: Driving the AD9233/AD9246/AD9254 ADCs in Receiver ............................................................................................ 84
AC-Coupled Baseband Applications............................................ 32
CN-0155: Precision Weigh Scale Design Using a 24-Bit Sigma-
CN-0052: Unipolar, Precision DC, Digital-to-Analog Delta ADC with InterNal PGA and AC Excitation .................... 88
Conversion Using the AD5450/AD5451/AD5452/AD5453 CN-0185: A Novel Analog-to-Analog Isolator Using an Isolated
8-/10-/12-/14-Bit DACs ................................................................. 35 Sigma-Delta Modulator, Isolated DC-to-DC Converter, and
CN-0053: Precision, Bipolar Configuration for the Active Filter ..................................................................................... 92
AD5450/AD5451/AD5452/AD5453 8-/10-/12-/14-Bit CN-0187: Crest Factor, Peak, and RMS RF Power Measurement
Multiplying DACs ........................................................................... 38 Circuit Optimized for High Speed, Low power, and
CN-0055: Programmable Gain Element Using the Single 3.3 V Supply ......................................................................... 96
AD5450/AD5451/AD5452/AD5453 Current Output DAC CN-0216: Precision Weigh Scale Design Using the AD7791
Family ............................................................................................... 41
24-Bit Sigma-Delta ADC with External ADA4528-1 Zero-Drift
CN-0073: High Accuracy, Bipolar Voltage Output Digital-to- Amplifiers ...................................................................................... 103
Analog Conversion Using the AD5765 DAC.............................. 43
CN-0237: Ultralow Power, 18-Bit, Differential PulSAR ADC
CN-0079: High Precision Digital-to-Analog Conversion Using Driver ............................................................................................. 108
the 16-Bit AD5542/AD5541 Voltage Output DAC, ADR421
Reference, and AD8628 Auto-Zero Op Amp .............................. 45
Circuits from the Lab Reference Designs Instrumentation Anthology
CN-0241: High-Side Current Sensing with Input Overvoltage CN-0373: Isolated USB to Isolated RS-485/Isolated RS-232
Protection .......................................................................................112 Interface ..........................................................................................161
CN-0326: Isolated Low Power pH Monitor with Temperature CN-0376: Channel-to-Channel Isolated Temperature Input
Compensation................................................................................118 (Thermocouple/RTD) for PLC/DCS Applications ...................167
CN-0357: Low Noise, Single-Supply, Toxic Gas Detector, Using CN-0381: Completely Integrated 4-Wire RTD Measurement
an Electrochemical Sensor with Programmable Gain TIA for System Using a Low Power, Precision, 24-Bit,
Rapid Prototyping ........................................................................ 125 Sigma-Delta ADC .........................................................................174
CN-0359: Fully Automatic High Performance Conductivity CN-0383: Completely Integrated 3-Wire RTD Measurement
Measurement System ................................................................... 130 System Using a Low Power, Precision, 24-Bit,
CN-0363: Dual-Channel Colorimeter with Programmable Sigma-Delta ADC .........................................................................184
Gain Transimpedance Amplifiers and Digital Synchronous CN-0384: Completely Integrated Thermocouple Measurement
Detection ........................................................................................140 System Using a Low Power, Precision, 24-Bit,
CN-0365: 16-Bit, 600 kSPS, Low Power Data Acquisition Sigma-Delta ADC .........................................................................195
System for High Temperature Environments ...........................148
CN-0387: Calibration-Free Return Loss Measurement
CN-0370: 16-Bit, Single-Supply LED Current Driver with Less System..............................................................................................207
Than ±1 LSB Integral and Differential Nonlinearity............... 155
REVISION HISTORY
2/2017—Revision 0: Initial Version

Circuit Note
CN-0006
Devices Connected/Referenced
Circuit Designs Using Analog Devices Products
AD5764 Complete Quad, 16-Bit, High Accuracy DAC
Apply these product pairings quickly and with confidence.
For more information and/or support call 1-800-AnalogD ADR02 Precision 5.0 V Voltage Reference
(1-800-262-5643) or visit www.analog.com/circuit.
High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion

Using the AD5764 DAC
CIRCUIT FUNCTION AND BENEFITS +15V
ADR02
2 VIN VOUT 6
This circuit provides high accuracy, bipolar data conversion GND
using the AD5764, a quad, 16-bit, serial input, bipolar voltage 4
output DAC. This circuit utilizes the ADR02 precision reference +15V –15V
to achieve optimal DAC performance over full operating 10µF 10µF
temperature range. The only external components needed for 100nF 100nF 100nF
this precision 16-bit DAC are a reference voltage source,

BIN/2sCOMP
decoupling capacitors on the supply pins and reference inputs, 32 31 30 29 28 27 26 25
and an optional short-circuit current setting resistor leading to +5V
REFGND
AVSS
NC
NC
REFCD
REFAB
AVDD
BIN/2sCOMP
savings in cost and board space. This circuit is well suited for
both closed-loop servo control and open-loop control SYNC 1 SYNC AGNDA 24
SCLK 2 SCLK VOUTA 23 VOUTA
applications. SDIN 3 SDIN VOUTB 22 VOUTB
CIRCUIT DESCRIPTION SDO 4
5
SDO
CLR
AD5764 AGNDB 21
AGNDC 20
The AD5764 is a high performance digital-to-analog converter LDAC 6 LDAC VOUTC 19 VOUTC
VOUTD 18
that offers guaranteed monotonicity, integral nonlinearity (INL) D0 7 D0 VOUTD
D1 8 D1 AGNDD 17
RSTOUT
of ±1 LSB (C-grade device), low noise, and 10 μs settling time.
RSTIN
DGND
PGND
DVCC
AVDD
AVSS
ISCC
Performance is guaranteed over wide operating supply voltage
ranges. The AVDD supply range is +11.4 V to +16.5 V, and the
9 10 11 12 13 14 15 16
100nF
100nF
RSTOUT
AVSS operating range is from −11.4 V to −16.5 V. The nominal RSTIN
10µF
full-scale output range is ±10 V. 10µF
100nF
A precision voltage reference must be used in order for the NC = NO CONNECT

DAC to achieve the optimum performance over its full +5V
10µF
5303-064
operating temperature range. The AD5764 incorporates +15V –15V
reference buffers, which eliminate the need for both a positive Figure 1. High Accuracy, Bipolar Configuration of the AD5764 DAC Using a
and negative external reference and associated buffers. This Precision Reference
leads to further savings in both cost and board space. Because
the voltages applied to the reference inputs (REFAB, REFCD) In any circuit where accuracy is important, careful considera-
are used to generate the buffered positive and negative internal tion of the power supply and ground return layout helps to
references for the DAC cores, any error in the external voltage ensure the rated performance. The PCB on which the AD5764
reference is reflected in the outputs of the device. is mounted must be designed so that the analog and digital
sections are physically separated and confined to certain areas
There are four possible sources of error to consider when
of the board. If the AD5764 is in a system where multiple
choosing a voltage reference for high accuracy applications:
devices require an AGND-to-DGND connection, the connec-
initial accuracy, temperature coefficient of the output voltage,
tion is to be made at one point only. The star ground point is
long term drift, and output voltage noise. Table 1 lists other 5 V
established as close as possible to the device. The AD5764 must
precision reference candidates from Analog Devices and their
have ample supply bypassing of 10 µF in parallel with 0.1 µF on
respective attributes.
each supply, located as close to the package as possible, ideally
right up against the device. The 10 µF capacitors are the
Rev. A
“Circuits from the Lab” from Analog Devices have been designed and built by Analog Devices
engineers. Standard engineering practices have been employed in the design and construction of
each circuit, and their function and performance have been tested and verified in a lab environment
at room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Devices be liable for direct, indirect, special, incidental, consequential, or punitive damages due to Tel: 781.329.4700 www.analog.com
any cause whatsoever connected to the use of any“Circuit from the Lab”. (Continued on last page) Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
CN-0006 Circuit Note
Table 1. Precision 5.0 V References

Initial Accuracy Max Long-Term Drift Typ Temp Drift Max 0.1 Hz to 10 Hz Noise
Part Number (mV) (ppm) (ppm/°C) Typ (µV p-p)
ADR435B ±2 40 3 8
ADR425B ±1 50 3 3.4
ADR02B ±3 50 3 10
ADR395B ±5 50 9 8
AD586T ±2.5 15 10 4
tantalum bead type. The 0.1 µF capacitor must have low

effective series resistance (ESR) and low effective series
LEARN MORE
inductance (ESL), such as the common ceramic types, which Kester, Walt. 2005. The Data Conversion Handbook. Analog
provide a low impedance path to ground at high frequencies to Devices. Chapters 3 and 7.
handle transient currents due to internal logic switching. MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
The power supply traces of the AD5764 must be as wide as Analog Devices.
possible to provide low impedance paths and reduce the effects MT-031 Tutorial, Grounding Data Converters and Solving the
of glitches on the power supply line. Fast switching signals, such Mystery of AGND and DGND. Analog Devices.
as clocks, must be shielded with digital ground to avoid
radiating noise to other parts of the board, and must never be MT-101 Tutorial, Decoupling Techniques. Analog Devices.
run near the reference inputs. A ground line routed between the Voltage Reference Wizard Design Tool.
SDIN and SCLK lines helps reduce crosstalk between them (not
required on a multilayer board, which has a separate ground
Data Sheets and Evaluation Boards
plane; however, it is helpful to separate the lines). It is essential AD5764 Data Sheet.
to minimize noise on the reference inputs because it couples AD5764 Evaluation Board.
through to the DAC output. Avoid crossover of digital and
ADR02 Data Sheet.
analog signals. Traces on opposite sides of the board must run
at right angles to each other. This reduces the effects of
feedthrough on the board. A microstrip technique is REVISION HISTORY
recommended, but not always possible with a double-sided 5/09—Rev. 0 to Rev. A
board. In this technique, the component side of the board is
Updated Format .................................................................. Universal
dedicated to the ground plane, and signal traces are placed on
the solder side. Best layout and performance are achieved with 10/08—Revision 0: Initial Version
at least a 4-layer multilayer board, where there is a ground plane
layer, a power supply layer, and two signal layers.
(Continued from first page) "Circuits from the Lab" are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may
use the "Circuits from the Lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use
of the "Circuits from the Lab". Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is" and without warranties
of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is
assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any
"Circuits from the Lab" at any time without notice, but is under no obligation to do so. Trademarks and registered trademarks are the property of their respective owners.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
CN08192-0-5/09(A)
Rev. A | Page 2 of 2
Circuit Note
CN-0016
AD9779A Dual 16-Bit, 1 GSPS DAC
For more information and/or support call 1-800-AnalogD ADL5370 300 MHz to 1000 MHz I/Q Modulator
Interfacing the ADL5370 I/Q Modulator to the AD9779A

Dual-Channel, 1 GSPS High Speed DAC
CIRCUIT FUNCTION AND BENEFITS a single 50 Ω resistor to ground from each of the DAC outputs
This circuit provides a simple, elegant interface between the provides the desired 500 mV dc bias. With just the four 50 Ω
ADL5370 I/Q modulator and the AD9779A high speed DAC. resistors in place, the voltage swing on each pin is 1 V p-p.
The ADL5370 and the AD9779A are well-matched devices This results in a differential voltage swing of 2 V p-p on each
because they have the same bias levels and similarly high input pair.
signal-to-noise ratios (SNR). The matched bias levels of 500 mV By adding resistors RSLI and RSLQ to the interface, the output
allow for a “glueless” interface—there is no requirement for a swing of the DAC can be reduced without any loss of DAC
level shifting network that would add noise and insertion loss resolution. The resistor is placed as a shunt between each side of
along with extra components. The addition of the swing- the differential pair, as shown in Figure 1. It has the effect of
limiting resistors (RSLI, RSLQ) allows the DAC swing to be reducing the ac swing without changing the dc bias already
scaled appropriately without loss of resolution or of the 0.5 V established by the 50 Ω resistors and the DAC output current.
bias level. The high SNR of each device preserves a high SNR The value of this ac swing-limiting resistor is chosen based on
through the circuit. the desired ac voltage swing. Figure 2 shows the relationship
CIRCUIT DESCRIPTION between the swing-limiting resistor and the peak-to-peak ac
The ADL5370 is designed to interface with minimal swing that it produces when 50 Ω bias-setting resistors are used.
components to members of Analog Devices family of Note that all Analog Devices I/Q modulators present a relatively
TxDAC® converters (AD97xx). The baseband inputs of the high input impedance on their baseband inputs (typically >1 kΩ).
ADL5370 require a dc common-mode bias voltage of 500 mV. As a result, the input impedance of the I/Q modulator will have
With each AD9779A output swinging from 0 mA to 20 mA, no effect on the scaling of the DAC output signal.
2.0
AD9779A ADL5370 1.8

93 19 1.6
DIFFERENTIAL SWING (V p-p)
OUT1_P IBBP
RBIP
1.4
50Ω RSLI
100Ω
RBIN 1.2
92 50Ω 20
OUT1_N IBBN 1.0
0.8
0.6
84 23
OUT2_N QBBN
0.4
RBQN
50Ω RSLQ 0.2
RBQP 100Ω
83 50Ω 24 0
08209-001
08209-002
OUT2_P QBBP 10 100 1k 10k

RL (Ω)
Figure 1. Interface Between the AD9779A and ADL5370 with 50 Ω Resistors Figure 2. Relationship Between the AC Swing-Limiting Resistor and the
to Ground to Establish the 500 mV DC Bias for the ADL5370 Baseband Inputs Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
(Simplified Schematic)
Rev. A
Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to Tel: 781.329.4700 www.analog.com
any cause whatsoever connected to the use of any“Circuit from the Lab”. (Continued on last page) Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
It is generally necessary to low-pass filter the DAC outputs to COMMON VARIATIONS
remove image frequencies when driving a modulator. The The interface described here can be used to interface
above interface lends itself well to the introduction of such a any TxDAC converter with ground referenced 0 mA to 20 mA
filter. The filter can be inserted between the dc bias setting output currents to any I/Q modulator with a 0.5 V input bias
resistors and the ac swing-limiting resistor. Doing so establishes level. For zero-IF applications, the AD9783 dual DAC provides
the input and output impedances for the filter. an LVDS interface, while the CMOS-driven AD9788 dual DAC
A simulated filter example is shown in Figure 3 with a third-order can generate a fine resolution complex IF input to the I/Q
elliptical filter with a 3 dB frequency of 3 MHz. Matching input modulator. The ADL5370/ADL5371/ADL5372/ADL5373/
and output impedances makes the filter design easier, so the ADL5374 family of I/Q modulators provides narrow-band
shunt resistor chosen is 100 Ω, producing an ac swing of 1 V p-p operation with high output 1 dB compression point and OIP3,
differential for a 0 mA to 20 mA DAC full-scale output current. whereas the ADL5375 provides broadband high performance
In a practical application, the use of standard value components, operation from 400 MHz to 6 GHz. The ADL5385 I/Q modula-
along with the input impedance of the I/Q modulator (2900 kΩ tor uses a 2 × LO and operates from 50 MHz to 2.2 GHz.
in parallel with a few picofarads of input capacitance), will slightly
change the frequency response of this circuit.
LEARN MORE
AN-772 Application Note, A Design and Manufacturing Guide
AD9779A LPI ADL5370 for the Lead Frame Chip Scale Package (LFCSP). Analog
93 2.7nH
19
OUT1_P IBBP Devices.
RBIP
50Ω 1.1nF
C1I
1.1nF
C2I
RSLI
100Ω MT-016 Tutorial, Basic DAC Architectures III: Segmented DACs.
RBIN
92 50Ω 20 Analog Devices.
OUT1_N IBBN
LNI
2.7nH MT-017 Tutorial, Oversampling Interpolating DACs. Analog
LNQ Devices.
84 2.7nH
23
OUT2_N QBBN MT-031 Tutorial, Grounding Data Converters and Solving the
RBQN
50Ω 1.1nF 1.1nF Mystery of 'AGND' and 'DGND'. Analog Devices.
RSLQ
C1Q C2Q 100Ω
RBQP
83 50Ω 24
MT-080 Tutorial, Mixers and Modulators. Analog Devices.
08209-003
OUT2_P QBBP
LPQ
2.7nH
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
Figure 3. DAC Modulator Interface with 3 MHz Third-Order, Low-Pass Filter Zumbahlen, Hank. 2006. Basic Linear Design. Analog Devices.
(Calculated Component Values) ISBN 0915550281. Chapters 4 and 11. Also available as
Linear Circuit Design Handbook. Elsevier-Newnes, 2008,
All the power supply pins of the ADL5370 must be connected to ISBN 0750687037, Chapters 4 and 11.
the same 5 V source. Adjacent pins of the same name can be
tied together and decoupled to a large area ground plane with a Data Sheets
0.1 µF capacitor. These capacitors should be located as close as AD9779A Data Sheet.
possible to the device. The power supply can range between
ADL5370 Data Sheet.
4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
REVISION HISTORY
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should 5/09—Rev. 0 to Rev. A
also be soldered to a low thermal and electrical impedance Updated Format .................................................................. Universal
ground plane. If the ground plane spans multiple layers on the
circuit board, they should be stitched together with nine vias
under the exposed paddle. The AN-772 application note
discusses the thermal and electrical grounding of the
LFCSP_VQ in greater detail.
use the "Circuits from the Lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of
the "Circuits from the Lab". Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is" and without warranties of any
kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed
by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any "Circuits
from the Lab" at any time without notice, but is under no obligation to do so. Trademarks and registered trademarks are the property of their respective owners.
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

CN08209-0-5/09(A)
Circuit Note
CN-0021
AD9779A Dual 16-Bit, 1 GSPS DAC
For more information and/or support call 1-800-AnalogD ADL5375-05 400 MHz to 6000 MHz I/Q Modulator
Interfacing the ADL5375 I/Q Modulator to the AD9779A

Dual-Channel, 1 GSPS High Speed DAC
CIRCUIT FUNCTION AND BENEFITS CIRCUIT DESCRIPTION

This circuit provides a simple, elegant interface between the The ADL5375 is designed to interface with minimal
ADL5375 I/Q modulator and the AD9779A high speed DAC. components to members of Analog Devices family of
The ADL5375 and the AD9779A are well-matched devices TxDAC® converters (AD97xx). The baseband inputs of the
because they have the same bias levels and similarly high ADL5375 require a dc common-mode bias voltage of 500 mV.
signal-to-noise ratios (SNR). The matched bias levels of 500 mV With each AD9779A output swinging from 0 mA to 20 mA, a
allow for a “glueless” interface—there is no requirement for a single 50 Ω resistor to ground from each of the DAC outputs
level shifting network that would add noise and insertion loss provides the desired 500 mV dc bias. With just the four 50 Ω
along with extra components. The addition of the swing- resistors in place, the voltage swing on each pin is 1 V p-p.
limiting resistors (RSLI, RSLQ) allows the DAC swing to be This results in a differential voltage swing of 2 V p-p on each
scaled appropriately without loss of resolution or of the 0.5 V input pair.
bias level. The high SNR of each device preserves a high SNR By adding resistors RSLI and RSLQ to the interface, the output
through the circuit. swing of the DAC can be reduced without any loss of DAC
resolution. The resistor is placed as a shunt between each side of
AD9779A ADL5375-05
93 21
OUT1_P IBBP
RBIP
50Ω RSLI
100Ω
RBIN
92 50Ω 22
OUT1_N IBBN
84 9
OUT2_N QBBN
RBQN
50Ω RSLQ
100Ω
RBQP
83 50Ω 10
08225-001
OUT2_P QBBP
Figure 1. Interface Between the AD9779A and ADL5375 with 50 Ω Resistors to Ground to Establish the
500 mV DC Bias for the ADL5375-05 Baseband Inputs (Simplified Schematic)
Rev. A
2.0 A simulated filter example is shown in Figure 3 with a third-

1.8 order elliptical filter with a 3 dB frequency of 10 MHz.
1.6 Matching input and output impedances makes the filter design
DIFFERENTIAL SWING (V p-p)
1.4
easier, so the shunt resistor chosen is 100 Ω, producing an ac
swing of 1 V p-p differential for a 0 mA to 20 mA DAC full-
1.2
scale output current. The simulated frequency response of this
1.0
filter is shown in Figure 4. In a practical application, the use of
0.8 standard value components along with the input impedance of
0.6 the I/Q modulator (2900 kΩ in parallel with a few picofarads of
0.4 input capacitance), will slightly change the frequency response.
0.2 All the power supply pins of the ADL5375 must be connected to
0
the same 5 V source. Adjacent pins of the same name can be
08225-002
10 100 1k 10k
tied together and decoupled to a large area ground plane with a
RL (Ω)
0.1 μF capacitor. These capacitors should be located as close as
Figure 2. Relationship Between the AC Swing-Limiting Resistor and the possible to the device. The power supply can range between
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
the differential pair, as shown in Figure 1. It has the effect of be tied to the same ground plane through low impedance paths.
reducing the ac swing without changing the dc bias already The exposed paddle on the underside of the package should
established by the 50 Ω resistors. also be soldered to a low thermal and electrical impedance
The value of this ac swing-limiting resistor is chosen based on ground plane. If the ground plane spans multiple layers on the
the desired ac voltage swing. Figure 2 shows the relationship circuit board, they should be stitched together with nine vias
between the swing-limiting resistor and the peak-to-peak ac under the exposed paddle. The AN-772 application note
swing that it produces when 50 Ω bias-setting resistors are used. discusses the thermal and electrical grounding of the
Note that all Analog Devices I/Q modulators present a relatively LFCSP_VQ in greater detail.
high input impedance on their baseband inputs (typically >1 kΩ).
COMMON VARIATIONS
As a result, the input impedance of the I/Q modulator will have
no effect on the scaling of the DAC output signal. The interface described here can be used to interface
any TxDAC converter with ground referenced 0 mA to 20 mA
It is generally necessary to low-pass filter the DAC outputs to
output currents to any I/Q modulator with a 0.5 V input bias
remove image frequencies when driving a modulator. The
level. For zero-IF applications, the AD9783 dual DAC provides
above interface lends itself well to the introduction of such a
an LVDS interface, while the CMOS-driven AD9788 dual DAC
filter. The filter can be inserted between the dc bias setting
can generate a fine resolution complex IF input to the I/Q
resistors and the ac swing-limiting resistor. Doing so establishes
modulator. The ADL5370/ADL5371/ADL5372/ADL5373/
the input and output impedances for the filter.
0 36
AD9779A LPI ADL5375-05 MAGNITUDE

93 771.1nH –10 30
21
OUT1_P IBBP
RBIP
50Ω 53.62nF 350.1pF RSLI
GROUP DELAY (ns)
–20 24
MAGNITUDE (dB)
C1I C2I 100Ω

RBIN
92 50Ω 22 GROUP DELAY
OUT1_N IBBN
LNI –30 18
771.1nH
LNQ
84 771.1nH –40 12
9
OUT2_N QBBN
RBQN
50Ω 53.62nF 350.1pF –50 6
RSLQ
C1Q C2Q 100Ω
RBQP
83 50Ω 10
08225-003
OUT2_P QBBP
–60 0
LPQ
08225-004
1 10 100
771.1nH
FREQUENCY (MHz)
Figure 3. DAC Modulator Interface with 10 MHz Third-Order, Low-Pass Filter Figure 4. Simulated Frequency Response for DAC Modulator Interface with
(Calculated Component Values) 10 MHz Third-Order Bessel Filter
Circuit Note CN-0021
ADL5374 family of I/Q modulators provides narrow-band
operation with high output 1 dB compression point and OIP3,
whereas the ADL5375 provides broadband high performance
operation from 400 MHz to 6 GHz. The ADL5385 I/Q modula-
tor uses a 2 × LO and operates from 50 MHz to 2.2 GHz.
LEARN MORE
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP). Analog
Devices.
MT-016 Tutorial, Basic DAC Architectures III: Segmented DACs.
Analog Devices.
MT-017 Tutorial, Oversampling Interpolating DACs. Analog
Devices.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of 'AGND' and 'DGND'. Analog Devices.
MT-080 Tutorial, Mixers and Modulators. Analog Devices.
Zumbahlen, Hank. 2006. Basic Linear Design. Analog Devices.
ISBN 0915550281. Chapters 4 and 11. Also available as
Linear Circuit Design Handbook. Elsevier-Newnes, 2008,
ISBN 0750687037, Chapters 4 and 11.
Data Sheets
AD9779A Data Sheet.
ADL5375 Data Sheet.
REVISION HISTORY
5/09—Rev. 0 to Rev. A
Updated Format.................................................................. Universal

CN08225-0-5/09(A)
Circuit Note
CN-0026
Circuit Designs Using Analog Devices Products AD5547/ Dual, Current Output, Parallel Input,
Apply these product pairings quickly and with confidence. AD5557 16-/14-Bit DAC
Rail-to-Rail Input/Output Operational
AD8628
Amplifier
Precision, Unipolar, Inverting Conversion Using the AD5547/AD5557 DAC
CIRCUIT FUNCTION AND BENEFITS matching and temperature tracking that minimize the number
of components needed for multiquadrant applications.
This circuit provides precision, unipolar, inverting data
conversion using the AD5547/AD5557 current output DAC This circuit uses the ADR03, which is a highly accuracy, high
with the ADR03 precision reference and AD8628 operational stability, 2.5 V precision voltage reference. As voltage reference
amplifier (op amp). This circuit provides accurate, low noise, temperature coefficient and long-term drift are primary
high speed output voltage capability and is well suited for considerations for applications requiring high precision
process control, automatic test equipment, and digital conversion, this device is an ideal candidate.
calibration applications. An op amp is used in the current-to-voltage (I-V) stage of this
CIRCUIT DESCRIPTION circuit. An op amp’s bias current and offset voltage are both
important selection criteria for use with precision current
The AD5547/AD5557 are dual-channel, precision 16-/14-bit,
output DACs. Therefore, this circuit employs the AD8628 auto-
multiplying, low power, current output, parallel input digital-to-
zero op amp, which has ultralow offset voltage (1 µV typical)
analog converters. They operate from a single 2.7 V to 5.5 V
and bias current (30 pA typical). The compensation capacitor,
supply with ±15 V multiplying references for 4-quadrant
C7, is optimized to compensate for the external output
outputs. Built-in 4-quadrant resistors facilitate the resistance
capacitance of the DAC.
+5V 2
C1 C2 U3 ADR03
1µF 0.1µF VIN
5
TRIM
6 +2.5V
VOUT
C4
GND 0.1µF
VREFA
4
R1A RCOMA ROFSA RFBA C7
2.2pF
VDD R1 R2 ROFS RFB
C3
0.1µF 2.5V IOUTA
AD5547/AD5557 16-BIT/ +V VOUTA
14-BIT AD8628
AGNDA
16-BIT/ U1 –V –2.5V TO 0V
14-BIT DATA C5
0.1µF
WR LDAC RS MSB A0, A1
C6
WR 1µF
LDAC 2
08248-001
RS
MSB –5V
A0, A1
Figure 1. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 V to –VREF (Simplified Schematic)
Rev. A
Note that the AD8628 has rail-to-rail input and output stages, voltage and low bias current. The ADR01 and ADR02 are other
but the output can only come within a few millivolts of either low noise references available from the same reference family as
rail depending on load current. For the circuit shown, the the ADR03. Other low noise references that would be suitable
output can swing from –2.5 V to approximately –1 mV. are the ADR441 and ADR445 products. The size of the
reference input voltage is restricted by the rail-to-rail voltage of
The input offset voltage of the op amp is multiplied by the
the op amp selected.
variable noise gain (due to the code-dependent output
resistance of the DAC) of the circuit. A change in this noise gain These circuits can also be used as a variable gain element by
between two adjacent digital codes produces a step change in utilizing the multiplying bandwidth nature of the R-2R
the output voltage due to the amplifier’s input offset voltage. structure of the AD5547/AD5557 DAC. In this configuration,
This output voltage change is superimposed on the desired remove the external precision reference and apply the signal to
change in output between the two codes and gives rise to a be multiplied to the reference input pins of the DAC.
differential linearity error, which, if large enough, could cause
the DAC to be nonmonotonic. In general, the input offset LEARN MORE
voltage should be a fraction of an LSB to ensure monotonic
ADIsimPower Design Tool.
behavior when stepping through codes. For the ADR03 and the
AD5547, the LSB size is Kester, Walt. 2005. The Data Conversion Handbook. Analog
Devices. See chapters 3 and 7.
2. 5 V
= 38 µV (1) MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
216
Analog Devices.
The input offset voltage of the AD8628 auto-zero op amp is
typically 1 µV, which is negligible compared to the LSB size. MT-031 Tutorial, Grounding Data Converters and Solving the
The input bias current of an op amp also generates an offset at Mystery of AGND and DGND. Analog Devices.
the voltage output as a result of the bias current flowing through MT-033 Tutorial, Voltage Feedback Op Amp Gain and
the feedback resistor, RFB. In the case of the AD8628, the input Bandwidth. Analog Devices.
bias current is only 30 pA typical, which flowing through the MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
RFB resistor (10 kΩ typical), produces an error of only 0.3 µV. Rail-to-Rail Issues. Analog Devices.
The AD5547/AD5557 DAC architecture uses a current-steering MT-055 Tutorial, Chopper Stabilized (Auto-Zero) Precision Op
R-2R ladder design that requires an external reference and op- Amps. Analog Devices.
amp to convert to an output voltage. VOUT can be calculated
for the AD5547 using the equation MT-101 Tutorial, Decoupling Techniques. Analog Devices.
−VREF × D Data Sheets
VOUT = (2)
216 AD5547 Data Sheet.
where D is the decimal equivalent of the input code. VOUT can
AD5557 Data Sheet.
be calculated for the AD5557 using the equation
AD8628 Data Sheet.
−VREF × D
VOUT = (3) ADR03 Data Sheet.
214
where D is the decimal equivalent of the input code.
COMMON VARIATIONS REVISION HISTORY
For multichannel applications, the AD8629 is a dual version of
the AD8628. The AD8605 is another excellent op amp Updated Format .................................................................. Universal
candidate for the I-V conversion circuit. It also has a low offset 10/08—Revision 0: Initial Version

CN08248-0-5/09(A)
Circuit Note
CN-0027
Circuit Designs Using Analog Devices Products AD5547/ Dual, Current Output, Parallel Input,
Apply these product pairings quickly and with confidence. AD5557 16-/14-Bit DAC
For more information and/or support call 1-800-AnalogD ADR03 Precision Voltage Reference
Rail-to-Rail Input/Output Operational
AD8628
Amplifier
Precision, Unipolar, Noninverting Configuration for the AD5547/AD5557 DAC
CIRCUIT FUNCTION AND BENEFITS matching and temperature tracking that minimize the number
This circuit provides precision, unipolar, noninverting data
conversion using the AD5547/AD5557 current output DAC This circuit uses the ADR03, which is a highly accuracy, high
with the ADR03 precision reference and AD8628 operational stability, 2.5 V precision voltage reference. As voltage reference
amplifier (op amp). This circuit provides accurate, low noise, temperature coefficient and long-term drift are primary
high speed output voltage capability and is well suited for considerations for applications requiring high precision
process control, automatic test equipment, and digital conversion, this device is an ideal candidate.
calibration applications. An op amp is used in the current-to-voltage (I-V) stage of this
CIRCUIT DESCRIPTION circuit. An op amp’s bias current and offset voltage are both
important selection criteria for use with precision current
The AD5547/AD5557 are dual-channel precision 16-/14-bit,
output DACs. Therefore, this circuit employs the AD8628 auto-
zero op amp, which has ultralow offset voltage (1 µV typical)
analog converters. They operate from a single 2.7 V to 5.5 V
and bias current (30 pA typical). C7 is a compensation
capacitor. The value of C7 for this application is 2.2 pF, which is
optimized to compensate for the external output capacitance of
the DAC.
+5V 2
C1 C2 U3
1µF 1µF U2A
VIN 5
TRIM
6
VOUT AD8628
GND
C4
4 ADR03 0.1µF –2.5V
+2.5V +5V C5
1µF
R1A RCOMA VREFA ROFSA RFBA C7
2.2pF C6
VDD U2B
R1 R2 ROFS RFB 0.1µF
C3
0.1µF IOUTA
16-BIT/ +V
14-BIT
AD5547/AD5557 AGNDA AD8628 VOUTA
16-BIT/ –V
14-BIT DATA
0V TO +2.5V
WR LDAC RS MSB A0, A1
WR
LDAC 2
08249-001
RS
MSB
A0, A1
Figure 1. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 V to +VREF (Simplified Schematic)
Rev. A
Note that the AD8628 has rail-to-rail input and output stages, ADR01 and ADR02 are other low noise references available
but the output can only come within a few millivolts of either from the same reference family as the ADR03. Other low noise
rail depending on load current. For the circuit shown, the references that would be suitable are the ADR441 and ADR445
output can swing from approximately +1 mV to +2.5 V. products. The size of the reference input voltage is restricted by
the rail-to-rail voltage of the op amp selected.
The input offset voltage of the op amp is multiplied by the
variable noise gain (due to the code-dependent output These circuits can also be used as a variable gain element by
resistance of the DAC) of the circuit. A change in this noise gain utilizing the multiplying bandwidth nature of the R-2R
between two adjacent digital codes produces a step change in structure of the AD5547/AD5557 DAC. In this configuration,
the output voltage due to the amplifier’s input offset voltage. remove the external precision reference and apply the signal to
This output voltage change is superimposed on the desired be multiplied to the reference input pins of the DAC.
change in output between the two codes and gives rise to a
differential linearity error, which, if large enough, could cause LEARN MORE
the DAC to be nonmonotonic. In general, the input offset
ADIsimPower Design Tool.
voltage should be a fraction of an LSB to ensure monotonic
behavior when stepping through codes. For the ADR03 and the Kester, Walt. 2005. The Data Conversion Handbook. Analog
AD5547, the LSB size is Devices. See chapters 3 and 7.
2. 5 V MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
16
= 38 µV (1) Analog Devices.
2
The input offset voltage of the AD8628 auto-zero op amp is MT-031 Tutorial, Grounding Data Converters and Solving the
typically 1 µV, which is negligible compared to the LSB size. Mystery of AGND and DGND. Analog Devices.
The input bias current of an op amp also generates an offset at MT-033 Tutorial, Voltage Feedback Op Amp Gain and
the voltage output as a result of the bias current flowing through Bandwidth. Analog Devices.
the feedback resistor, RFB. In the case of the AD8628, the input MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
bias current is only 30 pA typical, which flowing through the Rail-to-Rail Issues. Analog Devices.
RFB resistor (10 kΩ typical) produces an error of only 0.3 µV.
MT-055 Tutorial, Chopper Stabilized (Auto-Zero) Precision Op
The AD5547/AD5557 DAC architecture uses a current-steering Amps. Analog Devices.
R-2R ladder design that requires an external reference and op-
amp to convert to an output voltage. VOUT can be calculated
for the AD5547 using the equation Data Sheets
+VREF × D AD5547 Data Sheet.
VOUT = (2)
216 AD5557 Data Sheet.
where D is the decimal equivalent of the input code. VOUT can
AD8628 Data Sheet.
be calculated for the AD5557 using the equation
ADR03 Data Sheet.
+VREF × D
VOUT = (3)
214
where D is the decimal equivalent of the input code.
REVISION HISTORY
COMMON VARIATIONS
The AD8629 is a dual version of the AD8628. The AD8605 is
another excellent op amp candidate for the I-V conversion 10/08—Revision 0: Initial Version
circuit. It also has a low offset voltage and low bias current. The

CN08249-0-5/09(A)
Circuit Note
CN-0028
AD5547/ Dual, Current Output, Parallel Input,
Circuit Designs Using Analog Devices Products AD5557 16-/14-Bit DAC
For more information and/or support call 1-800-AnalogD Low Noise, Low Input Bias, JFET Operational
AD8512
(1-800-262-5643) or visit www.analog.com/circuit. Amplifier
Ultracompact, Precision 10.0 V Voltage
ADR01
Reference
Precision, Bipolar, Configuration for the AD5547/AD5557 DAC
CIRCUIT FUNCTION AND BENEFITS analog converters. They operate from a single 2.7 V to 5.5 V
This circuit provides precision, bipolar data conversion using
the AD5547/AD5557 current output DAC with the ADR01
matching and temperature tracking that minimize the number
precision reference and AD8512 operational amplifier
(op amp). This circuit provides accurate, low noise, high speed
output voltage capability and is well suited for process control, This circuit uses the ADR01, which is a highly accuracy, high
automatic test equipment, and digital calibration applications. stability, 10 V precision voltage reference. As voltage reference
temperature coefficient and long-term drift are primary
CIRCUIT DESCRIPTION
considerations for applications requiring high precision
The AD5547/AD5557 are dual-channel, precision 16-/14-bit, conversion, this device is an ideal candidate.
+15V 2
C1 C2 U3
1µF 0.1µF VIN 5
TRIM
+10V
6
VOUT
GND
U2A
4 ADR01
AD8512
C4
0.1µF
R1A RCOMA VREFA ROFSA RFBA

+5V
VDD R1 R2 ROFS RFB +15V C5 1µF
C9
2.2pF
C6 0.1µF
U2B
C3
0.1µF 16-BIT/ IOUTA
AD5547/AD5557
14-BIT +V VOUT
DAC A AD8512
U1 –V
16-BIT/ AGNDA
14-BIT DATA C7 0.1µF –10V TO +10V
WR LDAC RS MSB A0, A1 C8 1µF
WR
08250-001
LDAC 2 –15V
RS
MSB
A0, A1
Figure 1. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF (Simplified Schematic)
Rev. A
Rev. 0 | Page 16 of 215
An op amp is used in the current-to-voltage (I-V) stage of this COMMON VARIATIONS
circuit. An op amp’s bias current and offset voltage are both The AD8605 is another excellent op amp candidate for the I-V
important selection criteria for use with precision current conversion circuit. It also has a low offset voltage and low bias
output DACs. Therefore, this circuit employs the AD8512 current. The ADR02 and ADR03 are other low noise references
op amp, which has ultralow offset voltage (80 µV typical for available from the same reference family as the ADR01. Other
B-grade device) and bias current (25 pA typical). C9 is a low noise references that would be suitable are the ADR441 and
compensation capacitor. The value of C9 for this application is ADR445 products. The size of the reference input voltage is
2.2 pF, which is optimized to compensate for the external restricted by the rail-to-rail voltage of the op amp selected.
output capacitance of the DAC.
These circuits can also be used as a variable gain element by
The input offset voltage of the op amp is multiplied by the utilizing the multiplying bandwidth nature of the R-2R
variable noise gain (due to the code-dependent output structure of the AD5547/AD5557 DAC. In this configuration,
resistance of the DAC) of the circuit. A change in this noise gain remove the external precision reference and apply the signal to
between two adjacent digital codes produces a step change in be multiplied to the reference input pins of the DAC.
the output voltage due to the amplifier’s input offset voltage.
This output voltage change is superimposed on the desired
LEARN MORE
change in output between the two codes and gives rise to a
differential linearity error, which, if large enough, could cause ADIsimPower Design Tool.
the DAC to be nonmonotonic. In general, the input offset Kester, Walt. 2005. The Data Conversion Handbook. Analog
voltage should be a fraction of an LSB to ensure monotonic Devices. See chapters 3 and 7.
behavior when stepping through codes. For the ADR01 and the
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
AD5547, the LSB size is
Analog Devices.
10 V MT-031 Tutorial, Grounding Data Converters and Solving the
= 153 µV (1)
216 Mystery of AGND and DGND. Analog Devices.
The input bias current of an op amp also generates an offset at MT-033 Tutorial, Voltage Feedback Op Amp Gain and
the voltage output as a result of the bias current flowing through Bandwidth. Analog Devices.
the feedback resistor, RFB. In the case of the AD8512, the input
MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
bias current is only 25 pA typical, which flowing through the
Rail-to-Rail Issues. Analog Devices.
RFB resistor (10 kΩ typical) produces an error of only 0.25 µV.
The AD5547/AD5557 DAC architecture uses a current-steering
Amps. Analog Devices.
R-2R ladder design that requires an external reference and op-
amp to convert to an output voltage. VOUT can be calculated MT-101 Tutorial, Decoupling Techniques. Analog Devices.
for the AD5547 using the equation
Data Sheets
 VREF × D 
VOUT =  16 − 1  − VREF (2) AD5547 Data Sheet.
 2 
AD5557 Data Sheet.
where D = 0 to 65535 for 16-bit DAC (D is the decimal
equivalent of the input code). VOUT can be calculated for the AD8512 Data Sheet.
AD5557 using the equation ADR01 Data Sheet.
 VREF × D 
VOUT =  14 − 1  − VREF (3)
 2  REVISION HISTORY
where D = 0 to 16383 for 14-bit DAC (D is the decimal 5/09—Rev. 0 to Rev. A
equivalent of the input code).

CN08250-0-5/09(A)
Circuit Note
CN-0030
AD5390/
3 V/5 V, 16-/14-/12-Bit Digital-to-Analog
Circuit Designs Using Analog Devices Products AD5391/
Converter
Apply these product pairings quickly and with confidence. AD5392
For more information and/or support call 1-800-AnalogD AD7476 1 MSPS, 12-Bit ADC
AD780 Precision 2.5 V/3.0 V Voltage Reference
ADR431 Precision 2.5 V Voltage Reference
AD5390/AD5391/AD5392 Channel Monitor Function
CIRCUIT FUNCTION AND BENEFITS single-supply, 8-channel, 14-bit DAC. Devices are available both
in 64-lead LFCSP and 52-lead LQFP packages. All channels
In a multichannel DAC system, the ability to monitor all
have an on-chip output amplifier with rail-to-rail operation.
outputs at a single point is a significant advantage for
The AD5390/AD5391/AD5392 contain a channel monitor
troubleshooting and diagnostic analysis. This circuit provides
function that consists of a multiplexer addressed via the serial
multichannel DAC output channel monitoring using a single-
interface, allowing any channel output to be routed to the
channel SAR ADC.
monitor output (MON_OUT) pin for monitoring using an
CIRCUIT DESCRIPTION external ADC. The channel monitor function must be enabled
This circuit utilizes the internal multiplexer on the AD5390/ in the control register before any channels are routed to
AD5391/AD5392 to route any of the DAC output channels to a MON_OUT. The AD5390/AD5391/AD5392 also include two
single output pin (MON_OUT) for monitoring by the external uncommitted inputs (MON_IN1 and MON_IN2) to the
ADC (AD7476). This approach utilizes much less circuitry than internal multiplexer that allow the user the facility to monitor
would be required if each channel were monitored individually. inputs from external sources such as references or power
The AD5390/AD5391 are complete, single-supply, 16-channel, supplies. In Figure 1, the MON_IN1 pin on the AD5390
14-bit and 12-bit DACs, respectively. The AD5392 is a complete monitors the reference voltage from the AD780/ADR431.
5.0V
AVDD
DIN
AD780/ REFOUT/REFIN OUTPUT PORT
SYNC
ADR431
SCLK
AD5390 AVDD
MON_IN1
AD7476 CS
VOUT 0 MON_OUT VIN SCLK INPUT PORT
SDATA
GND
AGND CONTROLLER
VOUT 15
DAC_GND SIGNAL_GND
08252-001
Figure 1. Efficient Channel Monitoring Circuit (Simplified Schematic)
Rev. A
The AD7476 ADC is a SAR ADC that offers 12-bit resolution, COMMON VARIATIONS
single 2.35 V to 5.25 V power supply, integrated reference, low
power operation, small form factor, and serial interface, with Pin-compatible versions of the AD7476 are available for use in
throughput rates up to 1 MSPS in a 6-lead SOT-23 package. applications where lower resolution conversion is acceptable in
The reference for the part is taken internally from VDD, the monitoring function. The AD7477 provides 10-bit
allowing the widest dynamic input range to the ADC. Thus, resolution, and the AD7478 provides 8-bit resolution. The
the analog input range for the part is 0 V to VDD. The ADR431 reference can be substituted for the AD780.
conversion rate is determined by the SCLK, allowing
throughput rates up to 1 MSPS. LEARN MORE
The combination of the AD5390/AD5391/AD5392 and ADIsimPower Design Tool.
AD7476 provides a complete 8- or 16-channel analog output Kester, Walt. 2005. The Data Conversion Handbook. Analog
control solution with an efficient monitor function for system Devices. See chapters 3 and 7.
debug and fault and diagnostic analysis.
The AD5390/AD5391/AD5392 and the AD7476 must have
Analog Devices.
ample supply bypassing of 10 μF in parallel with 0.1 μF on each
supply pin, located as close to the packages as possible, ideally MT-031 Tutorial, Grounding Data Converters and Solving the
right up against the devices (this is not shown on the simplified Mystery of AGND and DGND. Analog Devices.
diagram). The 10 μF capacitors are the tantalum bead type. The MT-101 Tutorial, Decoupling Techniques. Analog Devices.
0.1 μF capacitor must have low effective series resistance (ESR) Voltage Reference Wizard Design Tool
and low effective series inductance (ESL), such as the common
ceramic types, which provide a low impedance path to ground Data Sheets and Evaluation Boards
at high frequencies to handle transient currents due to internal AD5390 Data Sheet.
logic switching.
AD5391 Data Sheet.
The power supply traces should be as wide as possible to
provide low impedance paths and reduce the effects of glitches AD5392 Data Sheet.
on the power supply line. Fast switching signals, such as clocks, AD7476 Data Sheet.
must be shielded with ground runs to avoid radiating noise to
AD780 Data Sheet.
other parts of the board and must never be run near the analog
signals. A ground line routed between the SDATA and SCLK ADR431 Data Sheet.
lines helps reduce crosstalk between them (not required on a AD5390/AD5391/AD5392 Evaluation Board.
multilayer board, which has a separate ground plane; however,
it is helpful to separate the lines). Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run REVISION HISTORY
at right angles to each other. This reduces the effects of 6/09—Rev. 0 to Rev. A
feedthrough on the board. A microstrip technique is Updated Format .................................................................. Universal
recommended but not always possible with a double-sided
board. In this technique, the component side of the board is 11/08—Revision 0: Initial Version
the solder side. Best layout and performance is achieved with at
least a 4-layer multilayer board, where there is a ground plane
layer, a power supply layer, and two signal layers.

CN08252-0-6/09(A)
Circuit Note
CN-0032
Circuit Designs Using Analog Devices Products AD7982 18-Bit, 1 MSPS PulSAR® 7.0 mW ADC
Apply these product pairings quickly and with confidence. Ultralow Noise XFET® 5.0 V Voltage
For more information and/or support call 1-800-AnalogD ADR435
Reference
Single-Supply, Differential 18-Bit ADC
ADA4941-1
Driver
Converting a Single-Ended Signal with the

AD7982 Differential PulSAR ADC

There are many applications that require a single-ended analog The differential input voltage range of the AD7982 is set by the
signal, either bipolar or unipolar, to be converted by a high voltage on the REF pin. For VREF = 5 V, the differential input
resolution, differential input ADC. This dc-coupled circuit voltage range is ±VREF = ±5 V. The voltage gain (or attenuation)
converts a single-ended input signal to a differential signal from the single-ended source, VIN, to OUTP of the ADA4941-1
suitable for driving the AD7982, an 18-bit, 1 MSPS member of is set by the ratio of R2 to R1. The ratio of R2 to R1 should be
the PulSAR family of ADCs. This circuit uses the ADA4941-1 equal to the ratio of VREF to the peak-to-peak input voltage at
single-ended-to-differential driver and the ADR435 ultralow VIN. For a peak-to-peak, single-ended input voltage of 10 V and
noise 5.0 V voltage reference. The circuit can accept many types VREF = 5 V, the ratio of R2 to R1 should be 0.5. The signal at
of single-ended input signals, including bipolar or unipolar, OUTP is inverted (gain = −1) by the upper half of the
ranging from high voltage to low voltage. Direct coupling is ADA4941-1, which supplies the opposite phase output signal at
maintained throughout. If board space is at a premium, all the OUTN. The absolute value of R1 determines the input
ICs shown in Figure 1 come in small packages, either impedance of the circuit. Feedback capacitor CF is chosen based
3 mm × 3 mm LFCSP or 3 mm × 5 mm MSOP. on the desired signal bandwidth, which is approximately
+7.0V 1/(2πR2CF). The 20 Ω resistors and the 2.7 nF capacitors act as
R5 VOFFSET1 R6 a 3 MHz single-pole low-pass noise filter.
ADR435
R3 VOFFSET2 R4 VREF Resistors R3 and R4 set the common-mode voltage on the IN−
input of the AD7982. The value of this common-mode voltage
+7.0V 10µF
+2.5V is VOFFSET2 × (1 + R2/R1), where VOFFSET2 = VREF × R3/(R3 + R4).
100nF
REF Resistors R5 and R6 set the common-mode voltage on the IN+
OUTN 20Ω REF VDD
IN+ input of the ADC. This voltage is equal toVOFFSET1 = VREF ×
2.7nF
AD7982 R5/(R5 + R6). The ADC’s common-mode voltage, which is
OUTP 2.7nF
100nF IN– equal to VOFFSET1, should be close to VREF/2. This implies that
IN 20Ω GND
R5 = R6. Table 1 shows some possible standard 1% values for
FB
the resistors for popular input voltage ranges.
ADA4941 SERIAL
INTERFACE Note that the ADA4941-1 operates on supply voltages of +7 V
–2.0V
VIN
R1 and −2 V. Since each output must swing from 0 V to +5 V, the
R2
positive supply voltage should be a few hundred millivolts
08267-001
CF greater than +5 V and the negative supply should be a few

hundred millivolts more negative than 0 V. For this circuit,
Figure 1. Single-Ended–to- Differential DC-Coupled Driver Circuit
(Simplified Schematic) supply voltages of +7 V and −2 V were chosen. The +7 V supply
Rev. A
Table 1. Circuit Values and Voltages for Popular Input Voltage Ranges
VIN (V) VOFFSET1 (V) VOFFSET2 (V) OUTP (V) OUTN (V) R1 (kΩ) R2 (kΩ) R4(kΩ) R3, R5, R6 (kΩ)
+20, −20 2.5 2.203 −0.01, 4.96 5.0, 0.04 8.06 1.00 12.70 10.00
+10, −10 2.5 2.000 0.01, 4.99 4.99, 0.01 4.02 1.00 15.0 10.00
+5, −5 2.5 1.667 0.00, 5.00 5.00, 0.00 2.00 1.00 20.0 10.00
also provides sufficient headroom to power the ADR435. Other COMMON VARIATIONS
voltages are possible, provided the absolute maximum total
For different reference voltages, the ADR43x family of
supply voltage on the AD4941-1 does not exceed 12 V and the
references has a wide range of values that can interface with the
headroom requirement of the ADR435 is observed.
ADC.
The AD7982 requires a +2.5 V supply for VDD as well as a VIO
supply (not shown in Figure 1), which can range between 1.8 V
LEARN MORE
and 5 V, depending upon the I/O logic interface levels.
Kester, Walt. 2005. The Data Conversion Handbook. Chapters 6
This circuit is not sensitive to power supply sequencing. The
and 7. Analog Devices.
AD7982 inputs can withstand up to ±130 mA maximum during
momentary overvoltage conditions. Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 2, “Optimizing Data Converter Interfaces.”
The AD7982 SPI-compatible serial interface (not shown in
Figure 1) features the ability, using the SDI input, to daisy-chain MT-031 Tutorial, Grounding Data Converters and Solving the
several ADCs on a single 3-wire bus and provides an optional Mystery of AGND and DGND. Analog Devices.
busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, and 5 V MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
logic, using the separate VIO supply. Rail-to-Rail Issues. Analog Devices.
Excellent layout, grounding, and decoupling techniques must be MT-074 Tutorial, Differential Drivers for Precision ADCs.
utilized in order to achieve the desired performance from the Analog Devices.
circuits discussed in this note. As a minimum, a 4-layer PCB
should be used with one ground plane layer, one power plane
layer, and two signal layers. Voltage Reference Wizard Design Tool.
All IC power pins must be decoupled to the ground plane with Data Sheets and Evaluation Boards
low inductance, multilayer ceramic capacitors (MLCC) of AD7982 Data Sheet.
0.01 µF to 0.1 µF (this is not shown in Figure 1 for simplicity).
AD7982 Evaluation Board.
Follow the recommendations on the individual data sheets for
the ICs referenced in the Learn More section. ADA4941-1 Data Sheet.
The product evaluation boards should be consulted for ADR435 Data Sheet.
recommended layout and critical component placement. These
can be accessed through the main product pages for the devices REVISION HISTORY
(see the Learn More section).

CN08267-0-7/09(A)
Circuit Note
CN-0041
Circuits from the Lab™ reference circuits are engineered and AD7356 Differential Input, Dual, 5 MSPS, 12-Bit
tested for quick and easy system integration to help solve today’s SAR ADC
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0041. AD8138 Low Distortion Differential ADC Driver
OP177 Ultraprecision Operational Amplifier
DC-Coupled, Single-Ended-to-Differential Conversion Using the AD8138 Low

Distortion Differential ADC Driver and the AD7356 5 MSPS, 12-Bit SAR ADC
CIRCUIT FUNCTION AND BENEFITS applying differential drive to the AD7356 is to use a differential
This circuit provides a dc-coupled, single-ended-to-differential amplifier, such as the AD8138. The AD8138 can be used as a
conversion of a bipolar input signal to the AD7356 5 MSPS, single-ended-to-differential amplifier or as a differential-to-
12-bit successive approximation register (SAR) analog-to-digital differential amplifier. It also provides common-mode level
converter (ADC). This circuit is designed to ensure maximum shifting. Figure 1 shows how the AD8138 can be used as a
performance of the AD7356 by providing adequate settling time single-ended-to-differential amplifier in a dc-coupled application.
and low impedance. The positive and negative outputs of the AD8138 are connected
to the respective inputs on the ADC through a pair of series
CIRCUIT DESCRIPTION resistors to minimize the loading effects of the switched capacitor
Differential operation requires VINx+ and VINx− of the ADC to be inputs of the ADC. The architecture of the AD8138 results in
driven simultaneously with two equal signals that are 180° out outputs that are very highly balanced over a wide frequency
of phase and are centered around the proper common-mode range without requiring tightly matched external components.
voltage. Because not all applications have a signal preconditioned The single-ended-to-differential gain of the circuit in Figure 1 is
for differential operation, there is often a need to perform a equal to RF/RG, where RF = RF1 = RF2 and RG = RG1 = RG2.
single-ended-to-differential conversion. An ideal method of
CF1
2.048V
RF1 1.024V +2.5V +2.25V TO +3.6V
0V
+5V
RS*
RG1
VDD VDRIVE
VOCM VINx–
+2.048V AD8138 AD7356
GND RG2 RS* VINx+
–2.048V REFA/REFB
–5V
2.048V
RF2 1.024V
+2.048V
0V
CF2 AGND DGND
+5V
10kΩ OP177
+1.024V
10µF
10µF 10kΩ
–5V
08480-001
*MOUNT AS CLOSE TO THE AD7356 AS POSSIBLE.

RS = 33Ω; RG1 = RG2 = RF1 = RF2 = 499Ω
CF1 = CF2 = 39pF
Figure 1. AD8138 as a DC-Coupled, Single-Ended-to-Differential Converter Driving the AD7356 Differential Inputs
(Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. B
Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices
each circuit, and their function and performance have been tested and verified in a lab environment at
room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause Tel: 781.329.4700 www.analog.com
whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 ©2009–2013 Analog Devices, Inc. All rights reserved.
If the analog inputs source being used has zero impedance, all COMMON VARIATIONS
four resistors (RG1, RG2, RF1, and RF2) should be the same as is The OP07D, an ultralow offset voltage op amp, is a lower cost
shown in Figure 1. If the source has a 50 Ω impedance and a 50 Ω alternative to the OP177. It offers similar performance with the
termination, for example, increase the value of RG2 by 25 Ω to exception of the offset voltage specification. Alternatively, the
balance this parallel impedance on the input and thus ensure that AD8628 or the AD8638 offers very high precision with very low
both the positive and negative analog inputs have the same gain. drift with time and temperature.
This also requires a small increase in RF1 and RF2 to compensate
for the gain loss caused by increasing RG1 and RG2. Complete LEARN MORE
analysis for the terminated source condition is found in the MT-031 Tutorial, Grounding Data Converters and Solving the
ADIsimDiffAmp interactive design tool and in the MT-076 Mystery of "AGND" and "DGND," Analog Devices.
Tutorial.
MT-036 Tutorial, Op Amp Output Phase-Reversal and Input
The AD7356 requires a driver that has a very fast settling time Over-Voltage Protection, Analog Devices.
due to the very short acquisition time required achieving 5 MSPS
MT-074 Tutorial, Differential Drivers for Precision ADCs,
throughput with a serial interface. The track-and-hold amplifier
Analog Devices.
on the front end of the AD7356 enters track mode on the rising
edge of the 13th SCLK period during a conversion. The ADC MT-075 Tutorial, Differential Drivers for High Speed ADCs
driver must settle before the track-and-hold returns to hold (38 ns Overview, Analog Devices.
later for 5 MSPS throughput on the AD7356 using an 80 MHz MT-076 Tutorial, Differential Driver Analysis, Analog Devices.
SCLK). The AD8138 has a specified 16 ns settling time that
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
satisfies this requirement.
John Ardizonni and Jonathan Pearson, “Rules of the Road” for
The voltage applied to the VOCM pin of the AD8138 sets up the
High-Speed Differential ADC Drivers (Analog Dialogue, Volume
common-mode voltage. In Figure 1, VOCM is connected to 1.024 V,
43, May 2009, Analog Devices).
which is a divided version of the internal 2.048 V reference on
the AD7356. If the on-chip 2.048 V reference on the AD7356 is ADIsimDiffAmp (Differential Amplifier Tool), Analog Devices.
to be used elsewhere in a system (as illustrated in Figure 1), the Data Sheets and Evaluation Boards
output from REFA or REFB must first be buffered. The OP177 AD7356 Data Sheet.
features the highest precision performance of any op amp
currently available and is a perfect choice for a reference buffer. AD7356 Evaluation Board.
Note that, in Figure 1, the AD8138 operates on dual 5 V supplies AD8138 Data Sheet.
whereas the AD7356 is specified for power supply voltages of OP177 Data Sheet.
2.25 V to 3.6 V. Care must be taken to ensure that the maximum OP07D Data Sheet.
input voltage limits of the AD7356 are not exceeded during
transient or power-on conditions (see MT-036 Tutorial). In REVISION HISTORY
addition, the circuit must be constructed on a multilayer 1/13—Rev. A to Rev. B
printed circuit board (PCB) with a large area ground plane. Changes to Figure 1 ...........................................................................1
Proper layout, grounding, and decoupling techniques must be
used to achieve optimum performance (see MT-031 Tutorial, 11/09—Rev. 0 to Rev. A
MT-101 Tutorial, and the AD7356 evaluation board layout). Updated Format .................................................................. Universal
Changes to Circuit Note Title ..........................................................1
2/09—Revision 0: Initial Release
(Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you
may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by
application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied
"as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular
purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices
reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so.

CN08480-0-1/13(B)
Rev. B | Page 2 of 2
Circuit Note
CN-0042
Circuit Designs Using Analog Devices Products AD7366/ Bipolar Input, Dual 12-/14-Bit, 2-Channel,
AD7367 SAR ADC
For more information and/or support call 1-800-AnalogD AD8021 Low Noise, High Speed Amplifier
Driving the AD7366/AD7367 Bipolar SAR ADC in Low-Distortion DC-Coupled

Applications
CIRCUIT FUNCTION AND BENEFITS The AD7366/AD7367 are fabricated on the Analog Devices,
The circuit described in this document provides single-ended, Inc., industrial CMOS process (iCMOS), which is a technology
low-distortion sampling of an industrial level, dc-coupled platform combining the advantages of low and high voltage
signal. The driver circuit shown in Figure 1 is optimized for CMOS. The input circuits of the AD7366/AD7367 operate on
applications requiring best distortion performance. Maximum VDD and VSS voltages of ±12 V nominal, while the rest of the
AD7366/AD7367 performance is achieved by providing ADC operates on an AVCC, a DVCC, and a VDRIVE of +5 V. The
iCMOS process, therefore, allows the AD7366/AD7367 to
adequate settling time and low impedance in the circuit.
accept high voltage bipolar signals in addition to reducing
CIRCUIT DESCRIPTION power consumption and package size.
The AD7366 and the AD7367 are, respectively, 12-bit and In applications where the signal source has high impedance,
14-bit, 1 MSPS, 2-channel, simultaneous sampling SAR ADCs. analog input signals should be buffered before being applied to
These devices have a total of four analog multiplexed inputs the inputs of the AD7366/AD7367 because large source
(two per channel), which operate in single-ended mode. The impedances significantly affect the ac performance of the ADC.
analog input range on the AD7366/AD7367 is programmable The choice of the op amp used to drive the inputs is a function
and can support ±10 V, ±5 V, and 0 V to 10 V using the internal of the particular application and depends on the analog input
2.5 V reference. An analog input range of ±12 V requires a 3 V voltage range selected. The driver amplifier must be able to
external reference. settle for a full-scale step to a 14-bit level (0.0061%) for the
AD7367 or a 12-bit level (0.024%) for the AD7366 in less than
the specified acquisition time of 140 ns.
+12V
+
+5V
10µF
CCOMP = 10pF
+
+5V/+2.5V
+ 0.1µF
AGND 500Ω
AD8021 VA1
–5V/–2.5V VDD DVCC AVCC VDRIVE
1kΩ AD7366/
AD7367*
VB1
+
1kΩ 15pF VSS

0.1µF
+
10µF
AGND DGND
08481-001
–12V
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 1. Typical Connection Diagram with the AD8021 for Driving the Analog Inputs of the AD7366/AD7367
(Simplified Schematic, Decoupling and All Connections Not Shown)
Rev. A
at room temperature. However, youare solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
any cause whatsoever connected to the use of any“Circuit fromthe Lab”. (Continued on last page) Fax: 781.461.3113 ©2008-2009 Analog Devices, Inc. All rights reserved.
The AD8021 high performance voltage feedback op amp is an LEARN MORE
ideal choice as a single-ended input buffer/driver for the MT-031 Tutorial, Grounding Data Converters and Solving
AD7366/AD7367 due to its exceptionally high performance, the Mystery of "AGND" and "DGND." Analog Devices.
high speed, low noise, and low distortion performance. It also
meets the above stated requirement when operating in single- MT-036 Tutorial, Op Amp Output Phase-Reversal and Input
ended mode. Figure 1 shows the configuration of the AD7366/ Over-Voltage Protection. Analog Devices.
AD7367 with the AD8021 in a single-ended configuration. The MT-101 Tutorial, Decoupling Techniques. Analog Devices.
AD8021 needs an external compensating NPO type capacitor Data Sheets and Evaluation Boards
(CCOMP), as indicated in Figure 1. The AD8021 is connected in
AD7366 Data Sheet.
the noninverting mode with a gain of 2. The AD7366/AD7367
programmable bipolar input voltage ranges (referenced to the AD7367 Data Sheet.
input of the AD8021) are ±5 V and ±2.5 V. AD8021 Data Sheet.
The circuit must be constructed on a multilayer PC board with OP177 Data Sheet.
a large area ground plane. Proper layout, grounding, and
decoupling techniques must be used to achieve optimum AD7366/AD7367 Evaluation Board.
performance (see MT-031 Tutorial, MT-101 Tutorial, and the
REVISION HISTORY
AD7366/AD7367 evaluation board layout).
COMMON VARIATIONS
The AD8022 is a suitable replacement for the AD8021 in high
frequency applications where a dual version is required. For
lower frequency applications, recommended op amps are the
AD797, AD845, and AD8610.
(Continued from first page) "Circuits from the Lab" are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you
may use the "Circuits from the Lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or
use of the "Circuits from the Lab". Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is" and without
warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no
responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the
right to change any "Circuits from the Lab" at any time without notice, but is under no obligation to do so. Trademarks and registered trademarks are the property of their respective
owners.
©2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and

CN08481-0-9/09(A)
Circuit Note
CN-0046
Circuit Designs Using Analog Devices Products Ultralow Distortion Differential
AD8352
Apply these product pairings quickly and with confidence. RF/IF Amplifier
For more information and/or support call 1-800-AnalogD 14-Bit, 105 MSPS/125 MSPS Analog-to-
(1-800-262-5643) or visit www.analog.com/circuit. AD9445
Digital Converter
Using the AD8352 as an Ultralow Distortion Differential RF/IF Front End

for High Speed ADCs
CIRCUIT FUNCTION AND BENEFITS input RF/IF frequency from the AD8352, impedance matching
These circuits provide both a single-ended and a differential is not required, thereby eliminating the need for this
configuration for driving high speed ADCs using the AD8352 termination resistor. The output 24 Ω series resistors provide
ultralow distortion differential RF/IF amplifier. The AD8352 isolation from the input capacitance of the ADC, and the
provides the gain, isolation, and distortion performance optimum value is determined empirically. The 100 MHz FFT
necessary for efficiently driving high linearity converters, such plots shown in Figure 3 and Figure 4 display the performance
as the AD9445. This device also provides balanced outputs results for the differential configuration.
whether driven differentially or single-ended, thereby In the single-ended input configuration shown in Figure 2, the
maintaining excellent second-order distortion levels. net input impedance at VIP is RN (200 Ω) plus the external
24.9 Ω balancing resistor, or ~225 Ω. This requires a 64.9 Ω
CIRCUIT DESCRIPTION
parallel resistor to provide the input impedance match for a 50 Ω
Figure 1 and Figure 2 illustrate two front-end circuits for source. If input reflections are minimal, this impedance match is
driving the AD9445 14-bit ADC at 105 MSPS. Figure 1 not required. The 200 Ω resistor (RN) is required to balance the
provides a differential input configuration, while Figure 2 output voltages to minimize second-order distortion.
provides a single-ended input configuration.
The single-ended configuration provides −3 dB bandwidths
In the differential configuration shown in Figure 1, the input similar to input differential drive and shows little or no
49.9 Ω resistor provides a differential input impedance to the degradation in overall third-order harmonic performance. The
50 Ω RF/IF source. When the driver is located less than single-ended, third-order distortion levels are similar to the
approximately one eighth of the wavelength of the maximum
5V
0.1µF
0.1µF
16
8, 13
50Ω SOURCE 1 11 0.1µF 24Ω
IF/RF INPUT 2
49.9Ω
RD RG AD8352 AD9445
CD
3
MINICIRCUITS
ADT1-1WT 4
10 0.1µF 24Ω
5
6, 7, 9, 12
14
08446-001
0.1µF
0.1µF
Figure 1. Differential Input to the AD8352 Driving the AD9445 14-Bit, 105 MSPS/125 MSPS ADC
(Simplified Schematic, All Connections Not Shown)
Rev. A
5V
0.1µF VOP 0.1µF 33Ω

VIP
50Ω 64.9Ω
VIN+
AC CD RD RG AD8352 AD9445
VIN–
VIN 33Ω
0.1µF VON 0.1µF

24.9Ω RN
200Ω
08446-002
0.1µF
Figure 2. Single-Ended Input to the AD8352 Driving the AD9445 ADC

(Simplified Schematic, All Connections Not Shown)
differential FFT plots in Figure 3 and Figure 4. The single- the AD9445 when no filtering is used. However, it should be
ended circuit avoids the use of a transformer or balun in noted that amplifier gains from 3 dB to 18 dB, with proper
front of the amplifier while still maintaining excellent selection of CD and RD, do not appreciably affect distortion
distortion up to approximately 100 MHz. However, at levels. These circuits, when configured properly, can result in
frequencies above approximately 100 MHz, second-order SFDR performance of better than 87 dBc at 70 MHz and 82 dBc
distortion increases when the AD8352 is driven single-ended at 180 MHz input. Single-ended drive, with appropriate CD and
due to phase-related errors. RD, gives similar results for SFDR and third-order intermodulation
0 levels as shown in these figures.
SNR = 67.26dBc
–10 SFDR = 83.18dBc
–20 NOISE FLOOR = –110.5dB Excellent layout, grounding, and decoupling techniques must be
FUND = –1.074dBFS
–30 SECOND = –83.14dBc utilized in order to achieve the desired performance from the
THIRD = –85.39dBc
–40 circuits discussed in this note. As a minimum, a 4-layer PCB
AMPLITUDE (dBFS)
–50
should be used with one ground plane layer, one power plane
–60
–70 layer, and two signal layers.
–80
All IC power pins must be decoupled to the ground plane
–90
–100 with low inductance multilayer ceramic capacitors (MLCC)
–110 of 0.01 µF to 0.1 µF (this is not shown in the diagrams for
–120 simplicity). Follow the recommendations on the individual
–130
–140
data sheets for the ICs.
–150 The product evaluation boards should be consulted for
08446-003
0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz) recommended layout and critical component placement. They
Figure 3. Single Tone Distortion, AD8352 Driving AD9445, Sampling Clock = 105 MSPS,
can be accessed through the main product pages for the devices
Analog Input Frequency = 100 MHz, AV = 10 dB. See Figure 1. or their data sheets.
0
In both configurations, RG is the gain setting resistor for the –10
SNR = 61.98dBc
NOISE FLOOR = –111.2dB
AD8352, with the RD and CD components providing –20 FUND1 = –7.072dBFS
FUND2 = –7.043dBFS
distortion cancellation. The AD9445 differential input –30 IMD (2F2-F1) = –89dBc
IMD (2F1-F2) = –88dBc
impedance is approximately 2 kΩ in parallel with 5 pF and –40
AMPLITUDE (dBFS)
–50
requires a 2.0 V p-p differential signal (VREF = 1 V) between –60
V IN+ and VIN− for a full-scale input signal. –70
–80
The output of the amplifier is ac-coupled to allow for an –90
optimum common-mode voltage at the ADC input. The –100
common-mode voltage at the input of the AD9445 is set to –110
3.5 V by an internal network. Input ac-coupling can be –120

–130
required if the source also requires a common-mode voltage –140
that is outside the optimum range of the AD8352. A VCM –150
08846-004
0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
common-mode pin is provided on the AD8352 that equally
FREQUENCY (MHz)
shifts both input and output common-mode levels. Increasing
Figure 4. Two Tone Intermodulation Distortion, AD8352 Driving AD9445,
the gain of the AD8352 increases the system noise and, thus, Sampling Clock = 105 MSPS, Analog Input Frequency = 98 MHz and
decreases the SNR (3.5 dB at 100 MHz input for AV = 10 dB) of 101 MHz, AV = 10 dB. See Figure 1.
COMMON VARIATIONS
Placing antialiasing filters between the ADC and the amplifier MT-073 Tutorial, High Speed Variable Gain Amplifiers (VGAs).
is a common approach for improving overall noise and Analog Devices.
broadband distortion performance for both band-pass and low- MT-075 Tutorial, Differential Drivers for High Speed ADCs
pass applications. For high frequency filtering, matching to the Overview. Analog Devices.
filter is required. The AD8352 maintains a 100 Ω output
impedance well beyond most applications and is well-suited MT-101 Tutorial, Decoupling Techniques. Analog Devices.
to drive most filter configurations with little or no Data Sheets
degradation in distortion.
AD8352 Data Sheet.
The AD8352 low distortion differential amplifier can be
AD8375 Data Sheet.
replaced by the high IP3, low noise figure AD8375 variable gain
amplifier (VGA). The AD8375 is a digitally controlled, variable AD8376 Data Sheet.
gain, wide bandwidth amplifier that provides precise gain AD9445 Data Sheet.
control across a broad 24 dB gain range, with 1 dB resolution.
The AD8376 is a dual version of the AD8375. (See Circuit Note
CN-0002, Using the AD8376 VGA to Drive Wide Bandwidth High Speed ADC Evaluation Kits and Evaluation Boards.
ADCs for High IF AC-Coupled Applications.)
REVISION HISTORY
LEARN MORE 8/09—Rev. 0 to Rev. A
CN-0002 Circuit Note, Using the AD8376 VGA to Drive Wide Updated Format ................................................................. Universal
Bandwidth ADCs for High IF AC-Coupled Applications.
Analog Devices.
Mystery of AGND and DGND. Analog Devices.

CN08446-0-8/09(A)
Circuit Note
CN-0050
Devices Connected/Referenced in this Circuit Note
Circuit Designs Using Analog Devices Products ADL5330 Variable Gain Amplifier (VGA)
Apply these product pairings quickly and with confidence. AD8318 70 dB Logarithmic Detector/Controller
For more information and/or support call 1-800-AnalogD
(1-800-262-5643) or visit www.analog.com/circuits.
Stable, Closed-Loop Automatic Power Control for RF Applications
CIRCUIT FUNCTION AND BENEFITS with an automatic gain control (AGC) loop. Figure 1 shows the
The circuit described in this document provides closed-loop, auto- ADL5330 operating in an AGC loop. The addition of the AD8318
matic power control using a VGA (ADL5330) and a log detector log amp allows the AGC to have improved temperature stability
(AD8318). Due to the high temperature stability of the AD8318, over a wide output power control range.
this circuit provides stability over temperature because the AD8318 To operate the ADL5330 VGA in an AGC loop, a sample of the
RF detector ensures the same level of temperature stability at the output RF must be fed back to the detector (typically using a
output of the ADL5330 VGA. The addition of the log amp detector directional coupler and additional attenuation). A setpoint voltage
converts the ADL5330 from an open-loop variable gain amplifier is applied by a DAC to the VSET input of the detector while VOUT
to a closed-loop output power control circuit. Because the AD8318, is connected to the GAIN pin of the ADL5330. Based on the
like the ADL5330, has a linear-in-dB transfer function, the POUT vs. detector’s defined linear-in-dB relationship between VOUT and the
setpoint transfer function also follows a linear-in-dB characteristic. RF input signal, the detector adjusts the voltage on the GAIN pin
(the detector’s VOUT pin is an error amplifier output) until the
CIRCUIT DESCRIPTION
level at the RF input corresponds to the applied setpoint voltage.
Although the ADL5330 variable gain amplifier provides accurate GAIN settles to a value that results in the correct balance between
gain control, precise regulation of output power can be achieved the input signal level at the detector and the setpoint voltage.
+5V +5V
RF INPUT RF OUTPUT
SIGNAL 120nH SIGNAL
VPSx COMx 120nH
100pF 100pF
INHI OPHI
ADL5330 100pF DIRECTIONAL
INLO OPLO COUPLER
100pF
ETC1-1-13 GAIN ETC1-1-13
(M/A-COM) (M/A-COM)
412Ω +5V ATTENUATOR
1kΩ
SETPOINT
VOUT VPSx 1nF
VOLTAGE
DAC* VSET INHI
AD8318
LOG AMP 1nF
CLPF INLO
220pF CMxP
08515-001
*SEE COMMON VARIATIONS SECTION
Figure 1. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318 (Simplified Schematic: Decoupling and
All Connections Not Shown)
Rev. B
The basic connections for operating the ADL5330 in an AGC T
loop with the AD8318 are shown in Figure 1. The AD8318 is a AM MODULATED INPUT T
1 MHz to 8 GHz precision demodulating logarithmic amplifier. 1

It offers a large detection range of 60 dB with ±0.5 dB
temperature stability. The gain control pin of the ADL5330 is
controlled by the output pin of the AD8318. This voltage, AD8318 OUTPUT
VOUT, has a range of 0 V to near VPSx. To avoid overdrive 2
recovery issues, the AD8318 output voltage can be scaled down
using a resistive divider to interface with the 0 V to 1.4 V gain
control range of the ADL5330.
A coupler/attenuation of 23 dB is used to match the desired 3
maximum output power from the VGA to the top end of the ADL5330 OUTPUT
linear operating range of the AD8318 (at approximately −5 dBm
08515-003
CH1 250mV Ω CH2 200mV M2.00ms
at 900 MHz). CH3 250mV Ω T 0.00000s
The detector’s error amplifier uses CLPF, a ground-referenced Figure 3. Oscilloscope Showing an AM Modulated Input Signal
capacitor pin, to integrate the error signal (in the form of a For the AGC loop to remain in equilibrium, the AD8318 must
current). A capacitor must be connected to CLPF to set the loop track the envelope of the ADL5330 output signal and provide
bandwidth and to ensure loop stability. the necessary voltage levels to the ADL5330 gain control input.
30 4 Figure 3 shows an oscilloscope screen shot of the AGC loop
20 3
depicted in Figure 1. A 100 MHz sine wave with 50% AM
modulation is applied to the ADL5330. The output signal from
10 2 the ADL5330 is a constant envelope sine wave with amplitude
OUTPUT POWER (dBm)
0 1
corresponding to a setpoint voltage at the AD8318 of 1.5 V.
Also shown is the gain control response of the AD8318 to the
ERROR (dB)
–10 0 changing input envelope.

–20 –1 T
AD8318 WITH PULSED VSET T

–30 –2
–40 –3
–50 –4
08515-002
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 1
SETPOINT VOLTAGE (V)
Figure 2. ADL5330 Output Power vs. AD8318 Setpoint Voltage,

PIN = −1.5 dBm
Figure 2 shows the transfer function of the output power vs. the ADL5330 OUTPUT
2
VSET voltage over temperature for a 900 MHz sine wave with
an input power of −1.5 dBm. Note that the power control of the
AD8318 has a negative sense. Decreasing VSET, which corres-
08515-004
ponds to demanding a higher signal from the ADL5330, tends CH1 2.00V CH2 50.0mVΩ M10.0µs A CH1 2.60V
T 20.2000µs
to increase GAIN.
Figure 4. Oscilloscope Showing the ADL5330 Output
The AGC loop is capable of controlling signals just under the
full 60 dB gain control range of the ADL5330. The performance Figure 4 shows the response of the AGC RF output to a pulse on
over temperature is most accurate over the highest power range, VSET. As VSET decreases to 1 V, the AGC loop responds with
where it is generally most critical. Across the top 40 dB range an RF burst. Response time and the amount of signal
of output power, the linear conformance error is well within integration are controlled by the capacitance at the AD8318
±0.5 dB over temperature. CLPF pin—a function analogous to the feedback capacitor
around an integrating amplifier. An increase in the capacitance
The broadband noise added by the logarithmic amplifier is results in slower response time.
negligible.
The circuit must be constructed on a multilayer printed circuit
board with a large area ground plane. Proper layout, grounding,
and decoupling techniques must be used to achieve optimum
performance (see the MT-031 Tutorial and the MT-101 Tutorial
and the ADL5330 and ADL8318 evaluation board layouts).
On the underside of the ADL5330 and AD8318 chip scale LEARN MORE
packages, there is an exposed compressed paddle. This paddle is Dana Whitlow, Design and Operation of Automatic Gain Control
internally connected to the chip’s ground. Solder the paddle to Loops for Receivers in Modern Communications Systems, Analog
the low impedance ground plane on the printed circuit board to Devices Wireless Seminar, Chapter 7, 2006.
ensure specified electrical performance and to provide thermal
relief. It is also recommended that the ground planes on all MT-031 Tutorial, Grounding Data Converters and Solving the
layers under the paddle be stitched together with vias to reduce Mystery of “AGND” and “DGND,” Analog Devices.
thermal impedance. MT-073 Tutorial, High Speed Variable Gain Amplifiers, Analog
Devices.
COMMON VARIATIONS
This circuit can be used to implement a constant power out MT-077 Tutorial, Log Amp Basics, Analog Devices.
function (fixed setpoint with variable input power) or a variable MT-078 Tutorial, High Speed Log Amps, Analog Devices.
power out function (variable setpoint with fixed or variable MT-101 Tutorial, Decoupling Techniques, Analog Devices.
input power). If a lower output power control range is desired,
the AD8318 log amp (60 dB power detection range) can be Data Sheets
replaced with either the AD8317 (50 dB power detection range) ADL5330
or the AD8319 (45 dB power detection range). For a constant AD8318
output power function, the lowest dynamic range detector
AD8317
(AD8319) is adequate because the loop always servos the
detector input power to a constant level. AD8319
The ADL5330 VGA, which is optimized for transmit applications, ADL5330 Evaluation Board
can be replaced by the AD8368 VGA. The AD8368 is optimized AD8318 Evaluation Board
for receive application low frequencies of up to 800 MHz and
provides 34 dB of linear-in-dB voltage-controlled variable gain. REVISION HISTORY
There are a number of DACs suitable for this application. All of 9/10—Rev. A to Rev. B
the following DACs have internal references: Changes to Figure 1 .......................................................................... 1
Changes to Circuit Description Section......................................... 1
Single: AD5660/AD5640/AD5620 (16-bit/14-bit/12-bit), Changes to Common Variations Section ....................................... 3
Dual: AD5663R/AD5643R/AD5623R (16-bit/14-bit/12-bit) 11/09—Rev. 0 to Rev. A
Quad: AD5664R/AD5644R/AD5624R (16-bit/14-bit/12-bit) Updated Format ................................................................. Universal
Changes to Circuit Note Title .......................................................... 1
owners.

CN08515-0-9/10(B)
Circuit Note
CN-0051
ADA4937-1 Ultralow Distortion Differential ADC
Driver
(1-800-262-5643) or visit www.analog.com/circuits. AD9246 14-Bit, 80 MSPS/105 MSPS/125 MSPS ADC
Driving the AD9233/AD9246/AD9254 ADCs in AC-Coupled Baseband Applications

The circuit described in this document and shown in Figure 1 The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/
uses the ADA4937-1 ADC driver to convert an ac-coupled, 105 MSPS/125 MSPS ADC, featuring a high performance
single-ended input signal to a differential signal suitable for sample-and-hold amplifier (SHA) and on-chip voltage reference.
driving the AD9246 14-bit, 125 MSPS analog-to-digital converter The wide bandwidth, truly differential SHA allows a variety of
(ADC). The ADA4937-1 is a low noise, ultralow distortion, high user-selectable input ranges and offsets, including single-ended
speed differential amplifier with low dc offset and excellent applications. The device can be applied in multiplexed systems
dynamic performance. It is an ideal choice for driving high that switch full-scale voltage levels in successive channels and
performance ADCs with resolutions up to 16 bits from dc to for sampling single-channel input frequencies well beyond the
100 MHz and is well suited for a wide variety of data acquisition Nyquist frequency of the ADC.
and signal processing applications. Combined with power and The AD9246 achieves its optimum performance when driven
cost savings over previously available ADCs, this circuit is differentially. The ADA4937-1 not only provides the single-
suitable for applications in communications, instrumentation, ended-to-differential conversion but also provides gain and
and medical imaging. The ADA4937-2 is a dual version of the level shifting. The output common voltage of the ADA4937-1
ADA4937-1 that can be used when driving a dual ADC. is set by connecting a resistive divider to the VOCM pin of the
ADA4937-1. If the pin is left floating, the VOCM voltage is
approximately midsupply and is set by an internal divider.
(VIN+) – (VIN–)
200Ω GAIN = =2 1.8V
VIN
76.8Ω 5V
50Ω 10µF 90.9Ω 10µF 33Ω AVDD DRVDD

+
VIN +IN 200Ω VIN–
VIN 10pF
VOCM ADA4937 AD9246
10µF 200Ω
90.9Ω –IN VIN+
10µF 33Ω AGND SENSE CML

49.9Ω 76.8Ω
08610-001
200Ω
Figure 1. ADA4937-1 Driving the AD9246 14-Bit ADC

Rev. A
any cause whatsoever connected to the use of any“Circuit fromthe Lab”. (Continued on last page) Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
The ADA4937-1 is powered with a single 5 V supply and is The circuit must be constructed on a multilayer PC board
configured for a gain-of-2 for a single-ended, input-to-differ- with a large area ground plane. Proper layout, grounding,
ential output. The 76.8 Ω termination resistor, in parallel with and decoupling techniques must be used to achieve optimum
the single-ended input impedance of 137 Ω, provides a 50 Ω ac performance (see MT-031 Tutorial, MT-101 Tutorial, and the
termination for the source. The additional 49.9 Ω resistor, 10 µF AD9246 evaluation board layout).
capacitor, and 76.8 Ω resistor connected to the 90.9 Ω resistor It is required that the exposed pad on the underside of both the
on the inverting input balance the ac impedance driving the AD9246 and the ADA4937-1 (LFCSP packages) be connected
noninverting input. A detailed analysis of this configuration can to a large area ground plane to achieve the best electrical and
be found in MT-076 Tutorial. thermal performance. The copper plane should have several
The signal generator has a symmetric, ground-referenced, bipolar vias to achieve the lowest possible resistive thermal path for
output. The VOCM pin of the ADA4937-1 is left unconnected; heat dissipation to flow through the bottom of the PCB. These
therefore, the internal divider sets the output common-mode vias should be solder filled or plugged.
voltage to midsupply. A portion of this is fed back to the summing
COMMON VARIATIONS
nodes, biasing −IN and +IN at 1.14 V. For a common-mode
voltage of 2.5 V, each ADA4937-1 output swings between 2.0 V The AD9246 (14-bit, 80 MSPS/105 MSPS/125 MSPS) ADC is pin
and 3.0 V, providing a 2 V p-p differential output for a 1 V p-p compatible with both the AD9233 (12-bit, 80 MSPS/105 MSPS/
single-ended input. 125 MSPS) and the AD9254 (14-bit, 150 MSPS).
The output of the ADC driver is ac-coupled to a single-pole, There are a few other amplifier configurations to consider when
low-pass noise filter. The low-pass filter reduces the noise band- driving ADCs. They are differential ac-coupled input to differ-
width at the ADC input and provides a degree of isolation from ential output, dc-coupled single-ended input to ac-coupled
the switched capacitor inputs of the ADC and the driver. In any differential output, dc-coupled single-ended input to differential
configuration, the optimum value of the shunt capacitor, C, is output, and dc-coupled differential input to differential output.
dependent on the input frequency and source impedance and In dc-coupled systems, the driver output common-mode
may need to be optimized. Table 1 displays recommended values voltage is set via the VOCM pin of the ADA4937-1. The
for the RC network. However, these values are dependent on the adjustable level of the output common-mode voltage allows the
input signal frequency and may require further optimization. ADA4937-1 output to match the input common-mode voltage
The input common-mode voltage to the ADC is set by the CML of the ADC. The internal common-mode feedback loop of the
pin of the AD9246 and the pair of 200 Ω resistors. In other ADA4937-1 also provides exceptional output balance and
applications, the CML pin of the ADC and the VOCM pin of the suppression of even-order harmonic distortion products. Often
ADA4937-1 are used to set the input common-mode voltage to in these applications, the ADC CML pin is connected directly to
the ADC (see the Common Variations section). The ADA4937-1 the VOCM pin of the driver to ensure that optimal ADC input
is fabricated using the Analog Devices, Inc., proprietary silicon- common-mode voltage is achieved. In other applications, the
germanium (SiGe), complementary bipolar process, enabling it VOCM pin can be driven from a low impedance source such as an
to achieve very low levels of distortion with an input voltage noise op amp. It can also be left floating but bypassed with a capacitor;
of only 2.2 nV/ √Hz. in this case the VOCM voltage is set at the midpoint of the voltage
applied to the two supply pins.
The circuit shown in Figure 1 was tested with a −1 dBFS signal
at various input frequencies. Figure 2 shows a plot of the second Table 1. RC Network Recommended Values
and third harmonic distortion (HD2/HD3) vs. input frequency. Input Frequency Range
–75 (MHz) R Series ( Ω) C Differential (pF)
G = +2
0 to 70 33 15
70 to 200 33 5
–80
HARMONIC DISTORTION (dBc)
200 to 300 15 5
HD3
>300 15 Open (no capacitor)
–85
HD2
–90
–95
–100
08610-002
0 20 40 60 80 100 120
FREQUENCY (MHz)
Figure 2. Second Harmonic Distortion (HD2) and Third Harmonic Distortion

(HD3) for the ADA4937-1 Driving the AD9246 ADC
LEARN MORE Data Sheets and Evaluation Boards
Rob Reeder and Jim Caserta, Wideband A/D Converter Front- ADA4937-1 Data Sheet.
End Design Considerations II: Amplifier- or Transformer Drive AD9246 Data Sheet
for the ADC? Ask The Application Engineer—36, Analog
Dialogue 41-02, February 2007.
MT-031 Tutorial, Grounding Data Converters and Solving the REVISION HISTORY
Mystery of "AGND" and "DGND," Analog Devices. 11/09—Rev. 0 to Rev. A
MT-074 Tutorial, Differential Drivers for Precision ADCs, Updated Format ................................................................. Universal
Analog Devices.
MT-075 Tutorial, Differential Drivers for High Speed ADCs
Overview, Analog Devices.
MT-076 Tutorial, Differential Driver Analysis, Analog Devices.
John Ardizonni and Jonathan Pearson, "Rules of the Road" for
High-Speed Differential ADC Drivers, Analog Dialogue,
Volume 43, May 2009, Analog Devices.
ADIsimDiffAmp (Differential Amplifier Tool), Analog Devices.

CN08610-0-11/09(A)
Circuit Note
CN-0052
Circuit Designs Using Analog Devices Products AD5450/AD5451/ 8-/10-/12-/14-Bit Multiplying DACs
Apply these product pairings quickly and with confidence. AD5452/AD5453
For more information and/or support call 1-800-AnalogD OP177 Ultra-Precision Operational
(1-800-262-5643) or visit www.analog.com/circuits. Amplifier
ADR01 Low Noise Precision 10 V Reference
Unipolar, Precision DC, Digital-to-Analog Conversion Using the

AD5450/AD5451/AD5452/AD5453 8-/10-/12-/14-Bit DACs

The circuit described in this document is a high performance, The circuit uses the AD5450/AD5451/AD5452/AD5453
unipolar, precision DAC configuration that employs the AD5450/ CMOS, current-output DACs, which provide 8-, 10-, 12- and
AD5451/AD5452/AD5453 family of precision multiplying DACs, 14-bit operation, respectively. Because this is a current-output
the OP177 low noise, high precision operational amplifier (op DAC, an op amp is required for current-to-voltage (I-V)
amp), and the ADR01 precision 10 V reference. Because the op conversion at the output of the DAC. Because an op amp bias
amp dictates the overall circuit dc performance in terms of current and offset voltage are both important selection criteria
precision, the OP177, a high precision, low noise op amp, is well for precision current output DACs, this circuit employs the
matched for performance-driven applications. This circuit also OP177 op amp, which has ultralow offset voltage (25 µV) and
uses the ADR01, which is a high accuracy, high stability, 10 V bias current (2 nA). The OP177 and the AD5450/AD5451/
precision voltage reference. Because voltage reference temperature AD5452/AD5453 can be easily configured to provide a two-
coefficient and long-term drift are primary considerations for quadrant multiplying operation or a unipolar output voltage
applications requiring high precision conversion, this device is swing, as shown in Figure 1.
also an ideal candidate.
VDD = 5V
VDD1 = 12V
C1 = 1.8pF
VDD RFB
VIN AD5450/ VDD1 = 12V
VREF AD5451/ IOUT1
VOUT VREF
AD5452/ OP177 VOUT = 0 TO –VREF
ADR01 0.1µF AD5453 VSS = –12V
SYNC SCLK SDIN GND VDD
10µF 0.1µF
µCONTROLLER AGND
VSS
10µF 0.1µF
VDD1
08611-001
10µF 0.1µF
Figure 1. Unipolar Precision DC Configuration

Rev. A
any cause whatsoever connected to the use of any“Circuit fromthe Lab”. (Continued on last page) Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
The AD5450/AD5451/AD5452/AD5453are designed on a 5 V 2.0
TA = 25°C
CMOS process and operate from a VDD power supply of 2.5 V to 1.6 VREF = 10V
VDD = 5V
5.5 V. The DACs accept VREF input ranges up to 10 V, as shown 1.2
with the ADR01 reference in Figure 1. The ADR01 requires a 0.8
supply voltage (VDD1) of 12 V minimum and can be driven from
0.4
the same supply voltage that powers the output amplifier.
INL (LSB)
0
When an output amplifier is connected in unipolar mode, the
–0.4
output voltage is given by
–0.8
VOUT = −VREF × (D/2N) –1.2
where D is the digital word loaded to the DAC, and N is the –1.6
number of bits (D = 0 to 255 (8-bit AD5450); D = 0 to 1023
–2.0
08611-002
(10-bit AD5451); D = 0 to 4095 (12-bit AD5452); D = 0 to 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384
16,383 (14-bit AD5453)). CODE
Figure 2. AD5453 14-Bit DAC Relative Accuracy Plot.

The input offset voltage of an op amp is multiplied by the
variable noise gain (due to the code-dependent output resis- Excellent grounding, layout, and decoupling techniques must be
tance of the DAC) of the circuit. A change in this noise gain used for proper operation of the circuit. All power supply pins
between two adjacent digital codes produces a step change in should be decoupled directly at the pin with a low inductance
the output voltage due to the amplifier’s input offset voltage. (low ESL) 0.1 µF ceramic capacitor. The connection to ground
This output voltage change is superimposed on the desired should be directly to a large area ground plane. Additional
change in output between the two codes and gives rise to a decoupling using a 1 µF to 10 µF electrolytic capacitor is recom-
differential linearity error, which, if large enough, may cause mended on each power supply where it enters the PC board.
the DAC to be nonmonotonic. In general, the input offset The decoupling capacitors are not shown in Figure 1 for
voltage should be a fraction of an LSB to ensure monotonic simplicity.
behavior when stepping through codes. To optimize high frequency performance, the I-V amplifier
Relative accuracy or endpoint nonlinearity is one of the most should be located as close to the DAC as possible. The AD5450/
widely used techniques in determining the accuracy perform- AD5451/AD5452/AD5453 data sheets show the schematics and
ance of a DAC circuit. This is a measure of the maximum layouts used for the evaluation boards.
deviation from a straight line passing through the endpoints of COMMON VARIATIONS
the DAC transfer function. It is measured after adjusting for
The OP1177 and AD8065 are other excellent op amp candidates
zero and full-scale error and is normally expressed in LSBs.
for the I-V conversion circuit. They also provide a low offset
Figure 2 shows the performance of the circuit shown in Figure 1
voltage and ultralow bias current.
using the AD5453 14-bit DAC and an OP177 amplifier.
The 10.0 V output ADR01 can be replaced by either the ADR02
or ADR03, which are low noise references available from the
same reference family as the ADR01 and provide 5.0 V and
2.5 V outputs, respectively. The ADR445 and ADR441 ultralow
noise references are also suitable substitutes that provide 5.0 V
and 2.5 V, respectively. Note that the size of the reference input
voltage is restricted by the rail-to-rail voltage of the operational
amplifier selected.
Kester, Walt. The Data Conversion Handbook. Chapters 3, 7. AD5450/AD5451/AD5452/AD5453 Data Sheets and
Analog Devices, 2005. Evaluation Boards.
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs. OP177 Data Sheet.
Analog Devices. AD8065 Data Sheet.
MT-033 Tutorial, Voltage Feedback Op Amp Gain and OP1177 Data Sheet.
Bandwidth. Analog Devices.
ADR01 Data Sheet.
ADR02 Data Sheet.
ADR03 Data Sheet.
Rail-to-Rail Issues. Analog Devices. ADR441 Data Sheet.
MT-101 Tutorial, Decoupling Techniques. Analog Devices. ADR445 Data Sheet.
ADIsimPower Design Tool. Analog Devices. REVISION HISTORY
Voltage Reference Wizard Design Tool. Analog Devices. 11/09—Rev. 0 to Rev. A
Updated Format ................................................................. Universal

CN08611-0-11/09(A)
Circuit Note
CN-0053
AD5450/AD5451/
Circuit Designs Using Analog Devices Products 8-/10-/12-/14-Bit Multiplying DACs
AD5452/AD5453
For more information and/or support call 1-800-AnalogD Dual High Performance FastFET™
AD8066
(1-800-262-5643) or visit www.analog.com/circuit. Amplifier
Low Noise, Precision 10 V
ADR01
Reference
Precision, Bipolar Configuration for the AD5450/AD5451/AD5452/AD5453

8-/10-/12-/14-Bit Multiplying DACs
CIRCUIT FUNCTION AND BENEFITS provide the current-to-voltage conversion and the signal
This circuit is a bipolar, precision DAC configuration that conditioning. A low noise reference such as the ADR01 is
employs an AD5450, AD5451, AD5452, orAD5453 precision required to drive the VREF input, and the optimum output noise
multiplying DAC and the AD8066 low noise op amp. The DAC performance is obtained by using a low noise, low bandwidth
is the core-programmable element, and the amplifier selection output amplifier. The main advantages of this circuit are
dictates the performance in terms of precision or speed. For an simplicity, constant reference input impedance, and the ability
accurate, high precision, low noise application, a dual opera- of VREF to exceed the DAC VDD supply voltage.
tional amplifier (op amp) such as the AD8066 can be used to
R3
20kΩ
VDD = 5V
R2 R5
20kΩ
VDD RFB C1
AD5450/ +12V R4
AD5451/ IOUT1 10kΩ +12V
VREF
VREF A1
±10V
R1
AD5452/
GND A2 VOUT = –VREF TO +VREF
AD5453 –12V
SYNC SCLK SDIN –12V
AGND
µCONTROLLER
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING ARE ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
08618-001
3. C1 PHASE COMPENSATION (1pF TO 5pF) MAY BE REQUIRED

IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 1. Bipolar Precision DC Conversion (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. A
any cause whatsoever connected to the use of any“Circuit from the Lab”. (Continued on last page) Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved.
CIRCUIT DESCRIPTION In general, the input offset voltage should be a fraction of an
In many applications, it may be necessary to generate a full LSB to ensure monotonic behavior when stepping through codes.
four-quadrant multiplying operation or a bipolar output voltage A compensation capacitor, C1, is used to prevent ringing or
swing as shown in Figure 1. This can be easily accomplished by instability in the closed loop. Typical values in the 1 pF to 5 pF
using a dual amplifier denoted by A1 and A2 and some external range can be used.
resistors. In this circuit, the A1 amplifier performs the current- In any circuit where accuracy is important, careful consider-
to-voltage conversion, and the second amplifier, A2, provides a ation of the power supply and ground return layout helps to
gain of 2. Biasing the external amplifier with an offset from the ensure the rated performance. The printed circuit board should
reference voltage results in a full four-quadrant multiplying be designed so that the analog and digital sections are separated
operation. In dc applications, a suitable reference to drive the and confined to certain areas of the board. If the DAC is in a
reference input is the ADR01. This is a high accuracy, high system where multiple devices require an AGND-to-DGND
stability, 10 V precision voltage reference. Because voltage connection, the connection should be made at one point only.
reference temperature coefficient and long-term drift are The star ground point should be established as close as possible
primary considerations for applications requiring high to the device.
precision conversion, this device is an ideal candidate. These DACs should have ample supply bypassing of 10 μF in
The AD5450/AD5451/AD5452/AD5453 DACs are designed on parallel with 0.1 μF on the supply located as close to the package
a 5 V CMOS process and operate from a VDD power supply of as possible, ideally right up against the device. The 0.1 μF
2.5 V to 5.5 V. They accept VREF input ranges of up to 10 V as capacitor should have low effective series resistance (ESR) and
shown in Figure 1, and the power supply for the output low effective series inductance (ESL), like the common ceramic
amplifiers must be a bipolar supply with enough headroom to types that provide a low impedance path to ground at high
accommodate the analog output range, VOUT. The transfer frequencies, to handle transient currents due to internal logic
function of this circuit shows that both negative and positive switching.
output voltages are created as the input code, D, is incremented Low ESR, 1 μF to 10 μF tantalum capacitors should also be
from Code 0 (VOUT = − VREF) to midscale (VOUT = 0 V ) to full- applied at the supplies to minimize transient disturbance and
scale (VOUT = +VREF). VOUT is represented by the following filter out low frequency ripple. To optimize high frequency
equation: performance, the I-V amplifier should be located as close to the
VOUT = VREF × (D/2N-1) – VREF. DAC as possible.
where: COMMON VARIATIONS
N is the resolution of the DAC . The OP2177 is another excellent dual op-amp candidate for the
D is the digital word loaded to the DAC ,and D = 0 to 255 (8-bit I-V conversion circuit. It also provides a low offset voltage (15 µV
AD5450), D = 0 to 1023 (10-bit AD5451), D = 0 to 4095 (12-bit typical) and ultralow bias current (0.5 nA typical). The ADR02
AD5452), or D = 0 to 16,383 (14-bit AD5453). and ADR03 with 5.0 V and 2.5 V output, respectively, are other
An op amp is used in the current-to-voltage (I-V) stage of this low noise references available from the same reference family as
circuit. The supply voltage of the op amp limits the reference the ADR01. Other low noise references that are suitable are the
voltage that can be used with the DAC. An op-amp’s bias ADR441 and ADR445. The size of the reference input voltage is
current and offset voltage are both important selection criteria restricted by the rail-to-rail output voltage of the operational
for precision current output DACs. Therefore, this circuit amplifier selected.
employs the AD8066 op amp, which has ultralow offset voltage
(0.4 mV typical) and bias current (2 pA typical).
The input offset voltage of an op amp is multiplied by the
variable noise gain (due to the code-dependent output
resistance of the DAC) of the circuit. A change in this noise gain
between two adjacent codes produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
LEARN MORE Data Sheets
Kester, Walt. The Data Conversion Handbook. Chapter 3, 7. AD5450/AD5451/AD5452/AD5453 Data Sheet
Analog Devices. 2005. AD8066 Data Sheet
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs. OP2177 Data Sheet
Analog Devices.
ADR01 Data Sheet
ADR02 Data Sheet
ADR03 Data Sheet
MT-033 Tutorial, Voltage Feedback Op Amp Gain and
Bandwidth. Analog Devices. ADR441 Data Sheet
MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and ADR445 Data Sheet
MT-101 Tutorial, Decoupling Techniques. Analog Devices. REVISION HISTORY
ADIsimPower Design Tool. Analog Devices. 1/10—Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Voltage Reference Wizard Design Tool, Analog Devices
Changes to Circuit Description....................................................... 2

CN08618-0-1/10(A)
Circuit Note
CN-0055
Circuit Designs Using Analog Devices Products AD5450/AD5451/ 8-/10-/12-/14-Bit Multiplying
Apply these product pairings quickly and with confidence. AD5452/AD5453 DAC
For more information and/or support call 1-800-AnalogD High Performance FastFET TM
(1-800-262-5643) or visit www.analog.com/circuit. AD8065
Amplifier
Programmable Gain Element Using the AD5450/AD5451/AD5452/AD5453

Current Output DAC Family
CIRCUIT FUNCTION AND BENEFITS temperature coefficients of the DAC. This approach is recom-
In applications where the DAC output voltage range is required mended in circuits where gains of greater than 1 are required.
to be larger than the input voltage, a programmable gain circuit D
VOUT = –Gain × VIN × (1)
can be used. This circuit provides a programmable gain 2N
function using a multiplying DAC, the AD5450/AD5451/ where D is the digital word loaded to the DAC. D = 0 to 255
AD5452/AD5453, and a fast, low offset operational amplifier, (8-bit AD5450), D = 0 to 1023 (10-bit AD5451), D = 0 to 4095
the AD8065. The maximum gain value and the temperature (12-bit AD5452), D = 0 to 16383 (14-bit AD5453); N is the
coefficient are set by external resistors, and the resolution of the number of bits.
programmable gain is set by the resolution of the DAC.
The key benefit of this circuit is its ability to overcome gain TC
CIRCUIT DESCRIPTION errors using resistor matching. The TC of the external resistors
The circuit shown in Figure 1 is the recommended method of needs to match each other but do not need to match that of the
increasing the gain of the circuit. R1, R2, and R3 should all have DAC internal ladder resistance.
similar temperature coefficients, but they need not match the
VDD = +5V
4.7pF
VDD RFB VDD1 = +12V
AD5450/
R1 AD5451/ IOUT1
VIN VREF AD5452/ AD8065 VOUT
R2 × R3 AD5453
R1 =
R2 + R3 SYNC SCLK SDIN GND VSS = –12V
R3
R2 + R3
GAIN =
R2
R2
µCONTROLLER
AGND
VDD VSS VDD1
10µF 0.1µF 10µF 0.1µF 10µF 0.1µF

08620-001
Figure 1. Programmable Gain Circuit Using a Current Output DAC (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. A
Resistor R1 is required because R1 plus the input impedance of LEARN MORE

the DAC must equal the total feedback resistance which is RFB
ADIsimPower Design Tool. Analog Devices.
plus R2||R3. The input impedance of the DAC is RFB, so
Kester, Walt. The Data Conversion Handbook. Chapter 3, 7.
R1 + RFB = RFB + R2||R3 (2)
Analog Devices. 2005.
R1 = R2||R3 (3)
The values of R1 and R2 must be chosen such that the output Analog Devices.
voltage does not exceed the output range of the operational
amplifier for the given supply voltage. Also note that the bias
Mystery of “AGND” and “DGND.” Analog Devices.
current of the operational amplifier is multiplied by the total
feedback resistance (RFB + R2||R3) to give an associated offset. MT-033 Tutorial, Voltage Feedback Op Amp Gain and
Thus, the values of R1 and R2 cannot be too large or they will Bandwidth. Analog Devices.
have a significant effect on the overall offset voltage. MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
The AD5450/AD5451/AD5452/AD5453 products are designed Rail-to-Rail Issues. Analog Devices.
on a 5 V CMOS process and operate from a VDD1 power supply MT-101 Tutorial, Decoupling Techniques. Analog Devices.
of 2.5 V to 5.5 V. The output amplifier is driven from a dual
Voltage Reference Wizard Design Tool. Analog Devices.
power supply voltage (VDD/VSS), which needs to be large enough
to accommodate the analog output range of the circuit. Data Sheets
Generally, ±12 V supplies are sufficient. The 4.7 pF capacitor is AD5450 Data Sheet
used to prevent ringing or instability in the closed-loop
application. AD5451 Data Sheet
The input offset voltage of an op amp is multiplied by the AD5452 Data Sheet
variable noise gain (due to the code-dependent output AD5453 Data Sheet
resistance of the DAC) of the circuit. A change in this noise gain AD8065 Data Sheet
between two adjacent digital codes produces a step change in
the output voltage due to the amplifier’s input offset voltage. OP1177 Data Sheet
This output voltage change is superimposed on the desired
change in output between the two codes and produces a diffe- REVISION HISTORY
rential linearity error, which if large enough, could cause the DAC 11/09—Rev. 0 to Rev. A
to be non-monotonic. The AD8065 benefits from both a low input
offset voltage and low bias currents to overcome this issue.
COMMON VARIATIONS
The OP1177 is another excellent op amp candidate for the I-V
conversion circuit. It also provides low offset voltage and
ultralow bias current. For the selection of the reference, the
input voltage is restricted by the rail-to-rail voltage of the
operational amplifier selected and also the gain set up by the
resistors R2 and R3.

CN08620-0-11/09(A)
Circuit Note
CN-0073
Circuit Designs Using Analog Devices Products AD5765 Complete Quad, 16-Bit, High Accuracy DAC
Apply these product pairings quickly and with confidence. ADR420 Precision 4.096 V Voltage Reference
High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion

Using the AD5765 DAC
CIRCUIT FUNCTION AND BENEFITS +5V

ADR420
2 VIN VOUT 6
This circuit provides high accuracy, bipolar data conversion GND
using the AD5765, a quad, 16-bit, serial input, bipolar voltage 4
output DAC. This circuit utilizes the ADR420 precision

+5V –5V
reference to achieve optimal DAC performance over a full
10µF
operating temperature range. The only external components 10µF
100nF
100nF 100nF
needed for this precision 16-bit DAC are a reference voltage
source, decoupling capacitors on the supply pins and reference BIN/2sCOMP
inputs, and an optional short-circuit current-setting resistor. 32 31 30 29 28 27 26 25
This implementation, therefore, leads to savings in cost and
REFGND
AVSS
NC
REFCD
REFAB
AVDD
BIN/2sCOMP
NC
reduced board space. The circuit is well suited for both closed-
loop servo control and open-loop control applications. SYNC 1 SYNC AGNDA 24
SCLK 2 SCLK VOUTA 23 VOUTA
CIRCUIT DESCRIPTION SDIN 3 SDIN VOUTB 22 VOUTB
The AD5765 is a high performance digital-to-analog converter SDO 4 SDO

AD5765 AGNDB 21
CLR 5 CLR AGNDC 20
that offers guaranteed monotonicity, integral nonlinearity (INL) LDAC 6 LDAC VOUTC 19 VOUTC
of ±1 LSB (C-grade device), low noise, and a 10 μs settling time. D0 7 D0 VOUTD 18 VOUTD
Performance is guaranteed over the following supply voltage D1 8 D1 AGNDD 17
RSTOUT
ranges: The AVDD supply range is from +4.75 V to +5.25 V,

RSTIN
DGND
PGND
DVCC
AVDD
AVSS
ISCC
and the AVSS supply range is from −4.75 V to −5.25 V. The
nominal full-scale output voltage range is ±4.096 V.
9 10 11 12 13 14 15 16
100nF
100nF
RSTOUT
A precision voltage reference must be used in order for the RSTIN
10µF
DAC to achieve the optimum performance over its full 10µF

100nF
operating temperature range. The AD5765 incorporates
reference buffers, which eliminate the need for both a positive NC = NO CONNECT
10µF
and negative external reference and associated buffers. This +5V
08273-001
leads to further savings in both cost and board space. Because +5V –5V
the voltages applied to the reference inputs (REFAB, REFCD) Figure 1. High Accuracy, Bipolar Configuration of the AD5765 DAC Using a
are used to generate the buffered positive and negative internal Precision Reference
references for the DAC cores, any error in the external voltage
reference is reflected in the outputs of the device. 2.048 V precision reference candidates from Analog Devices,
There are four possible sources of error to consider when Inc., and their respective attributes.
choosing a voltage reference for high accuracy applications: In any circuit where accuracy is important, careful considera-
initial accuracy, temperature coefficient of the output voltage, tion of the power supply and ground return layout helps to
long term drift, and output voltage noise. Table 1 lists other ensure the rated performance. The PCB on which the AD5765
Rev. 0
Table 1. Precision 2.048 V References
Initial Accuracy Max Long-Term Drift Typ Temp Drift Max 0.1 Hz to 10 Hz Noise
Part Number (mV) (ppm) (ppm/°C) Typ (µV p-p)
ADR430 ±1 40 3 3.5
ADR420 ±1 50 3 1.75
ADR390 ±4 50 9 5
is mounted must be designed so that the analog and digital LEARN MORE
sections are physically separated and confined to certain areas Kester, Walt. 2005. The Data Conversion Handbook. Analog
of the board. If the AD5765 is in a system where multiple Devices. Chapters 3 and 7.
devices require an AGND-to-DGND connection, the connec-
tion is to be made at one point only. The star ground point is
Analog Devices.
established as close as possible to the device. The AD5765 must
have ample supply bypassing of 10 µF in parallel with 0.1 µF on MT-031 Tutorial, Grounding Data Converters and Solving the
each supply, located as close to the package as possible, ideally Mystery of AGND and DGND. Analog Devices.
right up against the device. The 10 µF capacitors are the MT-101 Tutorial, Decoupling Techniques. Analog Devices.
tantalum bead type. The 0.1 µF capacitor must have low
Voltage Reference Wizard Design Tool.
effective series resistance (ESR) and low effective series
inductance (ESL), such as the common ceramic types, which Data Sheets and Evaluation Boards
provide a low impedance path to ground at high frequencies to AD5765 Data Sheet.
handle transient currents due to internal logic switching.
The power supply traces of the AD5765 must be as wide as
ADR420 Data Sheet.
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, must be shielded with digital ground to avoid REVISION HISTORY
radiating noise to other parts of the board and must never be 6/09—Revision 0: Initial Version
run near the reference inputs. A ground line routed between the
SDIN and SCLK lines helps reduce crosstalk between them (not
required on a multilayer board, which has a separate ground
plane; however, it is helpful to separate the lines). It is essential
to minimize noise on the reference inputs because it couples
through to the DAC output. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board must run
at right angles to each other. This reduces the effects of
feedthrough on the board. A microstrip technique is
recommended but not always possible with a double-sided
board. In this technique, the component side of the board is
the solder side. Best layout and performance are achieved with
at least a 4-layer multilayer board, where there are a ground
plane layer, a power supply layer, and two signal layers.

CN08273-0-6/09(0)
Rev. 0 | Page 2 of 2
Circuit Note
CN-0079
Apply these product pairings quickly and with confidence. AD5542 16-Bit Serial Input, Voltage Output DAC
AD8628 Auto-Zero Operational Amplifier
High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/AD5541

Voltage Output DAC, ADR421 Reference, and AD8628 Auto-Zero Op Amp
CIRCUIT FUNCTION AND BENEFITS This circuit provides precision, low power, voltage output,
This circuit provides precision data conversion using the digital-to-analog conversion. The AD5542 can be operated in
AD5542 voltage output DAC together with the ADR421BRZ either the buffered or unbuffered mode. The application and its
voltage reference and the AD8628 auto-zero op amp as the requirements on settling time, input impedance, noise, etc.,
reference buffer. The AD8628 reference buffer provide benefits determine which mode of operation is best. The selection of the
previously found only in expensive auto-zeroing or chopper- output buffer amplifier can be tailored to suit either dc
stabilized amplifiers. Using Analog Devices, Inc., circuit precision or fast settling time. Where the DAC is required to
topology, these zero-drift amplifiers combine low cost with high drive a load less than 60 kΩ, an output buffer will be required.
accuracy and low noise. No external capacitor is required, and The output impedance of the DAC is constant and code
the digital switching noise associated with most chopper- independent, but to minimize gain errors the input impedance
stabilized amplifiers is greatly reduced, thereby making this the of the output amplifier should be as high as possible. The output
optimum choice for reference buffering. amplifier should also have a 3 dB bandwidth of 1 MHz or
greater. The output amplifier adds another time constant to the
system, thereby increasing the settling time of the final output.
+5V
10µF
+
0.1µF
1µF 0.1µF
2
VIN AD8628
+2.5V
VOUT 6
ADR421 +5V
TRIM 5 0.1µF
GND
4 RFB
SERIAL
VDD REFF REFS
INTERFACE RFB
CS INV
DIN RINV *
OUT
SCLK
AD5541/AD5542
LDAC
08312-001
*OUTPUT AMPLIFIER SHOULD DGND AGNDF AGNDS

BE CHOSEN TO SUIT
APPLICATION NEEDS.
Figure 1. Precision DAC Configuration (Simplified Schematic)
Rev. 0
A higher 3 dB amplifier bandwidth results in a faster effective auto-zeroing frequencies, thereby maximizing the signal-to-
settling time of the combined DAC and amplifier. All devices in noise ratio for the majority of applications without the need for
the circuit can be powered from a single +5 V supply. The input additional filtering. The relatively high internal chopping
voltage range of the ADR421 reference is 4.5 V to 18 V. frequency of 15 kHz simplifies filter requirements for a wide,
useful, noise-free bandwidth in instrumentation and process
CIRCUIT DESCRIPTION
control applications.
This circuit utilizes the AD5542 voltage output DAC, providing
16-bit, fully accurate performance. The DAC architecture of the Measured results show that high accuracy, low noise
AD5541/AD5542 is a segmented R-2R voltage mode DAC. performance with minimum high frequency intermodulation
With this type of configuration the output impedance is distortions transferred to the output is achievable using the
independent of digital code, while the input impedance seen by AD8628 as a reference buffer in a high accuracy, high
the reference is heavily code dependent. For this reason, the performance system.
reference buffer choice is very important to account for the Integral nonlinearity (INL) error is the deviation in LSBs of the
code-dependent reference current, which may lead to linearity actual DAC transfer function from an idealized transfer
errors if the DAC reference is not adequately buffered. The op function. DNL error is the difference between an actual step
amp offset voltage, offset error temperature coefficient, and size and the ideal value of 1 LSB. The circuit in Figure 1
noise are important criteria when selecting a reference buffer provides 16-bit resolution with ±1 LSB INL error and ±1 LSB
with precision voltage output DACs. Offset errors in the DNL error. Figure 2 and Figure 3 show the INL and DNL
reference circuit cause gain errors on the DAC output. This performance of the circuit.
circuit employs the AD8628 zero-drift, single-supply, rail-to-
rail, input/output operational amplifier. With an offset voltage
of 1 μV, drift of less than 0.005 μV/°C, and noise of 0.5 μV p-p +1
(0.1 Hz to 10 Hz), the AD8628 is suited for applications where
INTEGRAL NON-LINEARITY (LSBs)
error sources need to be minimized. The output voltage is

dependent on the reference voltage, as shown in the following
equation:
V REF × D 0
VOUT =
2N
where D is the decimal data-word loaded to the DAC register
and N is the resolution of the DAC.
For a reference of 2.5 V, the equation is simplified to the
08312-002
following: –1
0 32,768 65,535
2.5 × D
CODE
VOUT = Figure 2. Integral Nonlinearity Error vs. Input Code
65,536
This gives a VOUT of 1.25 V for the midscale code and 2.5 V for
the full-scale code.
The LSB size is 2.5 V/65,536, or 38.1 µV. +0.8
DIFFERENTIAL NON-LINEARITY (LSBs)
There is a common misconception that auto-zero amplifiers are

not to be trusted because of intermodulation terms and
unwanted harmonics filtering through to the output due to the
internal switching action. Previous auto-zero amplifiers used
either auto-zeroing or chopper stabilization techniques. 0
Traditional auto-zeroing results in low noise energy at the auto-

zeroing frequency at the expense of higher low frequency noise,
due to aliasing of wideband noise into the auto-zeroed
frequency band. Chopping results in less low frequency noise at
08312-003
the expense of larger noise energy at the chopping frequency. –0.8

0 32,768 65,535
The AD8628 family uses both auto-zeroing and chopping in a CODE
patented “ping-pong” arrangement to obtain lower low
Figure 3. Differential Nonlinearity Error vs. Input Code
frequency noise together with lower energy at the chopping and
The offset error and gain error were measured to be 10 µV and In any circuit where accuracy is important, it is helpful to
170 µV, respectively. The gain error of ±5 LSBs and the zero- carefully consider the power supply and ground return layout
code error of ±1 LSB are within the specified 38 µV (with a on the board. The printed circuit board (PCB) containing the
2.5 V reference) at ambient temperature. circuit should have separate analog and digital sections. If the
Figure 4 shows a 0.1 Hz to 10 Hz noise plot for the circuit.The circuit is used in a system where other devices require an
output of the DAC, VOUT, was connected to the input of a 0.1 Hz AGND-to-DGND connection, the connection should be made
to 10 Hz bandwidth filter followed by an amplifier with a gain at one point only. This ground point should be as close as
of 10,000. The voltage noise is captured on a scope. A very low possible to the AD5542. The power supply to the AD5542
peak-to-peak voltage of 57 mV is observed (5.7 µV with respect should be bypassed with 10 μF and 0.1 μF capacitors. The
to the DAC output). capacitors should be as physically close as possible to the device,
with the 0.1 μF capacitor ideally right up against the device. The
10 μF capacitors are the tantalum bead type. It is important that
the 0.1 μF capacitor have low effective series resistance (ESR)
and low effective series inductance (ESL), as is typical of
common ceramic types of capacitors. This 0.1 μF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching. The
power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by
digital ground.
The circuit must be constructed on a multilayer PC board with
a large area ground plane. Proper layout, grounding, and
decoupling techniques must be used to achieve optimum
08312-004
Figure 4. A 0.1 Hz to 10 Hz Output Noise Plot; Full-Scale Code Loaded performance (see Tutorial MT-031, Grounding Data Converters
into DAC (1/f Noise = 57 mV/10,000 = 5.7 µV) and Solving the Mystery of AGND and DGND and Tutorial MT-
101, Decoupling Techniques).
Figure 5 shows the DAC output using the spectrum analyzer COMMON VARIATIONS
sweeping from 100 Hz to 100 kHz. No significant IMD terms The AD8538 is another excellent auto-zero op amp candidate to
were observed, thus showing that auto-zero amplifiers such as be used for buffering the reference in this circuit. It provides a
the AD8628 used as reference buffers are excellent choices. low offset voltage and ultralow bias current. The 2.5 V output
ADR421 can be replaced by either the ADR423 or the ADR424,
0
which are low noise references available from the same
reference family as the ADR421 and provide 3 V and 4.096 V,
–20 respectively. The ADR441 and the ADR431 ultralow noise
references are suitable substitutes that provide 2.5 V, also. Note
–40 that the size of the reference input voltage is restricted by
the rail-to-rail output voltage capability of the operational
POWER (dB)
–60 amplifier selected.

There is no output buffer used in this circuit because output
–80
buffer performance can be optimized for speed or dc precision,
depending on the system bandwidth and application need. The
–100
AD5661 would be an excellent choice for an output buffer. This
is a single-supply, 5 V to 16 V amplifier that uses Analog
08312-005
–120
100 1k 10k 100k
Devices’ patented DigiTrim™ technique to achieve low offset
FREQUENCY (Hz) voltage. It features low input bias current and wide signal
Figure 5. DAC Output Spectral Density Plot bandwidth. The AD8605 or the AD8655 would also be
(dB Referenced to Full Scale) excellent options.
LEARN MORE Data Sheets
Kester, Walt. 2005. The Data Conversion Handbook. Analog AD5541 Data Sheet.
Devices. Chapters 3 and 7. AD5542 Data Sheet.
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs. AD8628 Data Sheet.
Analog Devices.
ADR421 Data Sheet.
MT-016 Tutorial, Basic DAC Architectures III: Segmented DACs,
Analog Devices.
REVISION HISTORY
Rail-to-Rail Issues, Analog Devices.
Amps, Analog Devices.
Voltage Reference Wizard Design Tool.

CN08312-0-8/09(0)
Circuit Note
CN-0102
Circuits from the Lab™ reference circuits are engineered and 4.8 kHz, Ultralow Noise, 24-Bit, Σ-Δ ADC
tested for quick and easy system integration to help solve today’s AD7190
with PGA
information and/or support, visit www.analog.com/CN0102. ADP3303 5 V Low Dropout Linear Regulator
ADP3303 3.3 V Low Dropout Linear Regulator
Precision Weigh Scale Design Using the AD7190 24-Bit Sigma-Delta ADC with
Internal PGA
EVALUATION AND DESIGN SUPPORT digital converter (ADC) with an internal programmable gain
Circuit Evaluation Boards amplifier (PGA). The AD7190 simplifies the weigh scale design
AD7190 Evaluation Board (EVAL-AD7190EBZ) because most of the system building blocks are included on
Design and Integration Files the chip. The AD7190 maintains good performance over the
Schematics, Layout Files, Bill of Materials complete output data rate range, from 4.7 Hz to 4.8 kHz, which
allows it to be used in weigh scale systems that operate at low
CIRCUIT FUNCTION AND BENEFITS speeds along with higher speed weigh scale systems, such as
This circuit is a weigh scale system that uses the AD7190, an hopper scales.
ultralow noise, low drift, 24-bit sigma delta (Σ-Δ) analog-to-
ADP3303 (3.3V) DVDD
IN OUT
9V BATTERY IN OUT
SD NR 0.1µF 4.7µF
+ + GND FB: TYCO BMB2A1000LN2
1N4148 10µF 0.1µF
100Ω @
ADP3303 (5V) 100MHz AVDD
IN OUT
+ FB 1.5Ω
IN OUT
10µF 0.1µF SD NR 0.1µF 4.7µF 0.1µF 0.1µF
GND
+ +
0.1µF 10µF
+ +
0.1µF 10µF
0.01µF AVDD DVDD
REFIN1(+)
1µF DIN
REFIN1(–) 100Ω
LOAD CELL: DOUT/RDY
TEDEA HUNTLEIGH 0.01µF
505H-0002-F070 100Ω MICRO- USB
SCLK CONTROLLER
AD7190 100Ω
SENSE+
CS
0.01µF 100Ω
OUT+ SYNC
AIN3 100Ω
100Ω 1µF
AIN4 LCD
SENSE– 100Ω DRIVER
0.01µF
OUT–
BPDSW
DGND AGND LCD
08370-001
Figure 1. Weigh Scale System Using the AD7190 (Simplified Schematic: All Connections Not Shown)
Rev. A
CIRCUIT DESCRIPTION any voltage between 2.7 V and 5.25 V. The microcontroller uses
Because the AD7190 provides an integrated solution for weigh a 3.3 V power supply. Therefore, DVDD is also powered from
scales, it interfaces directly to the load cell. The only external 3.3 V. This simplifies the interface between the ADC and
components required are some filters on the analog inputs and microcontroller because no external level shifting is required.
capacitors on the reference pins for EMC purposes. The low level There are several methods to power the weigh scale system. It
signal from the load cell is amplified by the internal PGA of the can be powered from the main power supply bus or battery
AD7190. The PGA is programmed to operate with a gain of 128. powered (as shown in Figure 1). A 5 V low noise regulator is used
The conversions from the AD7190 are then sent to the micro- to ensure that the AD7190 and the load cell receive a low noise
controller where the digital information is converted to weight supply. The ADP3303 (5 V) is used to generate the 5 V supply
and displayed on the LCD. and is a low noise regulator. The filter network shown inside the
Figure 2 shows the actual test setup. A 6-wire load cell is used, dotted box ensures a low noise AVDD for the system. In addition,
because this gives the optimum system performance. A 6-wire noise reduction capacitors are placed on the regulator output as
load cell has two sense pins, in addition to the excitation, ground, recommended in the ADP3303 (5 V) data sheet. To optimize
and two output connections. The sense pins are connected to the EMC performance, the regulator output is filtered ahead of
the high side and low side of the Wheatstone bridge. The voltage the AD7190 and the load cell. The 3.3 V digital supply is generated
developed across the bridge can, therefore, be accurately measured, using the ADP3303 (3.3 V). It is essential that low noise regulators
regardless of the voltage drop due to the wiring resistance. In are used to generate all the power supply voltages to the AD7190
addition, the AD7190 has differential analog inputs, and it and the load cell, because any noise on the power supply or ground
accepts a differential reference. Connection of the load cell planes introduces noise into the system and degrades the circuit
differential SENSE lines to the AD7190 reference inputs creates performance.
a ratiometric configuration that is immune to low frequency Figure 3 shows the rms noise of the AD7190 for different output
changes in the power supply excitation voltage. In addition, it data rates when the gain is equal to 128. Figure 3 shows that the
eliminates the need for a precision reference. With a 4-wire load rms noise increases as the output data rate increases. However,
cell, the sense pins are not present, and the ADC reference pins the device maintains good noise performance over the complete
are connected to the excitation voltage and ground. With this range of the output data rates.
arrangement, the system is not completely ratiometric because 1k
there is a voltage drop between the excitation voltage and SENSE+

due to wiring resistance. There is also a voltage drop due to wire
resistance on the low side.
100
RMS NOISE (nV)
10
08370-003
1
1 10 100 1k 10k
OUTPUT DATA RATE (Hz)
Figure 3. RMS Noise for Different Output Data Rates

If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-scale
signal from the load cell is 10 mV when the excitation voltage is
5 V. A load cell has an offset, or TARE, associated with it. This
TARE can have a magnitude that is up to 50% of the load cell
full-scale output signal. The load cell also has a gain error that
can be up to ±20% of full scale. Some customers use a DAC to
remove or null the TARE. When the AD7190 uses a 5 V reference,
08370-002
its analog input range is equal to ±40 mV when the gain is set to
128 and the part is configured for bipolar operation. The wide
Figure 2. Weigh Scale System Setup Using the AD7190 analog input range of the AD7190 relative to the load cell full-
The AD7190 has separate analog and digital power supply pins. scale signal (10 mV) is beneficial because it ensures that the offset
The analog section must be powered from 5 V. The digital power and gain error of the load cell do not overload the front end of
supply is independent of the analog power supply and can be the ADC.
The AD7190 has an rms noise of 8.5 nV when the output data Figure 4 and Figure 5 show the actual (raw) conversions read
rate is 4.7 Hz. The number of noise-free counts is equal to back from the AD7190 when the load cell is attached. In practice, a
10 mV digital post filter is used in a weigh scale system. The additional
= 178,250 (1) averaging that is performed in the post filter further improves the
6.6 × 8.5 nV
number of noise-free counts at the expense of a reduced data rate.
where the factor of 6.6 converts the rms voltage into a peak-to- COMMON VARIATIONS
peak voltage.
Note that all noise specifications in this section are given for a
The resolution in grams is, therefore, equal to PGA gain of 128.
2 kg The AD7190 is a high precision ADC for high-end weigh scales.
= 0.01 g (2)
178,250 Other suitable ADCs are the AD7192 and AD7191. The AD7192 is
The noise-free resolution is equal to pin-for-pin compatible with the AD7190. However, its rms noise is
slightly higher. The AD7192 has an rms noise of 11 nV for an
log10 (178,250 )
log 2 (178,250 ) = = 17.4 bits (3) output data rate of 4.7 Hz, while the AD7190 has an rms noise of
log10 (2 ) 8.5 nV at this output data rate. The AD7191 is a pin-programmable
In practice, the load cell itself introduces some noise. There is device. It has four output data rates and four gain settings. Due to
also some time and temperature drift due to the load cell along its pin programmability and reduced feature set, it is an easy to use
with the drift of the AD7190. To determine the accuracy of the device. Its rms noise is the same as the rms noise of the AD7192.
complete system, the weigh scale can be connected to a PC via For medium-end weigh scales, the AD7799 is a suitable device.
the USB connector. Using LabVIEW software, the performance At an output data rate of 4.17 Hz, the AD7799 has an rms noise
of the weigh scale system can be evaluated. Figure 4 shows the of 27 nV.
measured output performance when a 1 kg weight is placed on
Finally, for low-end weigh scales, the AD7798, AD7781 and
the load cell and 500 conversions are gathered. The noise of the
AD7780 are suitable devices. The AD7798 has the same feature
system is calculated by the software to be 12 nV rms and 88 nV
set as the AD7799. At 4.17 Hz, its rms noise is 40 nV. The AD7780
peak-to-peak. This equates to 113,600 noise-free counts, or
and AD7781 have one differential analog input and are pin
16.8 bits of noise-free code resolution.
programmable, allowing an output data rate of 10 Hz and 17.6 Hz
and a gain of 1 or 128. The rms noise is 44 nV when the output
data rate is 10 Hz.
As with any high accuracy circuit, proper layout, grounding, and
decoupling techniques must be employed. See Tutorial MT-031,
Grounding Data Converters and Solving the Mystery of AGND
and DGND and Tutorial MT-101, Decoupling Techniques for
more details.
08370-004
A complete design support documentation package for this

Figure 4. Measured Output Code for 500 Samples Showing the Effects of Noise circuit note can be found at http://www.analog.com/CN0102-
DesignSupport.
08370-005
Figure 5. Measured Output in Grams for 500 Samples Showing the Effects of Noise
Figure 5 shows the performance in terms of weight. The peak-

to-peak variation in output is 0.02 grams over the 500 codes.
Therefore, the weigh scale system achieves an accuracy of
0.02 grams.
CIRCUIT EVALUATION AND TEST LEARN MORE
With the exception of the external load cell and the PC, the CN0102 Design Support Package:
circuit shown in Figure 1 is contained on the AD7190 http://www.analog.com/CN0102-DesignSupport
evaluation board (EVAL-AD7190EBZ ). Kester, Walt. 1999. Sensor Signal Conditioning. Section 2.
Interface to the evaluation board via a standard USB connector, J1. Analog Devices.
J1 is used to connect the evaluation board to the USB port of a PC. Kester, Walt. 1999. Sensor Signal Conditioning. Section 3.
A standard USB connector cable is included with the AD7190 Analog Devices.
evaluation board to allow the evaluation board to interface with
the USB port of the PC. Because the board is powered via the Kester, Walt. 1999. Sensor Signal Conditioning. Section 4.
USB connector, there is no need for an external power supply, Analog Devices.
although if preferred, one may be connected via J2. MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of
Equipment Needed ADC Input Noise—Is No Noise Good Noise? Analog Devices.
The EVAL-AD7190EBZ evaluation board and a PC running MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC
Windows® 2000, Windows XP, or Windows Vista (32-bit) are Basics, Analog Devices.
the only items required other than the external load cell. A Tedea MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
Huntleigh 505H-0002-F070 load cell was used to obtain the Advanced Concepts and Applications, Analog Devices.
results presented. The load cell is not shipped with the evaluation MT-031 Tutorial, Grounding Data Converters and Solving the
board and must be purchased from the manufacturer by the
Mystery of "AGND" and "DGND", Analog Devices.
customer.
Getting Starting
The EVAL-AD7190EBZ evaluation board ships with a CD
containing software to control the AD7190 that can be installed AD7190 Data Sheet
onto a standard PC. The software communicates with the AD7190 AD7190 Evaluation Board (EVAL-AD7190EBZ)
through the USB cable that accompanies the board. The software AD7191 Data Sheet
allows the user to read conversion data from the AD7190. Data
can be read from the AD7190 and displayed or stored for later AD7192 Data Sheet
analysis. AD7780 Data Sheet
Install the AD7190 evaluation board software using the supplied AD7781 Data Sheet
AD7190 evaluation board CD before connecting the board to AD7798 Data Sheet
the PC. For full details on this, refer to the UG-222 User Guide.
AD7799 Data Sheet
Functional Block
ADP3303 Data Sheet
Figure 1 shows the basic functional block diagram of the test setup.
Setup and Test REVISION HISTORY
Complete instructions for setup and testing of the AD7190 12/12—Rev. 0 to Rev. A
evaluation board can be found in UG-222 User Guide. Added Evaluation and Design Support Section ............................1
Changes to Common Variations Section .......................................3
After installing the software, configure the AD7190 evaluation Added Circuit Evaluation and Test Section, Equipment Needed
board for use with the external load cell by setting the Section, Getting Started Section, Functional Block Section, and
appropriate links (jumpers) as described in Table 1 of the Setup and Test Section ......................................................................4
UG-222 User Guide. Ensure that the links are set before Changes to Learn More Section ......................................................4
applying power to the evaluation board.
The load cell connects to the evaluation board header, J4. 8/09—Revision 0: Initial Version
Operation of the WeighScale Demo is described in UG-222.

CN08370-0-12/12(A)
Circuit Note
CN-0107
Circuits from the Lab™ tested circuit designs address
Pin Programmable, Low Noise, Low Power
common design challenges and are engineered for AD7780
24-Bit Σ-Δ ADC with PGA
quick and easy system integration. For more information
and/or support, visit www.analog.com/CN0107. ADP3303 3.3 V Low Dropout Linear Regulator
Weigh Scale Design Using the AD7780 24-Bit Sigma-Delta ADC with Internal PGA
EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS
Circuit Evaluation Boards This circuit is a weigh scale system that uses the AD7780. The
AD7780 Evaluation Board (EVAL-AD7780EBZ) AD7780 is a pin programmable, low power, low drift 24-bit Σ-Δ
Design and Integration Files ADC that includes a PGA and uses an internal clock. Therefore,
Schematics, Layout Files, Bill of Materials the device simplifies the weigh scale design since most of the
system building blocks are included on the chip. The device
consumes only 330 µA typically and is, therefore, suitable for
any low power or battery application. The AD7780 also has a
power-down mode that allows the user to switch off the power
to the bridge sensor and power down the AD7780 when not
converting, thus increasing the battery life.
ADP3303 (3.3V) DVDD

IN OUT +
+5V FROM IN OUT FB: TYCO BMB2A1000LN2
USB SD NR 0.1µF 10µF
GND
+
10µF 0.1µF 100Ω @
100MHz 1.5Ω AVDD
EXTERNAL
POWER FB
SUPPLY 1µF 1µF
+
0.1µF 10µF
+
0.1µF 10µF
0.01µF AVDD DVDD
LOAD CELL: REFIN(+)
505H-0002-F070 REFIN(–)
0.01µF SCLK USB
SENSE+ MICRO-
DOUT/RDY
CONTROLLER
0.01µF PDRST
OUT– OUT+
AIN(+)
1kΩ
0.1µF AD7780 PC
AIN(–)
SENSE– 1kΩ
0.01µF FILTER
GAIN
BPDSW
GND
AVDD AVDD
1MΩ 1MΩ
08394-001
Rev. A
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause Tel: 781.329.4700 www.analog.com/circuits
whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
With a 4-wire load cell, the sense pins are not present, and the
ADC reference pins are connected to the excitation voltage and
ground. With this arrangement, the system is not completely
ratiometric because there will be a voltage drop between the
excitation voltage and SENSE+ due to wiring resistance. There
will also be a voltage drop due to wire resistance on the low side.
The AD7780 has separate analog and digital power supply pins.
The analog and digital power supplies are independent of each
other, so AVDD and DVDD can be at different potentials. The
microcontroller uses a 3.3 V power supply. Therefore, DVDD is
also powered from 3.3 V. This simplifies the interface between
the ADC and the microcontroller because no external level
shifting is required. The 3.3 V digital supply is generated using
the ADP3303 (3.3 V) regulator.
There are several methods to power the weigh scale system. It
can be powered from the main power supply bus or it can be
powered from the ADP3303 (3.3 V). When the weigh scale is
excited with 5 V, then the main power supply bus must be used.
When exciting the load cell with 3.3 V, the main power supply
bus or the ADP3303 (3.3 V) can be used. The ADP3303 (3.3 V)
is a low noise regulator. In addition, noise reduction capacitors
are placed on the regulator output as recommended in the
ADP3303 (3.3 V) data sheet. To optimize the EMC, the
regulator output is filtered before being supplied to the AD7780
08394-002
and the load cell. It is essential that any regulators used to

Figure 2. Weigh Scale System Setup Using the AD7780 generate the power supply to the AD7780 and the load cell
are low noise regulators, as any noise on the power supply or
ground planes will introduce noise into the system and degrade
CIRCUIT DESCRIPTION the circuit performance.
Since the AD7780 provides an integrated solution for weigh scales, If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-
it interfaces directly to the load cell. The only external components scale signal from the load cell is 10 mV when the excitation
required are some filters on the analog inputs and capacitors on the voltage is 5 V. A load cell has an offset, or TARE, associated with
reference pins for EMC purposes. The low level signal from the it. This TARE can have a magnitude that is up to 50% of the
load cell is amplified by the AD7780’s internal PGA. The PGA is load cell full-scale output signal. The load cell also has a gain
programmed to operate with a gain of 128. The conversions from error that can be up to ±20% of full scale. Some customers use a
the AD7780 are then sent to the PC using the USB interface where DAC to remove or null the TARE. When the AD7780 uses a 5 V
the digital information is converted to weight. reference, its analog input range is equal to ±40 mV when the
Figure 2 shows the actual test setup. A 6-wire load cell is used, gain is set to 128. The wide analog input range of the AD7780
as this gives the optimum system performance. A 6-wire load relative to the load cell full-scale signal (10 mV) is beneficial, as
cell has two sense pins, in addition to the excitation, ground, it ensures that the offset and gain error of the load cell do not
and two output connections. The sense pins are connected overload the ADC’s front end.
to the high side and low side of the Wheatstone bridge. The The AD7780 has an rms noise of 49 nV when the output data
voltage developed across the bridge can, therefore, be accurately rate is 10 Hz. The number of noise-free counts is equal to
measured regardless of the voltage drop due to the wiring 10 mV
resistance. In addition, the AD7780 has a differential analog = 30,920 (1)
6.6 × 49 nV
input, and it accepts a differential reference. Connection of
the load cell differential SENSE lines to the AD7780 reference where the factor of 6.6 converts the rms voltage into a peak-to-
inputs creates a ratiometric configuration that is immune to peak voltage.
low frequency changes in the power supply excitation voltage.
The resolution in grams is, therefore, equal to COMMON VARIATIONS

2 kg Note: The noise specifications given in this section are for a
= 0.07 g (2) PGA gain of 128.
30,920
The noise free resolution is equal to The AD7780 is a low noise, low power ADC for weigh scale
design. Other suitable ADCs are the AD7798 and AD7781. The
log 10 (30,920) AD7781 has the same feature set as the AD7780, but it is a
log 2 (30,920) = = 14.9 bits (3)
log 10 (2) 20-bit ADC. The AD7798 allows a wider selection of output
In practice, the load cell itself will introduce some noise. There data rates. At 4.17 Hz, its rms noise is 40 nV.
will also be some time and temperature drift of the load cell For medium-end weigh scales, the AD7799 is a suitable device.
along with the AD7780’s drift. To determine the accuracy of the At an output data rate of 4.17 Hz, the AD7799 has an rms noise
complete system, the weigh scale can be connected to the PC of 27 nV.
via the USB connector. Using LabView software, the perfor- For precision weigh scale design, the AD7190, AD7192, and
mance of the weigh scale system can be evaluated. Figure 3 AD7191 are suitable. The AD7190 has an rms noise of 8.5 nV
shows measured output performance when a 1 kg weight is when the output data rate is programmed to 4.7 Hz. It also
placed on the load cell and 500 conversions are gathered (5 V offers a wide range of output data rates. It can operate up to
excitation voltage used). The noise of the system is calculated by 4.8 kHz and still maintain good performance. The AD7192 is
the software to 50 nV rms. This equates to 30,300 noise-free pin-for-pin compatible with the AD7190. However, its rms
counts or 14.9 bits of noise-free code resolution. noise is slightly higher. The AD7192 has an rms noise of 11 nV
Figure 4 shows the performance in terms of weight. The peak- for an output data rate of 4.7 Hz. The AD7191 is a pin
to-peak variation in output is 0.075 grams over the 500 codes. programmable device. It has four output data rates and four
So, the weigh scale system achieves an accuracy of 0.075 grams. gain settings. Due to its pin programmability and reduced
The plots show the actual (raw) conversions being read back feature set, it is an easy to use device. Its rms noise is the same
from the AD7780 when the load cell is attached. In practice, a as the AD7192’s rms noise.
digital post filter is used in a weigh scale system. As with any high accuracy circuit, proper layout, grounding,
and decoupling techniques must be employed. See Tutorial
MT-031, Grounding Data Converters and Solving the Mystery of
AGND and DGND and Tutorial MT-101, Decoupling Techniques
for more details.
A complete design support documentation package for
this circuit note can be found at the following address:
08394-003
http://www.analog.com/CN0107-DesignSupport.
Figure 3. Measured Output Code for 500 Samples Showing
the Effects of Noise CIRCUIT EVALUATION AND TEST
With the exception of the external load cell and the PC, the
circuit of Figure 1 is contained on the AD7780 evaluation board
(EVAL-AD7780EBZ ).
Interface to the evaluation board via a standard USB connector,
J1. J1 is used to connect the evaluation board to the USB port of
a PC. A standard USB connector cable is included with the
AD7780 evaluation board to allow the evaluation board to
interface with the USB port of the PC. Because the board is
08394-004
powered via the USB connector, there is no need for an external

Figure 4. Measured Output in Kilograms for 500 Samples Showing power supply, although if preferred, one may be connected via J2.
the Effects of Noise Equipment Needed
The additional averaging that is performed in the post filter will The EVAL-AD7780EBZ evaluation board and a PC running
further improve the number of counts at the expense of a reduced Windows 2000, Windows XP, or Windows Vista (32-bit) are the
data rate. only items required other than the external load cell. A Tedea
Huntleigh 505H-0002-F070 load cell was used to obtain the
results presented in this circuit note. The load cell is not
shipped with the evaluation board and must be purchased
from the manufacturer by the customer.
Getting Starting LEARN MORE
The EVAL-AD7780EBZ evaluation board is shipped with a CD CN0107 Design Support Package:
containing software that can be installed onto a standard PC to http://www.analog.com/CN0107-DesignSupport
control the AD7780. The software communicates with the
Kester, Walt. 1999. Sensor Signal Conditioning, Analog Devices.
AD7780 through the USB cable, which accompanies the board.
Sections 2, 3, 4.
The software allows you to read conversion data from the
AD7780. Data can be read from the AD7780 and displayed or MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of
stored for later analysis. ADC Input Noise—Is No Noise Good Noise? Analog Devices.
Install the AD7780 evaluation board software using the MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC
supplied AD7780 evaluation board CD before connecting the Basics, Analog Devices.
board to the PC. Complete details can be found in UG-078. MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
Functional Block Advanced Concepts and Applications, Analog Devices.
Figure 1 shows the basic functional block diagram of the test MT-031 Tutorial, Grounding Data Converters and Solving the
setup. Mystery of "AGND" and "DGND", Analog Devices.
Setup and Test MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Complete instructions for setup and test of the AD7780 Data Sheets and Evaluation Boards
evaluation board can be found in user guide UG-078.
AD7780 Data Sheet
After installing the software, the AD7780 evaluation board
AD7780 Evaluation Board
should be configured for use with the external load cell
by setting the appropriate links (jumpers) as described in AD7781 Data Sheet
Table 1 of UG-078. Make sure the links are set before applying AD7190 Data Sheet
power to the evaluation board.
AD7191 Data Sheet
The load cell connects to the evaluation board header J4.
AD7192 Data Sheet
Operation of the Weighscale Demo is described in UG-078.
AD7780 Data Sheet
AD7798 Data Sheet
AD7799 Data Sheet
ADP3303 Data Sheet
REVISION HISTORY
Added Evaluation and Design Support Section ............................1
Changes to Circuit Description Section .........................................3
Added Circuit Evaluation and Test Section ...................................4
(Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may
use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of
the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties
Circuits from the Lab circuits at any time without notice but is under no obligation to do so.

CN08394-0-11/10(A)
Circuit Note
CN-0108
Circuits from the Lab™ tested circuit designs address
Pin Programmable, Low Noise, Low Power
20-Bit Σ-Δ ADC with PGA
and/or support, visit www.analog.com/CN0108. ADP3303 3.3 V Low Dropout Linear Regulator
Weigh Scale Design Using the AD7781 20-Bit Sigma-Delta ADC with Internal PGA
Circuit Evaluation Boards This circuit is a weigh scale system that uses the AD7781.
AD7781 Evaluation Board (EVAL-AD7781EBZ) The AD7781 is a pin programmable, low power, low drift 20-bit
Design and Integration Files Σ-Δ converter that includes a PGA and uses an internal clock.
Schematics, Layout Files, Bill of Materials Therefore, the device simplifies the weigh scale design since
most of the system building blocks are included on the chip.
The device consumes only 330 µA typically and is, therefore,
suitable for any low power or battery application. The AD7781
also has a power-down mode that allows the user to switch off
the power to the bridge sensor and power down the AD7781
when not converting, thus increasing the battery life.
ADP3303 (3.3V) DVDD

IN OUT +
+5V FROM IN OUT FB: TYCO BMB2A1000LN2
USB SD NR 0.1µF 10µF
GND
+
10µF 0.1µF 100Ω @
100MHz 1.5Ω AVDD
EXTERNAL FB
POWER 1µF
SUPPLY 1µF
+
0.1µF 10µF
+
0.1µF 10µF
0.01µF AVDD DVDD
LOAD CELL: REFIN(+)
505H-0002-F070 REFIN(–)
0.01µF SCLK USB
SENSE+ MICRO-
DOUT/RDY
CONTROLLER
0.01µF PDRST
OUT– OUT+
AIN(+)
1kΩ
0.1µF AD7781 PC
AIN(–)
SENSE– 1kΩ
0.01µF FILTER
GAIN
BPDSW
GND
AVDD AVDD
1MΩ 1MΩ
08395-001
Rev. A
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause Tel: 781.329.4700 www.analog.com/circuits
With a 4-wire load cell, the sense pins are not present, and the
ADC reference pins are connected to the excitation voltage and
ground. With this arrangement, the system is not completely
ratiometric because there will be a voltage drop between the
will also be a voltage drop due to wire resistance on the low side.
The AD7781 has separate analog and digital power supply pins.
The analog and digital power supplies are independent of each
other, so AVDD and DVDD can be at different potentials. The
microcontroller uses a 3.3 V power supply. Therefore, DVDD is
also powered from 3.3 V. This simplifies the interface between
the ADC and the microcontroller because no external level
shifting is required. The 3.3 V digital supply is generated using
the ADP3303 (3.3 V) regulator.
There are several methods to power the weigh scale system. It
can be powered from the main power supply bus or it can be
powered from the ADP3303 (3.3 V). When the weigh scale is
excited with 5 V, then the main power supply bus must be used.
When exciting the load cell with 3.3 V, the main power supply
bus or the ADP3303 (3.3 V) can be used. The ADP3303 (3.3 V)
is a low noise regulator. In addition, noise reduction capacitors
are placed on the regulator output as recommended in the
ADP3303 (3.3 V) data sheet. To optimize the EMC, the
regulator output is filtered before being supplied to the AD7781
08395-002
and the load cell. It is essential that any regulators used to

Figure 2. Weigh Scale System Using AD7781 generate the power supply to the AD7781 and the load cell are
low noise regulators, as any noise on the power supply or
CIRCUIT DESCRIPTION ground planes will introduce noise into the system and degrade
Since the AD7781 provides an integrated solution for weigh scales, the circuit performance.
it interfaces directly to the load cell. The only external components If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-
required are some filters on the analog inputs and capacitors on the scale signal from the load cell is 10 mV when the excitation
reference pins for EMC purposes. The low level signal from the voltage is 5 V. A load cell has an offset, or TARE, associated with
load cell is amplified by the AD7781’s internal PGA. The PGA is it. This TARE can have a magnitude that is up to 50% of the
programmed to operate with a gain of 128. The conversions from load cell full-scale output signal. The load cell also has a gain
the AD7781 are then sent to the PC using the USB interface where error that can be up to ±20% of full scale. Some customers use a
the digital information is converted to weight. DAC to remove or null the TARE. When the AD7781 uses a 5 V
Figure 2 shows the actual test setup. A 6-wire load cell is used, reference, its analog input range is equal to ±40 mV when the
as this gives the optimum system performance. A 6-wire load gain is set to 128. The wide analog input range of the AD7781
cell has two sense pins, in addition to the excitation, ground, relative to the load cell full-scale signal (10 mV) is beneficial, as
and two output connections. The sense pins are connected to it ensures that the offset and gain error of the load cell do not
the high side and low side of the Wheatstone bridge. The overload the ADC’s front-end.
voltage developed across the bridge can, therefore, be accurately The AD7781 (C grade) has an rms noise of 49 nV when the
measured regardless of the voltage drop due to the wiring output data rate is 10 Hz. The number of counts is equal to
resistance. In addition, the AD7781 has a differential analog
10 mV
input, and it accepts a differential reference. Connection of the = 30,920 (1)
load cell differential SENSE lines to the AD7781 reference 6.6 × 49 nV
inputs creates a ratiometric configuration that is immune to low where the factor of 6.6 converts the rms voltage into a peak-to-
frequency changes in the power supply excitation voltage. peak voltage.
The resolution in grams is COMMON VARIATIONS
2 kg Note: The noise specifications given in this section are for a
= 0.07g (2) PGA gain of 128.
30,920
The noise-free resolution is equal to The AD7781 is a low noise, low power ADC for weigh scale
design. Other suitable ADCs are the AD7798 and AD7780. The
log 10 (30,920) AD7780 has the same feature set as the AD7781, but it is a
log 2 (30,920) = = 14.9 bits (3)
log 10 (2) 24-bit ADC. The AD7798 allows a wider selection of output
In practice, the load cell itself will introduce some noise. There data rates. At 4.17 Hz, its rms noise is 40 nV.
will also be some time and temperature drift of the load cell For medium-end weigh scales, the AD7799 is a suitable device.
along with the AD7781’s drift. To determine the accuracy of the At an output data rate of 4.17 Hz, the AD7799 has an rms noise
complete system, the weigh scale can be connected to the PC of 27 nV.
via the USB connector. Using LabView software, the perfor-
For precision weigh scale design, the AD7190, AD7192, and
mance of the weigh scale system can be evaluated. Figure 3
AD7191 are suitable. The AD7190 has an rms noise of 8.5 nV
shows measured output performance when a 1 kg weight is
when the output data rate is programmed to 4.7 Hz. It also
placed on the load cell and 500 conversions are gathered (5 V
offers a wide range of output data rates. It can operate up to
excitation voltage used). The noise of the system is calculated by
4.8 kHz and still maintain good performance. The AD7192 is
the software to be 50 nV rms. This equates to 30,300 noise-free
pin-for-pin compatible with the AD7190. However, its rms
counts or 14.9 bits of noise-free code resolution.
noise is slightly higher. The AD7192 has an rms noise of 11 nV
Figure 4 shows the performance in terms of weight. The peak- for an output data rate of 4.7 Hz. The AD7191 is a pin
to-peak variation in output is 0.075 grams over the 500 codes. programmable device. It has four output data rates and four
So, the weigh scale system achieves an accuracy of 0.075 grams. gain settings. Due to its pin programmability and reduced
feature set, it is an easy to use device. Its rms noise is the same
as the AD7192’s rms noise.
As with any high accuracy circuit, proper layout, grounding,
for more details.
08395-003
A complete design support documentation package for

the Effects of Noise this circuit note can be found at the following address:
http://www.analog.com/CN0108-DesignSupport.
CIRCUIT EVALUATION AND TEST

With the exception of the external load cell and the PC, the
circuit of Figure 1 is contained on the AD7780 Evaluation
Board (EVAL-AD7781EBZ ).
Interface to the evaluation board via a standard USB connector,
J1. J1 is used to connect the evaluation board to the USB port of
08395-004
a PC. A standard USB connector cable is included with the

AD7781 evaluation board to allow the evaluation board to
Figure 4. Measured Output in Kilograms for 500 Samples Showing interface with the USB port of the PC. Because the board is
the Effects of Noise
powered via the USB connector, there is no need for an external
power supply, although if preferred, one may be connected via J2.
The plots show the actual (raw) conversions being read back Equipment Needed
from the AD7781 when the load cell is attached. In practice, a
The EVAL-AD7781EBZ evaluation board and a PC running
digital post filter is used in a weigh scale system. The additional
Windows 2000, Windows XP, or Windows Vista (32-bit) are the
averaging that is performed in the post filter will further im-
only items required other than the external load cell. A Tedea
prove the number of noise-free counts at the expense of a reduced
Huntleigh 505H-0002-F070 load cell was used to obtain the
data rate.
results presented in this circuit note. The load cell is not
shipped with the evaluation board and must be purchased
from the manufacturer by the customer.
Getting Starting
LEARN MORE
The EVAL-AD7781EBZ evaluation board is shipped with a CD
containing software that can be installed onto a standard PC to CN0108 Design Support Package:
control the AD7781. The software communicates with the http://www.analog.com/CN0108-DesignSupport
AD7781 through the USB cable, which accompanies the board. Kester, Walt. 1999. Sensor Signal Conditioning, Analog Devices.
The software allows you to read conversion data from the Sections 2, 3, 4.
AD7781. Data can be read from the AD7781 and displayed or
MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of
stored for later analysis.
ADC Input Noise—Is No Noise Good Noise? Analog Devices.
Install the AD7781 evaluation board software using the
MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC
supplied AD7781 evaluation board CD before connecting the
Basics, Analog Devices.
board to the PC. Complete details can be found in user guide
UG-079. MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
Advanced Concepts and Applications, Analog Devices.
Functional Block
Figure 1 of this circuit note shows the basic functional block
diagram of the test setup.
Setup and Test
Complete instructions for setup and test of the AD7781 Data Sheets and Evaluation Boards
evaluation board can be found in user guide UG-079. AD7190 Data Sheet
After installing the software, the AD7781 evaluation board AD7191 Data Sheet
should be configured for use with the external load cell by
AD7192 Data Sheet
setting the appropriate links (jumpers) as described in Table 1
of UG-079. Make sure the links are set before applying power to AD7780 Data Sheet
the evaluation board. AD7781 Data Sheet
The load cell connects to the evaluation board header J4. AD7781 Evaluation Board
Operation of the Weighscale Demo is described in UG-079.
AD7798 Data Sheet
AD7799 Data Sheet
ADP3303 Data Sheet
REVISION HISTORY
Added Evaluation and Design Support Section ............................1
Changes to Common Variations Section .......................................3
(Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may
use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of
the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties
Circuits from the Lab circuits at any time without notice but is under no obligation to do so.

CN08395-0-11/10(A)
Circuit Note
CN-0109
Circuit Designs Using Analog Devices Products AD9958/ 500 MSPS/1 GSPS Direct Digital
Apply these product pairings quickly and with confidence. AD9858 Synthesizer (DDS)
For more information and/or support call 1-800-AnalogD Clock Distribution IC and Pin Programmable
AD9515
(1-800-262-5643) or visit www.analog.com/circuit. Mini-Divider
AD6645 14-Bit, 80 MSPS/105 MSPS ADC
Low Jitter Sampling Clock Generator for High Performance ADCs Using the
AD9958/AD9858 500 MSPS/1 GSPS DDS and AD9515 Clock Distribution IC
CIRCUIT FUNCTION AND BENEFITS Wenzel crystal oscillator (www.wenzel.com). Data was taken on
This circuit uses a direct digital synthesizer (DDS) with sub- two different DDSes: the AD9958 (500 MSPS) and the
Hertz tuning resolution as a low jitter sampling clock source for AD9858 (1 GSPS).
high performance ADCs. The AD9515 clock distribution IC BPF AD6645
FFT
ANALYSIS
provides PECL logic levels to the ADC. However, the AD9515 WENZEL
ULN-SERIES
internal divider feature also allows the DDS to run at a higher CRYSTAL AIN = 170.3MHz
frequency into the AD9515 front end, effectively increasing OSCILLATOR
input slew rate. A higher slew rate into the AD9515 input
RECONSTRUCTION
squaring circuit can help reduce broadband jitter in the AD9958, AD9858 FILTER
clock path.
DDS LPF/BPF AD9515
Jitter on the ADC sampling clock produces degradation in the
DIFFERENTIAL PECL
overall signal-to-noise ratio (SNR). The relationship is given by
08396-001
ROHDE AND SCHWARZ SMA GENERATOR SAMPLING CLOCK
Equation 1. 500MHz AND 1GHz @ +6dBm
Figure 1. DDS-Based ADC Sampling Clock Generator

 1 
SNR = 20 log10   (1) (Simplified Diagram)
 2πft 
 j  By evaluating the contribution of the ADC’s differential non-
where f is the full-scale analog input frequency, and tj is the rms linearity and thermal noise and then applying the DDS-based
jitter. "SNR" in Equation 1 is the SNR due solely to clock jitter clock and measuring the ADC SNR, the added jitter attributable
and does not depend on the resolution of the ADC. to the DDS-based clock can be derived. For more details on the
measurement setup and the jitter calculations, refer to
The following data supports low jitter attainable from a DDS in Application Note AN-823. Also, Application Note AN-837 is
clocking applications. Further details on Equation 1 and its use instructive for designing DAC reconstruction filters with
for evaluating the jitter on ADC sampling clocks can be found optimal stop-band performance.
in Application Note AN-501.
Table 1 shows data for the AD9958 test results. The data
CIRCUIT DESCRIPTION confirms that better jitter performance is achieved as the
The circuit configuration in Figure 1 shows a DDS-based clock frequency, or slew rate, of the DDS output frequency is
generator, consisting of a DDS followed by a reconstruction increased and as the DDS output filter pass band is decreased.
filter and an AD9515 clock distribution IC, used to provide the Table 2 shows the AD9858 with a 5% band-pass filter, a
sampling clock for an analog-to-digital converter (ADC). The 225 MHz low-pass filter, and various levels of DDS output
DDS sampling clock is derived from a Rohde and Schwarz power. As expected, lower jitter is achieved as power is
SMA signal generator. The jitter measurement was made by increased and bandwidth reduced. With a 5% band-pass filter,
using the clock derived from the DDS and the AD9515 as the the majority of the spurs from the DAC are attenuated. The
sampling clock for the high performance AD6645 14-bit, jitter in this case is much more dependent on noise coupling
80 MSPS/105 MSPS ADC. The analog input signal for the ADC between the DAC output and the limiter input. This is proven
is a filtered 170.3 MHz sine wave derived from a low jitter by the strong correlation between jitter reduction and increased
Rev. 0
slew rate. Note that rms jitter values consistently less than 1 ps Data Converters and Solving the Mystery of AGND and DGND
can be achieved using the AD9858 circuit. and MT-101 Tutorial, Decoupling Techniques) in order to
These circuits must be constructed on multilayer PC boards achieve these performance levels. Consult the evaluation board
with large area ground planes using proper grounding, layout, documentation for the AD9958, AD9858, AD9515, and
and decoupling techniques (see MT-031 Tutorial, Grounding AD6645 for more guidance.
Table 1. Jitter Response of AD9958 and AD9515 vs. fOUT, Power, Frequency, and Filter BW
DDS DDS Output DDS Output DDS AD9515 AD9515 Output Jitter
Sample Frequency Power Reconstruction Divider Output Frequency (rms)
Product Rate (MHz) (MHz) (dBm) Filter (MHz) Setting (MHz) (ps)
AD9958/AD9515 500 38.88 −3.6 200 LPF 1 38.88 4.1
AD9958/AD9515 500 38.88 −3.6 200 LPF 2 19.44 4.1
AD9958/AD9515 500 38.88 −4.7 47 LPF 1 38.88 2.4
AD9958/AD9515 500 38.88 −4.7 47 LPF 2 19.44 2.4
AD9958/AD9515 500 38.88 −3.3 5% BPF 1 38.88 1.5
AD9958/AD9515 500 38.88 −3.3 5% BPF 2 19.44 1.5
AD9958/AD9515 500 77.76 −3.8 200 LPF 1 77.76 2.5
AD9958/AD9515 500 77.76 −3.8 200 LPF 2, 4 38.88, 19.44 2.5
AD9958/AD9515 500 77.76 −4.9 85 LPF 1 77.76 1.5
AD9958/AD9515 500 77.76 −4.9 85 LPF 2, 4 38.88, 19.44 1.5
AD9958/AD9515 500 77.76 −3.8 5% BPF 1 77.76 1.1
AD9958/AD9515 500 77.76 −3.8 5% BPF 2, 4 38.88, 19.44 1.1
AD9958/AD9515 500 155.52 −5.5 200 LPF 2 77.76 1.5
AD9958/AD9515 500 155.52 −5.5 200 LPF 4, 8 38.88, 19.44 1.5
AD9958/AD9515 500 155.52 −5.6 5% BPF 2 77.76 0.68
AD9958/AD9515 500 155.52 −5.6 5% BPF 4, 8 38.88, 19.44 0.68
Table 2. Jitter Response of AD9858 and AD9515 vs. fOUT, Power, Frequency, and Filter BW
DDS DDS Output DDS AD9515 Jitter
Sample Frequency DDS Output Reconstruction Divider Output AD9515 Output (rms)
Product Rate (MHz) (MHz) Power (dBm) Filter (MHz) Setting Frequency (MHz) (ps)
AD9858/AD9515 1000 155.52 +7.7 225 LPF 2 77.76 0.56
AD9858/AD9515 1000 155.52 +7.7 225 LPF 4,8 38.88, 19.44 0.56
AD9858/AD9515 1000 155.52 +7.7 5% BPF 2 77.76 0.33
AD9858/AD9515 1000 155.52 +7.7 5% BPF 4, 8 38.88, 19.44 0.33
AD9858/AD9515 1000 155.52 +2.6 225 LPF 2 77.76 0.63
AD9858/AD9515 1000 155.52 +2.6 225 LPF 4, 8 38.88, 19.44 0.63
AD9858/AD9515 1000 155.52 +1.1 5% BPF 2 77.76 0.42
AD9858/AD9515 1000 155.52 +1.1 5% BPF 4, 8 38.88, 19.44 0.42
AD9858/AD9515 1000 155.52 −3.2 225 LPF 2 77.76 0.73
AD9858/AD9515 1000 155.52 −3.2 225 LPF 4, 8 38.88, 19.44 0.73
AD9858/AD9515 1000 155.52 −4.6 5% BPF 2 77.76 0.64
AD9858/AD9515 1000 155.52 −4.6 5% BPF 4, 8 38.88, 19.44 0.64
COMMON VARIATIONS Data Sheets and Evaluation Boards
Analog Devices offers a variety of direct digital synthesizer, AD6645 Data Sheet.
clock distribution chips, and clock buffers to build a DDS-based AD9515 Data Sheet.
clock generator. Refer to www.analog.com/dds and
AD9858 Data Sheet.
www.analog.com/clock for more information.
AD9958 Data Sheet.
LEARN MORE AD6645 Evaluation Board.
AN-501 Application Note, Aperture Uncertainty and ADC AD9515 Evaluation Board.
System Performance. Analog Devices. AD9858 Evaluation Board.
AN-823 Application Note, Direct Digital Synthesizers in AD9958 Evaluation Board.
Clocking Applications. Analog Devices.
AN-837 Application Note, DDS-Based Clock Jitter Performance REVISION HISTORY
vs. DAC Reconstruction Filter Performance. Analog Devices.
Kester, Walt. 2005. The Data Conversion Handbook. Analog
Devices. Chapters 6 and 7.
Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 2, “Optimizing Data Converter Interfaces.”
Kester, Walt. 2006. High Speed System Applications. Analog
Devices. Chapter 3, “DACs, DDSs, PLLs, and Clock
Distribution.”

CN08396-0-7/09(0)
Circuit Note
CN-0112
10-Bit, 1% Resistor Tolerance Digital
Apply these product pairings quickly and with confidence. AD5292
Potentiometer
(1-800-262-5643) or visit www.analog.com/circuit. Rail-to-Rail Input and Output, Low Noise,
OP184
High Slew Rate Operational Amplifier
Variable Gain Noninverting Amplifier Using the AD5292 Digital

Potentiometer and the OP184 Op Amp

This circuit provides a low cost, high voltage, variable gain The circuit employs the AD5292 digital potentiometer in
noninverting amplifier using the AD5292 digital potentio- conjunction with the OP184 operational amplifier, providing
meter in conjunction with the OP184 operational amplifier. a low cost, variable gain noninverting amplifier.
The circuit offers 1024 different gains, controllable through an The input signal, VIN, is amplified by the OP184. The op amp offers
SPI-compatible serial digital interface. The ±1% resistor low noise, high slew rate, and rail-to-rail inputs and outputs.
tolerance performance of the AD5292 provides low gain error The maximum circuit gain is defined in Equation 1.
over the full resistor range, as shown in Figure 2.
The circuit supports rail-to-rail inputs and outputs for both R AB R
single-supply operation at +30 V and dual-supply operation at G = 1+ → R 2 = AB (1)
R2 G–1
±15 V, and is capable of delivering up to ±6.5 mA output current.
In addition, the AD5292 has an internal 20-times programma- The maximum current through the AD5292 is ±3 mA, which
ble memory that allows a customized gain setting at power-up. limits the maximum input voltage, VIN, based on the circuit gain
as described in Equation 2.
The circuit provides accuracy, low noise, and low THD and is
well suited for signal instrumentation conditioning.
VDD VIN ≤ 0.003 × R2 (2)
VIN
+15V/+30V
When the input signal connected to VIN is higher than the
V+
OP184 VOUT theoretical maximum value from Equation 2, R2 should be
V–
–15V/GND
increased, and the new gain can be recalculated using Equation 1.
R2
4.99kΩ ± 1%
C1 The ±1% internal resistor tolerance of the AD5292 ensures a low gain
VSS
10pF
error, as shown in Figure 2.
VDD RAW
The circuit gain equation is
+15V/+30V
RAB 20kΩ
AD5292 SERIAL (1024 – D )× R AB 1024

INTERFACE G = 1+ (3)
08426-001
VSS R2
–15V/GND
where D is the code loaded in the digital potentiometer.
Figure 1. Variable Gain NonInverting Amplifier Simplified Schematic

(Decoupling and All Connections Not Shown)
Rev. B
5 5 VDD
VIN
V+
4 4 OP184 VOUT
V–
GAIN
C1 VSS
3 3
ERROR (%)
10pF
GAIN
SERIAL
INTERFACE
2 2
RAB 20kΩ
GAIN
ERROR (%) AD5292
08426-004
1 1
D × RAB (1024 – D) × RAB
1024 1024
0 0
Figure 4. Logarithmic Gain Circuit
08426-002
0 200 400 600 800 1000
10k
CODE (Decimal)
Figure 2. Gain and Gain Error vs. Decimal Code
175 1k
20 PHASE, RAW = 10kΩ 150
PHASE, RAW = 20kΩ
125
10 PHASE, RAW = 100Ω
GAIN
GAIN, RAW = 20kΩ 100
100
0 75
GAIN, RAW = 10kΩ
PHASE (Degrees)
50
GAIN (dBV)
–10 25
GAIN, RAW = 100Ω
0 10
–20
–25
–30 –50
–75
–40 1
08426-005
–100 0 500 1000
–125 CODE (Decimal)
–50
–150
–175
Figure 5. Logarithmic Gain Function
–60
08426-003
600 1k 10k 100k 200k

The circuit gain is defined in Equation 4
FREQUENCY (Hz)
Figure 3. Gain and Phase vs. Frequency for AC Input Signal (1024 – D ) 1024
G = 1+ = (4)
D D
When the circuit input is an ac signal, the parasitic capacitances
of the digital potentiometer can cause undesirable oscillation in where D is the code loaded in the digital potentiometer. A gain
the output. This can be avoided, however, by connecting a small plot vs. code is shown in Figure 5.
capacitor, C1, between the inverter input and its output. A value The AD5292 has a 20-times programmable memory, which
of 10 pF was used for the gain and phase plots shown in Figure 3. allows presetting the output voltage in a specific value at power-up.
A simple modification of the circuit provides a logarithmic gain Excellent layout, grounding, and decoupling techniques must be
function, as shown in Figure 4. In this case, the digital utilized in order to achieve the desired performance from the
potentiometer is configured in the ratiometric mode. circuits discussed in this note (see Tutorial MT-031, Grounding
Data Converters and Solving the Mystery of AGND and DGND
and Tutorial MT-101, Decoupling Techniques). As a minimum, a
4-layer PCB should be used with one ground plane layer, one
power plane layer, and two signal layers.
COMMON VARIATIONS MT-091 Tutorial, Digital Potentiometers, Analog Devices.
The AD5291 (8 bits with 20-times programmable power-up MT-101 Tutorial, Decoupling Techniques, Analog Devices.
memory) and the AD5293 (10 bits with no power-up memory)
are both ±1% tolerance digital potentiometers that are suitable Data Sheets and Evaluation Boards
for this application. AD5291 Data Sheet.
AD5292 Data Sheet.
LEARN MORE AD5292 Evaluation Board.
MT-031 Tutorial, Grounding Data Converters and Solving the AD5293 Data Sheet.
Mystery of "AGND" and "DGND", Analog Devices. OP184 Data Sheet.
MT-032 Tutorial, Ideal Voltage Feedback (VFB) Op Amp, Analog
Devices. REVISION HISTORY
MT-087 Tutorial, Voltage References, Analog Devices. 3/10—Rev. A to Rev. B
Changes to Circuit Function and Benefits Section....................... 1
Corrected trademark ........................................................................ 1

CN08426-0-3/10(B)
Circuit Note
CN-0114
Circuit Designs Using Analog Devices Products Digital Potentiometer, 10 Bits, 1% Resistor
AD5292
Tolerance
For more information and/or support call 1-800-AnalogD AD8221 Precision Instrumentation Amplifier
Low Cost, High Voltage, Programmable Gain Instrumentation Amplifier Using the
AD5292 Digital Potentiometer and the AD8221 In-Amp
+IN
CIRCUIT FUNCTION AND BENEFITS VDD +VS
+15V/+30V
The circuit shown in Figure 1 provides a low cost, high voltage, +15V/+30V
SERIAL RAB
programmable gain instrumentation amplifier using the AD5292 INTERFACE 20kΩ RAW
AD8221 VOUT
digital potentiometer and the AD8221 instrumentation AD5292 VREF
amplifier. VSS
–15V/GND
08433-001
–15V/GND
The circuit offers 1,024 different gain settings, controllable –VS
–IN
through an SPI digital interface. The ±1% resistor tolerance
Figure 1. Programmable Gain Instrumentation Amplifier (Simplified
performance of the AD5292 provides low gain error over the Schematic: Decoupling and All Connections Not Shown)
full resistor range, as shown in Figure 2.
4
The circuit provides a high performance instrumentation
amplifier that delivers the industry’s highest CMRR over
frequency in its class and dynamic programmable gain for 3
both single supply operation at +30 V and dual supply
GAIN ERROR (%)
operation at ±15 V. In addition, the AD5292 has an internal

20-times programmable memory that allows the user to 2
customize the instrumentation amplifier gain at power-up.
The circuit provides accurate, low noise, high gain and is well
1
suited for signal instrumentation conditioning, precision data
acquisition, biomedical analysis, and aerospace instrumentation.
CIRCUIT DESCRIPTION 0
08433-002
0 250 500 750 1000
This circuit employs the AD5292 digital potentiometer in CODE (Decimal)
conjunction with the AD8221 instrumentation amplifier, Figure 2. Gain Error vs. Code
providing an overall low cost, high voltage, programmable gain
49.4 k 49.4 k (1)
instrumentation amplifier. G  1  1  500
R AB RAW _ MIN
The differential input signal, +IN and –IN, is amplified by the
AD8221. The instrumentation amplifier offers accuracy, low The circuit gain formula for any particular AD5292 resistance is
noise, high CMRR, and high slew rate. 49.4 k (2)
G  1
The maximum circuit gain is defined in Equation 1, where (1024  D)  RAB
1024
RAW_MIN is the wiper resistance of the AD5292 in the rheostat
mode and represents the minimum value of the gain-setting This equation is plotted in Figure 3 as a function of D, the
resistance (100 Ω). decimal code.
Rev. A
500
Equation 1 limits the maximum circuit gain to 500. Equation 2
can be solved for D, yielding Equation 4, which calculates the
400 minimum allowable resistance (in terms of the digital code) in
the AD5292 without exceeding the current limit.
300  49.4kΩ × 1024  (4)
D ≥ 1024 −  
GAIN
 R AB × (G − 1) 
200
where D is the code loaded in the digital potentiometer, and G
is the maximum gain calculated from Equation 3.
100
When the input to the circuit is an ac signal, the parasitic
capacitances in the digital potentiometer can cause a reduction
0 in the maximum AD8221 bandwidth. A gain and phase plot is
08433-003
0 500 1000
CODE (Decimal)
shown in Figure 5.
175
Figure 3. Gain vs. Decimal Code 20
GAIN, RAW = 100Ω GAIN, RAW = 10kΩ
150
GAIN, RAW = 4kΩ
The maximum current allowed through the AD5292 is ±3 mA, 10
125
which limits the allowable circuit gain as a function of differential 100

0 GAIN, RAW = 20kΩ PHASE, RAW = 100Ω 75
input voltage.
PHASE (Degrees)
PHASE, RAW = 4kΩ 50
GAIN (dBV)
Equation 3 shows the maximum gain limit as a function of the –10 25
differential input voltage, VIN. This equation is derived by –20

0
PHASE, RAW = 10kΩ –25
substituting RAB = VIN /3 mA into Equation 1. The equation is –50
–30 PHASE, RAW = 20kΩ
plotted in Figure 5. –75
–40 –100
148
G ≤ 1+ –125
VIN –50
(3) –150
–60 –175
500
08433-005
600 1k 10k 100k 200k
FREQUENCY (Hz)
400 Figure 5. Gain and Phase vs. Frequency (Vertical Scale Compressed to Show
All Gain Curves)
The AD5292 has a 20-times programmable memory, which

MAXIMUM GAIN
300
allows presetting the output voltage in a specific value at power-
up.
200
Excellent layout, grounding, and decoupling techniques must be
used to achieve the desired performance from the circuits
100
discussed in this note (see MT-031 Tutorial and MT-101
Tutorial). As a minimum, a 4-layer PCB should be used with
0 one ground plane layer, one power plane layer, and two signal
08433-004
0 10 20 30
DIFFERENTIAL INPUT VOLTAGE (V)
layers.
Figure 4. Allowable Gain vs. Differential Input Voltage COMMON VARIATIONS
The AD5291 (eight bits with 20-times programmable power-up
memory) and the AD5293 (10 bits, no power-up memory) are
both ±1% tolerance digital potentiometers that are suitable for
this application.
MT-031 Tutorial, Grounding Data Converters and Solving AD5292 Data Sheet.
the Mystery of "AGND" and "DGND." Analog Devices. AD5292 Evaluation Board.
MT-032 Tutorial, Ideal Voltage Feedback (VFB) Op Amp. AD8221 Data Sheet.
Analog Devices.
MT-061 Tutorial, Instrumentation Amplifier (In-Amp) Basics.
AD5291 Data Sheet.
Analog Devices.
AD5293 Data Sheet.
MT-087 Tutorial, Voltage References. Analog Devices.
MT-091 Tutorial, Digital Potentiometers. Analog Devices. REVISION HISTORY
MT-095 Tutorial, EMI, RFI, and Shielding Concepts. Analog
Changes to Circuit Function and Benefits Section....................... 1
Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices. 8/09—Revision 0: Initial Version
owners.

CN08433-0-3/10(A)
Circuit Note
CN-0118
4.8 kHz, Ultralow Noise, 24-Bit Σ-Δ
AD7191
Circuits from the Lab™ reference circuits are engineered and tested ADC
for quick and easy system integration to help solve today’s analog,
ADP3303 5 V Low Dropout Linear Regulator
mixed-signal, and RF design challenges. For more information
and/or support, visit www.analog.com/CN0118. 3.3 V Low Dropout Linear
ADP3303
Regulator
Precision Weigh Scale Design Using the AD7191 24-Bit Sigma-Delta ADC
with Internal PGA

This circuit is a weigh scale system that uses the AD7191. The Since the AD7191 provides an integrated solution for weigh
AD7191 is a pin programmable, low noise, low drift, 24-bit Σ-Δ scales, it interfaces directly to the load cell. The only external
converter that includes a PGA and uses an internal clock. components required are some filters on the analog inputs and
Therefore, the device simplifies the weigh scale design because capacitors on the reference pins for EMC purposes. The low
most of the system building blocks are included on chip. The level signal from the load cell is amplified by the AD7191’s
device has four output data rates and four gain settings that are PGA. The PGA is programmed to operate with a gain of 128.
selected using dedicated pins. This simplifies the interface to The conversions from the AD7191 are then sent to the
the ADC. microcontroller where the digital information is converted to
weight and displayed on the LCD.
ADP3303 (3.3V) DVDD
IN OUT
9V BATTERY +
IN OUT
SD NR 0.1µF 4.7µF
+
1N4148 GND
+
10µF 0.1µF FB: TYCO BMB2A1000L N2
ADP3303 (5V) 100Ω @

100MHz 1.5Ω AVDD
IN OUT
IN OUT FB
0.1µF 0.1µF
SD NR 0.1µF 4.7µF
+ GND
10µF 0.1µF
+ +
0.1µF 10µF
+ +
0.1µF 10µF
0.01µF AVDD DVDD
LOAD CELL: REFIN(+)
TEDEA HUNTLEIGH 1µF 100Ω
REFIN(–) DOUT/RDY USB
505H-0002-F070 0.01µF 100Ω MICRO-
SENSE+ SCLK
100Ω CONTROLLER
PDOWN LCD
0.01µF
OUT– OUT+ DVDD DRIVER
AIN3
100Ω 100kΩ
1µF
AIN4 AD7191 LCD
SENSE– 100Ω ODR2
0.01µF ODR1
PGA2
PGA1
BPDSW CHAN
DGND AGND
08473-001
Rev. A
dotted box ensures a low noise AVDD for the system. In
addition, noise reduction capacitors are placed on the regulator
output as recommended in the ADP3303 (5 V) data sheet. To
optimize the EMC performance, the regulator output is filtered
before being supplied to the AD7191 and the load cell. The
3.3 V digital supply is generated using the ADP3303 (3.3 V). It
is essential that low noise regulators are used to generate all the
power supply voltages to the AD7191 and the load cell, as any
noise on the power supply or ground planes will introduce
noise into the system and degrade the circuit performance.
If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-
scale signal from the load cell is 10 mV when the excitation
voltage is 5 V. A load cell has an offset or TARE associated with
it. This TARE can have a magnitude that is up to 50 % of the
load cell’s full-scale output signal. The load cell also has a gain
error that can be up to ±20% of full scale. Some customers use a
DAC to remove or null the TARE. When the AD7191 uses a 5 V
reference, its analog input range is equal to ±40 mV when the
gain is set to 128. The wide analog input range of the AD7191
08473-002
relative to the load cell full-scale signal (10 mV) is beneficial, as

it ensures that the offset and gain error of the load cell do not
Figure 2. Weigh Scale System Using the AD7191
overload the ADC’s front-end.
Figure 2 shows the actual test setup. A 6-wire load cell is used, as
this gives the optimum system performance. A 6-wire load cell The AD7191 has an rms noise of 15 nV when the output data
has two sense pins in addition to the excitation, ground, and two rate is 10 Hz. The number of noise-free counts is equal to
output connections. These sense pins are connected to the high 10 mV
= 101,000 (1)
side and low side of the Wheatstone bridge. The voltage 6.6 × 15 nV
developed across the bridge can, therefore, be accurately
measured. In addition, the AD7191 has differential analog where the factor of 6.6 converts the rms voltage to a peak-to-
inputs and accepts a differential reference. Connection of the peak voltage.
load cell differential SENSE lines to the AD7191 reference inputs The resolution in grams is, therefore, equal to
creates a ratiometric configuration that is immune to low 2 kg
frequency changes in the power supply excitation voltage. With a = 0.02 g (2)
101,000
4-wire load cell the sense pins are not present, and the ADC
reference pins are connected to the excitation voltage and and the noise-free code resolution is equal to
ground. With this arrangement, the system is not completely log10 (101,000 )
ratiometric because there will be a voltage drop between the log 2 (101,000 ) = = 16.6 bits (3)
log10 (2 )
will also be a voltage drop due to wire resistance on the low side. In practice, the load cell itself will introduce some noise. There
also will be some drift due to time and temperature due to the
The AD7191 has separate analog and digital power supplies.
load cell along with the AD7191’s drift. To determine the
The digital power supply is independent of the analog power
accuracy of the complete system, the weigh scale can be
supply, and it can equal any voltage between 2.7 V and 5.25 V.
connected to the PC via the USB connector. Using LabView
The microcontroller uses a 3.3 V power supply. Therefore,
software, the performance of the weigh scale system can be
DVDD is also powered from 3.3 V. This simplifies the interface
evaluated. Figure 3 shows the measured output performance
between the ADC and the microcontroller because no external
when a 1 kg weight is placed on the load cell and 500 conver-
level shifting is required.
sions are gathered. The noise of the system is calculated by the
There are several methods to power the weigh scale system. It software to be 17 nV rms and 98 nV peak-to-peak. This
can be powered from the mains power supply or battery equates to 102,000 noise-free counts or 16.6 bits of noise-free
powered (as shown in Figure 1). A 5 V low noise regulator is code resolution.
used to ensure that the AD7191 and the load cell receive a low
Figure 4 shows the performance in terms of weight. The peak-
noise supply. A low noise ADP3303 (5 V) regulator is used to
to-peak variation in output is 0.02 grams over the 500 codes.
generate the 5 V supply. The filter network shown inside the
Therefore, the weigh scale system achieves an accuracy of 0.02
grams.
pin-programmable, allowing an output data rate of 10 Hz and
17.6 Hz and a gain of 1 or 128. The rms noise is 44 nV when the
output data rate is 10 Hz.
08473-003
Figure 3. Measured Output Code for 500 Samples Showing for more details.
LEARN MORE
Kester, Walt. 1999. Sensor Signal Conditioning. Sections 2, 3, 4.
Analog Devices.
08473-004
Figure 4. Measured Output in Grams for 500 Samples Showing MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
the Effects of Noise Advanced Concepts and Applications, Analog Devices.
The plots show the actual conversions being read back from the
AD7191 when the load cell is attached. In practice, a digital post
filter is used in a weigh scale system. The additional averaging
that is performed in the post filter will further improve the MT-101 Tutorial, Decoupling Techniques, Analog Devices.
number of noise-free counts at the expense of a reduced data rate.
COMMON VARIATIONS AD7190 Data Sheet
Note: All noise specifications in this section are given for a PGA AD7191 Data Sheet
gain of 128.
The AD7191 is a pin-programmable ADC for high-end weigh
scales. Other suitable ADCs are the AD7190 and AD7192. The AD7192 Data Sheet
AD7190 has an rms noise of 8.5 nV when the output data rate is AD7780 Data Sheet
programmed to 4.7 Hz. It also offers a wide range of output data AD7781 Data Sheet
rates. It can operate up to 4.8 kHz and still maintain good
performance. The AD7192 is pin-for-pin compatible with the AD7798 Data Sheet
AD7190. However, its rms noise is slightly higher. The AD7192 AD7799 Data Sheet
has an rms noise of 11 nV for an output data rate of 4.7 Hz. ADP3303 Data Sheet
For medium-end weigh scales, the AD7799 is a suitable device.
At an output data rate of 4.17 Hz, the AD7799 has an rms noise REVISION HISTORY
of 27 nV.
Finally, for low-end weigh scales, the AD7798, AD7781 and
Changes to Circuit Description Section......................................... 3
AD7780 are suitable devices. The AD7798has the same feature
set as the AD7799. At 4.17 Hz, its rms noise is 40 nV. The 10/09—Revision 0: Initial Version
AD7780 and AD7781 have one differential analog input and are

CN08473-0-7/13(A)
Circuit Note
CN-0119
Circuits from the Lab™ reference circuits are engineered and 4.8 kHz, Ultralow Noise 24-Bit Σ-Δ ADC
tested for quick and easy system integration to help solve today’s AD7192
with PGA
information and/or support, visit www.analog.com/CN0119. ADP3303 5 V Low Dropout Linear Regulator
Precision Weigh Scale Design Using the AD7192

24-Bit Sigma-Delta ADC with Internal PGA

This circuit is a weigh scale system that uses the AD7192. The Since the AD7192 provides an integrated solution for weigh
AD7192 is an ultralow noise, low drift, 24-bit Σ-Δ converter scales, it interfaces directly to the load cell. The only external
that includes a PGA. Therefore, the device simplifies the weigh components required are some filters on the analog inputs and
scale design because most of the system building blocks are capacitors on the reference pins for EMC purposes. The low
included on chip. Since the part operates with an output data level signal from the load cell is amplified by the AD7192’s
rate from 4.7 Hz to 4.8 kHz and maintains good performance PGA. The PGA is programmed to operate with a gain of 128.
over the complete output data rate range, this allows the part to The conversions from the AD7192 are then sent to the
be used in weigh scale systems that operate at low speeds along microcontroller where the digital information is converted to
with higher speed weigh scale systems, such as hopper scales. weight and displayed on the LCD.
ADP3303 (3.3V) DVDD

IN OUT
9V BATTERY +
IN OUT
SD NR 0.1µF 4.7µF
+
1N4148 GND
+
10µF 0.1µF FB: TYCO BMB2A1000L N2
ADP3303 (5V) 100Ω @

100MHz 1.5Ω AVDD
IN OUT
IN OUT FB
0.1µF 0.1µF
SD NR 0.1µF 4.7µF
+ GND
10µF 0.1µF
+ +
0.1µF 10µF
+ +
0.1µF 10µF
0.01µF AVDD DVDD
LOAD CELL: REFIN(+)
TEDEA HUNTLEIGH 1µF
505H-0002-F070 REFIN(–) 100Ω
0.01µF DIN
SENSE+ 100Ω
DOUT/RDY
100Ω MICRO-
0.01µF SCLK USB
OUT– OUT+
AIN3 100Ω CONTROLLER
100Ω CS
1µF AD7192 100Ω
SYNC
AIN4
SENSE– 100Ω
0.01µF
LCD
BPDSW DRIVER
DGND AGND
08474-001
LCD
Rev. A
Figure 2 shows the actual test setup. A 6-wire load cell is used, noise supply. An ADP3303 (5 V) low noise regulator is used to
as this gives the optimum system performance. A 6-wire load generate the 5 V supply. The filter network shown inside the
cell has two sense pins, in addition to the excitation, ground, dotted box ensures a low noise AVDD for the system. In
and two output connections. These sense pins are connected to addition, noise reduction capacitors are placed on the regulator
the high side and low side of the Wheatstone bridge. The output as recommended in the ADP3303 (5 V) data sheet. To
voltage developed across the bridge can, therefore, be accurately optimize the EMC performance, the regulator output is filtered
measured. In addition, the AD7192 has differential analog before being supplied to the AD7192 and the load cell. The 3.3 V
inputs, and it accepts a differential reference. Connection of the digital supply is generated using the ADP3303 (3.3 V). It is
load cell differential SENSE lines to the AD7192 reference essential that low noise regulators are used to generate all the
inputs creates a ratiometric configuration that is immune to low power supply voltages to the AD7192 and the load cell, as any
frequency changes in the power supply excitation voltage. With noise on the power supply or ground planes will introduce
a 4-wire load cell, the sense pins are not present, and the ADC noise into the system and degrade the circuit performance.
reference pins are connected to the excitation voltage and If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-
ground. With this arrangement, the system is not completely scale signal from the load cell is 10 mV when the excitation
ratiometric because there will be a voltage drop between the voltage is 5 V. A load cell has an offset or TARE associated with
excitation voltage and SENSE+ due to wire resistance. There it. This TARE can have a magnitude that is up to 50% of the
will also be a voltage drop due to wire resistance on the load cell’s full-scale output signal. The load cell also has a gain
low side. error, which can be up to ±20% of full scale. Some customers
The AD7192 has separate analog and digital power supplies. use a DAC to remove or null the TARE. When the AD7192 uses
The digital power supply is independent of the analog power a 5 V reference, its analog input range is equal to ±40 mV when
supply and can equal any voltage between 2.7 V and 5.25 V. The the gain is set to 128 and the part is configured for bipolar
microcontroller uses a 3.3 V power supply. Therefore, DVDD is operation. The wide analog input range of the AD7192 relative
also powered from 3.3 V. This simplifies the interface between to the load cell’s full-scale signal (10 mV) is beneficial as it
the ADC and the microcontroller because no external level ensures that the offset and gain error of the load cell do not
shifting is required. overload the ADC’s front end.
There are several methods to power the weigh scale system. It The AD7192 has an rms noise of 11 nV when the output data
can be powered from the mains power supply or battery rate is 4.7 Hz. The number of noise-free counts is equal to
powered (as shown in Figure 1). A 5 V low noise regulator is
10 mV
used to ensure that the AD7192 and the load cell receive a low = 137,740 (1)
6.6 × 11 nV
where the factor of 6.6 converts the rms voltage into a peak-to-
peak voltage.
The resolution in grams is
2 kg
= 0.015 g (2)
137,740
The noise-free code resolution is equal to
log10 (137,740)
log 2 (137,740) = = 17 bits (3)
log10 (2)
In practice, the load cell itself will introduce some noise. There
will also will be some drift due to time and temperature of the
load cell along with the AD7192’s drift. To determine the
accuracy of the complete system, the weigh scale can be
connected to the PC via the USB connector. Using LabView
software, the performance of the weigh scale system can be
evaluated. Figure 4 shows the measured output performance
when a 1 kg weight is placed on the load cell and 500
08474-002
conversions are gathered. The noise of the system is calculated

by the software to be 14 nV and is 98 nV peak-to-peak. This
Figure 2. Weigh Scale System Using the AD7192
equates to 102,000 noise-free counts or 16.6 bits of noise-free
code resolution.
For medium-end weigh scales, the AD7799 is a suitable device.
At an output data rate of 4.17 Hz, the AD7799 has an rms noise
of 27 nV.
Finally, for low-end weigh scales, the AD7798, AD7781, and
AD7780 are suitable devices. The AD7798 has the same features
set as the AD7799. At 4.17 Hz, its rms noise is 40 nV. The
08474-003
AD7780 and AD7781 have one differential analog input and are
Figure 3. Measured Output Code for 500 Samples Showing pin programmable, allowing an output data rate of 10 Hz and
the Effects of Noise 17.6 Hz and a gain of 1 or 128. The rms noise is 44 nV when the
output data rate is 10 Hz.
and decoupling techniques must be employed. See Tutorial MT-
031, Grounding Data Converters and Solving the Mystery of
for more details.
08474-004 LEARN MORE
Figure 4. Measured Output Code for 500 Samples Showing Analog Devices.
Figure 4 shows the performance in terms of weight. The MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC
variation in output is 0.02 grams over the 500 codes. So, the Basics, Analog Devices.
weigh scale system achieves an accuracy of 0.02 grams.
MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
The plots show the actual conversions being read back from the Advanced Concepts and Applications, Analog Devices.
AD7192 when the load cell is attached. In practice, a digital post
filter is used in a weigh scale system. The additional averaging MT-031 Tutorial, Grounding Data Converters and Solving the
that is performed in the post filter will further improve the Mystery of "AGND" and "DGND", Analog Devices.
number of noise-free counts at the expense of a reduced MT-101 Tutorial, Decoupling Techniques, Analog Devices.
data rate.
COMMON VARIATIONS
AD7190 Data Sheet
Note: All noise specifications in this section are given for a PGA
gain of 128. AD7191 Data Sheet
The AD7192 is a high precision ADC for high-end weigh scales. AD7192 Data Sheet
Other suitable ADCs are the AD7190 and AD7191. The AD7192 Evaluation Board
AD7190 is pin-for-pin compatible with the AD7192. However, AD7780 Data Sheet
its rms noise is slightly lower. The AD7190 has an rms noise of
8.5 nV for an output data rate of 4.7 Hz while the AD7192 has AD7781 Data Sheet
an rms noise of 11 nV at this output data rate. The AD7191 is a AD7798 Data Sheet
pin programmable device. It has four output data rates and four AD7799 Data Sheet
gain settings. Due to its pin programmability and reduced
feature set, it is an easy to use device. Its rms noise is the same ADP3303 Data Sheet
as the AD7192’s rms noise.
REVISION HISTORY
Changes to Circuit Description Section ......................................... 3

CN08474-0-7/13(A)
Circuit Note
CN-0123
Circuit Designs Using Analog Devices Products AD5360 16-Channel, 16-Bit Voltage-Output DAC
Apply these product pairings quickly and with confidence. AD790 High Speed Precision Comparator
(1-800-262-5643) or visit www.analog.com/circuit. AD8597 Low Noise Amplifier
ADR435 5 V Ultralow Noise Voltage Reference
Automated Calibration Technique That Reduces the AD5360 16-Channel, 16-Bit DAC
Offset Voltage to Less Than 1 mV

The circuit described in this document and shown in Figure 1 The AD5360 is a 16 channel, 16-bit digital to analog converter.
provides a method of calibrating that removes an unknown The nominal output range is ±10 V when used with a 5 V
offset error. When using high precision, high resolution DACs reference. The AD5360 contains two offset DACs. Each offset
in industrial process control and instrumentation applications, DAC is connected to a group of eight DACs and is used to
low offset is often a critical specification. The circuit uses built- adjust the mid-scale point of the output span. For example, the
in features of the AD5360 in conjunction with an external offset DAC can be programmed to change the output span from
comparator and an operational amplifier to determine if the ±10 V to −8 V to +12 V, or other values as required by the
DAC output voltages are above or below a ground reference application.
signal. With the amount of offset known, the user can adjust the
codes sent to the DAC to null out the offset.
+15V –15V +5V
AD5360 VDD VSS DVCC
INPUT DAC 0
AND DAC 0 VOUT0
REGISTER
SPECIAL
FUNCTION
REGISTERS DAC 1
SERIAL DAC 1 VOUT1
INTERFACE REGISTER
GPIO
DAC 14 DAC 14 VOUT14
REGISTER
DAC 15 DAC 15 VOUT15

REGISTER
MUX
MON_OUT
VREF0 VREF1 GPIO AGND DGND
+5V
+5V
1kΩ +15V
+15V ADR435 +15V LATCH
+5V
510Ω
VLOGIC +VS
AD8597
AD790 100nF
–VS
–15V
08521-001
–15V
Figure 1. Autocalibration Circuit for AD5360 DAC That Reduces the Offset Voltage to Less Than 1 mV
(Simplified Schematic: Decoupling and All Connections Not Shown).
Rev.0
The AD5360 is factory trimmed to have a very low offset. The When comparator output trips back to the low state, SIGGND
trimming is done with the offset DAC at its default value, and is somewhere between those two codes. Due to the errors of the
the offset error due to the offset DAC is effectively removed. components used in the circuit, there is typically a span of three
When the value of the offset DAC is changed from its default or four codes between comparator trip points. There is no way
value, however, its offset error affects the offset error of the to determine exactly which code gives the lowest offset output
main DACs. using this method, but by picking a code that is the average of
The circuit described here allows for the offset error of the main the two trip point codes, the DAC channel offset is typically less
DACs to be measured and calibrated out under those conditions. than 1 mV from SIGGND.
The circuit relies on a general-purpose I/O pin and an on-chip Excellent layout, grounding, and decoupling techniques must be
monitor multiplexer. The GPIO (general-purpose I/O) pin is set used to achieve the desired performance from the circuits
as an input, and by reading the GPIO internal register, the logic discussed in this note (see MT-031 Tutorial and MT-101 Tutorial).
status of the GPIO pin is determined. The analog multiplexer is As a minimum, a 4-layer PCB should be used with one ground
programmable to connect any of the 16 DAC outputs to a single plane layer, one power plane layer, and two signal layers.
pin, the MON_OUT pin. The multiplexer switches have a low
but finite on resistance, RON so that any current drawn from COMMON VARIATIONS
MON_OUT creates a voltage drop across RON and, therefore, an The AD5362 is an 8-channel version of the AD5360. The AD5361
output error. To prevent this, MON_OUT is buffered by an and AD5363 are 14-bit versions of the AD5360 and AD5362,
AD8597 low-noise amplifier. The low pass filter following the respectively. The AD8599 is a dual version of the AD8597.
amplifier reduces the amount of noise seen by the AD790 high
The circuit described here can be used with any of the AD536x
speed precision comparator and prevents false triggering.
devices mentioned above. The reference can also be changed to
The AD790 can be operated on ±15 V supplies, making it give different output ranges if required.
compatible with the AD5360. The AD790 also requires an
additional +5 V VLOGIC supply when operating on ±15 V supplies.
LEARN MORE
In addition, the AD790 has a 15 V maximum differential input MT-031 Tutorial, Grounding Data Converters and Solving the
voltage; therefore, it can tolerate the output voltages from the Mystery of "AGND" and "DGND," Analog Devices.
AD5360 without attenuation. In Figure 1, the comparator output MT-083 Tutorial, Comparators, Analog Devices.
is low if the channel offset is positive, indicating that the output
voltage must be reduced to remove the offset. The comparator
output is high if the channel offset is negative, indicating that Data Sheets and Evaluation Boards
the output voltage must be increased to remove the offset. AD5360
To calibrate a DAC, the DAC channel is loaded with the digital AD5361
value, which should ideally provide a voltage equal to SIGGND
AD5362
(that is, 0 V). In this example the DAC channel is assumed to
have a negative offset. Reading the GPIO register shows that the AD5363
comparator output is low, indicating that the input must be AD5360, AD5361, AD5362, AD5363 Evaluation Board
incremented until the output toggles. As progressively higher
AD8597
codes are written to the DAC input register, the GPIO register is
read until the comparator trips to the high state. The AD790 has AD790
a maximum hysteresis band of 0.65 mV; therefore, reducing the ADR435
DAC code again allows a more accurate determination of the
REVISION HISTORY
DAC offset.
owners.

CN08521-0-9/09(0)
Circuit Note
CN-0131
Circuit Designs Using Analog Devices Products AD5360 16-Channel, 16-Bit Voltage Output DAC
For more information and/or support call 1-800-AnalogD ADR431/
2.5 V Ultralow Noise Voltage Reference
(1-800-262-5643) or visit www.analog.com/circuit. ADR421
ADR435 5 V Ultralow Noise Voltage Reference
16 Channels of Programmable Output Span Using the AD5360

16-Bit Voltage Output DAC
CIRCUIT FUNCTION AND BENEFITS AD5360 is four times the reference voltage, with the mid-scale
This circuit is a multichannel DAC configuration with different point at 0 V. The ADR431 and ADR421 are low noise precision
output spans on groups of channels. It utilizes the AD5360 to 2.5 V references. The ADR435 is a low noise precision 5 V
provide 16 DAC channels with 16 bits of resolution. The reference. When connected as shown in Figure 1, the AD5360
AD5360 is configured to have eight channels with an output will have an output span of ±5 V on VOUT0 to VOUT7 and an
span of ±10 V and eight channels with an output span of ±5 V. output span of ±10 V on VOUT8 to VOUT15. The AD5360 has
two offset DAC registers, which allow the mid-scale point of the
CIRCUIT DESCRIPTION span to be altered within the limits of part functionality and
The AD5360 is a 16-channel, 16-bit DAC available both in headroom.
56-lead LFCSP and 52-lead LQFP packages. The AD5360 has The circuit must be constructed on a multilayer PC board with
two reference input pins. VREF0 is the reference pin for DAC a large area ground plane. Proper layout, grounding, and
channels VOUT0 to VOUT7. VREF1 is the reference pin for decoupling techniques must be used to achieve optimum
DAC channels VOUT8 to VOUT15. performance (see Tutorial MT-031 and Tutorial MT-101).
Figure 1 shows a typical configuration for the AD5360 using
two external references. The nominal output span for the
15V 5V
0.1µF
10µF 0.1µF
2.5V
ADR431/
ADR421
VDD DVCC
VREF0
0.1µF VOUT0
±5V
5V VOUT7
ADR435 AD5360
VOUT8
±10V
VREF1
VOUT15
0.1µF
VSS SIGGND AGND DGND
0.1µF
10µF
08609-001
–15V
Figure 1. 16 Channels of Programmable Output Voltage Span Using the AD5360 DAC (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. 0
COMMON VARIATIONS Data Sheets and Evaluation Boards
The AD5362 is an 8-channel version of the AD5360. The AD5360 Data Sheet
AD5361 and AD5363 are 14-bit versions of the AD5360 and
AD5362, respectively.
AD5361 Data Sheet
The circuit described here can be used with any of the AD536x
devices mentioned above. The references can also be changed to AD5362 Data Sheet
give different output ranges if required. AD5363 Data Sheet
ADR421 Data Sheet
LEARN MORE
ADR431 Data Sheet
Kester, Walt. The Data Conversion Handbook. Chapter 3, 7.
ADR435 Data Sheet
Analog Devices. 2005.
Analog Devices.
REVISION HISTORY
Voltage Reference Wizard Design Tool. Analog Devices.

CN08609-0-10/09(0)
Circuit Note
CN-0133
3-Axis, ±2 g/±4 g/±8 g/±16 g Digital
Apply these product pairings quickly and with confidence. ADXL345
Accelerometer
(1-800-262-5643) or visit www.analog.com/circuit. Precision Analog Microcontroller, 12-Bit
ADuC7024
Analog I/O, ARM7TDMI® MCU
Sensing Low-g Acceleration Using the ADXL345 Digital Accelerometer Connected

to the ADuC7024 Precision Analog Microcontroller
CIRCUIT FUNCTION AND BENEFITS estate. Additionally, the ADXL345 includes a variety of built-in
The ADXL345 is a small, thin, low power, 3-axis accelerometer features. Activity/inactivity detection, tap/double-tap detection,
with high resolution (13-bit) measurement up to ±16 g. Digital and free-fall detection are all done internally with no need for
output data is formatted as 16-bit twos complement and is the host processor to perform any calculations. A built-in
accessible through either an SPI (3- or 4-wire) or I2C digital 32-stage FIFO memory buffer reduces the burden on the host
interface. processor, allowing algorithm simplification and power savings.
Additional system level power savings can be implemented
The ADXL345 is well suited for mobile device applications. It using the built-in activity/inactivity detection and by using the
measures the static acceleration of gravity in tilt-sensing appli- ADXL345 as a “motion switch” to turn the whole system off
cations, as well as dynamic acceleration resulting from motion when no activity is felt and on when activity is sensed again.
or shock. Its high resolution (4 mg/LSB) enables measurement
of inclination changes of about 0.25°. Using a digital output The ADXL345 communicates via I2C or SPI interface. The
accelerometer such as the ADXL345 eliminates the need for circuits described in this document demonstrate how to
analog-to-digital conversion, reducing system cost and real implement communication via these protocols.
VSUP
C3
0.47µF
VSUP
60 59 42 56 55 20 21
IOVDD
IOVDD
AVDD
VREF
DACVDD
DACREF
LVDD
VSUP 1 6
48 7 VDD I/O VS
P1.2/SPM2/PLAI(2) CS
UART
47 14
P1.3/SPM3/PLAI(3) SCL
1
46 13 11
50 P1.4/SPM4/PLAI(4)/IRQ2 SDA RES
2 P1.0/T1/SPM0/PLAI(0) 12 ADXL345
45 10
49 P1.5/SPM5/PLAI(5)/IRQ3 SDO NC
3 P1.1/SPM1/PLAI(1) 3
RES
4 31 8
IRQ0/P0.4/PWMTRIP/PLAO(1) INT1
32 9
IRQ1/P0.5/ADCBUSY/PLAO(2) INT2 GND GND GND
VSUP 2 4 5
ADuC7024
SW2 R1 R2
1kΩ 1kΩ
GND 28
RST GND
DACGND
GNDREF
15 SW1 VSUP
IOGND
IOGND
BM/P0.0/CMPOUT/PLAI(7)
DGND
AGND
SW3
+ C1 C2
1.8V–3.2V
2AAA 10µF 0.1µF
19 22 7 57 58 41
08654-001
Figure 1. ADXL345 and ADuC7024 in 4-Wire SPI Configuration (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. 0
Devices be liable for direct, indirect, special, incidental, consequential, or punitive damages due to Tel: 781.329.4700 www.analog.com
VSUP
C3
0.47µF
VSUP
60 59 42 56 55 20 21
IOVDD
IOVDD
AVDD
VREF
DACVDD
DACREF
VSUP
R3 R4 1 6
10kΩ 10kΩ
UART 7 VDD I/O VS
CS
1 48 14
P1.2/SPM2/PLAI(2) SCLK
50
2 P1.0/T1/SPM0/PLAI(0) 47 13 ADXL345 11
P1.3/SPM3/PLAI(3) SDIO RES
49
3 P1.1/SPM1/PLAI(1) 12 10
ALT ADDRESS NC
4 3
RES
31 8
IRQ0/P0.4/PWMTRIP/PLAO(1) INT1
32 9
IRQ1/P0.5/ADCBUSY/PLAO(2) INT2 GND GND GND
VSUP
ADuC7024 2 4 5
SW2 R1 R2
1kΩ 1kΩ
GND 28
RST GND
DACGND
15
GNDREF SW1 VSUP
IOGND
IOGND
BM/P0.0/CMPOUT/PLAI(7)
DGND
AGND
SW3
+ C1 C2
1.8V–3.2V
2AAA 10µF 0.1µF
19 22 7 57 58 41
08654-002
Figure 2. ADXL345 and ADuC7024 in I2C Configuration (Simplified Schematic: Decoupling and All Connections Not Shown)
CIRCUIT DESCRIPTION COMMON VARIATIONS

This circuit uses an ADuC7024 precision analog microcon- Figure 1 shows the ADXL345 in a 4-wire SPI configuration.
troller in conjunction with the ADXL345 digital accelerometer. The ADXL345 can also communicate via 3-wire SPI. Figure 3
Both are I2C- and SPI-ready. Figure 1 shows the ADXL345 and outlines this configuration.
ADuC7024 in an SPI configuration, and Figure 2 shows the
same devices in an I2C configuration. The CS pin (Pin 7 on the ADXL345 PROCESSOR
ADXL345) is used to select the desired interface. I2C mode is CS D OUT
enabled if the CS pin is tied high to VDD I/O. In SPI mode, CS is SDIO D IN/OUT
toggled to signify the beginning and end of each transmission. SDO
08654-003
When CS is pulled high, this indicates that no SPI transmission SCLK D OUT
is occurring or that an I2C transmission may occur.
Figure 3. 3-Wire SPI Connection Diagram
Both schematics are simplified, but required connections
(supplies, ground connections, etc.) are shown. In these The circuit described uses the ADuC7024 microcontroller. The
schematics, the ADuC7024 is programmed via UART same configuration can be applied with any SPI- or I2C-capable
(connected to Pin 49 and Pin 50). SW2 and SW3 are Reset microcontroller, as outlined in the diagrams in Figure 4. The
and Download buttons, respectively, for programming the standard I2C and SPI connections are used. Pin functions for
microcontroller. SW1 is an on/off power switch. the two protocols are listed in Table 1.
Table 1. ADXL345 Pin Functionality in SPI and I2C Communication Modes

Functionality
ADXL345 Pin Number Pin Name I2C SPI
7 CS (Connect to VDD for I2C) Chip Select
12 SDO/ALT ADDRESS Alternate Address Select Serial Data Output
Serial Data Input (SPI 4-Wire)/
13 SDA/SDI/SDIO Serial Data Serial Data Input and Output (SPI 2-Wire)
14 SCL/SCLK Serial Communications Clock Serial Communications Clock
VDD I/O
ADXL345 PROCESSOR ADXL345 RP RP PROCESSOR
CS D OUT CS
SDI D OUT SDA D IN/OUT
SDO D IN ALT ADDRESS
SCLK D OUT SCL D OUT
08654-004
Figure 4. SPI (left) and I2C (right) Connection Diagrams
LEARN MORE
This circuit is used in the ADXL345 Development Board
(model number EVAL-ADXL345Z-DB). For information on
ADXL345 operation and register functions, please refer to the
ADXL345 data sheet.
For information on programming the ADuC7024, please see
the ADuC7024 data sheet. Sample code for the I2C configuration
shown in Figure 2 is available at www.analog.com/static/
imported-files/circuit_notes/CN0133_Source_Code.zip.
ADXL345 Data Sheet
ADXL345 Evaluation Tools
ADuC7024 Data Sheet
ADuC7024 Evaluation Tools
REVISION HISTORY

CN08654-0-10/09(0)
Circuit Note
CN-0140
1.2 GHz to 2.5 GHz, Dual-Balanced Mixer,
Circuit Designs Using Analog Devices Products ADL5356
LO Buffer, IF Amplifier, and RF Balun
Apply these product pairings quickly and with confidence. AD8376 Ultralow Distortion IF Dual VGA
(1-800-262-5643) or visit www.analog.com/circuit. AD9258 14-Bit, 125 MSPS, 1.8 V Dual ADC
12-Output Clock Generator with
AD9517-4
Integrated 1.6 GHz VCO
High Performance, Dual Channel IF Sampling Receiver

This circuit is a high performance, dual channel IF sampling This circuit includes the RF front end, as well as the IF sampling
receiver, also called a “main” and “diversity” receiver in receiver. It is composed of a dual balanced mixer, broadband IF
base station terminology. The downconverting receiver uses SAW filter, digitally controlled dual VGA, and dual ADC. The
a single IF frequency of 153.6 MHz and includes a dual circuit also includes a synthesizer, which generates the ADC
downconverting mixer, digitally controlled dual VGA, dual sampling clock.
ADC, and clock synthesizer. The circuit takes an incoming The ADL5356 dual balanced mixer is designed to downconvert
RF waveform and outputs a dual 14-bit resolution digital data radio frequencies (RF) primarily between 1200 MHz and
stream. It is optimized for high frequency IF sampling and 2500 MHz to lower intermediate frequencies (IF) between
provides exceptional spurious-free dynamic range (SFDR) 30 MHz and 450 MHz.
performance of 79.61 dBc with a sampling rate of 122.88 MSPS
at the high gain setting.
5V
1.8V 1.8V
EPCOS 5V AVDD DVDD
B5206 1µH
18pF SAW FILTER 18pF 470pF 330nH 330nH 33Ω
14
1/2 CML
165Ω 1/2
153.6MHz 72nH 58nH AD8376 309Ω 3.3pF 20pF 56nH AD9258
165Ω
18pF FC = 153.6MHz 18pF 330nH 330nH 33Ω CML CLK+

5 470pF CLK–
BW = 20MHz 1µH
5V 5V
A0 TO 3V 122.88MHz
330nH 330nH A4 5V
390Ω AD9517-4
1.21kΩ 5V 0.1µF 0.1µF 0.1µF
1:1
REFIN OUT0
GM ON OP LG 50Ω 57.6Ω REFIN 200Ω
22pF
IN 22pF REF IN 0.1µF
LOI2 200Ω
30.72MHz CP
OUT0
50Ω 50Ω
BYPASS LF
0.1µF
RF IN LO IN 1.5kΩ
1950MHz 1796.4MHz
LOSW 470pF 430Ω
CT 100pF
1/2 10nF
ADL5356
10nF 10pF 0.22µF
NOTES
08713-001
1. ALL PINS AND CONNECTIONS TO ADL5356, AD8376, AD9258 AND AD9417 NOT SHOWN.
CONSULT PRODUCT DATA SHEETS FOR DETAILED INFORMATION.
Figure 1. Broadband Dual Channel IF Sampling Receiver (Simplified Schematic: Only One-Half of the Receiver Is Shown. All Connections and Decoupling Not Shown)
Rev. 0
The RF and LO input ports are already ac-coupled to prevent provide bias to the open-collector output pins. An optimized
nonzero dc voltages from damaging the RF balun or LO input differential fourth order band-pass antialiasing filter is
circuits, which are part of the ADL5356. The ADL5356 is implemented at the DGA outputs before analog-to-digital
configured for single-ended LO operation with a recommended conversion. Note that the antialiasing filter is terminated with
LO drive of 0 dBm. With the LOSW pin of the mixer grounded, shunt input and output resistances of about 300 Ω. The shunt
only one of the two LO channels (LOI2) is used in this circuit. resistances at either end of the filter, 309 Ω at the input and
The mixer differential IF interface requires pull-up choke 330 Ω (through two 165 Ω bias setting resistors) at the output,
inductors to bias the open-collector outputs and to set the combine to present the AD8376 with a nominal 150 Ω load
output impedance match. The shunting impedance of the choke impedance.
inductors used to couple dc current into the IF amplifier should The band-pass antialiasing attenuates the output noise of the
be selected to provide the desired output return loss. The real AD8376 outside of the intended Nyquist zone. In general, the
part of the mixer output impedance is approximately 200 Ω, SNR improves several dB by including a reasonable order
which matches many commonly used SAW filters without the antialiasing filter. The antialiasing filter is comprised of a fourth
need for a transformer. order Butterworth filter with a resonant tank circuit. The
The receiver channel filtering is mainly performed by a resonant tank helps ensure that the ADC input looks like a real
153.6 MHz, 20 MHz bandwidth Epcos model B5206 SAW filter resistance at the target center frequency by resonating out the
which follows the mixer. The typical insertion loss (IL) of this capacitive portion of the ADC load (see AN-742 and AN-827
filter is about 9 dB. The natural matched impedance of this application notes). In addition, the ac-coupling capacitors and
SAW filter is 100 Ω differential. A simple L-C reactive network the bias chokes introduce additional zeros into the transfer
matches the SAW filter to the mixer 200 Ω differential output function. The overall frequency response takes on a band-pass
and the AD8376 VGA 150 Ω differential input impedance. characteristic, helping to reject noise outside of the intended
Nyquist zone. The filter provides a 20 MHz pass band centered
Table 1 highlights the cascaded performance of the dual mixer at 153.6 MHz with 0.3 dB flatness and an insertion loss of
plus SAW filter. Note that IP3 is the third-order intercept point; about 3 dB.
IP1dB is the input referred −1 dB compression point; and NF is
the noise figure. The ADC utilized is the 14-bit AD9258, which samples at rates
up to 125 MSPS. The AD9258’s analog inputs are driven by the
A receiver gain control of 24 dB is provided by the AD8376 AD8376 through the band-pass antialiasing filter. The ADC
dual, high output linearity VGA that is optimized for ADC sampling rate is set to 122.88 MSPS with a full-scale input range
interfacing. Two independent 5-bit binary codes change each of 2 V p-p. The AD9258 differential clock signal is provided by
attenuator setting in 1 dB steps such that the gain of each the AD9517-4, a clock generation IC with on-chip VCO. The
amplifier can be set from +20 dB to −4 dB. The output third LVPECL level output, OUT0, is used for low jitter. The
order intercept point ( IP3) and noise floor essentially remain AD9517-4 uses its internal VCO frequency of 1474.56 MHz to
constant across the 24 dB available gain range. This is a valuable derive the 122.88 MHz output clock to the ADC. A loop filter,
feature in a variable gain receiver where it is desirable to
designed with the ADISimCLK simulation software, provides
maintain a constant instantaneous dynamic range as the
a 60 kHz cutoff frequency and 50° of phase margin, giving
receiver gain is modified. The output IP3 of the AD8376 and
timing jitter of about 160 fs rms. This jitter corresponds to a
the subsequent antialiasing filter is in excess of 50 dBm with a
theoretical SNR of 76 dB, assuming a 153.6 MHz input, using
2 V p-p composite signal.
the formula SNR = 20 log(1/2π × fIN × tj).
The AD8376 provides a 150 Ω input impedance and is tuned to
Using this circuit, exceptional SFDR performance of
drive a 150 Ω load impedance. The open-collector output
79.61 dBc at 153.6 MHz is achieved at maximum gain,
structure requires dc bias through an external bias network. A
as shown in Figure 2.
set of 1 μH choke inductors are used on each channel output to
Table 1. Cascaded performance of the dual mixer plus SAW filter (RF =1950 MHz, LO = 1796.4 MHz, IF = 153.6 MHz,
RF power = −10 dBm, LO power = 0 dBm)
Gain (dB) IP3 (dBm) IP1dB (dBm) NF (dB)
ADL5356 8.2 30.0 11.5 9.7
ADL5356 + SAW −0.3 28.6 11.7 10.9
08713-002
Figure 2. Measured Single-Tone Performance of the Circuit in Figure 1 for a 1950 MHz RF Input Signal. Sampling Frequency = 122.88 MSPS, IF Input = 153.6 MHz
COMMON VARIATIONS
Front-end LNAs and attenuators are not included in this circuit Excellent layout, grounding, and decoupling techniques must be
but can easily be interfaced to the 50 Ω single-ended RF inputs utilized in order to achieve the desired performance from the
of the ADL5356 mixer. For a complete receiver design, circuits discussed in this note. As a minimum, a 4-layer PCB
ADL5521/ADL5523 LNAs may be incorporated. should be used with one ground plane layer, one power plane
The standard configuration using the ADL5356 allows layer, and two signal layers.
reception of RF signals from 1.2 GHz to 2.4 GHz, but it is All IC power pins must be decoupled to the ground plane with
possible to use the ADL5358 mixer, which covers RF input low inductance multilayer ceramic capacitors (MLCC) of
frequencies from 500 MHz to 1700 MHz. 0.01 μF to 0.1 μF (for simplicity, not shown in the diagrams).
An Epcos (www.epcos.com) SAW filter follows the mixer and Follow the recommendations on the individual data sheets and
provides the necessary channel selectivity over a bandwidth in Tutorial MT-101.
ranging from 20 MHz to 40 MHz, depending on the chosen The product evaluation boards should be consulted for
filter. The circuit shown uses a 20 MHz bandwidth, 153.6 MHz recommended layout and critical component placement. These
centered SAW filter (part number: B5206) but can also can be accessed through the product pages for the devices.
accommodate other pin-compatible filters. Even though the AD8376 and AD9258 (or other ADC) may be
Some empirical optimization may be needed to help powered from different supplies, sequencing is not an issue
compensate for actual PCB parasitics in SAW filter matching because the input signal to the ADC is ac-coupled.
and antialias filter implementation. Details of designing the The individual data sheet for the ADC should be consulted
interstage filters can be found in the AN-742 and AN-827 regarding the proper sequencing of the AVDD and the DVDD
application notes. power supplies (if separate supplies are used).
To ensure repeatability of band response, 1% capacitors are
recommended for the SAW filter matching components and the
antialiasing filter. In addition, Coilcraft 0603CS or similar
inductors are recommended. Other resistors, capacitors, and
inductors can be 10% values.
AN-742 Application Note. Frequency Domain Response of AD8376 Data Sheet
Switched Capacitor ADCs. Analog Devices. AD9258 Data Sheet
AN-827 Application Note. A Resonant Approach to Interfacing
Amplifiers to Switched-Capacitor ADCs. Analog Devices.
AD9517-4 Data Sheet
CN-0002 Circuit Note, Using the AD8376 VGA to Drive Wide
Bandwidth ADCs for High IF AC-Coupled Applications, AD9517-4 Evaluation Board
Analog Devices. ADL5356 Data Sheet
CN-0046 Circuit Note, An Ultra Low Distortion Differential ADL5356 Evaluation Board
RF/IF Front-End for High Speed ADCs, Analog Devices.
Kester, Walt. High Speed System Applications, Chapter 2 REVISION HISTORY
“Optimizing Data Converter Interfaces,” Analog Devices, 1/10—Revision 0: Initial Version
2006.
MT-007 Tutorial, Aperture Time, Aperture Jitter, Aperture Delay
Time—Removing the Confusion, Analog Devices.
MT-073 Tutorial, High Speed Variable Gain Amplifiers (VGAs),
Analog Devices.
MT-075 Tutorial, Differential Drivers for High Speed ADCs
Overview, Analog Devices.

CN08713-0-1/10(0)
Circuit Note
CN-0155
Circuits from the Lab™ tested circuit designs address 4.8 kHz, Ultralow Noise, 24-Bit Σ-Δ ADC
with PGA and AC Excitation
and/or support, visit www.analog.com/CN0155. ADP3303 5 V Low Dropout Linear Regulator
Precision Weigh Scale Design Using a 24-Bit Sigma-Delta ADC

with Internal PGA and AC Excitation
Circuit Evaluation Boards This circuit is an ac excited weigh scale system that uses the
AD7195 Evaluation Board (EVAL-AD7195EBZ) AD7195, an ultralow noise, low drift, 24-bit Σ-Δ ADC with
Design and Integration Files internal PGA and drivers to implement ac excitation of the
Schematics, Layout Files, Bill of Materials load cell.
ADP3303-3.3V DVDD
IN OUT
9V BATTERY IN OUT 0.1µF 4.7µF
SD NR
+
BAT721C 10µF GND
0.1µF FB: TYCO BMB2A1000LN2
ADP3303-5V 100Ω @ AVDD

100MHz
IN OUT
+ 1.5Ω
IN OUT 0.1µF 4.7µF
10µF 0.1µF 0.1µF 0.1µF
SD NR
GND
1MΩ + +
0.1µF 10µF
+ +
0.1µF 10µF
AVDD DVDD
ACX2
NPX BSH201 1MΩ ACX1
SENSE+ 0.01µF
REFIN1(+)
1µF
DIN
REFIN1(–) 100Ω
OUT– OUT+
0.01µF
DOUT/RDY
AD7195 100Ω
SENSE– SCLK MICRO
100Ω CONTROLLER
USB
0.001µF
CS
AIN3 100Ω
100Ω
0.01µF
SYNC
AIN4 100Ω
100Ω
0.001µF LCD
NPX BSH112 DRIVER
BPDSW
LOAD CELL:
TEDEA HUNTLEIGH ACX1
505H-0002-F070 LCD
ACX2
DGND AGND
09015-001
Figure 1. Weigh Scale System Using the AD7195 with AC Excitation (Simplified Schematic: All Connections Not Shown)
Rev. A
The AD7195 simplifies the weigh scale design in low offset
systems because most of the system building blocks are
included on the chip. The AD7195 maintains good performance
over the complete output data rate range, from 4.7 Hz to 4.8 kHz,
which allows it to be used in weigh scale systems that operate at
low speeds along with higher speed weigh scale systems.
CIRCUIT DESCRIPTION
With ac excitation, the polarity of the excitation voltage to the
load cell is switched using external MOSFETs. Consecutive
values are then averaged, which removes dc induced offsets.
The AD7195 contains the internal logic to control the switching
of the external MOSFETs. The driver signals from the AD7195
are precisely timed and nonoverlapping, which ensures that no
short circuit occurs when switching the polarity of the bridge
drive voltage. Pull-up and pull-down 1 MΩ resistors are
connected to ACX2 and ACX2 to prevent short-circuiting
during power-up.
09015-002
The AD7195 provides an integrated solution for ac excited load
cells. The AD7195 can accept an inverted reference voltage, Figure 2. Weigh Scale System Setup Using the AD7195
which is required when the excitation voltage to the load cell is
With this arrangement, the system is not completely ratiometric
inverted. The AD7195 synchronizes the ac excitation with the
because there is a voltage drop between the EXC+/EXC− pins
conversions and performs the averaging. Only a few external
and the SENSE+/SENSE− due to wiring resistance.
components are required. Along with the MOSFET transistors,
the only other external components required are some filters on The AD7195 has separate analog and digital power supply pins.
the analog inputs and capacitors on the reference pins for EMC The analog section must be powered from 5 V. The digital
purposes. power supply is independent of the analog power supply and
can be any voltage between 2.7 V and 5.25 V.
The low level signal from the load cell is amplified by the
AD7195 internal PGA. The PGA is programmed to operate The microcontroller uses a 3.3 V power supply. Therefore,
with a gain of 128. The conversions from the AD7195 are then DVDD is also powered from 3.3 V. This simplifies the interface
sent to the PC via the USB connector. Using LabView™ software, between the ADC and microcontroller because no external level
the conversions are converted to weight and displayed. shifting is required.
Figure 2 shows the actual test setup. A 6-wire load cell is used There are several methods to power the weigh scale system. It
because this gives the optimum system performance. A 6-wire can be powered from the main power supply bus or battery
load cell has two sense pins in addition to the excitation, powered (as shown in Figure 1). A 5 V low noise regulator is
ground, and two output connections. The sense pins are used to ensure that the AD7195 and the load cell receive a low
connected to the high side and low side of the Wheatstone noise supply. The ADP3303 (5 V) is used to generate the 5 V
bridge. The voltage developed across the bridge can, therefore, supply and is a low noise regulator. The filter network shown
be accurately measured regardless of the voltage drop due to the inside the dotted box ensures a low noise AVDD for the system.
wiring resistance. In addition, the AD7195 has differential In addition, noise reduction capacitors are placed on the
analog inputs, and it accepts a differential reference. regulator output as recommended in the ADP3303 (5 V) data
Connection of the load cell differential SENSE lines to the sheet. To optimize the EMC performance, the regulator output
AD7195 reference inputs creates a ratiometric configuration is filtered ahead of the AD7195 and the load cell. The 3.3 V
that is immune to low frequency changes in the power supply digital supply is generated using the ADP3303 (3.3 V). It is
excitation voltage. In addition, it eliminates the need for a essential that low noise regulators be used to generate all the
precision reference. With a 4-wire load cell, the sense pins are power supply voltages to the AD7195 and the load cell because
not present, and the ADC reference pins are connected to the any noise on the power supply or ground planes introduces
excitation pins EXC+ and EXC−. noise into the system and degrades the circuit performance.
If a 2 kg load cell with a sensitivity of 2 mV/V is used, the full-
scale signal from the load cell is 10 mV when the excitation
voltage is 5 V. A load cell has an offset, or TARE, associated
with it. The noise of the system is calculated by the software to
be 10 nV rms and 51 nV peak-to-peak. This equates to 196,000
noise-free counts, or 17.5 bits of noise-free code resolution Figure 4 shows the performance in terms of weight. The peak-
(calculated from the measured peak-to-peak noise). The TARE to-peak variation in output is 0.01 grams over the 500 codes.
can have a magnitude that is up to 50% of the load cell full-scale Therefore, the weigh scale system achieves an accuracy of
output signal. The load cell also has a gain error that can be up 0.01 grams.
to ±20% of full scale. Some customers use a DAC to remove or The plots show the actual (raw) conversions read back from the
null the TARE. When the AD7195 uses a 5 V reference, its AD7195 when the load cell is attached. In practice, a digital post
analog input range is equal to ±40 mV when the gain is set to filter is used in a weigh scale system. The additional averaging
128 and the part is configured for bipolar operation. The wide that is performed in the post filter further improves the number
analog input range of the AD7195 relative to the load cell full- of noise-free counts at the expense of a reduced output data rate.
scale signal (10 mV) is beneficial because it ensures that the
offset and gain error of the load cell do not overload the ADC’s As with any high accuracy circuit, proper layout, grounding,
front end. and decoupling techniques must be employed. See Tutorial
The AD7195 has an rms noise of 6 nV and a peak-to-peak noise AGND and DGND, and Tutorial MT-101, Decoupling
of 40 nV when the first filter notch is programmed to 4.7 Hz. Techniques, for more details.
This corresponds to an output data rate of 1.17 Hz when ac
excitation is used (sinc4 filter selected). The number of noise- A complete design support package for this circuit note can be
free counts is equal to found at http://www.analog.com/CN0155-DesignSupport.
COMMON VARIATIONS
10 mV
= 250,000 (1) Other weigh scale circuits, which do not require ac excitation,
40 nV are described in the following Circuit Notes: CN-0102, CN-0107,
The resolution in grams is, therefore, equal to CN-0108, CN-0118, and CN-0119.
2 kg CIRCUIT EVALUATION AND TEST

= 0.008 g (2)
250,000 With the exception of the external load cell and the PC, the
circuit shown in Figure 1 is contained on the AD7195 eval-
The noise free resolution is equal to uation board (EVAL-AD7195-EBZ ).
( ) Interface to the evaluation board is via a standard USB connec-
( )
log10 250,000
log 2 250,000 = = 17.9 bits (3)
log10 2 () tor, J1. J1 is used to connect the evaluation board to the USB
port of a PC. A standard USB connector cable is included with
In practice, the load cell itself introduces some noise. Figure 3 the AD7195 evaluation board to allow the evaluation board to
shows the measured output performance when a 1 kg weight is interface with the USB port of the PC. The AD7195 evaluation
placed on the load cell and 500 conversions are gathered. board can be powered using a 9 V battery, B1, or using an
external 9 V dc source connected at J31. The 9 V is regulated
down to 5 V using the on-board ADP3303-5, a high precision,
low power 5 V output regulator. Using link J1, this regulated 5
V can be used as the supply to the AD7195.To use this option,
link J1 should be placed in the 5 VBAT position.
Equipment Needed
The EVAL-AD7195-EBZ evaluation board and a PC running
09015-003
Windows® 2000, Windows XP, or Windows Vista (32-bit) are

Figure 3. Measured Output Code for 500 Samples Showing the only items required other than the external load cell. A
the Effects of Noise Tedea Huntleigh 505H-0002-F070 load cell was used to obtain
the results presented in this circuit note. The load cell is not
shipped with the evaluation board and must be purchased from
the manufacturer by the customer.
09015-004
Figure 4. Measured Output in Grams for 500 Samples Showing

Getting Starting
The EVAL-AD7195-EBZ evaluation board is shipped with a CD LEARN MORE
containing software that can be installed onto a standard PC to CN0155 Design Support Package:
control the AD7195. The software communicates with the http://www.analog.com/CN0155-DesignSupport
AD7195 through the USB cable, which accompanies the board.
The software allows conversion data to be read from the AD7195
Analog Devices.
and displayed or stored for later analysis.
The AD7195 evaluation board software should be installed
using the supplied AD7195 evaluation board CD before
connecting the board to the PC. Complete details can be found MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC
in the AD7195 evaluation board user guide (see the CN0155 Basics, Analog Devices.
Design Support Package: http://www.analog.com/CN0155- MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
DesignSupport). Advanced Concepts and Applications, Analog Devices.
Functional Block MT-031 Tutorial, Grounding Data Converters and Solving the
The evaluation board user guide shows the basic functional Mystery of "AGND" and "DGND," Analog Devices.
block diagram of the test setup (see the CN0155 Design Support MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Package: http://www.analog.com/CN0155-DesignSupport).
Setup and Test
AD7195 Data Sheet
Complete instructions for setup and testing of the AD7195
evaluation board can be found in AD7195 evaluation board AD7195 Evaluation Board
user guide (see the CN0155 Design Support Package: ADP3303 Data Sheet
http://www.analog.com/CN0155-DesignSupport).
After the software is installed, the AD7195 evaluation board REVISION HISTORY
should be configured for use with the external load cell by
setting the appropriate links (jumpers) as described in
theAD7195 evaluation board user guide (see the CN0155 Changes to Circuit Note Title ..........................................................1
Design Support Package: http://www.analog.com/CN0155- Added Evaluation and Design Support Section ............................1
DesignSupport). Make sure the links are set before applying Changes to Circuit Function and Benefits Section .......................1
power to the evaluation board. Changes to Circuit Description Section .........................................2
The load cell connects to the evaluation board header J4.
Changes to Learn More Section ......................................................4
Operation of the Weighscale Demo is described in the AD7195
evaluation board user guide (see the CN0155 Design Support 7/10—Revision 0: Initial Version
Package: http://www.analog.com/CN0155-DesignSupport).
application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is"
and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular

CN09015-0-11/10(A)
Circuit Note
CN-0185
AD7400A Isolated Sigma-Delta Modulator
ADuM5000 Isolated DC-to-DC Converter
AD8646 Dual, 24 MHz, Rail-to-Rail, I/O Op Amp
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s 150 mA, Low Quiescent Current, CMOS
ADP121
analog, mixed-signal, and RF design challenges. For more Linear Regulator
information and/or support, visit www.analog.com/CN0185. High Accuracy, 100 mA, Low Dropout
ADP3301
Linear Regulator
ADG849 3 V/5 V CMOS 0.5 Ω SPDT/2:1 Mux in SC70
Ultralow Noise, LDO XFET® 3.0 V Voltage
ADR443
Reference
A Novel Analog-to-Analog Isolator Using an Isolated Sigma-Delta Modulator,

Isolated DC-to-DC Converter, and Active Filter
EVALUATION AND DESIGN SUPPORT The circuit is based on the AD7400A, a second-order, sigma-delta
Circuit Evaluation Boards (Σ-Δ) modulator with a digitally isolated 1-bit data stream output.
CN-0185 Circuit Evaluation Board (EVAL-CN0185-EB1Z) The isolated analog signal is recovered with a fourth-order active
Design and Integration Files filter based on the dual, low noise, rail-to-rail AD8646 op amp.
Schematics, Layout Files, Bill of Materials With the ADuM5000 as the power supply for the isolated side,
the two sides are completely isolated and use only one power
CIRCUIT FUNCTION AND BENEFITS supply for the system. The circuit has 0.05% linearity and benefits
The circuit shown in Figure 1 is a complete low cost from the noise shaping provided by the modulator of the AD7400A
implementation of an analog-to-analog isolator. The circuit and the analog filter. The applications of the circuit include
provides isolation of 2500 V rms (1 minute per UL 1577). motor control and shunt current monitoring, and the circuit is
also a good alternative to isolation systems based on optoisolators.
+5V_ISO +5V
POWER IN
VISO VDD1 OUT IN +5.5V TO +12V
GNDISO GND1
RCIN GND SD
VSEL
RCOUT ADP3301-5
RCSEL
VISO VDD1 +3VREF
GNDISO GND1
ADuM5000 OUT IN
GND_ISO VOUT VIN
GND
GND EN
ADR443
ADP121-3.3
VIN+ 22Ω
1% VDD1 VDD2
+3VREF
VIN+ MDAT
0.1µF
VIN– MCLKOUT ADG849 100pF 100pF
VIN– 24kΩ 51kΩ
1% 5% 1% 5%
GND1 GND2
22Ω
1% AD7400A
24kΩ 51kΩ
GND_ISO 1/2 +5V 1/2
1% 1%
AD8646 AD8646
VOUT
68pF 8.2pF
5% 5%
09499-001
22Ω 22Ω
1% 1%
Figure 1. Analog Isolator Using AD7400A (Simplified Schematic: All Connections and Decoupling Not Shown
Rev. B
CIRCUIT DESCRIPTION Analog Active Filter Design
A block diagram of the circuit is shown in Figure 1. The analog The cutoff frequency of the low-pass filter mostly depends on
input is sampled at 10 MSPS by the AD7400A Σ-Δ modulator. the desired bandwidth of the circuit. There is a trade-off between
The 22 Ω resistors and 0.1 µF capacitor form a differential input the cutoff frequency and noise performance, and there is more
noise reduction filter with a cutoff frequency of 145 kHz. The noise if the cutoff frequency of the filter increases. This is especially
output of the AD7400A is an isolated 1-bit data stream. The true in this design because the Σ-Δ modulator shapes the noise
quantization noise is shaped by a second-order Σ-Δ modulator, and moves a large portion into the higher frequencies. The
which shifts the noise to the higher frequencies (see the MT-022 cutoff frequency in this design is 100 kHz.
Tutorial). For a given cutoff frequency, the smaller the transition band of
To reconstruct the analog input signal, follow the data stream by the filter is, the smaller the noise is that passes through the filter.
an ADG849 switch connected to a 3 V ADR443 reference to Of all the filter responses (Butterworth, Chebyshev, Bessel, and
stabilize the peak-to-peak output of the MDAT. so on), the Chebyshev filter was chosen for this design because it
has a smaller transition band for a given filter order. However,
The signal is then filtered by an active filter whose order is higher
this smaller transition band comes at the expense of a slightly
than the order of the modulator. A fourth-order Chebyshev filter is
worse transient response.
used for better noise attenuation. Compared to other filter
responses (Butterworth or Bessel), the response of the The fourth-order filter is made up of two second-order filters,
Chebyshev provides the steepest rolloff for a given filter order. with a Sallen-Key structure. The Analog Filter Wizard and the
The filter is implemented using the dual AD8646, a rail-to-rail, NI Multisim were used to design the filter. The parameters used
input and output, low noise, single-supply op amp. include the following:
The ADuM5000 is an isolated dc-to-dc converter based on • Filter type = low-pass, Chebyshev, 0.01 dB ripple
Analog Devices, Inc., iCoupler® technology. It is used for the • Order = 4
power supply to the isolated side of the circuit containing the • fC = 100 kHz, Sallen-Key (updated format for clarity)
AD7400A. The isoPower® technology of the ADuM5000 uses The recommended values generated by the program were
high frequency switching elements to transfer power through a used with the exception of the feedback resistors, which were
chip-scale transformer. reduced to 22 Ω.
The circuit must be constructed on a multilayer printed circuit Measurements
board (PCB) with a large area ground plane. Proper layout, The circuit has a gain of 4.6875 and an output offset voltage of
grounding, and decoupling techniques must be used to achieve 1.5 V. A differential signal of 0 V results in a digital bit stream of
optimum performance (see the MT-031 Tutorial, Grounding Data 1s and 0s, where each occurs 50% of the time. The ADR443 output
Converters and Solving the Mystery of "AGND" and "DGND," the is 3.0 V; therefore, after filtering, there is a 1.5 V dc offset. A
MT-101 Tutorial, Decoupling Techniques, and the ADuC7060/ differential input of 320 mV ideally results in a stream of all 1s,
ADuC7061 evaluation board layout). Ensure that the PCB layout which after filtering, yields a 3.0 V DC output. Therefore, the
meets the emissions standards and isolation requirements between effective gain of the circuit is
the two isolated sides (see the AN-0971 Application Note).
GAIN = (3.0 − 1.5)/0.32 = 4.6875
In order not to overdrive the AD8646, the input signal must be
lower than the power supply (5 V). The output of the AD7400A From the measurements, the actual measured offset is 1.504V , and
is a stream of 1s and 0s with an amplitude equal to the the gain is 4.69. The dc transfer function of the system is shown
AD7400A VDD2 supply voltage. Therefore, the VDD2 digital in Figure 2. Linearity was measured as 0.0465%.
supply is 3.3 V supplied by the ADP121 linear regulator. 2.9
Alternatively, if a 5 V supply is used for VDD2, attenuate the
digital output signal before connecting to the active filter. In 2.7
either case, well regulate the supply because the final analog
OUTPUT VOLTAGE (V)
2.5
output is directly proportional to VDD2.
The 5 V supply for the circuit in Figure 1 is supplied from an 2.3
ADP3301 5 V linear regulator, which accepts an input voltage 2.1

of 5.5 V to 12 V.
1.9
1.7
1.5
09499-002
0 50 100 150 200 250

INPUT VOLTAGE (mV)
Figure 2. System DC Transfer Function

Figure 3 shows the output voltage with no dc offset voltage CIRCUIT EVALUATION AND TEST
vs. the input frequency. The input signal voltage is 40 mV p-p, The circuit can be easily evaluated using a signal generator and an
which causes an output signal of 40 × 4.6875= 190 mV p-p. oscilloscope after powering on the circuit with a 6 V power supply.
Note that there is approximately 10 mV of peaking in the
frequency response function, corresponding to about 0.42 dB. Equipment Needed (Equivalents Can Be Substituted)
The system has good noise performance, with a noise density of The following equipment is needed:
2.50 µV/√Hz at 1 kHz and 1.52 µV/√Hz at 10 kHz. • A multifunction calibrator (dc source), Fluke 5700A
A complete design support package for this circuit note can be • A digital multimeter, Agilent 3458A, 8.5 digits
found at www.analog.com/CN0185-DesignSupport. • A spectrum analyzer, Agilent 4396B
240 • A function generator, Agilent 33250A
• A power supply, 6 V
200 200
Setup and Test
P-P OUTPUT VOLTAGE (mV)
160 100
The block diagram of the linearity measurement setup is shown in
PHASE (Degrees)
Figure 4. Connect the 6 V power supply to the EVAL-CN0185-EB1Z
120 0 power terminal.
The dc input voltage is generated with the Fluke 5700A, and the
80 –100 Agilent 3458A DVM is used to measure the output. The dc output
from the Fluke 5700A is stepped, and the data recorded with a
40 –200 1 mV increase from 1 mV to 250 mV.
DC POWER
0 SUPPLY
09499-003
100 1k 10k 100k 1M

FREQUENCY (Hz) +6V GND
Figure 3. Frequency and Phase Response of the Circuit for a
40 mV Peak-to-Peak Input Signal 1mV TO
250mV DIGITAL
DC SOURCE
EVAL-CN0185-EB1Z MULTIMETER
COMMON VARIATIONS FLUKE 5700A
09499-004
AGILENT 3458
The circuit can be used for isolated voltage monitoring and for
Figure 4. Test Setup for Measuring Linearity
current sensing applications where the voltage across a shunt
resistor is monitored. The requirements of the input signal for To measure the frequency response, connect the equipment as
the system are detailed in the AD7400A data sheet. shown in Figure 5. Set the 33250A function generator for a
If the ADuM6000 is used instead of the ADuM5000, the entire 40 mV peak-to-peak sine-wave output with a 0 dc offset. Then,
circuit is rated to 5 kV. sweep the frequency of the signal from 100 Hz to 500 kHz and
record the data using the Agilent 4396B spectrum analyzer.
The ADP1720 or ADP7102 linear regulator can be used as a
substitute for the ADP3301, if desired. DC POWER
SUPPLY
+6V GND
SIGNAL 100Hz TO
500kHz SPECTRUM
GENERATOR
EVAL-CN0185-EB1Z ANALYZER
AGILENT 09499-005
AGILENTY 4396B
33250A
Figure 5. Test Setup for Measuring Frequency Response
CN0185 Design Support Package: AD7400A Data Sheet
http://www.analog.com/CN0185-DesignSupport AD7400A Evaluation Board
ADIsimPower™ Design Tool, Analog Devices. ADuM5000 Data Sheet
Analog Filter Wizard Design Tool, Analog Devices. ADuM5000 Evaluation Board
Cantrell, Mark. Application Note AN-0971, Recommendations AD8646 Data Sheet
for Control of Radiated Emissions with isoPower Devices.
ADP121 Data Sheet
Analog Devices.
ADP3301 Data Sheet
Chen, Baoxing, John Wynne, and Ronn Kliger. High Speed
Digital Isolators Using Microscale On-Chip Transformers, ADG849 Data Sheet
Analog Devices, 2003. ADR443 Data Sheet
Chen, Baoxing. iCoupler® Products with isoPower™ Technology: REVISION HISTORY
Signal and Power Transfer Across Isolation Barrier Using
9/13—Rev. A to Rev. B
Microtransformers, Analog Devices, 2006.
Added ADR443.............................................................Throughrout
Chen, Baoxing. “Microtransformer Isolation Benefits Digital Changes to Devices Connected/Referenced Section and
Control.” Power Electronics Technology. October 2008. Figure 1 ...............................................................................................1
Ghiorse, Rich. Application Note AN-825, Power Supply Changes to Circuit Description Section, Measurements Section,
Considerations in iCoupler® Isolation Products, and Figure 2 ........................................................................................2
Analog Devices. Changes to Figure 3 ...........................................................................3
Change to Data Sheets and Evaluation Boards Section ...............4
Krakauer, David. “Digital Isolation Offers Compact, Low-
Cost Solutions to Challenging Design Problems.”
Analog Dialogue. Volume 40, December 2006.
Changes to Figure 1 ...........................................................................1
MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC Basics, Changes to Figure 3 and Common Variations Section ................3
Analog Devices.
MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC 4/11—Revision 0: Initial Version
Mystery of "AGND" and "DGND," Analog Devices.
USB 2.0 Specifications, USB Implementers Forum, Inc.
Wayne, Scott. “iCoupler® Digital Isolators Protect RS-232, RS-485,
and CAN Buses in Industrial, Instrumentation, and
Computer Applications.” Analog Dialogue. Volume 39,
October 2005.
Zumbahlen, Hank. Application Note AN-649, Using the
Analog Devices Active Filter Design Tool, Analog Devices.

CN09499-0-9/13(B)
Circuit Note
CN-0187
ADL5502 450 MHz to 6 GHz Crest Factor Detector
Circuits from the Lab™ reference circuits are engineered and Differential/Single-Ended Input, Dual,
tested for quick and easy system integration to help solve today’s AD7266 Simultaneous Sampling, 2 MSPS, 12-Bit,
analog, mixed-signal, and RF design challenges. For more 3-Channel SAR Analog-to-Digital Converter
information and/or support, visit www.analog.com/CN0187. Low Cost, Quad, CMOS, High Speed, Rail-to-
ADA4891-4
Rail Amplifier
150 mA, Low Quiescent Current, CMOS Linear
ADP121
Regulator in 5-Lead TSOT or 4-Ball WLCSP
Crest Factor, Peak, and RMS RF Power Measurement Circuit Optimized for
High Speed, Low Power, and Single 3.3 V Supply

Circuit Evaluation Boards The circuit shown in Figure 1 measures peak and rms power
CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ) at any RF frequency from 450 MHz to 6 GHz over a range of
System Demonstration Platform (EVAL-SDP-CB1Z) approximately 45 dB. The measurement results are converted
Design and Integration Files to differential signals in order to eliminate noise and are
Schematics, Layout Files, Bill of Materials provided as digital codes at the output of a 12-bit SAR ADC
with serial interface and integrated reference. A simple two-
point calibration is performed in the digital domain.
+3.3V +3.3V
+3.3V
*SEE TEXT 220Ω
442Ω +3.3V AVDD DVDD
8 U2-B 27Ω
1000pF 0.1µF ENBL * * U2-A
CFLTR* VA1
1 FLTR VRMS 7 U6
U1
0.01µF
ADL5502 220Ω
AD7266 SDP
2 VPOS PEAK 6 U3-B BOARD
* * VDRIVE
220Ω AND
0.01µF 0.01µF 27Ω SUPPORT
RFIN 3 RFIN CNTL 5 CONTROL +1.25V U2-D VA2 CIRCUITS
COMM (HIGH RESET; +2.5V
75Ω 4 LOW PEAK HOLD) 10kΩ DCAP A
U2-C CS
NOTE: U2 AND U3 ARE ADA4891-4
0.47µF 10kΩ DOUTA
0.47µF SCLK
220Ω
442Ω +3.3V
+3.3V 27Ω
+5.5V U3-A
U3-A VB1
VIN VOUT
1µF U5 1µF
ADP121
EN 220Ω
GND
220Ω
27Ω
VB2
+1.25V U3-D
U3-D
+2.5V
10kΩ DCAP B
U3-C
AGND DGND
0.47µF 10kΩ
09569-001
0.47µF
Figure 1. High Speed, Low Power, Crest Factor, Peak, and RMS Power Measurement System (Simplified Schematic: All connections and Decoupling Not Shown)
Rev.0
The ADL5502 is a mean-responding (true rms) power detector The internal filter capacitor of the ADL5502 provides averaging
in combination with an envelope detector to accurately in the square domain but leaves some residual ac on the output.
determine the crest factor (CF) of a modulated signal. It can be Signals with high peak-to-average ratios, such as W-CDMA or
used in high frequency receiver and transmitter signal chains CDMA2000, can produce ac residual levels on the ADL5502
from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz. VRMS dc output. To reduce the effects of these low frequency
The peak-hold function allows the capture of short peaks in the components in the waveforms, some additional filtering is
envelope with lower sampling rate ADCs. Total current required. The internal square-domain filter capacitance of the
consumption is only 3 mA @ 3 V. ADL5502 can be augmented by connecting a CFLTR capacitor
The ADA4891-4 is a high speed, quad, CMOS amplifier that between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be
offers high performance at a low cost. Current consumption is reduced further by adding capacitance to the VRMS output.
only 4.4 mA/amplifier at 3 V. The amplifier features true single- The combination of the internal 100 Ω output resistance and
supply capability, with an input voltage range that extends 300 mV the added output capacitance produces a low-pass filter to
below the negative rail. The rail-to-rail output stage enables reduce output ripple of the VRMS output (see the Selecting the
the output to swing to within 50 mV of each rail, ensuring Square-Domain Filter and Output Low-Pass Filter section of the
maximum dynamic range. Low distortion and fast settling time ADL5502 data sheet for more details).
makes it ideal for this application. To measure the peak of a waveform, the control line (CNTL)
The AD7266 is a dual, 12-bit, high speed, low power, successive must be temporally set to a logic high (reset mode for >1 µs)
approximation ADC that operates from a single 2.7 V to 5.25 V and then set back to a logic low (peak-hold mode). This allows
power supply and features sampling rates up to 2 MSPS. The the ADL5502 to be initialized to a known state. When setting
device contains two ADCs, each preceded by a 3-channel the device to measure peak, peak-hold mode should be toggled
multiplexer, and a low noise, wide bandwidth track-and-hold for a period in which the input rms power and crest factor (CF)
amplifier that can handle input frequencies in excess of 30 MHz. is not likely to change.
Current consumption is only 3 mA at 3 V. It also contains an If the ADL5502 is in peak-hold mode and the CF changes from
internal 2.5 V reference. high to low or the input power changes from high to low, a
The circuit operates on a single +3.3 V supply from the faulty peak measurement is reported. The ADL5502 simply
ADP121, a low quiescent current, low dropout, linear regulator keeps reporting the highest peak that occurred when the peak-
that operates from 2.3 V to 5.5 V and provides up to 150 mA hold mode was activated and the input power or the CF was
of output current. The low 135 mV dropout voltage at 150 mA high. Unless CNTL is reset, the PEAK output does not reflect
load improves efficiency and allows operation over a wide input the new peak in the signal.
voltage range. The low 30 μA of quiescent current at full load The ADL5502 is capable of sourcing a VRMS output current of
makes the ADP121 ideal for battery-operated portable equipment. approximately 3 mA. The output current is sourced through the
The ADP121 is available in output voltages ranging from 1.2 V on-chip, 100 Ω series resistor; therefore, any load resistor forms
to 3.3 V. The parts are optimized for stable operation with small a voltage divider with this on-chip resistance. It is
1 μF ceramic output capacitors. The ADP121 delivers good recommended that the ADL5502 VRMS output drive high
transient performance with minimal board area. resistive loads to preserve output swing. If an application
requires driving a low resistance load (as well as in cases where
Short-circuit protection and thermal overload protection increasing the nominal conversion gain is desired), a buffering
circuits prevent damage in adverse conditions. The ADP121 is circuit is necessary.
available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halide-
free WLCSP packages and utilizes the smallest footprint The PEAK output is designed to drive 2 pF loads. It is
solution to meet a variety of portable applications. recommended that the ADL5502 PEAK output drive low
capacitive loads to achieve a full output response time. The
CIRCUIT DESCRIPTION effects of larger capacitive loads are particularly visible when
The RF signal being measured is applied to the ADL5502. tracking envelopes during the falling transitions. When the
A single 75 Ω termination resistor at the RF input in parallel envelope is in a fall transition, the load capacitor discharges
with the input impedance of the ADL5502 provides a through the on-chip load resistance of 1.9 kΩ. If the larger
broadband match of 50 Ω. More precise resistive or reactive capacitive load is unavoidable, the additional capacitance can be
matches can be applied for narrow frequency band use (see counteracted by putting a shunt resistor to ground on the PEAK
the RF Input Interfacing section of the ADL5502 data sheet). output to allow for fast discharge. Such a shunt resistor also
makes the ADL5502 run higher current, and it should not be
lower than 500 Ω.
Rev. 0| Page 2 of 7
Typical measured performance characteristics of the circuit are
presented in Figure 2 through Figure 5. 2.0
1.8
10
1.6
1.4
OUTPUT (V)
1.2
1
1.0
OUTPUT (V)
0.8
450MHz 0.6 450MHz

900MHz 900MHz
0.1 1900MHz 0.4 1900MHz
2350MHz 2350MHz
2600MHz 0.2 2600MHz
09569-005
0 0.2 0.4 0.6 0.8 1.0
INPUT (V rms)
0.01
09569-002
–25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
Figure 5. Measured PEAK Output vs. Input Level (Linear Scale), 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
Figure 2. Measured VRMS Output vs. Input Level (Log Scale), 450 MHz,
The turn-on time and pulse response is strongly influenced by
2.0 the size of the square-domain filter (CFLTR) and output shunt
1.8
capacitor connected to the VRMS output. Figure 6 (taken from
the ADL5502 data sheet) shows a plot of the output response to
1.6
an RF pulse on the RFIN pin, with a 0.1 μF output filter
1.4
capacitor and no square-domain filter capacitor (CFLTR). The
falling edge is particularly dependent on the output shunt
OUTPUT (V)
1.2
1.0 capacitance.
450MHz
0.8 900MHz
1900MHz
0.6 2350MHz PULSED RFIN
2600MHz
0.4
400mV rms RF INPUT
0.2
VRMS (250mV/DIV)
0
09569-003
250mV rms
0 0.2 0.4 0.6 0.8 1.0
INPUT (V rms)
160mV rms
Figure 3. Measured VRMS Output vs. Input Level (Linear Scale), 450 MHz,
70mV rms
10
09569-053
VRMS
1ms/DIV
Figure 6. Output Response to Various RF Input Pulse Levels, Supply3 V,
1 900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF
OUTPUT (V)
To improve the falling edge of the enable and pulse responses,

450MHz
900MHz
a resistor can be placed in parallel with the output shunt
0.1 1900MHz capacitor. The added resistance helps to discharge the output
2350MHz
2600MHz filter capacitor. Although this method reduces the power-off
time, the added load resistor also attenuates the output (see the
Output Drive Capability and Buffering section of the ADL5502
0.01 data sheet). Figure 7 (taken from the ADL5502 data sheet)
09569-004
–25 –20 –15 –10 –5 0 5 10 15

INPUT (dBm) shows the improvement obtained by adding a parallel 1 kΩ
Figure 4. Measured PEAK Output vs. Input Level (Log Scale), 450 MHz, resistor.
Rev. 0| Page 3 of 7
PULSED RFIN Figure 8 and Figure 9 show plots of the VRMS and PEAK error
at 25°C, the temperature at which the ADL5502 is calibrated.
400mV rms RF INPUT
Note that the error is not zero; this is because the ADL5502
does not perfectly follow the ideal linear equation, even within
VRMS (250mV/DIV)
250mV rms its operating region. The error at the calibration points is,
however, equal to zero by definition.
160mV rms
70mV rms 3
09569-054
VRMS
1ms/DIV 1
Figure 7. Output Response to Various RF Input Pulse Levels, Supply 3 V,
ERROR (dB)
900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF
0
with Parallel 1 kΩ
450MHz
–1 900MHz
1900MHz
The RMS and PEAK outputs of the ADL5502 pass through 2350MHz
unity gain buffers that drive cross-coupled stages for converting –2 2600MHz
the single-ended outputs to differential signals. The internal

+2.5 V reference of the AD7266 (via the DCAPA and DCAPB pins) –3
09569-008
–25 –20 –15 –10 –5 0 5 10 15
passes through another unity gain buffer and a voltage divider. INPUT (dBm)
This sets the common-mode voltage of the network to +1.25 V. Figure 8. Measured VRMS Linearity Error vs. Input Level, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
The AD7266 achieves simultaneous samples of the RMS and
PEAK outputs and transfers the data within a 1 µs response
3
time. The data is provided on a single serial data line. Because
slope and intercept vary from device to device, board-level
2
calibration must be performed to achieve high accuracy. In
general, calibration is performed by applying two input power
1
levels to the ADL5502 and measuring the corresponding output
ERROR (dB)
voltages. The calibration points are generally chosen to be

0
within the linear operating range of the device. The best-fit line
is characterized by calculating the conversion gain (or slope) 450MHz
–1 900MHz
and intercept using the following equations: 1900MHz
2350MHz
Gain = (VVRMS2 − VVRMS1)/(VIN2 − VIN1) (1) –2 2600MHz
Intercept = VVRMS1 − (Gain × VIN1) (2)

–3 09569-009
where: –25 –20 –15 –10 –5 0 5 10 15
INPUT (dBm)
VIN is the rms input voltage to RFIN. Figure 9. Measured PEAK Linearity Error vs. Input Level, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
VVRMS is the voltage output at VRMS.
Once gain and intercept are calculated, an equation can be When the characteristics (slope and intercept) of the VRMS and
written that allows calculation of an (unknown) input power PEAK outputs are known, the calibration for the CF calculation
based on the measured output voltage. is complete. A three-stage process must be taken to measure
VIN = (VVRMS − Intercept)/Gain (3) and calculate the crest factor of any waveform. First, the
For an ideal (known) input power, the law conformance error of unknown signal must be applied to the RF input, and the
the measured data can be calculated as corresponding VRMS level is measured. This level is indicated
in Figure 10 as VVRMS-UNKNOWN. The RF input, VIN, is calculated
V – Intercept  using VVRMS-UNKNOWN and Equation 3.
ERROR (dB) = 20 × log  VRMS, MEASURED  (4)
 Gain × VIN, IDEAL 
 
Rev. 0| Page 4 of 7
3.0
OUTPUT (V) 2.5

PEAK OF
UNKNOWN WAVEFORM
VRMS OF 2.0
CREST FACTOR (dB)

UNKNOWN WAVEFORM
3 (RESULT INDEPENDENT 1.5
VPEAK-UNKNOWN OF WAVEFORM)
450MHz
VVRMS-UNKNOWN 1.0 900MHz
PEAK OF
CW, CF = 0dB 1900MHz
2 2350MHz
VPEAK-CW 0.5
2600MHz
09569-057
1
0
0 VIN INPUT (V rms)
–0.5
Figure 10. Procedure for Crest Factor Calculation
–1.0
09569-012
–25 –15 –5 5 15
INPUT (dBm)
Next, the CW reference level of PEAK, VPEAK-CW, is calculated

Figure 12. Measured Crest Factor of CW Signals vs. Input Level, 450 MHz,
using VIN (that is, the output voltage that would be seen if the 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
incoming waveform was a CW signal).
VPEAK-CW = (VIN GainPEAK) + InterceptPEAK (5)
The performance of this or any high speed circuit is highly
Finally, the actual level of PEAK, VPEAK-UNKNOWN, is measured and dependent on proper PCB layout. This includes, but is not
the CF can be calculated as limited to, power supply bypassing, controlled impedance lines
CF = 20 log10 (VPEAK-UNKNOWN /VPEAK-CW) (6) (where required), component placement, signal routing, and
where VPEAK-CW is used as a reference point to compare power and ground planes. (See MT-031 Tutorial, MT-101 Tutorial,
VPEAK-UNKNOWN. If both VPEAK values are equal, then the CF is 0 dB, and article, A Practical Guide to High-Speed Printed-Circuit-
as shown in Figure 11 with the CW signal (taken from the Board Layout, for more detailed information regarding PCB
ADL5502 data sheet). Across the dynamic range, the calculated layout.)
CF hovers about the 0 dB line. Likewise, for complex waveforms A complete design support package for this circuit note can be
of 3 dB, 6 dB, and 9 dB CFs, the calculations accurately hover found at http://www.analog.com/CN0187-DesignSupport.
about the corresponding CF levels.
COMMON VARIATIONS
10 For applications that require less RF detection range, the
8-TONE WAVEFORM, 9dB CF
9 AD8363 rms detector can be used. The AD8363 has a detection
8 range of 50 dB and operates at frequencies up to 6 GHz. For
7 non-rms detection applications, the AD8317/AD8318/AD8319
CREST FACTOR (dB)
6
or ADL5513 can be used. These devices offer varying detection
5
ranges and have varying input frequency ranges up to 10 GHz
(see CN-0150 for more details).
4
3
2
This circuit uses the EVAL-CN0187-SDPZ circuit board and the
1
CW, 0dB CF EVAL-SDP-CB1Z System Demonstration Platform (SDP)
0
evaluation board. The two boards have 120-pin mating
–1
connectors, allowing for the quick setup and evaluation of the
09569-058
–25 –20 –15 –10 –5 0 5 10 15

INPUT (dBm) circuit’s performance. The EVAL-CN0187-SDPZ board contains
the circuit to be evaluated, as described in this note, and the
Figure 11. Reported Crest Factor of Various Waveforms
SDP evaluation board is used with the CN0187 evaluation
software to capture the data from the EVAL-CN0187-SDPZ
circuit board.
Rev. 0| Page 5 of 7
The data in this circuit note were generated using a Rohde &
Equipment Needed Schwarz SMT-03 RF signal source and an Agilent E3631A
• PC with a USB port and Windows® XP or Windows Vista® power supply. The signal source was set to the frequencies
(32-bit), or Windows® 7 (32-bit) indicated in the graphs, and the input power was stepped and
data recorded in 1 dB increments.
• EVAL-CN0187-SDPZ circuit evaluation board
Information and details regarding how to use the evaluation
• EVAL-SDP-CB1Z SDP evaluation board
software for data capture can be found in the CN0187
• CN0187 evaluation software Evaluation Software Readme file.
• Power supply: +6 V, or +6 V “wall wart” Information regarding the SDP board can be found in the
SDP User Guide.
• RF signal source
• Coaxial RF cable with SMA connectors
LEARN MORE
Getting Started
CN0187 Design Support Package:
Load the evaluation software by placing the CN0187 Evaluation http://www.analog.com/CN0187-DesignSupport
Software disc in the CD drive of the PC. Using "My Computer,"
SDP User Guide
locate the drive that contains the evaluation software disc and
open the Readme file. Follow the instructions contained in the Ardizzoni, John. A Practical Guide to High-Speed Printed-Circuit-
Readme file for installing and using the evaluation software. Board Layout, Analog Dialogue 39-09, September 2005.
Functional Block Diagram CN-0150 Circuit Note, Software-Calibrated, 1 MHz to 8 GHz,
70 dB RF Power Measurement System Using the AD8318
See Figure 1 of this circuit note for the circuit block diagram,
Logarithmic Detector, Analog Devices.
and the “EVAL-CN0187-SDPZ-SCH” pdf file for the circuit
schematics. This file is contained in the CN0187 Design MT-031 Tutorial, Grounding Data Converters and Solving the
Support Package. Mystery of “AGND” and “DGND”, Analog Devices.
Setup MT-073 Tutorial, High Speed Variable Gain Amplifiers (VGAs),
Connect the 120-pin connector on the EVAL-CN0187-SDPZ Analog Devices.
circuit board to the connector marked “CON A” on the MT-077 Tutorial, Log Amp Basics, Analog Devices.
EVAL-SDP-CB1Z evaluation (SDP) board. Nylon hardware MT-078 Tutorial, High Speed Log Amps, Analog Devices.
should be used to firmly secure the two boards, using the holes
provided at the ends of the 120-pin connectors. Using an MT-081 Tutorial, RMS-to-DC Converters, Analog Devices.
appropriate RF cable, connect the RF signal source to the MT-101 Tutorial, Decoupling Techniques, Analog Devices.
EVAL-CN0187-SDPZ board via the SMA RF input connector. Whitlow, Dana. Design and Operation of Automatic Gain
With power to the supply off, connect a +6 V power supply to Control Loops for Receivers in Modern Communications
the pins marked “+6 V” and “GND” on the board. If available, a Systems. Chapter 8. Analog Devices Wireless Seminar. 2006.
+6 V "wall wart" can be connected to the barrel jack connector
on the board and used in place of the +6 V power supply. Data Sheets and Evaluation Boards
Connect the USB cable supplied with the SDP board to the USB CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ)
port on the PC. Note: Do not connect the USB cable to the mini System Demonstration Platform (EVAL-SDP-CB1Z)
USB connector on the SDP board at this time.
ADL5502 Data Sheet
Test
ADL5502 Evaluation Board
Apply power to the +6 V supply (or “wall wart”) connected to
EVAL-CN0187-SDPZ circuit board. Launch the evaluation AD7266 Data Sheet
software and connect the USB cable from the PC to the USB AD7266 Evaluation Board
mini-connector on the SDP board. The software will be able to
ADA4891 Data Sheet
communicate to the SDP board if the Analog Devices System
Development Platform driver is listed in the Device Manager.
Once USB communications are established, the SDP board can
now be used to send, receive, and capture serial data from the
EVAL-CN0187-SDPZ board.
Rev. 0| Page 6 of 7
REVISION HISTORY

CN09569-0-4/11(0)
Rev. 0| Page 7 of 7
Circuit Note
CN-0216
Low Power, Buffered, 24-Bit Sigma-Delta
Circuits from the Lab™ reference circuits are engineered and AD7791
ADC
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more Precision, Ultralow Noise, Rail-to-Rail
ADA4528-1
information and/or support, visit www.analog.com/CN0216. Input/Output, Zero-Drift Op Amp
High Accuracy anyCAP® 100 mA Low
ADP3301
Dropout Linear Regulator
Precision Weigh Scale Design Using the AD7791 24-Bit Sigma-Delta ADC
with External ADA4528-1 Zero-Drift Amplifiers
EVALUATION AND DESIGN SUPPORT Ultralow noise, low offset voltage, and low drift amplifiers are
Circuit Evaluation Boards used at the front end for amplification of the low-level signal
CN-0216 Circuit Evaluation Board (EVAL-CN0216-SDPZ) from the load cell. The circuit yields 15.3 bit noise-free code
System Demonstration Platform (EVAL-SDP-CB1Z) resolution for a load cell with a full-scale output of 10 mV.
Design and Integration Files This circuit allows great flexibility in designing a custom low-
Schematics, Layout Files, Bill of Materials level signal conditioning front end that gives the user the ability
to easily optimize the overall transfer function of the combined
CIRCUIT FUNCTION AND BENEFITS
sensor-amplifier-converter circuit. The AD7791 maintains good
The circuit in Figure 1 is a precision weigh scale signal performance over the complete output data range, from 9.5 Hz
conditioning system. It uses the AD7791, a low power buffered to 120 Hz, which allows it to be used in weigh scale applications
24-bit sigma-delta ADC along with two external ADA4528-1 that operate at various low speeds.
zero-drift amplifiers. This solution allows for high dc gain with
a single supply.
+5.0V
+5.0V 0.1µF 10µF
ADA4528-1
VDD
AD7791
100pF SDP BOARD
R1 11.3kΩ REFIN(+) AND
1µF
REFIN(–) SUPPORT CIRCUITS
C1 3.3µF
100pF DIN
RG 33Ω
+5.0V 60.4Ω DOUT/RDY
LOAD CELL: C2 3.3µF 33Ω
TEDEA HUNTLEIGH SCLK
SENSE+ 33Ω
505H-0002-F070 R3 1kΩ 1µF C3
CS
R2 11.3kΩ AIN(+) 33Ω
OUT– OUT+ 10µF C5
+5.0V AIN(–)
R4 1kΩ
1µF C4
SENSE– ADA4528-1
GND
ADP3301-5.0 5.0V
VIN
IN OUT
10µF 0.1µF IN OUT
0.1µF 4.7µF
SD NR
ERR
GND
10164-001
Figure 1. Weigh Scale System Using the AD7791 (Simplified Schematic, All Connections and Decoupling Not Shown)
Rev. 0
CIRCUIT DESCRIPTION
The two ADA4528-1 op amps are configured as the first stage of
Figure 2 shows the actual test setup. For testing purposes, a a three op amp instrumentation amplifier. A third op amp
6-wire Tedea-Huntleigh 505H-0002-F070 load cell is used. connected as a difference amplifier would normally be used for
Current flowing through a PCB trace produces an IR voltage the second stage, but in the circuit of Figure 1, the differential
drop, and with longer traces, this voltage drop can be several input of the AD7791 performs this function.
millivolts or more, introducing a considerable error. A 1 inch The gain is equal to 1 + 2R1/RG. Capacitors C1 and C2 are
long, 0.005 inch wide trace of 1 oz copper has a resistance of placed in the feedback loops of the op amps and form 4.3 Hz
approximately 100 mΩ at room temperature. With a load cutoff frequency low-pass filters with R1 and R2. This limits the
current of 10 mA, this can introduce a 1 mV error. amount of noise entering the sigma-delta ADC. C5 in
A 6-wire load cell has two sense pins, in addition to the conjunction with R3 and R4 form a differential filter with a
excitation, ground, and two output connections. The sense pins cutoff frequency of 8 Hz, which further limits the noise. C3 and
are connected to the high side (excitation pin) and low side C4 in conjunction with R3 and R4 form common-mode filters
(ground pin) of the Wheatstone bridge. The voltage developed with a cutoff frequency of 159 Hz.
across the bridge can be accurately measured regardless of the The ADP3301 low noise regulator powers the AD7791,
voltage drop due to wire resistance. In addition, the AD7791 ADA4528-1, and the load cell. In addition to decoupling
accepts differential analog inputs and a differential reference as capacitors, a noise reduction capacitor is placed on the regulator
well. These two sense pins are connected to the AD7791 output as recommended in the ADP3301 data sheet. It is
reference inputs to create a ratiometric configuration that is essential that the regulator is low noise, because any noise on
immune to low frequency changes in the power supply the power supply or ground plane introduces noise into the
excitation voltage. The ratiometric connection eliminates the system and degrades the circuit performance.
need for a precision voltage reference.
Unlike a 6-wire load cell, a 4-wire load cell does not have sense
pins, and the ADC differential reference pins are connected
directly to the excitation voltage and ground. With this
connection, there exists a voltage difference between the
excitation pin and the reference pin on the ADC due to wire
resistance. There will also be a voltage difference on the low side
(ground) due to wire resistance. The system will not be
completely ratiometric.
The Tedea-Huntleigh 2 kg load cell has a sensitivity of 2 mV/V
and a full-scale output of 10 mV when the excitation voltage is
5 V. A load cell also has an offset, or TARE, associated with it.
In addition, the load cell also has a gain error. Some customers
use a DAC to remove or null the TARE. When the AD7791 uses
10164-002
a 5 V reference, its differential analog input range is equal to
±5 V, or 10 V p-p. The circuit in Figure 1 amplifies the load cell
Figure 2. Weigh Scale System Setup Using the AD7791
output by a factor of 375 (1 + 2R1/RG), so the full-scale input
range referred to the load cell output is 10 V/375 = 27 mV p-p. The 24-bit sigma-delta ADC AD7791 converts the amplified
This extra range relative to the 10 mV p-p load cell full-scale signal from the load cell. The AD7791 is configured to operate
signal is beneficial as it ensures that the offset and gain error of in the buffered mode to accommodate the impedance of the
the load cell do not overload the ADC’s front end. R-C filter network on the analog input pins.
The low-level amplitude signal from the load cell is amplified by Figure 3 shows the AD7791’s rms noise for different output data
two ADA4528-1 zero-drift amplifiers. A zero-drift amplifier, as rates. This plot shows that the rms noise increases as the output
the name suggests, has a close to zero offset voltage drift. The data rate increases. However, the device maintains good noise
amplifier continuously self-corrects for any dc errors, making it performance over the complete range of output data rates.
as accurate as possible. Besides having low offset voltage and
drift, a zero-drift amplfier also exhibits no 1/f noise. This
important feature allows precision weigh scale measurement at
dc or low frequency.
100
Therefore, the corresponding noise-free code resolution of the
total system is:
log10 (39,557 )
log 2 (39,557 ) = = 15.3 bits
10 log10 (2)
RMS NOISE (µV)
Figure 4 shows a plot of the ADC codes for 500 samples

(52.6 sec for 9.5 Hz data rate). Note that the peak-to-peak
spread is about 160 codes.
1
0.1
10164-003
1 10 100 1000
OUTPUT DATA RATE (Hz)
Figure 3. AD7791 RMS Noise for Different Output Data Rates and a 2.5 V
Reference (5 V p-p Input Range), Buffer On
The AD7791 rms noise of 1.1 µV for a 9.5 Hz output data rate
and a reference of 2.5 V yields the following number of noise-
free counts:
5V
= 688,705
6.6 × 1.1 μ V
where the factor of 6.6 converts the rms voltage into a peak-to-
peak voltage.
The corresponding noise-free code resolution is, therefore:
log10 (688,705)
10164-004
log 2 (688,705) = = 19.5 bits
log10 (2)
Note that this represents the performance of the AD7791 the Effects of Noise
without the load cell or the input amplifier connected.
Figure 5 shows the same data presented in a histogram. Figure 4
The ADA4528-1 has 5.9 nV/√Hz of voltage noise density and, and Figure 5 show the actual (raw) conversions read back from
therefore, the input amplifiers and resistors will add noise to the the AD7791. In practice, a digital post filter is typically used in a
system. In addition, the load cell itself will add noise. weigh scale system. The additional averaging that is performed
In the circuit of Figure 1, a 5 V reference is used, therefore, the in the post filter will further improve the number of noise-free
peak-to-peak input range is 10 V. The LSB is, therefore, equal to counts at the expense of a reduced data rate.
10 V The resolution of the system in grams can be calculated by
1LSB = = 0.596 μV
224 2 kg
= 0.05 g
The 10 mV p-p full-scale signal from the load cell produces a 39,557
3.75 V p-p signal into the ADC, which is approximately 38% of As with any high accuracy circuit, proper layout, grounding,
the ADC range. and decoupling techniques must be employed. See Tutorial
Seven sets of 500 samples each were taken with the load cell MT-031, Grounding Data Converters and Solving the Mystery of
connected (no load). The peak-to-peak code spread for each AGND and DGND and Tutorial MT-101, Decoupling Techniques
sample set was calculated, and the seven values averaged to for more details. A complete design support package for this
yield a code spread of 159 counts. This corresponds to 159 × circuit note can be found at www.analog.com/CN0216-
0.596 µV = 94.8 µV p-p noise based on a full-scale input to the DesignSupport.
ADC of 3.75 V p-p.
Therefore, the number of noise-free counts is
3.75 V
= 39,557
94.8 μ V
Getting Started
Load the evaluation software by placing the CN0216 Evaluation
Software disc in the CD drive of the PC. Using My Computer,
open the Readme file. Follow the instructions contained in the
Readme file for installing and using the evaluation software.
Functional Block Diagram
See Figure 1 of this circuit note for the circuit block diagram,
and the PDF file “EVAL-CN0216-SDPZ-SCH” for the circuit
schematics. This file is contained in the CN0216 Design
Support Package.
Setup
Connect the 120-pin connector on the EVAL-CN0216-SDPZ
circuit board to the connector marked “CON A” on the
EVAL-SDP-CB1Z evaluation (SDP) board. Nylon hardware
should be used to firmly secure the two boards, using the holes
provided at the ends of the 120-pin connectors. Connect the
10164-005
load cell the EVAL-CN0216-SDPZ board.

Figure 5. Measured Histogram for 500 Samples Showing With power to the supply off, connect a +6 V power supply to
the pins marked “+6 V” and “GND” on the board. If available, a
COMMON VARIATIONS +6 V "wall wart" can be connected to the barrel jack connector
Other ADCs and circuits suitable for weigh scale applications on the board and used in place of the +6 V power supply.
are discussed in CN-0102 (AD7190), CN-0107 (AD7780), CN- Connect the USB cable supplied with the SDP board to the USB
0108 (AD7781), CN-0118 (AD7191), CN-0119 (AD7192), and port on the PC. Note: Do not connect the USB cable to the mini
CN-0155 (AD7195). USB connector on the SDP board at this time.
The AD7171 is a 16-bit sigma-delta ADC. Test
For a lower power consumption solution, use the ADA4051-2. Apply power to the +6 V supply (or “wall wart”) connected to
The ADA4051-2 is a dual micropower, zero-drift amplifier with EVAL-CN0216-SDPZ circuit board. Launch the evaluation
only 20 µA of supply current per amplifier. software and connect the USB cable from the PC to the USB
mini-connector on the SDP board. The software will be able to
CIRCUIT EVALUATION AND TEST communicate to the SDP board if the Analog Devices System
This circuit uses the EVAL-CN0216-SDPZ circuit board and Development Platform driver is listed in the Device Manager.
the EVAL-SDP-CB1Z system demonstration platform (SDP) Once USB communications are established, the SDP board can
evaluation board. The two boards have 120-pin mating now be used to send, receive, and capture serial data from the
connectors, allowing for the quick setup and evaluation of the EVAL-CN0216-SDPZ board.
circuit’s performance. The EVAL-CN0216-SDPZ board contains
Information and details regarding how to use the evaluation
the circuit to be evaluated, as described in this note, and the
software for data capture can be found in the CN0216
SDP evaluation board is used with the CN-0216 evaluation
Evaluation Software Readme file.
software to capture the data from the EVAL-CN0216-SDPZ
circuit board. Information regarding the SDP board can be found in the
SDP User Guide.
Equipment Needed
Analyzing the Data
• PC with a USB port and Windows XP or Windows Vista
(32-bit), or Windows 7 (32-bit) At least 500 samples of the ADC output data should be taken.
Once the sample set is exported to a spreadsheet program, such
• EVAL-CN0216-SDPZ circuit evaluation board
as Excel, the samples can be analyzed. The standard deviation of
• EVAL-SDP-CB1Z SDP evaluation board the samples is approximately equal to the rms noise, assuming a
• CN0216 evaluation software Gaussian noise distribution. The peak-to-peak noise is
approximately equal to the rms value multiplied by 6.6.
• Tedea-Huntleigh 505H-0002-F070 load cell or equivalent
The peak-to-peak noise can also be taken directly from the
• Power supply: +6 V, or +6 V “wall wart” sample set by simply taking the difference between the largest
and smallest sample. In practice, the results obtained using this
method were approximately the same as the value obtained by CN-0102 Circuit Note, Precision Weigh Scale Design Using the
multiplying the rms value by 6.6. AD7190 24-Bit Sigma-Delta ADC with Internal PGA,
The values obtained from the sample set are in LSBs, so they Analog Devices.
must be converted into voltage, where 1 LSB = 0.596 µV for a CN-0107 Circuit Note, Weigh Scale Design Using the AD7780
5 V reference. 24-Bit Sigma-Delta ADC with Internal PGA, Analog
If desired, the results of several sample sets can be averaged to Devices.
get a more accurate measurement. CN-0108 Circuit Note, Weigh Scale Design Using the AD7781
Noise-free code resolution is calculated from the peak-to-peak 20-Bit Sigma-Delta ADC with Internal PGA, Analog
noise as described previously in this circuit note. Devices.
CN-0118 Circuit Note, Precision Weigh Scale Design Using the
LEARN MORE AD7191 24-Bit Sigma-Delta ADC with Internal PGA,
Kester, Walt. 1999. Sensor Signal Conditioning. Section 2. Analog Devices.
Analog Devices.
CN-0119 Circuit Note, Precision Weigh Scale Design Using the
Kester, Walt. 1999. Sensor Signal Conditioning. Section 3. AD7192 24-Bit Sigma-Delta ADC with Internal PGA,
Analog Devices. Analog Devices.
Kester, Walt. 1999. Sensor Signal Conditioning. Section 4. CN-0155 Circuit Note, Precision Weigh Scale Design Using a 24-
Analog Devices. Bit Sigma-Delta ADC with Internal PGA and AC Excitation,
MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of Analog Devices.
AD7791 Data Sheet
ADA4528-1 Data Sheet
MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC
Advanced Concepts and Applications, Analog Devices. ADP3301 Data Sheet
MT-031 Tutorial, Grounding Data Converters and Solving the CN-0216 Circuit Evaluation Board (EVAL-CN0216-SDPZ)
Mystery of "AGND" and "DGND", Analog Devices. System Demonstration Platform (EVAL-SDP-CB1Z)
MT-063 Tutorial, Basic Three Op Amp In-Amp Configuration,
Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices. REVISION HISTORY
Wong, Vicky, AN-1114 Application Note, Lowest Noise Zero- 9/11—Revision 0: Initial Version
Drift Amplifier Has 5.6 nV/√Hz Voltage Noise Density,
Analog Devices.

CN10164-0-9/11(0)
Circuit Note
CN-0237
ADA4940-1/ Single/Dual, Ultralow Power, Low
Circuits from the Lab® reference designs are engineered and ADA4940-2 Distortion Differential ADC Driver
analog, mixed-signal, and RF design challenges. For more AD7982 18-Bit, 1 MSPS PulSAR ADC
information and/or support, visit www.analog.com/CN0237.
Ultralow Noise XFET Voltage Reference
ADR435
with Current Sink and Source Capability
Ultralow Power, 18-Bit, Differential PulSAR ADC Driver

EVALUATION AND DESIGN SUPPORT CIRCUIT DESCRIPTION
Design and Integration Files Modern high resolution SAR ADCs, such as the AD7982 18-bit,
Schematics, Layout Files, Bill of Materials 1 MSPS PulSAR® ADC, require a differential driver for optimum
performance. In such applications, the ADC driver takes either
a differential or single-ended signal and performs the level
The circuit shown in Figure 1 uses the ultralow power AD7982 shifting required to drive the input of the ADC at the right level.
18-bit, 1 MSPS analog-to-digital converter (ADC) driven by
Figure 1 shows the ADA4940-1 differential amplifier level
the ADA4940-1, a low power fully differential amplifier. The
shifting and driving the 18-bit AD7982 differential input
ADR435 low noise precision 5.0 V voltage reference is used to
successive approximation PulSAR ADC. Using four resistors,
supply the 5 V needed for the ADC. All the ICs shown in Figure 1
the ADA4940-1 can either buffer the signal with a gain of 1 or
are available in small packages, either 3 mm × 3 mm LFCSP or
amplify the signal for more dynamic range. The ac and dc
3 mm × 5 mm MSOP, which helps to reduce board cost and space.
performances are compatible with those of the AD7982 18-bit,
Power dissipation of the ADA4940-1 in the circuit is typically 1 MSPS PulSAR® ADC and other 16-bit and 18-bit members of
6.25 mW. The 18-bit, 1 MSPS AD7982 ADC consumes only the family, which have sampling rates of up to 2 MSPS. This
7 mW at 1 MSPS. This power also scales with the throughput. circuit can also accept a single-ended input signal to generate
The ADR435 consumes only 4.7 mW, making the total power the same fully differential output signal.
dissipated by the system less than 18 mW.
+7.5V
ADR435
R3 R4 +5V
1kΩ 1kΩ
VIN+ 10µF
+5.0V +2.5V
+IN
–OUT 22Ω REF VDD
IN–
+2.5V 2.7nF
VOCM AD7982
+OUT 2.7nF
0.1µF IN+
22Ω GND
–IN
ADA4940-1
SERIAL
R1 INTERFACE
1kΩ
10144-001
VIN–
R2
1kΩ
Figure 1. High Performance 18-Bit Differential ADC Driver (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. A
Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog
Devices engineers. Standard engineering practices have been employed in the design and
construction of each circuit, and their function and performance have been tested and verified in a lab
environment at room temperature. However, you are solely responsible for testing the circuit and
determining its suitability and applicability for your use and application. Accordingly, in no event shall One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Tel: 781.329.4700 www.analog.com
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) Fax: 781.461.3113 ©2011–2015 Analog Devices, Inc. All rights reserved.
The AD7982 operates on a single VDD supply of 2.5 V. It For the tests on this circuit, the signal generator provided a
contains a low power, high speed, 18-bit sampling ADC and a 10 V p-p differential output. The VOCM input is bypassed for
versatile serial interface port. The reference voltage (REF) is noise reduction and set externally with 1% resistors to maximize
applied externally from the ADR435 precision low dropout the output dynamic range on the 5 V reference. With an output
(0.3 V) band gap reference, and can be set independently of the common-mode voltage of 2.5 V, each ADA4940-1 output
supply voltage. swings between 0 V and 5 V, opposite in phase, providing a gain
The ADA4940-1 operates from a 5 V single supply and offers of 1 and a 10 V p-p differential signal to the ADC input.
sufficient headroom on the outputs, which swing from 0 V to The FFT performance is shown in Figure 3 and is summarized as
5 V with a 2.5 V common-mode and accommodate a full-scale follows:
input to the ADC. The ADA4940-1 is dc-coupled on the input
 Dynamic range = 97.33 dB
and the output, and its outputs drive the inputs of the AD7982.
 SNR = 96.67 dBFS
It also allows single-ended to differential conversion if needed.
 SINAD = 96.52 dBFS
The gain is set by the ratio of the feedback resistor (R2 = R4) to  THD = −111.03 dBFS
the gain resistor (R1 = R3). For R1 = R2 = R3 = R4 = 1 kΩ, the
single-ended input impedance is approximately 1.33 kΩ. In Figure 2 shows the typical INL and DNL performance of the
addition, the circuit can be used to convert either single-ended AD7982.
or differential inputs to a differential output. If needed, a
termination resistor in parallel with the input can be used.
Whether the input is a single-ended input or differential input,
the input impedance of the amplifier can be calculated as shown
in the MT-076 Tutorial and in the DiffAmpCalc™ Differential
Amplifier Calculator (www.analog.com/DiffAmpCalc).
A single-pole, 2.7 MHz, RC (22 Ω, 2.7 nF) noise filter is placed
between the op amp output and the ADC input to help limit the
10144-002
noise at the ADC input and to reduce the effect of kickbacks
coming from the capacitive DAC input of the SAR ADC.
Figure 2. INL and DNL Plot for 20 kHz Signal, with Sampling Frequency of
1 MSPS (Min/Max INL = +1.6 LSB/−1.1 LSB and DNL = ±0.5 LSB)
10144-003
Figure 3. FFT Plot for 1 kHz Signal, 0.5 dB Below Full Scale, with Sampling Frequency of 1 MSPS
COMMON VARIATIONS Equipment Needed
The circuit is proven to work with good stability and accuracy In addition to the two evaluation boards, external 5 V power
with the component values shown. Other ADCs can be used supplies are required for the ADA4940-1. A wall wart supplies
in place of the AD7982 to achieve the maximum desired the 9 V dc voltage for the EVAL-SDP-CB1Z. Other appropriate
performance. The ADA4940-1/ADA4940-2 are optimal for voltages are supplied to the AD7982 evaluation board from the
driving 16-bit and 18-bit ADCs with minimal degradation in EVAL-SDP-CB1Z.
performance. Faster sampling 18-bit ADCs include the AD7984 A low distortion signal source, the Audio Precision® SYS-2702,
(1.33 MSPS) and AD7986 (2 MSPS). Differential 16-bit ADCs was used to achieve the required performance. A PC with
include the AD7688 (500 kSPS) and the AD7693 (500 kSPS). Windows® XP or Windows 7 equipped with an USB port was
The ADA4940-1/ADA4940-2 rail-to-rail outputs can be driven to used to run the PulSAR evaluation software.
within 0.5 V of each power rail without significant ac performance
Getting Started
degradation. Other differential ADC drivers such as the AD8137
and ADA4941-1 can also be used to replace the ADA4940-1 for Install the evaluation software as described at the EVAL-SDP-
applications when speed, input impedance, or other factors dictate. CB1Z and EVAL-AD7982SDZ product pages.
CIRCUIT EVALUATION AND TEST Connect the ADA49xx-1 EVAL-BRDZ, EVAL-AD7982SDZ,

and EVAL-SDP-CB1Z boards together as shown in Figure 5.
This circuit was tested using a EVAL-AD7982SDZ PulSAR
Connect a 9 V wall wart to the EVAL-AD7982SDZ, connect the
AD7982 evaluation board connected to the EVAL-SDP-CB1Z
USB cable to EVAL-SDP-CB1Z, and connect the external 5 V
system demonstration platform.
power supply to the ADA49xx-1 EVAL-BRDZ.
The EVAL-AD7982SDZ is a user evaluation board intended to
For more information on differential amplifier evaluation
ease standalone testing of performance and functionality for the
boards like the ADA49xx-1 EVAL-BRDZ, see the UG-132.
18-bit AD7982 PulSAR ADC.
The EVAL-SDP-CB1Z board is a platform intended for use in Setup and Test
evaluation, demonstration, and development of systems using An Audio Precision SYS-2702 source was used to provide the
Analog Devices, Inc. precision converters. It provides the input signal to the EVAL-AD7982SDZ. The PulSAR evaluation
necessary communications between the converter and the PC, software was used to monitor the ADC output results.
programming or controlling the device, transmitting or receiving
data over a USB link as shown in Figure 4 and Figure 5.
10144-004
Figure 4. PulSAR ADC Evaluation Platform
5V POWER 9V WALL
SUPPLY SUPPLY
5V 9V
VIN+
PC WITH
AUDIO USB
AD49xx-1 SDP FFT
PRECISION VIN– EVAL-AD7982SDZ
EVAL-BRDZ BOARD ANALYSIS
SYS-2702
SOFTWARE
10144-005
120-PIN
CONNECTOR
Figure 5. Test Setup Functional Block Diagram

CN-0237 Design Support Package: ADA4940-1 Data Sheet
www.analog.com/CN0237-DesignSupport ADA4940-2 Data Sheet
DiffAmpCalc™ Differential Amplifier Calculator ADA4940 Evaluation Board
Ardizzoni, John. A Practical Guide to High-Speed Printed-Circuit- AD7982 Data Sheet
Board Layout, Analog Dialogue 39-09, September 2005.
MT-031 Tutorial. Grounding Data Converters and Solving the
ADR435 Data Sheet
Mystery of “AGND” and “DGND”. Analog Devices.
MT-074 Tutorial. Differential Drivers for Precision ADCs. REVISION HISTORY
Analog Devices. 2/15—Rev. 0 to Rev. A
MT-075 Tutorial. Differential Drivers for High Speed ADCs Reorganized Layout............................................................ Universal
Overview. Analog Devices. Changes to Circuit Function and Benefits Section and Figure 1 .....1
Changes to Circuit Description Section, Figure 2, and Figure 3 ......2
MT-076 Tutorial. Differential Driver Analysis. Analog Devices.
Changes to Circuit Evaluation and Test Section, Figure 4, and
MT-101 Tutorial. Decoupling Techniques. Analog Devices. Figure 5 ................................................................................................3
(Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors.
While you may use the Circuits from the Lab reference designs in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual
property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the
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noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties
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CN10144-0-2/15(A)
Circuit Note
CN-0241
Circuits from the Lab™ reference circuits are engineered and ADA4096-2 30 V, Micropower, Overvoltage Protection,
tested for quick and easy system integration to help solve today’s Rail-to-Rail Input/Output Amplifier
analog, mixed-signal, and RF design challenges. For more AD7920 250 kSPS, 12-bit, 250 kSPS ADC in 6-Lead SC70
High Accuracy Ultralow IQ 500 mA anyCAP®
ADP3336
Adjustable Low Dropout Linear Regulator
High-Side Current Sensing with Input Overvoltage Protection
EVALUATION AND DESIGN SUPPORT in Figure 1, uses the overvoltage protected ADA4096-2 op amp
Circuit Evaluation Boards connected as a difference amplifier to monitor the high-side
CN-0241 Circuit Evaluation Board (EVAL-CN0241-SDPZ) current. The ADA4096-2 has input overvoltage protection,
System Demonstration Platform (EVAL-SDP-CB1Z) without phase reversal or latch-up, for voltages of 32 V higher
Design and Integration Files than and lower than the supply rails.
Schematics, Layout Files, Bill of Materials The circuit is powered by the ADP3336 adjustable low dropout
500 mA linear regulator, which can also be used to supply power to
other parts of the system, if desired. Its input voltage can range
High-side current monitors are likely to encounter overvoltage from 5.2 V to 12 V when set for a 5 V output. To save power,
conditions from transients or when the monitoring circuits are the current sensing circuit can be powered down by removing
connected, disconnected, or powered down. This circuit, shown power to the ADP3336; however, the power source, such as a
solar panel, can still operate.
+5V
*SEE TEXT 20kΩ
+5V* VDD
VA 1kΩ
SCLK
+5V/2.5A +V VOUT R
INPUT 0.1Ω 1kΩ VIN AD7920 SDATA
–V
SUPPLY C CS
VB
20kΩ GND
2Ω ADA4096-2 OPTIONAL FILTER

LOAD
SDP BOARD
ADP3336 +5V
+6V IN IN OUT
1µF 210kΩ 470pF 1µF
FB
SD
64.9kΩ
GND
10155-001
Figure 1. High-Side Current Sensing with Input Overvoltage Protection (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. A
VCC
R1 R2 R5 R7
I1 I3
D6 D10 Q20
Q5 Q6 Q11 Q12
D3 C2 D9 Q18
Q3 Q4
OUT
Q13 Q14
D4 Q7 Q8 C1
Q9 Q10 D8 Q17
×1 Q19
+IN OVP Q1 Q2 R6
D2 I2 Q16
–IN OVP R3 R4 Q15 D7
D11
10155-002
D1
VEE
Figure 2. ADA4096-2 Simplfied Schemactic
This applies voltage to the inputs of the unpowered ADA4096-2; Figure 3 shows the input current limiting capability of the
however, no latch-up or damage occurs for input voltages up to ADA4096-2 provided by low RDSON internal series FETs (green
32 V. If slower throughput rates are required, the AD7920 can curves) compared to using a 5 kΩ external series resistor with
also be powered down between samples. The AD7920 draws a an unprotected op amp (red curves).
maximum of 5 µW when powered down and 15 mW when Figure 3 was generated with the ADA4096-2 in a unity-gain
powered up. The ADA4096-2 requires only 120 µA under buffer configuration with the supplies connected to GND (or
operational conditions. When operating at 5 V, this is only ±15 V) and the positive input swept until it exceeds the supplies
0.6 mW. The ADP3336 draws only 1 µA in the shutdown mode. by 32 V. In general, input current is limited to 1 mA during positive
CIRCUIT DESCRIPTION overvoltage conditions and 200 μA during negative undervoltage
The circuit is a classic high-side current sensing circuit topology conditions. For example, at an overvoltage of 20 V, the ADA4096-2
with a single sense resistor. The other four resistors (dual 1 kΩ/ input current is limited to 1 mA, providing a current limit
20 kΩ divider) are in a thin film network (for ratio matching) equivalent to a series 20 kΩ resistor.
and are used to set the difference amplifier gain. This amplifies 7
VCC = +15V
VEE = –15V
6
VEE = 0V
the difference between the two voltages seen across the sense 5
resistor and rejects the common-mode voltage. 4
INPUT BIAS CURRENT (mA)
VOUT = (VA − VB) (20 kΩ/1 kΩ) 3

2
Figure 2 shows a simplified schematic of the ADA4096-2. The 1
input stage comprises two differential pairs (Q1 to Q4 and Q5 to 0
Q8) operating in parallel. When the input common-mode voltage –1

–2
approaches VCC − 1.5 V, Q1 to Q4 shut down as I1 reaches its
–3
minimum voltage compliance. Conversely, when the input –4
common-mode voltage approaches VEE + 1.5 V, Q5 to Q8 shut –5
down as I2 reaches its minimum voltage compliance. This topology –6
LOW RDSON SERIES FET
5kΩ SERIES RESISTOR
allows for maximum input dynamic range because the amplifier –7
10155-003
–48 –40 –32 –24 –16 –8 0 8 16 24 32 40 48

can function with its inputs at 200 mV outside the rail (at room VIN (V)
temperature). Figure 3. Input Current Limiting Capability
As with any rail-to-rail input amplifier, VOS mismatch between
Figure 3 also shows that the current limiting circuitry is active
the two input pairs determines the CMRR of the amplifier. If the
whether the amplifier is powered or not.
input common-mode voltage range is within 1.5 V of each rail,
transitions between the input pairs are avoided, thus improving Figure 3 represents input protection under abnormal conditions
the CMRR by approximately 10 dB. only. The correct amplifier operation input voltage range (IVR)
is specified in Table 2 to Table 4 of the ADA4096-2 data sheet.
The ADA4096-2 inputs are protected from input voltage excursions
up to 32 V outside each rail. This feature is of particular importance The AD7920 is a 12-bit, high speed, low power, successive
in applications with power supply sequencing issues that can cause approximation ADC. The part operates from a single 2.35 V to
the signal source to be active before the supplies to the amplifier 5.25 V power supply and features throughput rates up to 250 kSPS.
are applied. The part contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled 10000
using CS and the serial clock, SCLK, allowing the devices to 9000 8818
interface with microprocessors or DSPs. The input signal is 8000
NUMBER OF OCCURANCES
sampled on the falling edge of CS, and the conversion is initiated at 7000
this point. There are no pipeline delays associated with the part. 6000
The AD7920 uses advanced design techniques to achieve very 5000

low power dissipation at high throughput rates. 4000
To enter power-down mode, the conversion process must be 3000
interrupted by bringing CS high anywhere after the second falling 2000
edge of SCLK, and before the tenth falling edge of SCLK. 1005
1000
Once CS is brought high in this window of SCLKs, the part 177
0
enters power-down mode, the conversion that was initiated by the
10155-004
2309 2310 2311
falling edge of CS is terminated, and SDATA goes back into CODE
three-state. If CS is brought high before the second SCLK falling Figure 4. Histogram of Codes for 10,000 Samples Before Power Down
edge, the part remains in normal mode and does not power The SD shutdown pin connected to the ADP3336 was then
down. This avoids accidental power down due to glitches on asserted low in the software causing the output of the LDO to
the CS line. turn off. After approximately 1 minute, the shutdown pin on the
To exit this mode of operation and power up the AD7920 again, ADP3336 was then asserted high, turning the output back on,
a dummy conversion is performed. On the falling edge of CS, and the same number of data samples were acquired. Figure 5
the device begins to power up and continues to power up as long shows the results of this acquisition.
as CS is held low until after the falling edge of the tenth SCLK. 10000
9081
The device is fully powered up once 16 SCLKs have elapsed, and 9000
valid data results from the next conversion. 8000

NUMBER OF OCCURANCES
If CS is brought high before the tenth SCLK falling edge, the 7000
AD7920 goes back into power-down mode again. This avoids 6000
accidental power up due to glitches on the CS line or an inadvertent 5000
burst of eight SCLK cycles while CS is low. Although the device 4000
can begin to power up on the falling edge of CS, it powers down
3000
again on the rising edge of CS as long as it occurs before the tenth
2000
SCLK falling edge.
1000
Further details regarding the timing can be found in the AD7920 530 388
0
data sheet.
10155-005
2309 2310 2311
CODE
Test Results
Figure 5. Histogram of Codes for 10,000 Samples After Power Down
An important measure of the performance of the circuit is the
amount of noise in the final output voltage measurement. Figure 5 shows that the output of the ADA4096-2 did not latch
during power down when the input was held high.
Figure 4 shows a histogram of 10,000 measurement samples.
This data was taken with the CN-0241 Evaluation Board connected A complete design support package for this circuit note can be
to the EVAL-SDP-CB1Z SDP-B evaluation board. Details of the found at www.analog.com/CN0241-DesignSupport.
setup are described in the Circuit Evaluation and Test section. COMMON VARIATIONS
The power supply was set to 3.0 V, and 10,000 samples of data The circuit is proven to work with good stability and accuracy.
were acquired at the maximum rate of 250 kSPS without having This board is also compatible with the SDP-S controller board
turned the output of the LDO off. Figure 4 shows the results of (EVAL-SDP-CS1Z).
this acquisition. The peak-to-peak noise is approximately 2 LSBs,
A slight modification to the circuit shown in Figure 1 allows
corresponding to about 0.3 LSB rms.
monitoring the current for input supply voltages up to 30 V. Rather
than connect the +V pin of the ADA4096-2 to 5 V from the
ADP3336, connect it directly to the input supply being monitored.
In this configuration, the ADA4096-2 is powered directly from
the input supply.
CIRCUIT EVALUATION AND TEST Setup
This circuit uses the EVAL-CN0241-SDPZ circuit board and Connect the 120-pin connector on the EVAL-CN0241-SDPZ
the EVAL-SDP-CB1Z SDP-B controller board. The two boards circuit board to the CON A connector on the EVAL-SDP-CB1Z
have 120-pin mating connectors, allowing for the quick setup controller (SDP-B) board. Use Nylon hardware to firmly secure
and evaluation of the performance of the circuit. The EVAL- the two boards, using the holes provided at the ends of the 120-pin
CN0241-SDPZ board contains the circuit to be evaluated, as connectors. With power to the supply off, connect a 6 V power
described in this note, and the SDP-B controller board is used supply to the +6 V and GND pins on the board. If available, a
with the CN0241 evaluation software to capture the data from 6 V wall wart can be connected to the barrel connector on the
the EVAL-CN0241-SDPZ circuit board. board and used in place of the 6 V power supply. Connect the
USB cable supplied with the SDP-B board to the USB port on
Equipment Needed
the PC. Do not connect the USB cable to the mini-USB connector
The following equipment is needed: on the SDP-B board at this time.
• A PC with a USB port and Windows® XP, Windows Vista®, Connect the 5 V/2.5 A dc supply to +VIN and GND on J1 of
or Windows® 7 (32-bit) the EVAL-CN0241-SDPZ board. Connect the 2 Ω/12 W load
• EVAL-CN0241-SDPZ circuit evaluation board resistor to LOAD and GND of the EVAL-CN0241-SDPZ board.
• EVAL-SDP-CB1Z SDP-B controller board
Test
• CN0241 SDP evaluation software
Apply power to the 6 V supply (or wall wart) connected to the
• DC power supply capable of driving 6 V/1 A
EVAL-CN0241-SDPZ circuit board. Launch the evaluation
• DC power supply capable of driving 5 V/2.5 A
software and connect the USB cable from the PC to the USB
• 2 Ω/12 W load resistor
miniconnector on the SDP-B board.
Getting Started Once USB communications are established, the SDP-B board
can be used to send, receive, and capture serial data from the
Load the evaluation software by placing the CN0241 evaluation
EVAL-CN0241-SDPZ board.
software CD in the CD drive of the PC. Using My Computer,
locate the drive that contains the evaluation software. Turn the 5 V/2.5 A dc supply on when data is ready to be acquired.
Adjust the voltage output accordingly to output the amount of
current needed to be measured.
See Figure 1 of this circuit note for the circuit block diagram and
Figure 6 shows a screenshot of the CN0241 SDP evaluation
the EVAL-CN0241-SDPZ-SCH-RevA.pdf file for the circuit
software interface, and Figure 7 shows a screenshot of the
schematics. This file is contained in the CN0241 Design
Support Package. EVAL-CN0241-SDPZ evaluation board. Information regarding
the SDP-B board can be found in the SDP-B User Guide.
10155-006
Figure 6. CN-0241 SDP Evaluation Software Interface
TO PC
LOAD
INPUT
SUPPLY
USB
EVAL-CN0241-SDPZ
EVAL-SDP-CB1Z
6V SUPPLY
10155-007
Figure 7. EVAL-CN0241-SDPZ Evaluation Board Connected to the SDP Board
CN0241 Design Support Package: CN-0241 Circuit Evaluation Board (EVAL-CN0241-SDPZ)
http://www.analog.com/CN0241-DesignSupport System Demonstration Platform (EVAL-SDP-CB1Z)
SDP-B User Guide ADA4096-2 Data Sheet
Ardizzoni, John. A Practical Guide to High-Speed Printed- AD7920 Data Sheet
Circuit-Board Layout, Analog Dialogue 39-09, September
ADP3336 Data Sheet
2005.
MT-031 Tutorial, Grounding Data Converters and Solving the REVISION HISTORY
Mystery of “AGND” and “DGND”, Analog Devices. 5/12—Rev. 0 to Rev. A
Changes to Circuit Function and Benefits Section and Figure 1 ......1
MT-035, Op Amp Inputs, Outputs, Single-Supply, and Rail-to-
Changes to Figure 6 ...........................................................................5
Rail Issues, Analog Devices.
MT-036 Tutorial, Op Amp Output Phase-Reversal and Input 1/12—Revision 0: Initial Version
Over-Voltage Protection, Analog Devices.
MT-068 Tutorial, Difference and Current Sense Amplifiers,
Analog Devices.

CN10155-0-5/12(A)
Circuit Note
CN-0326
3-Channel, Low Noise, Low Power,
Circuits from the Lab™ reference circuits are engineered and AD7793
24-Bit Sigma Delta ADC
analog, mixed-signal, and RF design challenges. For more Quad-Channel Isolators with
ADuM5401
information and/or support, visit www.analog.com/CN0326. Integrated DC/DC Converter
MicroPower RRIO Low Noise
AD8603
Precision Single CMOS Op Amp
Isolated Low Power pH Monitor with Temperature Compensation

EVALUATION AND DESIGN SUPPORT The circuit gives 0.5% accurate readings for pH values from 0 to
Circuit Evaluation Boards 14 with greater than 14-bits of noise-free code resolution and is
CN0326 Evaluation Board (EVAL-CN0326-PMDZ) suitable for a variety of industrial applications such as chemical,
System Demonstration Platform (EVAL-SDP-CB1Z) food processing, water, and wastewater analysis.
SDP PMOD Interposer Board (SDP-PMD-IB1Z) This circuit supports a wide variety of pH sensors that have very
Design and Integration Files high internal resistance that can range from 1 MΩ to several
Schematics, Layout Files, Bill of Materials GΩ, and digital signal and power isolation provides immunity
CIRCUIT FUNCTION AND BENEFITS to noise and transient voltages often encountered in harsh
industrial environments.
The circuit shown in Figure 1 is a completely isolated low power
pH sensor signal conditioner and digitizer with automatic
temperature compensation for high accuracy.
3.3VISO
FERRITE BEAD: BEAD

MURATA BLM21PG331SN1D
3.3VISO 3.3V
AVDD DVDD
210µA
IOUT2
10kΩ VISO VDD1
AIN2(+)
1µF
TO
Pt1000 3.3VISO CS VOA VIA CS
RTD pH SENSOR AD7793
1MΩ
P1 J1 10kΩ SCLK VOB VIB SCLK
AD8603 AIN1(+)
1µF DIN DIN
VOC VIC
AIN1(–)
AIN2(–) DOUT/
VID VOD DOUT/RDY
10kΩ RDY
RFIN(+)/AIN3(+)
5kΩ 1µF
RFIN(–)/AIN3(–) GNDISO GND1
GND
ADUM5401
11821-001
GNDISO
Figure 1. pH Sensor Circuit (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
CIRCUIT DESCRIPTION Circuit Details
Fundamentals of pH Measurements The design provides a complete solution for pH sensor with
The pH value is a measure of the relative amount of hydrogen temperature compensation. The circuit has three critical stages:
and hydroxide ions in an aqueous solution. In terms of molar the pH probe buffer, the ADC, and the digital and power
concentrations, water at 25°C contains 1 × 10−7 moles/liter of isolator as shown in Figure 1.
hydrogen ions and the same concentration of hydroxide ions. A The AD8603, a precision micro power (50 μA maximum) and
neutral solution is one in which the hydrogen ion concentration low noise (22 nV/√Hz) CMOS operational amplifier configured
exactly equals the hydroxide ion concentration. pH is another as a buffer to the input of one of the channels of the AD7793.
way of expressing the hydrogen ion concentration and is The AD8603 has a typical input bias current of 200 fA that
defined as follows: provides an effective solution to the pH probe that has high
pH  – log( H  )
internal resistance.
The pH sensing and temperature compensation system is based on
Therefore, if the hydrogen ion concentration is 1.0 × 10−2
the AD7793, 24-bit sigma-delta (Σ-Δ) with. It has three differential
moles/liter, the pH is 2.00.
analog inputs and has an on-chip, low noise, programmable gain
The pH electrodes are electrochemical sensors used by many amplifier (PGA) that ranges from unity gain to 128. The AD7793
industries but are of particular importance to the water and waste- consumes only a maximum of 500 μA making it suitable for any
water industry. The pH probe consists of a glass measuring low power applications. It has a low noise, low drift internal band
electrode and a reference electrode, which is analogous to a battery. gap reference and can accept external differential reference. The
When the probe is place in a solution, the measuring electrode output data rate from the part is software programmable and
generates a voltage depending on the hydrogen activity of the can be varied from 4.17 Hz to 470 Hz.
solution, which is compared to the potential of the reference
electrode. As the solution becomes more acidic (lower pH) the The ADuM5401, quad-channel digital isolator with an
integrated dc-to-dc converter provides the digital signal and
potential of the glass electrode becomes more positive (+mV) in
power isolation between the microcontroller and the AD7793
comparison to the reference electrode; and as the solution becomes
digital lines. The iCoupler chip-scale transformer technology is
more alkaline (higher pH) the potential of the glass electrode
becomes more negative (−mV) in comparison to the reference used to isolate the logic signals and the power feedback path in
the dc-to-dc converter.
electrode. The difference between these two electrodes is the meas-
ured potential. A typical pH probe ideally produces 59.154 mV/pH Buffer for pH Sensor Interface
units at 25oC. This is expressed in the Nernst equation as follows The electrode of a typical pH probe is made up of glass that
2.303 R  T  273.1  creates an extremely high resistance that can range from 1 MΩ
Ea–   pH – pH ISO  to 1 GΩ and acts as a resistance in series with the pH voltage
nF
source as shown in Figure 2.
where:
210µA
E = voltage of the hydrogen electrode with unknown activity IOUT2
ܽ = ±30 mV, zero point tolerance pH SENSOR

IBIAS
3.3VISO AD7793
J1
T = ambient temperature in oC 1GΩ
10kΩ
pH 1MΩ AD8603 AIN1(+)
n = 1 at 25 oC, valence (number of charges on ion) VOUT
1µF
F = 96485 coulombs/mol, Faraday constant AIN1(–)
AIN2(–)
R = 8.314 volt-coulombs /°K mol, Avogadro's number 10kΩ
RFIN(+)/AIN3(+)
+1.05V
pH = hydrogen ion concentration of an unknown solution 5kΩ
1µF
RFIN(–)/AIN3(–)
pHISO = 7, reference hydrogen ion concentration GND

11821-002
The equation shows that the voltage generated is dependent on

Figure 2. pH Sensor and Buffer Interface to ADC (Simplified Schematic: All
the acidity or alkalinity of the solution and varies with the hydrogen Connections, RTD, and Decoupling Not Shown.)
ion activity in a known manner. The change in temperature of
the solution changes the activity of its hydrogen ions. When the The buffer amplifier bias current flowing through this series
solution is heated, the hydrogen ions move faster which result resistance introduces an offset error in the system. To isolate the
in an increase in potential difference across the two electrodes. circuit from this high source resistance, a buffer amplifier with
In addition, when the solution is cooled, the hydrogen activity high input impedance and very low input bias current is needed
decreases causing a decrease in the potential difference. Electrodes for this application. The AD8603 is used as a buffer amplifier for
are designed ideally to produce a zero volt potential when this application as shown in Figure 2. The low input current of
placed in a buffer solution with a pH of 7. the AD8603 minimizes the voltage error produced by the bias
current flowing through the electrode resistance.
A good reference on the theory of pH is pH Theory and Practice,
Radiometer Analytical SAS, Villeurbanne Cedex, France.
For 200 fA typical input bias current, the offset error is 0.2 mV Table 2. Standard RTD Accuracy for DIN-43760
(0.0037 pH) for a pH probe that has 1 GΩ series resistance at Class Tolerance
25oC. Even at the maximum input bias current of 1 pA, the DIN 43760 Class A ±0.06% @ 0°C
error is only 1 mV. DIN 43760 Class B ±0.12% @ 0°C
The cut-off frequency of the 10 kΩ/1 µF low pass noise filter for
the buffer amplifier output is given by f= 1/2πRC, or 16 Hz. Table 3. Standard RTD Accuracy for ASTM E-1137
Guarding, shielding, high insulation resistance standoffs, and Grade Tolerance
other such standard picoamp methods must be used to minimize ASTM E-1137 Grade A ±0.05% @ 0°C
leakage at the high impedance input of the AD8603 buffer. ASTM E-1137 Grade B ±0.10% @ 0°C
ADC Channel 1 Configuration, pH sensor
The RTD resistance value can be computed as
This stage involves measuring the small voltage generated by
the pH electrode. Table 1 shows the specifications of a typical RTD Resistance = RTD 0 (1 + T α )
pH probe. Based on the Nernst equation, the full range voltage where:
from the probe can range from ±414 mV (±59.14 mV/pH) at RTD Resistance = Resistance value at T
25°C to ±490 mV (±70 mV/pH) at 80°C. RTD0 = Resistance value at 0°C
Table 1. Specifications of a Typical pH Probe T = ambient temperature
α = 0.00385 Ω/Ω/°C, temperature coefficient defined by DIN
Measurement Range pH 0 to pH 14
Std. 43760-1980 and IEC 751-1983
pH at zero voltage pH 7.00 ± 0.25
Accuracy pH 0.05 in the range from 20°C to The RTD resistance varies from 0°C (1000 Ω) to 100°C (1385 Ω),
25°C producing a voltage signal range of 210 mV to 290 mV with
Resolution pH 0.01 210 µA excitation current.
0.1 mV
The precision 5 kΩ resistor generates the 1.05 V used as an
Operating Temperature Maximum 80°C
external reference. With a gain of one, the analog input range is
Reaction time ≤ 1 sec for 95% of final value
±1.05 V (±VREF/G). This architecture gives a ratiometric
configuration. Changes in the value of the excitation current do
When reading the pH probe output voltage, the ADC uses the not affect the accuracy of the system.
external 1.05 V reference and is configured with a gain of 1. The
full-scale input range is ±VREF/G = ±1.05 V, and the maximum Although 100 Ω Pt RTDs are popular, other resistances (200 Ω,
signal from the pH probe is ±490 mV at 80°C. 500 Ω, 1000 Ω, etc.) and materials (Nickel, Copper, Nickel Iron)
can be specified. This application uses a 1 kΩ DIN 43760 Class A
Because the output of the sensor is bipolar, and the AD7793 RTD for temperature compensation of the pH sensor. A 1000 Ω
operates from a single power supply, the signal generated by the RTD is less sensitive to wiring resistance errors than a 100 Ω RTD.
pH probe should be biased above ground so that it is within the
acceptable common-mode range of the ADC. This bias voltage A 2-wire connection is made as shown in Figure 3. A constant
is generated by injecting the 210 µA IOUT2 current into the current is applied through the leads of the RTD, and the voltage
5 kΩ, 0.1% resistor as shown in Figure 2. This generates the across the RTD itself is measured. The measuring device is the
1.05 V common-mode bias voltage that also serves as the ADC AD7793 that exhibits high input impedance and low input bias
reference voltage. current. The sources of errors in this scheme are lead resistance,
the stability of the constant current source produced by AD7793,
ADC Channel 2 Configuration, RTD and the input impedance and/or bias current in the input
The second channel of the ADC monitors the voltage generated amplifier, and the associated drift.
across an RTD being driven by the IOUT2 current output pins
of the AD7793. The 210 μA excitation current drives the series
combination of the RTD and precision resistor (5 kΩ, 0.1%).
(See Figure 1).
The temperature coefficient for pure platinum is 0.003926 Ω/Ω/°C.
The normal coefficient for industrial RTDs is 0.00385 Ω/Ω/°C
per the DIN Std. 43760-1980 and IEC 751-1983. The accuracy
of an RTD is usually stated at 0°C. The DIN 43760 standard
recognizes two classes as shown in Table 2, and ASTM E–1137
recognizes two grades as shown in Table 3.
210µA
IOUT2
10kΩ
AIN2(+)
1µF
RLEAD
Pt1000 AD7793
RTD P1
DIN 43760
CLASS A
RLEAD
AIN2(–)
10kΩ
RFIN(+)/AIN3(+)
210µA 1µF
RFIN(–)/AIN3(–)
GND
5kΩ, 0.1%
11821-003
Figure 3. 2-Wire Pt RTD Connections (Simplified Schematic: All Connections
and Decoupling Not Shown)
Another possibility for eliminating wiring resistance errors is
11821-004
the 3-wire RTD configuration that is described in detail in
Circuit Note CN-0287. Figure 4. Evaluation Software Calibration Settings Window
Output Coding The user is required to use a minimum of two buffer solutions,
The output code for an input voltage on either channel is where a neutral pH buffer with a value of pH-7 should be used
to remove the offset introduced by the pH probe and by the system.
 AIN × GAIN  The neutral buffer solution can be used to set the first point for
Code = 2 N –1  +1 
  calibration. The pH of the second buffer solution depends on
 V REF  the pH of the solution to be measured. A pH-10 buffer solution
where: can be used when measuring alkaline base solutions, and a pH-
AIN is the analog input voltage. 4 buffer can be used when measuring acidic solutions. For more
GAIN is the in-amp setting. precise measurement, a three point calibration can be
N = 24 performed. This can be done by using two different sets of
The EVAL-SDP-CB1Z system demonstration platform board buffer solutions in Step 2 and in Step 3 as shown in Figure 4,
and the PC processes the data output from the AD7793. where the pH-7 solution is used to remove the offset.
Digital and Power Isolation The software includes a list of buffer solution recommended by
the NIST. Each buffer solution described in the list has its own
The ADuM5401 isolates the ADC digital signals and also
temperature coefficient from 0°C to 95°C, which can be found
supplies isolated regulated 3.3 V power to the circuit. The input
in “pH Theory and Practice” by Radiometer Analytical. The
to the ADuM5401 (VDD1) should be between 3.0 V and 3.6 V.
software uses this table to correlate the mV input from the pH
Take care with the layout of the ADuM5401 to minimize
probe to the correct pH value that correspond to the temperature
EMI/RFI problems. For more details, please refer to Application
read from the RTD sensor using linear interpolation to fill in
Note AN-1109, Recommendations for Control of Radiated
the gaps in the table. The user is given an option to enable/
Emissions with iCoupler Devices.
disable the option for continuous temperature compensation by
System Calibration clicking the green button as shown in Figure 4.
In order to accurately measure the RTD resistance, the ±5% Buffer solutions are commonly found in the market for pH
variation in the IOUT2 current must be taken into account. The sensor calibration. Other NIST-certified pH reference can also
AIN3(+) input to the AD7793 is used to measure the voltage be used for calibration. Because of the variety of buffer solutions
dropped across the precision 5 kΩ 0.1% resistor. The exact available, the software also provides the user an option to use
IOUT2 current is then determined by dividing this voltage by 5 kΩ. their desired NIST-certified pH reference for calibration as
The RTD resistance is calculated by dividing the voltage across the shown in Figure 4.
RTD by the exact IOUT2 current.
The software also provides the user an option to use other RTD
A two-point calibration procedure shown in Figure 4 is used to resistance values, but by default it is set to 1000 Ω.
calibrate the pH meter in the EVAL-CN0326-PMDZ evaluation
software.
System Noise Considerations 0.5 0.40
pH SENSOR SIMULATED OUTPUT VOLTAGE (mV)

For an output data rate of 16.7 Hz and a gain of 1, the rms noise 0.4
200MΩ 0.35
of the AD7793 equals 1.96 μV (noise is referred to input, taken 0.3

0.03
from AD7793 data sheet). The peak-to-peak noise is
LINEARITY ERROR (%)

0.2
100MΩ
1MΩ 0.25
6.6 × RMS Noise = 6.6 × 1.96 µV = 12.936 µV 0.1
If the pH meter has a sensitivity of 59 mV/pH, the pH meter 0 0.20
should measure the pH level to a noise-free resolution of –0.1

0.15
12.936 μV / (59 mV/pH) = 0.000219 pH –0.2 SIMULATED pH

OUTPUT VOLTAGE 0.10
This includes only the noise contribution of the AD7793. The –0.3
0.05
actual system results are presented in the next section. –0.4
Test Data and Results –0.5 0
11821-006
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
All data capture was performed using the CN0326 LabVIEW ADC OUTPUT pH READING (pH)
evaluation software. A Yokogawa GS200 precision voltage Figure 6. pH Sensor Simulated Output Voltage (with Associated Linearity
source was used to simulate the input of a pH sensor. Error Plot) vs. ADC Output pH Reading (Shown for Probe Resistance of
1 MΩ, 100 MΩ, and 200 MΩ)
By sweeping the precision voltage from −420 mV to +420 mV
The test data was taken using the board shown in Figure 7.
in 1 mV increments, the EVAL-CN0326-PMDZ was able to
Complete documentation for the system can be found in the
capture the data according to the user defined calibration option.
CN-0326 Design Support package.
The peak-to-peak noise of the AD8603 buffer and the AD7793
in the actual system was determined by shorting the input pH
probe BNC connector and acquiring 1000 samples. As seen by
the histogram in Figure 5, the code spread is approximately 500
codes, which translates to a peak-to-peak noise of 31.3 µV, with
an equivalent pH reading spread of 0.00053 pH peak-to-peak.
11821-007
35
30 Figure 7. Photo of EVAL-CN0326-PMDZ Board
25 COMMON VARIATIONS
Other suitable ADCs are the AD7792 and AD7785. Both parts
COUNTS
20
have the same feature set as the AD7793. However, the AD7792
15 is a 16-bit ADC while the AD7785 is a 20-bit ADC.
10
The AD8607 buffer amplifier is available in an 8-lead MSOP
package . It is a dual micropower rail-to-rail input/output
5 amplifier which is in the same family as the AD8603.
Other families of ADuM5401 includes a variety of channel
0
11821-005
6FB864 6FB900 6FB980 6FBA00 6FBA58 configuration such as the ADuM5402/ADuM5403/ADuM5404

ADC CODE
which also provides four independent isolation channels.
Figure 5. Histogram Showing Output Code Spread with AD7793 Input Pins
Shorted Together
The system was tested with three different resistors in series This circuit uses the EVAL-CN0326-PMDZ circuit board, the
with the ADC input to simulate the different impedances of the EVAL-SDP-CB1Z System Demonstration Platform (SDP)
high impedance glass electrode. The system was also calibrated evaluation board and the SDP-PMD-IB1Z, a PMOD interposer
to give 60 mV/pH. According to Figure 6, the linearity error board for the EVAL-SDP-CB1Z. The SDP and the SDP-PMD-
increases with the increase of simulated glass electrode IB1Z boards have 120-pin mating connectors, allowing the
impedance. Figure 6 also shows that over the entire simulated quick setup and evaluation of the circuit’s performance. In order
pH output voltage range, the linearity error is less than 0.5% to evaluate the EVAL-CN0326-PMDZ board using the SDP-
with for a 200 MΩ pH probe impedance. PMD-IB1Z and the SDP, the EVAL-CN0326-PMDZ is
connected to the SDP-PMD-IB1Z by a standard 100 mil-
spaced, 25 mil square, right angle pin-header connector.
Equipment Required Functional Block Diagram
The following equipment is needed: The functional block diagram of the test set-up is shown in
Figure 8. The test set-up should be connected as shown. A
• A PC with a USB port and Windows® XP and Windows®
screenshot of the main software window is shown in Figure 9.
Vista (32-bit), or Windows® 7 (32-bit)
Pt1000
• EVAL-CN0326-PMDZ circuit evaluation board RTD
• EVAL-SDP-CB1Z circuit evaluation board 6V SUPPLY PC
• SDP-PMD-IB1Z SDP interposer board P1

1MΩ
• CN0326 Evaluation Software PRECISION EVAL-CN0326-PMDZ SDP-PMD-IB1Z EVAL-SDP-CB1Z
11821-008
VOLTAGE
J1
•
SOURCE
Power supply: 6 V wall wart or equivalent
Figure 8. pH Sensor Block Diagram Test Set-up
• Yokogawa 2000 Precision DC Power Supply or
equivalent
Getting Started
Load the evaluation software by placing the CN-0326 Evaluation
Software disc in the CD drive of the PC. Using "My Computer,"
open the Readme file. Follow the instructions contained in the
Readme file for installing and using the evaluation software.
Setup
The CN0326 evaluation kit includes self-installing software on a
CD. The software is compatible with Windows® XP (SP2) and Vista
(32-bit and 64-bit). If the setup file does not run automatically,
you can run the setup.exe file from the CD.
Install the evaluation software before connecting the evaluation
board and SDP board to the USB port of the PC to ensure that
the evaluation system is correctly recognized when connected to
the PC.
11821-009
1. After installation from the CD is complete, power up the
SDP-PMD-IB1Z evaluation board as described in the Figure 9. Evaluation Software Main Window
Power Supplies Configuration section. Connect the SDP
board (via either Connector A) to the SDP-PMD-IB1Z Power Supply Configuration
evaluation board and then to the USB port of the PC The SDP-PMD-IB1Z must be supplied with 6 V dc power
that will be used for evaluation using the supplied cable. supply and its jumper, JP1, should be set to 3.3 V to give power
to the EVAL-CN0326-PMDZ.
2. Connect the 12-pin right angle male pin header of the
EVAL-CN0326-PMDZ to the 12-pin right angle female
pin header of the SDP-PMD-IB1Z.
3. Before running the program shown in Figure 9, connect
the pH probe at the BNC terminal and the RTD sensor
to the terminal jack of the EVAL-CN0326-PMDZ.
4. After all the peripherals and power supply are all
connected and turned on, click Connect on the GUI
shown in Figure 9. When the evaluation system is
successfully detected by the PC, the EVAL-CN0326-
PMDZ circuit board can now be evaluated using the
software shown in Figure 9.
Test Kester, Walt. 1999. Temperature Sensors. Section 7. Analog
Agilent E3631A and Yokogawa GS200 precision voltage supplies Devices.
were used to simulate the sensor output. The negative terminal Chen, Baoxing. 2006. iCoupler® Products with isoPower®
of the Yokogawa is connected to the negative terminal of the Technology: Signal and Power Transfer Across Isolation Barrier
ADC for the pH sensor. The positive terminal is in series with Using Microtransformers. Analog Devices.
the resistor, which is connected to the positive terminal of the
ADC as shown in Figure 8. The Yokogawa generates the Wayne, Scott. 2005. “iCoupler® Digital Isolators Protect RS-232,
±420 mV, which then simulates the pH sensor output, and the RS-485, and CAN Buses in Industrial, Instrumentation, and
series resistor is then varied to simulate the impedance of the Computer Applications.” Analog Dialogue, Volume 39. Analog
glass electrode of the pH probe as shown in Figure 8. Devices (October).
The CN-0326 Evaluation Software is used to capture the data Brian Kennedy and Mark Cantrell, Recommendations for
from the EVAL-CN0326-PMDZ circuit board using the setup Control of Radiated Emissions with iCoupler Devices,
seen in Figure 8. Application Note AN-1109, Analog Devices.
Details regarding the use of the software can be found in the pH Theory and Practice, Radiometer Analytical, SAS,
CN-0326 Software User Guide. Villeurbanne Cedex, France.
LEARN MORE AD7793 Data Sheet
CN-0326 Design Support Package:
www.analog.com/CN0326-DesignSupport
ADUM5401 Data Sheet
ADC Input Noise—Is No Noise Good Noise? Analog Devices. ADuM5401 Evaluation Board
MT-022 Tutorial, ADC Architectures III: Sigma-Delta ADC AD8603 Data Sheet
MT-023 Tutorial, ADC Architectures IV: Sigma-Delta ADC REVISION HISTORY
MT-037 Tutorial, Op Amp Input Offset Voltage.
MT-038 Tutorial, Op Amp Input Bias Current
MT-040 Tutorial, Op Amp Input Impedance
MT-095 Tutorial, EMI, RFI, and Shielding Concepts
MT-101 Tutorial, Decoupling Techniques, Analog Devices
Kester, Walt. 1999. High Impedance Sensors. Section 5. Analog
Devices.

CN11821-0-9/13(0)
Circuit Note
CN-0357
5.0 V, Ultralow Noise, Zero Drift, RRIO,
ADA4528-2
Dual Op Amp
Circuits from the Lab® reference designs are engineered and 1024-Position,1% Resistor Tolerance Error,
AD5270-20
tested for quick and easy system integration to help solve today’s 50-TP Memory Digital Rheostat
information and/or support, visit www.analog.com/CN0357. Micropower, 0.1% Accurate,1.2 Voltage
ADR3412
Reference
AD8500 Micropower, RRIO, Op Amp
AD7790 Low Power, 16-Bit Sigma-Delta, ADC
Low Noise, Single-Supply, Toxic Gas Detector, Using an Electrochemical Sensor with
Programmable Gain TIA for Rapid Prototyping
EVALUATION AND DESIGN SUPPORT The circuit shown in Figure 1 uses the ADA4528-2, dual auto
Circuit Evaluation Boards zero amplifier, which has a maximum offset voltage of 2.5 µV at
CN-0357 Circuit Evaluation Board (EVAL-CN0357-PMDZ) room temperature and an industry leading 5.6 µV/√Hz of
SDP to Pmod Interposer Board (PMD-SDP-IB1Z) voltage noise density. In addition, the AD5270-20 programmable
System Demonstration Platform (EVAL-SDP-CB1Z) rheostat is used rather than a fixed transimpedance resistor,
Design and Integration Files allowing for rapid prototyping of different gas sensor systems,
Schematics, Layout Files, and Bill of Materials without changing the bill of materials.
The ADR3412 precision, low noise, micropower reference
establishes the 1.2 V common-mode, pseudo ground reference
The circuit shown in Figure 1 is a single-supply, low noise, voltage with 0.1% accuracy and 8 ppm/°C drift.
portable gas detector, using an electrochemical sensor. The
For applications where measuring fractions of ppm gas
Alphasense CO-AX carbon monoxide sensor is used in this
concentration is important, using the ADA4528-2 and the
example.
ADR3412 makes the circuit performance suitable for interfacing
Electrochemical sensors offer several advantages for with a 16-bit ADC, such as the AD7790.
instruments that detect or measure the concentration of many
toxic gases. Most sensors are gas specific and have usable
resolutions under one part per million (ppm) of gas
concentration.
3.3V
VREF
U4 R3 U2-B REF(+) VDD

AVCC AVCC 12.4kΩ
ADR3412 R4 U1 ADA4528-2 R10 U5 1.2V
U2-A 3.3kΩ
1.2V 12.4kΩ ADA4528-2 AD8500 AIN1(–)
VIN VOUT CO-AX DOUT/RDY TO
CE WE R8 AIN1(+) PROCESSOR
GND R2 100kΩ R12 DIN
C10 C8
0.1µF 0.1µF
RE 33Ω 150Ω
C3 C4
0.02µF 0.02µF C9 U8 SCLK
Q1 10µF
MMBFJ270 C2 R9
C14 AD7790
5.6nF CS
D S 0.02µF 3.3kΩ
3.3V W A GND REF(–)
AGND
R5 R6 AGND
12.4kΩ 12.4kΩ G
U3-B
12332-001
R1 AD5270-20
1MΩ
Figure 1. Low Noise Gas Detector Circuit (Simplified Schematic: all Connections and Decoupling not Shown)
Rev. 0
Circuits from the Lab® reference designs from Analog Devices have been designed and built by Analog
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) Fax: 781.461.3113 ©2014 Analog Devices, Inc. All rights reserved.
CIRCUIT DESCRIPTION Table 1. Typical Carbon Monoxide Sensor Specifications
Figure 2 shows a simplified schematic of an electrochemical Parameter Value
sensor measurement circuit. Electrochemical sensors work by Sensitivity 55 nA/ppm to
100 nA/ppm
allowing gas to diffuse into the sensor through a membrane and
(65 nA/ppm
by interacting with the working electrode (WE). The sensor typical)
reference electrode (RE) provides feedback to Amplifier U2-A, Response Time (t90 from 0 ppm to 400 ppm CO) <30 seconds
which maintains a constant potential with the WE terminal by Range (ppm) CO, Guaranteed Performance) 0 ppm to
varying the voltage at the counter electrode (CE). The direction 2,000 ppm
of the current at the WE terminal depends on whether the Overrange Limit (Specifications Not 4,000 ppm
reaction occurring within the sensor is oxidation or reduction. Guaranteed)
In the case of a carbon monoxide sensor, oxidation takes place; The output voltage of the transimpedance amplifier is
therefore, the current flows into the working electrode, which
requires the counter electrode to be at a negative voltage (typically VO = 1.2 V + IWE × RF (1)
300 mV to 400 mV) with respect to the working electrode. The where IWE is the current into the WE terminal, and RF is the
op amp driving the CE terminal should have an output voltage transimpedance feedback resistor (shown as the AD5270-20
range of approximately ±1 V with respect to VREF to provide U3-B rheostat in Figure 1).
sufficient headroom for operation with different types of sensors The maximum response of the CO-AX sensor is 100 nA/ppm,
(Alphasense Application Note AAN-105-03, Designing a and its maximum input range is 2000 ppm of carbon monoxide.
Potentiostatic Circuit, Alphasense, Ltd.). These values result in a maximum output current of 200 μA and
IWE a maximum output voltage determined by the transimpedance
RF resistor, as shown in Equation 2.
+ VREF
nA
RE VO = 1.2 V + 2000 ppm × 100 × RF
–
CE WE ppm
VREF VOUT
IWE IWE
VO = 1.2 V + 200 µA × RF (2)
12332-002
SENSOR
Applying 1.2 V to VREF of the AD7790 allows a usable range of
Figure 2. Simplified Electrochemical Sensor Circuit ±1.2 V at the output of the transimpedance amplifier, U2-B.
The current into the WE terminal is less than 100 nA per ppm Selecting a 6.0 kΩ resistor for the transimpedance feedback
of gas concentration; therefore, converting this current into an resistor gives a maximum output voltage of 2.4 V.
output voltage requires a transimpedance amplifier with a very Equation 3 shows the circuit output voltage as a function of
low input bias current. The ADA4528-2 op amp has CMOS inputs ppm of carbon monoxide, using the typical response of the
with a maximum input bias current of 220 pA at room sensor of 65 nA/ppm.
temperature, making it a very good fit for this application. μV
VO = 1.2 V + 390 (3)
The ADR3412 establishes the pseudo ground reference for the ppm
circuit, which allows for single-supply operation while consuming The AD5270-20 has a nominal resistance value of 20 kΩ. There
very little quiescent current (100 µA maximum). are 1024 resistance positions, resulting in resistance step sizes of
Amplifier U2-A sinks enough current from the CE terminal to 19.5 Ω. The 5 ppm/°C resistance temperature coefficient of the
maintain a 0 V potential between the WE terminal and the AD5270-20 is better than that of most discrete resistors, and its
RE terminal on the sensor. The RE terminal is connected to the 1 µA of supply current is a very small contributor to the overall
inverting input of Amplifier U2-A; therefore, no current flows power consumption of the system.
in or out of it. This means that the current comes from the Resistor R4 keeps the noise gain at a reasonable level. Selecting
WE terminal and it changes linearly with gas concentration. the value of this resistor is a compromise between the magnitude of
Transimpedance Amplifier U2-B converts the sensor current into the noise gain and the sensor settling time errors, when exposed
a voltage proportional to the gas concentration. to high concentrations of gas. For the example shown in
The sensor selected for this circuit is an Alphasense CO-AX Equation 4, R4 = 33 Ω, which results in a noise gain of 183.
carbon monoxide sensor. Table 1 shows the typical 6.0 kΩ
NG = 1 + = 183 (4)
specifications associated with carbon monoxide sensors of this
general type. 33 Ω
Warning: carbon monoxide is a toxic gas, and concentrations

higher than 250 ppm can be dangerous; therefore, take extreme
care when testing this circuit.
The input noise of the transimpedance amplifier appears at the CIRCUIT EVALUATION AND TEST
output, amplified by the noise gain. For this circuit, only low The circuit shown in Figure 1 uses the EVAL-CN0357-PMDZ
frequency noise is of interest because the frequency of operation circuit evaluation board, the PMD-SDP-IB1Z interposer board,
of the sensor is very low. The ADA4528-2 has a 0.1 Hz to 10 Hz and the EVAL-SDP-CB1Z system demonstration platform (SDP-
input voltage noise of 97 nV p-p; therefore, the noise at the B) controller board. In addition, the EVAL-CN0357-PMDZ
output is 18 µV p-p, as shown in Equation 5. comes in a Pmod form factor, making it possible to connect the
VOUTPUTNOISE = 97 nV × NG = 18 µVp-p (5) board to any Pmod controller board, allowing for rapid
Because this is a very low frequency 1/f noise, the noise is very hard prototyping.
to filter. However, because the sensor response is also very slow, The CN-0357 Evaluation Software communicates with the SDP
it is possible to use a very low frequency, low-pass filter (R5 and board to capture data from the EVAL-CN0357-PMDZ circuit
C6) with a cutoff frequency of 0.16 Hz. Even with such a low evaluation board.
frequency filter, its effect on the sensor response time is Equipment Needed
negligible, when compared to the 30 second response time of
the sensor. The following equipment is needed for evaluating the
CN-0357 circuit:
The noise free code resolution of the system is determined from
the peak-to-peak output noise. The maximum output of the • PC with USB port and Windows® XP, or Windows Vista
ADA4528-2 is 2.4 V, so the noise free number of counts is (32-bit), or Windows 7 (32-bit)
• EVAL-CN0357-PMDZ evaluation board
2.4 V (6)
Total Noise Free Counts = = 64,865 • PMD-SDP-IB1Z interposer Board
18 µV p − p • EVAL-SDP-CB1Z controller board
The noise free code resolution becomes • CN-0357 Evaluation Software
• Calibration gas (less than 250 ppm)
Noise Free Code Resolution = log2(64,865) = 15.9 bits (7)
• EVAL-CFTL-6V-PWRZ or equivalent 6 VDC power
To take advantage of the entire ADC range available (±1.2 V), supply
the AD8500 micropower, rail-to-rail input/output amplifier is
chosen to drive the input of the AD7790. If the entire range is Getting Started
not necessary, the AD8500 can be removed and the internal Load the evaluation software by placing the CN-0357
buffer of the AD7790 can be used in its place. Evaluation Software CD into the CD drive of the PC. Using My
One important characteristic of electrochemical sensors is their Computer, locate the drive that contains the evaluation
very long time constant. When first powered up, it can take several software CD and run the setup.exe. Follow the on screen
minutes for the output to settle to its final value. When exposed prompts for installing and using the evaluation software.
to a midscale step in concentration of the target gas, the time Functional Block Diagram
required for the sensor output to reach 90% of its final value can A functional block diagram of the test setup is shown in Figure 3.
be in the order of 25 seconds to 40 seconds. If the voltage between There is a complete schematic of the evaluation board
the RE terminal and the WE terminal has a sudden change in contained in the CN-0357 Design Support Package, including
magnitude, it can take several minutes for the output current of printouts of the gerber files, as well as a bill of materials.
the sensor to settle. This long time constant also applies when
cycling power to the sensor. To avoid very long start-up times, PC
P-channel JFET Q1 shorts the RE terminal to the WE terminal
USB
when the supply voltage drops below the gate-to-source
threshold voltage (~2.0 V) of the JFET.
COMMON VARIATIONS
USB
Electrochemical sensors operate with very small amounts of
current, making them well suited for portable, battery-powered +6V POWER EVAL-SDP-CB1Z
instruments. If lower power is required, the ADA4505-2
amplifier has a maximum input bias current of 2 pA and J1 CON A
120-PIN SDP
120-PIN SDP
consumes only 10 µA per amplifier. However, the noise of the OR

12-PIN
CO-AX CON B
ADA4505-2 is greater than that of the ADA4528-2. SENSOR
PMD-SDP-IB1Z
The ADR291 precision voltage reference consumes only 12 µA

12332-003
EVAL-CN0357-PMDZ
and can be substituted for the ADR3412, if lower power is
required. Figure 3. Test Setup Functional Block Diagram
More information can be found in Circuit Note CN-0234.
Setup Figure 4 shows the circuit response after rapidly removing the
Connect the electrochemical sensor to the socket on the EVAL- sensor from the 175 ppm CO atmosphere and is a better
CN0357-PMDZ circuit evaluation board. representation of circuit performance.
Connect the EVAL-CN0357-PMDZ to the interposer board and A photo of the EVAL-CN0357-PMDZ board is shown in
ensure that the jumper on the interposer board selects +3.3 V as Figure 5.
the configuration. Next, connect the SDP-B board to the
interposer board and apply power to the interposer board via
the DC barrel jack.
Connect the USB cable supplied with the SDP-B board to the
USB port on the PC and to the SDP-B board.
The software can communicate with the SDP board if the
Analog Devices System Development Platform driver appears
in the Device Manager. When USB communications are
established, the SDP board can now send, receive, and capture
serial data from the EVAL-CN0357-PMDZ circuit evaluation
board.
Test
Navigate to the installation location of the CN-0357 Evaluation
Software and open the CN0357.exe file. (The file should be located
12332-004
in a folder named Analog Devices in the start menu of the
operating system.) Figure 4. Response to a 175 ppm to 0 ppm Step of Carbon Monoxide
When the application opens, the software automatically connects to

the SDP-B board. If multiple SDP-B controller boards are
connected, the selected board will have a light emitting diode
(LED) blinking.
12332-005
The CN-0357 Evaluation Software User Guide contains
information and details regarding how to use the evaluation
Figure 5. EVAL-CN0357-PMDZ Evaluation Board
software for data capture.
The input signal for this board is gas concentration; therefore, a
calibration gas source is required. When testing with carbon
monoxide, consider that 250 ppm is the maximum short term
exposure limit.
The software is designed to be used with any electrochemical
sensor, so it is important to input the correct specifications for the
chosen sensor.
The maximum sensor sensitivity and sensor range are needed to
calculate and set the resistance of the AD5270-20 digital rheostat.
This value is a signed value. Positive values are used to describe
sensors than sink current, whereas negative values are used to
describe sensors that source current.
The typical sensor sensitivity is used to calculate the system
conversion coefficient of ppm/mV.
Pressing the Run button begins acquisition of concentration data at
1 second intervals.
CN-0357 Design Support Package: CN-0357 Circuit Evaluation Board (EVAL-CN0357-PMDZ)
http://www.analog.com/CN0357-DesignSupport System Demonstration Platform (EVAL-SDP-CB1Z)
AN-1114, Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz ADA4528-2 Data Sheet
Voltage Noise Density, Analog Devices.
AD5270-20 Data Sheet
MS-2066 Article, Low Noise Signal Conditioning for Sensor-
ADR3412 Data Sheet
Based Circuits, Analog Devices.
AD8500 Data Sheet
Rail-to-Rail Issues, Analog Devices. AD7790 Data Sheet
CN-0234 Circuit Note, Single Supply, Micropower Toxic Gas
Detector Using an Electrochemical Sensor, Analog Devices.
Alphasense Application Note AAN-105-03, Designing a
Potentiostatic Circuit, Alphasense Limited.
REVISION HISTORY

CN12332-0-7/14(0)
Circuit Note
CN-0359
10 MHz, 20 V/μs, G = 1, 10, 100, Low Power, Precision Analog
AD8253 1000, iCMOS Programmable Gain ADuCM360 Microcontroller with Dual Sigma-
Instrumentation Amplifier Delta ADCs, ARM Cortex-M3
30 V, High Speed, Low Noise, Low Bias CMOS Rail-to-Rail General-
ADA4627-1 AD8542
Circuits from the Lab® reference Current, JFET Operational Amplifier Purpose Amplifiers
designs are engineered and 1.2 A, 20 V, 700 kHz/1.4 MHz,
Low Cost, Precision JFET Input
tested for quick and easy system ADA4000-1 ADP2300 Nonsynchronous Step-Down
Operational Amplifiers
Regulator
integration to help solve today’s
analog, mixed-signal, and RF 30 V, Zero-Drift, Rail-to-Rail Output 650 kHz/1.3 MHz, Step-Up PWM
ADA4638-1 ADP1613
Precision Amplifier DC-to-DC Switching Converters
design challenges. For more
information and/or support, visit Low Capacitance, Low Charge
Precision, Ultralow Noise, RRIO,
ADA4528-2 ADG1211 Injection, ±15 V/+12 V, iCMOS
www.analog.com/CN0359. Dual, Zero-Drift Op Amp
Quad SPST Switches
4 MHz, 7 nV/√Hz, Low Oﬀset and 2.1 Ω On Resistance, ±15 V/+12 V/
ADA4077-2 ADG1419
Drift, High Precision Amplifiers ±5 V, iCMOS SPDT Switch
CMOS, Single-Supply, Rail-to-Rail 3.3 V Slew Rate Limited, Half
AD8592 Input/Output Operational ADM3483 Duplex, RS-485/RS-422
Amplifiers with Shutdown Transceivers
Fully Automatic High Performance Conductivity Measurement System
EVALUATION AND DESIGN SUPPORT the conductivity measurement to be referenced to room

Circuit Evaluation Boards temperature.
CN-0359 Circuit Evaluation Board (EVAL-CN0359-EB1Z) The system accommodates 2- or 4-wire conductivity cells, and
Design and Integration Files 2-, 3-, or 4-wire RTDs for added accuracy and flexibility.
Schematics, Layout Files, Bill of Materials The circuit generates a precise ac excitation voltage with
CIRCUIT FUNCTION AND BENEFITS minimum dc offset to avoid a damaging polarization voltage on
the conductivity electrodes. The amplitude and frequency of the
The circuit shown in Figure 1 is a completely self-contained,
ac excitation is user-programmable.
microprocessor controlled, highly accurate conductivity
measurement system ideal for measuring the ionic content of An innovative synchronous sampling technique converts the
liquids, water quality analysis, industrial quality control, and peak-to-peak amplitude of the excitation voltage and current
chemical analysis. to a dc value for accuracy and ease in processing using the dual,
24-bit Σ-Δ ADC contained within the precision analog
A carefully selected combination of precision signal conditioning
microcontroller.
components yields an accuracy of better than 0.3% over a
conductivity range of 0.1 μS to 10 S (10 MΩ to 0.1 Ω) with The intuitive user interface is an LCD display and an encoder
no calibration requirements. push button. The circuit can communicate with a PC using an
RS-485 interface if desired, and operates on a single 4 V to 7 V
Automatic detection is provided for either 100 Ω or 1000 Ω
supply.
platinum (Pt) resistance temperature devices (RTDs), allowing
Rev. B
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) Fax: 781.461.3113 ©2015–2016 Analog Devices, Inc. All rights reserved.
+3.3V
J2 J4 S1
AVDD ADM3483 J-LINK ENCODER
R13 AIN0 RS-485 PEC11R-S
J3 1.5kΩ ADC0 PWM0
100Ω OR 1 +15V
AIN7/IEXC ADC1 AIN1 PWM1
1000Ω J1
Pt RTD 2 AIN8 AIN2 −15V
ADC2 PWM2 +4V TO +7V
AIN6 ADC3 AIN3 +3.3V
ADuCM360 128 × 64
LCD POWER
RX AIN5/IEXC P0.0 U2WRI +1.65V SUPPLIES
+3.3V MCCOG128064A6S-SPTLY
AIN6 P2.0 U4WRI
3 AIN5/IEXC +VEXC
1kΩ P1.2 A0
AIN7/IEXC
+0.115V P2.1 A1 −VEXC
4
AIN9 AIN8
36Ω AIN9 DAC
AGND EP
R20
1.2kΩ
ADG1419 ¼
R23 +VEXC ADG1211 820pF
R34
430Ω +15V R19
J5 1 1kΩ –VEXC G1 = 1, 10, 100, 1000 + ADA4638-1 7.5kΩ +3.3V
PWM0 +15V AD8253 C50 U10 − 24Ω
2 A0, A1, PWM1 4.7µF
− U2WRI − U12B ADC3
V1P-P –15V
½ ADA4528-2
U15 +1.65V + 10nF
1k Ω
5 + 430Ω R31
YX REF
¼ 1nF 1.2kΩ
−15V ADG1211
ADA4000-1 R36 820pF
VOUT1 =
3 +15V +3.3V G1 × 0.16 × V1P-P
430Ω +15V
+ R29
4 + + ADA4638-1 7.5kΩ
U14 +1.65V C73
U22B 4.7µF U13 − 24Ω
− PWM2
CONDUCTIVITY −15V − − U12A ADC2
−15V
CELL 470kΩ 1k Ω +1.65V + ½ ADA4528-2 10nF
1nF ½ AD8542 1nF
IP-P R38
1nF ¼ 1.2kΩ
ADG1211
R41 820pF
R47,1.0kΩ
G2 = 1, 10, 100, 1000 430Ω +15V R37
+ ADA4638-1 7.5kΩ
+15V AD8253
+15V C84 +3.3V
− U16 − 24Ω
A0, A1, 4.7µF
PWM1 U20B ADC1
ADA4627-1 U19 + U4WRI −
V2 –15V
+ P-P U18 +1.65V + ½ ADA4528-2 10nF
1k Ω
−15V 430Ω
− REF ¼ R52
ADG1211 1nF 1.2kΩ
VOUT2 =
−15V R42 G1 × 0.16 × V2P-P
430Ω +15V R48
G2 × VOUT2 820pF
YX = × 1mS + + ADA4638-1 7.5kΩ
G1 × VOUT1 +1.65V C93
U22A 4.7µF U21 − 24Ω
PWM2 − U20A ADC0
−
–15V
+1.65V + ½ ADA4528-2 10nF
1k Ω
12970-001
½ AD8542 1nF
Figure 1. High Performance Conductivity Measurement System (Simplified Schematic: All Connections and Decoupling Not Shown)
R14
CIRCUIT DESCRIPTION 110kΩ
The excitation square wave for the conductivity cell is generated 1nF
by switching the ADG1419 between the +VEXC and −VEXC R15
15kΩ +15V
voltages using the PWM output of the ADuCM360 − G = 8.33 +VEXC
microcontroller. It is important that the square wave has a R16 U9A
DAC 13kΩ
FROM + ½ ADA4077-2 0V TO +10V
precise 50% duty cycle and a very low dc offset. Even small ADuCM360
dc offsets can damage the cell over a period of time. 0V TO +1.2V
R27
27kΩ
The +VEXC and −VEXC voltages are generated by the
ADA4077-2 op amps (U9A and U9B), and their amplitudes are 1nF
R24
controlled by the DAC output of the ADuCM360, as shown in 27kΩ
Figure 2. − −VEXC
R22 U9B
13kΩ
12970-002
+ ½ ADA4077-2 0V TO −10V
−15V
Figure 2. Excitation Voltage Sources

The ADA4077-2 has a typical offset voltage of 15 μV (A grade), a The ADuCM360 generates the PWM0 square wave switching
0.4 nA bias current, a 0.1 nA offset current, and an output current signal for the ADG1419 switch as well as PWM1 and PWM2
of up to ±10 mA, with a dropout voltage of less than 1.2 V. The synchronizing signals for the synchronous sampling stages.
U9A op amp has a closed-loop gain of 8.33 and converts the The cell voltage and the three timing waveforms are shown in
ADuCM360 internal DAC output (0 V to 1.2 V) to the +VEXC Figure 3.
voltage of 0 V to 10 V. The U9B op amp inverts the +VEXC and
generates the −VEXC voltage. R22 is chosen such that R22 = CELL VOLTAGE +VEXC
0
R24||R27 to achieve first-order bias current cancellation. The
–VEXC
error due to the 15 μV offset voltage of U9A is approximately
(2 × 15 μV) ÷ 10 V = 3 ppm. The primary error introduced by PWM0
the inverting stage is therefore the error in the resistor matching
between R24 and R27. TRACK −V TRACK −V
PWM1
HOLD –V
The ADG1419 is a 2.1 Ω, on-resistance SPDT analog switch SETUP HOLD
with an on-resistance flatness of 50 mΩ over a ±10 V range, TRACK +V
PWM2
making it ideal for generating a symmetrical square wave from
12970-003
HOLD +V HOLD +V
the ±VEXC voltages. The symmetry error introduced by the SETUP HOLD
ADG1419 is typically 50 mΩ ÷1 kΩ = 50 ppm. Resistor R23 Figure 3. Cell Voltage and Track-and-Hold Timing Signals
limits the maximum current through the sensor to 10 V/1 kΩ = The output of the AD8253 in amp (U15) drives two parallel
10 mA. track-and-hold circuits composed of ADG1211 switches
The voltage applied to the cell, V1, is measured with the (U17A/U17B), series resistors (R34/R36), hold capacitors
AD8253 instrumentation amplifier (U15). The positive input (C50/C73), and unity-gain buffers (U10/U13).
to U15 is buffered by the ADA4000-1 (U14). The ADA4000-1 The ADG1211 is a low charge injection, quad SPST analog
is chosen because of its low bias current of 5 pA to minimize switch, operating on a ±15 V power supply with up to ±10 V
the error in measuring low currents associated with low input signals. The maximum charge injection due to switching
conductivities. The negative input of the AD8253 does not is 4 pC, which produces a voltage error of only 4 pC ÷ 4.7 μF =
require buffering. 0.9 μV.
The offset voltages of U14 and U15 are removed by the The PWM1 signal causes the U10 track-and-hold buffer to
synchronous sampling stage and do not affect the measurement track the negative cycle of the sensor voltage and then hold it
accuracy. until the next track cycle. The output of the U10 track-and-hold
U15 and U18 are AD8253 10 MHz, 20 V/μs, programmable gain buffer is therefore a dc level corresponding to the negative
(G = 1, 10, 100, 1000) instrumentation amplifiers with gain error amplitude of the sensor voltage square wave.
of less than 0.04%. The AD8253 has a slew rate of 20 V/μs and a Similarly, the PWM2 signal causes the U13 track-and-hold
settling time of 1.8 μs to 0.001% for G = 1000. Its common-mode buffer to track the positive cycle of the sensor voltage and then
rejection is typically 120 dB. hold it until the next track cycle. The output of the U13 track-
The U19 (ADA4627-1) stage is a precision current to voltage and-hold buffer is therefore a dc level corresponding to the
converter that converts the current through the sensor to a positive amplitude of the sensor voltage square wave.
voltage. The ADA4627-1 has an offset voltage of 120 μV The bias current of the track-and-hold buffers (ADA4638-1) is
(typical, A grade), a bias current of 1 pA (typical), a slew rate 45 pA typical, and the leakage current of the ADG1211 switch
of 40 V/μs, and a 550 ns settling time to 0.01%. The low bias is 20 pA typical. Therefore, the worst-case leakage current on
current and offset voltage make it ideal for this stage. The the 4.7 μF hold capacitors is 65 pA. For a 100 Hz excitation
symmetry error produced by the 120 μV offset error is only frequency, the period is 10 ms. The drop voltage over one-half
120 μV/10 V = 12 ppm. the period (5 ms) due to the 65 pA leakage current is (65 pA ×
The U22A and U22B (AD8542) buffers supply the 1.65 V 5 ms) ÷ 4.7 μF = 0.07 μV.
reference to the U18 and U15 instrumentation amplifiers, The offset voltage of the ADA4638-1 zero-drift amplifier is only
respectively. 0.5 μV typical and contributes negligible error.
The following is a description of the remainder of the signal path in The final stages in the signal chain before the ADC are the
the voltage channel (U17A, U17B, U10, U13, U12A, and U12B). ADA4528-2 inverting attenuators (U12A and U12B) that have
The operation of the current channel (U17C, U17D, U16, U21, a gain of −0.16 and a common-mode output voltage of +1.65 V.
U20A, and U20B) is identical. The ADA4528-2 has an offset voltage of 0.3 μV typical and
therefore contributes negligible error.
The attenuator stage reduces the ±10 V maximum signal to System Accuracy Measurements
±1.6 V with a common-mode voltage of +1.65 V. This range is The following four resistors affect the accuracy in the VOUT1
compatible with the input range of the ADuCM360 ADC input, voltage channel: R19, R20, R29, and R31.
which is 0 V to 3.3 V (1.65 V ± 1.65 V) for an AVDD supply of
The following five resistors affect the accuracy in the VOUT2
3.3 V.
current channel: R47, R37, R38, R48, and R52.
The attenuator stages also provide noise filtering and have a
Assuming that all nine resistors are 0.1% tolerance, and
−3 dB frequency of approximately 198 kHz.
including the 0.04% gain error of the AD8253, a worst-case
The differential output of the voltage channel, VOUT1, is error analysis yields approximately 0.6%. The analysis is
applied to the AIN2 and AIN3 inputs of the ADuCM360. The included in the CN-0359 Design Support Package.
differential output of the current channel, VOUT2, is applied to
In practice, the resistors are more likely to combine in an RSS
the AIN0 and AIN1 inputs of the ADuCM360.
manner, and the RSS error due to the resistor tolerances in the
The equations for the two outputs are given by positive or negative signal chain is √5 × 0.1% = 0.22%.
VOUT1 = G1 × 0.16 × V1P-P (1) Accuracy measurements were taken using precision resistors
VOUT2 = G2 × 0.16 × V2P-P (2) from 1 Ω to 1 MΩ (1 S to 1 μS) to simulate the conductivity cell.
Figure 4 shows the results, and the maximum error is less than
The cell current is given by
0.1%.
IP-P = V1P-P × YX (3) 0.04
The V2P-P voltage is given by

0.02
V2P-P = IP-P × R47 (4)
0
Solving Equation 4 for IP-P and substituting into Equation 3
yields the following for YX:
ERROR (%)
–0.02
V2P  P
YX  (5)
V1P  P  R 47 –0.04
Solving Equation 1 and Equation 2 for V1P-P and V2P-P and –0.06
substituting into Equation 5 yields the following:

–0.08
G2  VOUT2
YX  (6)
G1  VOUT1  R 47 –0.10
12970-004
1µ 10µ 0.1m 1m 10m 0.1 1
CONDUCTIVITY (S)
G2  VOUT2
YX   1 mS (7) Figure 4. System Error (%) vs. Conductivity of 1 μS to 1 S
G1  VOUT1
RTD Measurement
Equation 7 shows that the conductivity measurement depends
Conductivity measuring system accuracy is only as good as
on G1, G2, and R47, and the ratio of VOUT2 to VOUT1.
its temperature compensation. Because common solution
Therefore, a precision reference is not required for the ADCs
temperature coefficients vary in the order of 1%/°C to 3%/°C
within the ADuCM360.
or more, measuring instruments with adjustable temperature
The AD8253 gain error (G1 and G2) is 0.04% maximum, and compensation must be used. Solution temperature coefficients
R47 is chosen to be a 0.1% tolerance resistor. are somewhat nonlinear and usually vary with the actual
From this point, the resistors in the VOUT1 and VOUT2 signal conductivity, as well. Therefore, calibration at the actual
chain determine the overall system accuracy. measuring temperature yields the best accuracy.
The software sets the gain of each AD8253 as follows: The ADuCM360 contains two matched, software configurable,
excitation current sources. They are individually configurable
 If the ADC code is over 93.2% of full scale, the gain of the
to provide a current output of 10 μA to 1 mA, and matching is
AD8253 is reduced by a factor of 10 on the next sample.
better than 0.5%. The current sources allow the ADuCM360
 If the ADC code is less than 9.13% of full scale, the gain of
to easily perform 2-wire, 3-wire, or 4-wire measurements for
the AD8253 is increased by a factor of 10 on the next sample.
either Pt100 or Pt1000 RTDs. The software also automatically
detects if the RTD is Pt100 or Pt1000 during the setup procedure.
The following discussion shows simplified schematics of how
the different RTD configurations operate. All mode switching is
accomplished in the software, and there is no need to change
the external jumper settings.
Figure 5 shows the configuration for 4-wire RTDs. The 3-wire connection is another popular RTD configuration
ADuCM360
that eliminates lead resistance errors, as shown in Figure 6.
R13
1.5kΩ AIN7/
RP J3
0.1% IEXC R13 ADuCM360
1 IEXC V7 – V8 – VP + 1.5kΩ AIN7/
TO ADC RP J3 IEXC
100Ω OR AIN8 1 0.1% IEXC
1000Ω V7 – V8
Pt RTD RP TO ADC
2 AIN6 AIN8
100Ω OR
1000Ω 2 AIN6
V6 – V5 Pt RTD
RX V8 – V5
TO ADC TO ADC
AIN5/
RP 3 IEXC RX
– VP +
AIN5/ IEXC
RP
+3.3V 3 IEXC
1kΩ +3.3V
RP 4 +0.115V AIN9 1kΩ
RP 4
36Ω +0.115V AIN9
12970-005
V6 – V5
RX = × 1.5kΩ 36Ω
V7 – V8
12970-006
V8 – V5
RX = × 1.5kΩ
Figure 5. Configuration for 4 Wire RTD Connection V7 – V8
The parasitic resistance in each of the leads to the remote RTD Figure 6. Configuration for 3-Wire RTD Connection
is shown as RP. The excitation current (IEXC) passes through The second matched IEXC current source (AIN5/IEXC)
a precision 1.5 kΩ resistor and the RTD. The on-chip ADC develops a voltage across the lead resistance in series with
measures the voltage across the resistor (V7 − V8). Terminal 3 that cancels the voltage dropped across the lead
It is important that the R13 resistor and the IEXC excitation resistance in series with Terminal 1. The measured V8 − V5
current value be chosen such that the ADuCM360 maximum voltage is therefore free of lead resistance error.
input voltage at AIN7 does not exceed AVDD − 1.1 V; otherwise, Figure 7 shows the 2-wire RTD configuration where there is no
the IEXC current source does not function properly. compensation for lead resistance.
The RTD voltage is accurately measured using the two sense R13 ADuCM360
leads that connect to AIN6 and AIN5. The input impedance is 1.5kΩ AIN7/
RP J3 IEXC
1 0.1% IEXC V7 – V8
approximately 2 MΩ (unbuffered mode, PGA gain = 1), and the 100Ω OR
TO ADC
AIN8
current flowing through the sense lead resistance produces 1000Ω
Pt RTD 2 AIN6
minimum error. The ADC then measures the RTD voltage
(V6 − V5).
RX
AIN5/ V8 – V9
The RTD resistance is then calculated as 3 IEXC TO ADC
V6  V5 +3.3V
RX   1.5 kΩ (8)
V7  V8 1kΩ
RP 4 +0.115V AIN9
The measurement is ratiometric and does not depend on an 36Ω
12970-007
accurate external reference voltage, only the tolerance of the RX =
V8 – V9
× 1.5kΩ – 2R P
V7 – V8
1.5 kΩ resistor. In addition, the 4-wire configuration eliminates
the error associated with the lead resistances. Figure 7. Configuration for 2-Wire RTD Connection
The ADuCM360 has a buffered or unbuffered input option. If The 2-wire configuration is the lowest cost circuit and is suitable
the internal buffer is activated, the input voltage must be greater for less critical applications, short RTD connections, and higher
than 100 mV. The 1 kΩ/36 Ω resistor divider provides a 115 mV resistance RTDs such as Pt1000.
bias voltage to the RTD that allows buffered operation. In the
unbuffered mode, Terminal 4 of J3 can be grounded and
connected to a grounded shield for noise reduction.
Conductivity Theory the temperature, a second temperature sensor and compensation
The resistivity, ρ, of a material or liquid is defined as the network must be used.
resistance of a cube of the material with perfectly conductive The contacting-type sensor typically consists of two electrodes
contacts on opposite faces. The resistance, R, for other shapes that are insulated from one another. The electrodes, typically
can be calculated by Type 316 stainless steel, titanium palladium alloy, or graphite,
R = ρL/A (9) are specifically sized and spaced to provide a known cell
constant. Theoretically, a cell constant of 1.0/cm describes two
where:
electrodes, each sized 1 cm2 in area, and spaced 1 cm apart. Cell
L is the distance between the contacts.
constants must be matched to the measurement system for a
A is the area of the contacts.
given range of operation. For instance, if a sensor with a cell
Resistivity is measured in units of Ω cm. A 1 Ω cm material has constant of 1.0/cm is used in pure water with a conductivity of
a resistance of 1 Ω when contacted on opposite faces of a 1 cm × 1 μS/cm, the cell has a resistance of 1 MΩ. Conversely, the same
1 cm × 1 cm cube. cell in seawater has a resistance of 30 Ω. Because the resistance
Conductance is the reciprocal of resistance, and conductivity ratio is so large, it is difficult for ordinary instruments to
is the reciprocal of resistivity. The unit of measurement of accurately measure such extremes with only one cell constant.
conductance is Siemens (S), and the unit of measurement of When measuring the 1 μS/cm solution, the cell is configured with
conductivity is S/cm, mS/cm, or μS/cm. large area electrodes spaced a small distance apart. For example,
All aqueous solutions conduct electricity to some degree. a cell with a cell constant of 0.01/cm results in a measured cell
Adding electrolytes such as salts, acids, or bases to pure water resistance of approximately 10,000 Ω rather than 1 MΩ. It is
increases the conductivity (and decreases resistivity). easier to accurately measure 10,000 Ω than 1 MΩ; therefore, the
measuring instrument can operate over the same range of cell
For the purposes of this circuit note, Y is the general symbol for
resistance for both ultrapure water and high conductivity seawater
conductivity measured in S/cm, mS/cm, or μS/cm. However, in
by using cells with different cell constants.
many cases, the distance term is dropped for convenience, and
the conductivity is simply expressed as S, mS, or μS. The cell constant, K, is defined as the ratio of the distance between
the electrodes, L, to the area of the electrodes, A:
A conductivity system measures conductivity by means of
electronics connected to a sensor called a conductivity cell K = L/A (10)
immersed in a solution, as shown in Figure 8. The instrumentation then measures the cell conductance, Y:
Y = I/V (11)
The conductivity of the liquid, YX, is then calculated:
YX = K × Y (12)
TO I/V There are two types of conductivity cells: those with two electrodes,
CONVERTER
V and those with four electrodes, as shown in Figure 9. The
electrodes are often referred to as poles.
2-POLE 4-POLE
EVAL-CN0359-EB1Z
A = AREA OF ELECTRODE SURFACE (cm2)

L = DISTANCE BETWEEN ELECTRODES (cm)
A I A V = EXCITATION VOLTAGE
I = CELL CURRENT
K = L/A = CELL CONSTANT (cm–1)
Y = MEASURED CONDUCTANCE = I/V (S)
L
YX = WATER CONDUCTIVITY = K × Y (S/cm)
12970-008
Figure 8. Interface Between Conductivity Cell and EVAL-CN0359-EB1Z
The electronic circuitry impresses an alternating voltage on the

12970-009
sensor and measures the size of the resulting current, which is

related to the conductivity. Because conductivity has a large Figure 9. 2-Pole and 4-Pole Conductivity Cells
temperature coefficient (up to 4%/°C), an integral temperature
The 2-pole sensor is more suitable for low conductivity
sensor is incorporated into the circuitry to adjust the reading to
measurements, such as purified water, and various biological
a standard temperature, usually 25°C (77°F). When measuring
and pharmaceutical liquids. The 4-pole sensor is more suitable
solutions, the temperature coefficient of the conductivity of the
the high conductivity measurements, such as waste water and
water itself must be considered. To compensate accurately for
seawater analysis.
The cell constants for 2-pole cells range from approximately Power Supply Circuits
0.1/cm to 1/cm, and the cell constants for 4-pole cells range To simplify system requirements, all the required voltages
from 1/cm to 10/cm. (±15 V and +3.3 V) are generated from a single 4 V to 7 V
The 4-pole cell eliminates the errors introduced by polarization supply, as shown in Figure 10.
of the electrodes and field effects that can interfere with the The ADP2300 buck regulator generates the 3.3 V supply for the
measurement. board. The design is based on the downloadable ADP230x Buck
The actual configuration of the electrodes can be that of parallel Regulator Design Tool.
rings, coaxial conductors, or others, rather than the simple The ADP1613 boost regulator generates a regulated +15 V
parallel plates shown in Figure 8. supply and an unregulated −15 V supply. The −15 V supply is
Regardless of the type of cell, it is important not to apply a generated with a charge pump. The design is based on the
dc voltage to any electrode, because ions in the liquid will ADP161x Boost Regulator Design Tool.
accumulate on the electrode surface, thereby causing Details regarding the selection and design of power supplies are
polarization, measurement errors, and damage to the electrode. available at www.analog.com/ADIsimPower.
Take special care with sensors that have shields, as in the case of Use proper layout and grounding techniques to prevent the
coaxial sensors. The shield must be connected to the same potential switching regulator noise from coupling into the analog circuits.
as the metal container holding the liquid. If the container is See the Linear Circuit Design Handbook, the Data Conversion
grounded, the shield must be connected to Pin 5 of J5, the Handbook, the MT-031 Tutorial, and the MT-101 Tutorial for
circuit board ground. further details.
The final precaution is not to exceed the rated excitation voltage
or current for the cell. The CN-0359 circuit allows programmable
excitation voltages from 100 mV to 10 V, and the R23 (1 kΩ)
series resistor limits the maximum cell current to 10 mA.
100nF
+4V TO +7V BST 22µH +3.3V +3.3V
VIN EMI
SW FILTER
EN
ADP2300 B120
10kΩ
100nF 10µF 22µF 100nF 7.5kΩ +1.65V
FB
GND +0.8V 10kΩ
2.4kΩ
−15V
−15V UNREGULATED EMI
FILTER
½ BAT54S 22µF 100nF
22µH
10µF
½ BAT54S
100nF 47µF 1N4148 +15V
EMI
VIN SW
FILTER
+15V REGULATED
100nF EN
ADP1613 200kΩ
FREQ +1.235V
FB
33nF EMI FILTERS:
SS 18kΩ BNX025H01
COMP
GND 3.3nF 56pF
12970-010
47kΩ
Figure 10. Power Supply Circuits
Figure 11 shows the LCD backlight driver circuit. After connecting, the conductivity cell and the RTD the board
+3.3V are powered up. The LCD screen appears as shown in Figure 12.
5.1kΩ 100nF Push the encoder knob to enter the setting menu, and then
+2.9V
input the EXC Voltage, EXC Frequency, TEMP Coefficient,
36kΩ
+3.3V +3.3V and Cell Constant, as shown in Figure 13.
+ +
K1 K2
+3.3V 6.8Ω U6B U6A 6.8Ω +3.3V
− −
400mV 400mV
½ AD8592 ½ AD8592
12970-011
A1 A2
12970-013
60mA LCD DISPLAY 60mA
SETTING SCREEN SETTING EXCITATION VOLTAGE
Figure 11. LCD Backlight Drivers
Figure 13. LCD Display Screens
Each half of the AD8592 op amp acts as a 60 mA current source
Rotating the knob moves the cursor up and down through the
to supply the LCD backlight currents. The AD8592 can source and
various parameters.
sink up to 250 mA, and the 100 nF capacitor ensures a soft startup.
Set the cursor to EXC Voltage and push the knob until it clicks.
Software Operation and User Interface
Position the cursor over the first digit in the number to be set
The EVAL-CN0359-EB1Z comes preloaded with the code by rotating the knob. Push the button, and the cursor blinks.
required to make the conductivity measurements. The complete Change the number by rotating the knob, and push the knob
system hardware and software operation can be found in the when the desired number is reached. After setting all the digits
CN-0359 User Guide at www.analog.com/CN0359-UserGuide. in the number, position the cursor on Save and push the button
The CN-0359 user interface is intuitive and easy to use. All to save the setting.
user inputs are from a dual function push button/rotary Continue the process and set the EXC Frequency, TEMP
encoder knob. The encoder knob can be turned clockwise or Coefficient, and Cell Constant.
counterclockwise (no mechanical stop), and can also be used
After setting all the constants, select RETURN TO HOME and
as a push button.
push the knob. The system is now ready to make measurements.
Figure 12 is a photo of the EVAL-CN0359-EB1Z board that
If numbers are entered that are outside the allowable range, the
shows the LCD display and the position of the encoder knob.
buzzer sounds.
POWER
If the conductivity cell is incorrectly connected, the screen
displays Sensor Incorrect.
If the RTD is incorrectly connected, the screen displays RTD
Incorrect use 25°C. The system can still make measurements
without the RTD connected, but uses 25°C as the compensation
3 temperature.
2 RS-485
1 1
RTD
2 COMMON VARIATIONS
3
4 The system shown in the CN-0359 uses the ADuCM360
precision analog microcontroller for a highly integrated
1
2 JTAG
conductivity measurement.
CONDUCTIVITY 3
4
If the user desires a discrete ADC, the AD7794 24-bit, Σ-Δ
5 ADC is a good choice.
12970-012
Figure 12. Photo of EVAL-CN0359-EB1Z Board Showing Home Screen in

Measurement Mode
CIRCUIT EVALUATION AND TEST 3. Connect the 6 V power supply (EVAL-CFTL-6V-PWRZ)
This circuit uses the EVAL-CN0359-EB1Z circuit board, an to J1 of the EVAL-CN0359-EB1Z circuit board.
external power supply, conductivity cell, and an RTD. 4. Turn on the power by connecting the EVAL-CFTL-6V-
PWRZ, and then push the button on the EVAL-CN0359-
Equipment Needed EB1Z circuit board.
The following equipment is needed: 5. Follow the procedure previously described in the Software
 The EVAL-CN0359-EB1Z circuit board Operation and User Interface section and enter the
following parameters: EXC Voltage, EXC Frequency,
 A 6 V power supply or wall wart (EVAL-CFTL-6V-PWRZ)
TEMP Coefficient, and Cell Constant.
 A conductivity cell
6. Return to the main screen and wait for the ADuCM360 to
 Pt100 or Pt1000 2-wire, 3-wire, or 4-wire RTD (if the RTD
flush the buffers and display the conductivity and the
is not connected, the conductivity measurement is referenced
temperature. If the screen shows an error and the buzzer
to 25°C)
beeps more than 20 times, check the sensor connections.
Setup
Connectivity for Prototype Development
Take the following steps to set up the circuit for evaluation:
The EVAL-CN0359-EB1Z is designed to be powered with the
1. Connect the conductivity cell as follows: EVAL-CFTL-6V-PWRZ 6 V power supply. The EVAL-CN0359-
a. 4-wire cell: connect an outside current electrode to J5 EB1Z requires only the power supply and the external
Pin 1 and the closest inner voltage electrode to J5 Pin 2. conductivity cell and RTD for operation.
Connect the second outside current electrode to J5
The EVAL-CN0359-EB1Z also has an RS-485 connector, J2,
Pin 4 and the closest inner voltage electrode to Pin 3.
that allows an external PC to interface with the board.
b. 2-wire cell: connect one electrode to J5 Pin 1 and Pin 2
Connector J4 is a JTAG interface for programming and
and connect the second electrode to J5 Pin 3 and Pin 4.
debugging the ADuCM360.
c. If the conductivity cell has a shield, connect it to J5 Pin 5.
2. Connect the RTD as follows (if used): Figure 14 is a typical PC connection diagram showing an
a. 4-wire RTD (see Figure 5): connect the positive RS-485 to RS-232 adapter.
current excitation wire to J3 Pin 1 and the positive 6V
PC
voltage sense wire to J3 Pin 2. Connect the negative SUPPLY
current excitation wire to J3 Pin 4 and the negative

voltage sense wire to J3 Pin 3.
J1
RS-485 TO
b. 3-wire RTD (see Figure 6): connect the positive CONDUCTIVITY J5 J2 RS-232
CELL
current excitation wire to J3 Pin 1. Connect the ADAPTER
EVAL-CN0359-EB1Z
negative current excitation wire to J3 Pin 4. Connect
the negative voltage sense wire to J3 Pin 3. RTD J3 J4 JTAG
12970-014
c. 2-wire RTD (see Figure 7): connect one RTD wire to
J3 Pin 1 and the other wire to J3 Pin 4. Figure 14. Test Setup Functional Diagram
d. If the RTD wires are shielded, connect the shield to J5
Pin 5.
LEARN MORE REVISION HISTORY
CN-0359 Design Support Package: 9/2016—Rev. A to Rev. B
www.analog.com/CN0359-DesignSupport Change to Evaluation and Design Support Section ......................1
ADIsimPower Design Tool. Analog Devices Changes to Figure 3...........................................................................3
Changes to Software Operation and User Interface Section and
Linear Circuit Design Handbook. Analog Devices/Elsevier. Figure 12 .............................................................................................8
Op Amp Applications Handbook. Analog Devices/Elsevier.
The Data Conversion Handbook. Analog Devices/Elsevier. 11/2015—Rev. 0 to Rev. A
Change to Setup Section ...................................................................9
A Designer's Guide To Instrumentation Amplifiers, 3rd Edition.
Analog Devices. 1/2015—Revision 0: Initial Version
MT-101 Tutorial. Decoupling Techniques. Analog Devices.
"Section 7: Temperature Sensors" in Sensor Signal Conditioning.
Analog Devices.
AD8253 Data Sheet
AD8592 Data Sheet
AD8542 Data Sheet
ADuCM360 Data Sheet
ADP2300 Data Sheet
ADP1613 Data Sheet
ADG1211 Data Sheet
ADG1419 Data Sheet
ADM3483 Data Sheet
(Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its
licensors. While you may use the Circuits from the Lab reference designs in the design of your product, no other license is granted by implication or otherwise under any patents or
other intellectual property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable.
However, Circuits from the Lab reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied
warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of
patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without
notice but is under no obligation to do so.

CN12970-0-9/16(B)
Circuit Note
CN-0363
24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs
AD7175-2
Settling and True Rail-to-Rail Buffers
ADA4528-1 Precision, Ultralow Noise, RRIO, Zero-Drift Op Amp
Precision, 20 MHz, CMOS, Rail-to-Rail
AD8615
Circuits from the Lab® reference designs are engineered Input/Output Operational Amplifier
and tested for quick and easy system integration to AD5201 33-Position Digital Potentiometer
help solve today’s analog, mixed-signal, and RF design
challenges. For more information and/or support, visit 0.2 μV/°C Offset Drift, 105 MHz Low Power,
ADA4805-1
www.analog.com/CN0363. Low Noise, Rail-to-Rail Op Amp
ADG633 CMOS, ±5 V/+5 V/+3 V, Triple SPDT Switch
ADG733 CMOS, 2.5 V Low Voltage, Triple SPDT Switch
ADG704 CMOS, Low Voltage, 4 Ω, 4-Channel Multiplexer
ADG819 0.5 Ω, CMOS,1.8 V to 5.5 V, 2:1 Mux/SPDT Switch
Dual-Channel Colorimeter with Programmable Gain Transimpedance Amplifiers and

Digital Synchronous Detection
EVALUATION AND DESIGN SUPPORT By using modulated light and digital synchronous detection
Circuit Evaluation Boards rather than a constant (dc) source, the system strongly rejects
CN-0363 Circuit Evaluation Board (EVAL-CN0363-PMDZ) any noise sources at frequencies other than the modulation
Design and Integration Files frequency, providing excellent accuracy.
Schematics, Layout Files, Bill of Materials The dual-channel circuit measures the ratio of light absorbed by
the liquids in the sample and reference containers at three
different wavelengths. This measurement forms the basis of
The circuit shown in Figure 1 is a dual-channel colorimeter many chemical analysis and environmental monitoring
featuring a modulated light source transmitter, programmable instruments used to measure concentrations and characterize
gain transimpedance amplifiers on each channel, and a very materials through absorption spectroscopy.
low noise, 24-bit Σ-Δ analog-to-digital converter (ADC). The
output of the ADC connects to a standard FPGA mezzanine
card. The FPGA takes the sampled data from the ADC and
implements a synchronous detection algorithm.
Rev. 0
270pF
33kΩ
8.2pF
1MΩ 2.5V_REF
U3-C U3-A U1
AVDD 3.3V
1/3 ADG633 1/3 ADG633
2.2µF
2.2kΩ 470pF AD7175-2 IOVDD
1kΩ V_REF_P
U2 AIN0 IOVDD
ADA4528-1 4.7nF
2.2µF 0.1µF
1kΩ V_REF_N
S1336-44BK 0.1VREF AIN1 DGND 5.0V
GAIN0 470pF AVDD
C67 2.2kΩ AVDD1
100kΩ V_SAMPLE_P
1µF AIN2
2.5V_REF AVDD2 1µF 1µF
270pF V_SAMPLE_N
AIN3 REGCAPD
REFERENCE 33kΩ
REGCAPA
8.2pF AIN4
2.5V_REF 1µF 1µF
1MΩ 2.5V_REF
U7-A AVSS
AVDD REFOUT 0Ω
U7-C 1/3 ADG633 2.2kΩ
1/3 ADG633 2.2µF 470pF GPIO1 IOVDD
1kΩ REF+
SAMPLE
U6 1µF 1µF GPIO0

S1336-44BK ADA4528-1
4.7nF 10kΩ 10kΩ
2.2µF 1kΩ
0.1VREF REF– SYNC/ERROR
GAIN0 CS
2.2kΩ 470pF AD_CS
1µF 100kΩ SCLK AD_CLK
SPLITTER XTAL1
S1 2.5V_REF DIN AD_DIN
NT31-414 XTAL2/CLKIO DOUT/RDY AD_DOUT
U10 AVDD
ADG704 2.5V_REF R72
WP154A4SUREQBFZGC AVDD 0.1VREF R45
33Ω 100kΩ
RED S1 D U9 ADA4805 100Ω 24.3kΩ
GREEN S2 C18 C19 C44
10µF 10µF 0.1µF 1kΩ 1µF
BLUE S3 1µF
AVDD S4 AVDD
EN
VDD A0
0.1µF
GND A1 IOVDD
AVDD U14
2.5V_REF AD5201
VDD 10kΩ
AVDD
A
CS
RDAC REG
U4 VDRIVE AVDD DA_CS

100Ω SDI
ADG819 S2 W
SPI
33Ω CLK
Q3 AVDD U13 ADA4805 IOVDD IOVDD
MMBT2222A B SHDN
D 0.1µF 0.1µF EN
0.1µF
U11 AD8615 VSS GND 10kΩ VCC
S1 Y A
GND U16
SN74LVC1G
IN1
LED_CLK
100Ω
12568-001
10kΩ
Figure 1. Dual-Channel Colorimeter with Programmable Gain Transimpedance Amplifiers and Lock-In Amplifiers
(Simplified Schematic: All Connections and Decoupling Not Shown)
CIRCUIT DESCRIPTION component of the modulation signal. The result of these

A clock set to a user-programmable frequency modulates one of operations are two low frequency demodulated signals
the three LED colors with a constant current driver built around representing the in-phase and quadrature components of the
the AD8615 op amp, the ADG819 switch, and the AD5201 received light on each channel, respectively. A narrow FIR
digital potentiometer. The beam splitter sends half the light low pass filter removes all other frequency components, making
through the sample container and half through the reference it easy to calculate the magnitude and phase shift of the amplitude
container. The ADA4528-1, configured as a transimpedance measured at the photodiodes, while rejecting any light or electrical
amplifier, then converts the photodiode current into an output noise at frequencies different from the LED clock. The ADG704
voltage square wave, whose amplitude is proportional to the multiplexer connects the power rail to one of the three LED
light transmitted through the sample or reference containers. colors, allowing the user to select the test wavelength through a
The transimpedance amplifiers use the ADG633 single-pole, 2-bit address. The AD8615 and an NPN transistor make up a
double-throw (SPDT) switches to select one of two transimpedance simple current source, with the LED current given by
gains. The AD7175-2 Σ-Δ ADC samples the voltage and sends I LED  VNON  INVERTING / R EMITTER
the digital data to an FPGA for digital demodulation.
where:
The FPGA implements synchronous demodulation by first VNON-INVERTING is the voltage at the non-inverting input of the
synchronizing a numerically generated sine wave with the LED AD8615.
clock, and then multiplying this sine wave with the sampled REMITTER is the value of the resistor connected to the emitter of
ADC data. In addition, a 90° shifted version of this sine wave is Transistor Q3.
also multiplied with the ADC data to obtain the quadrature
The ADG819 SPDT switch is connected to the set point voltage desired resistor, while a second switch connects the next stage
and to ground, and its control pin is connected to the reference of the system to the selected feedback loop. The voltage at the
clock. As the clock oscillates between high and low, the set point output of the amplifier is
to the current source changes from 0 mA to the desired output VTIA OUTPUT  I PHOTODIODE  RFEEDBACK
current, thereby generating a square wave signal.
The AD5201 digital potentiometer acts as a programmable instead of
resistor divider from the 2.5 V reference, allowing 33 different VTIA OUTPUT  I PHOTODIODE  (RFEEDBACK  RON ADG633 )
current output settings for the LED current.
which represents a gain error. However, because one of the
Both the sample and reference containers receive one-half of the ADG633 devices is outside the feedback loop, the output
LED light energy, and absorb different amounts of light impedance of this stage is the on resistance of the ADG633
depending on the type and concentration of material in each (typically 52 Ω), rather than the very low output impedance
container. The photodiode on the opposite side of each associated with the output of an op amp in closed-loop
container generates a small current proportional to the amount operation. The error due to the leakage current of the ADG633
of light received. (5 pA typical) is negligible.
The first stage of each receiver channel consists of an ADA4528-1 Even the best rail-to-rail output amplifiers like the ADA4528-1
op amp configured as a transimpedance amplifier to convert the cannot swing their output completely to the rails. In addition,
output current of the photodiode to a voltage. The ADA4528-1 the input offset voltage on the ADA4528-1, although very small,
is an auto-zero amplifier resulting in negligible offset, no 1/f noise, can be negative. Rather than including a negative power supply
and very low broadband noise (5.9 nV/√Hz). Like all auto-zero to guarantee that the amplifier never clips, and that it can drive
amplifiers, there is a noise spike at the auto-zero frequency. For to 0.0 V, an ADA4805-1 op amp provides a buffered 100 mV
the ADA4528-1, the frequency is approximately 200 kHz, but voltage to bias the anode of the photodiode and the ADA4528-1.
the circuit signal bandwidth rolls off well before then. The ADA4805-1 is ideally suited as a reference voltage buffer
The input bias current of the op amp multiplied by the feedback because it maintains unity gain stability when driving large
resistor value appears at the output as an offset voltage. The capacitive loads used for decoupling. A second ADA4805-1 is
input offset of the op amp voltage appears at the output with a also used to buffer the output of the AD5201 digital potentiometer
gain dependent on the feedback resistor and the shunt that sets the LED current.
resistance of the photodiode. In addition, any op amp input CF1
voltage offset appears across the photodiode, causing the dark
current of the photodiode to increase. The ADA4528-1 is RF1
therefore ideally suited for this application because of its low CF2
ID
offset voltage (2.5 μV).
RF2
ID ADG633 ADG633
Figure 2 shows a typical transimpedance amplifier with a single
feedback resistor and its ideal transfer function.
VO = ID × RF2
ID
RF
11406-003
ID IB
V' = ID × (RF2 + RON)
VO = ID × RF Figure 3. Programmable Gain Transimpedance Amplifier

VD = 0V
12568-002
The output voltage of the photodiode amplifier swings between

0.1 V and 5.0 V. For the 33 kΩ range, the 4.9 V output span
Figure 2. Transimpedance Amplifier Transfer Function
corresponds to a full-scale photodiode current of 148.5 μA. For
Because some solutions under test can have very strong absorption the 1 MΩ range, it corresponds to a full-scale photodiode
characteristics, it is sometimes necessary to use large feedback current of 4.9 μA. When operating in the 1 MΩ gain setting, it
resistors to measure the very small currents generated by the is important to shield the photodiode from external light to
photodiode, while at the same time being able to measure large prevent the amplifier from saturating. Although the
currents corresponding to highly diluted solutions. To address synchronous detection scheme described in the following
this challenge, the photodiode amplifiers of Figure 1 include sections strongly attenuates any frequencies that are not
two different selectable gains. One gain is set at 33 kΩ, while the synchronous with the LED clock, the detection scheme cannot
other is set at 1 MΩ. Using a single SPDT switch connected to function properly if the ADC is returning saturated data.
the output of the op amp to switch feedback resistors results in
The gain setting for each channel is independently selectable
transimpedance gain error due to the on resistance of the ADG633.
through the FPGA board.
To avoid this problem, Figure 3 shows a better configuration
where the ADG633 switch inside the feedback loop selects the
ADC Sampling Rate and Modulation Frequency Selection For example, in this system, the effective output data rate is
The AD7175-2 ADC is configured with the sinc5+sinc1 filter 25 kSPS; therefore, if a modulation frequency of approximately
with an output data rate of 250 kSPS to sample both channels 1 kHz is desired, the frequency must be 1020 Hz (n = 12) or
with single-cycle settling. This configuration results in an 943 Hz (n = 13) to avoid alias problems. Using this method to
effective sampling rate of 25 kSPS on each channel (data for select a modulation frequency eliminates the need for sharp
each channel is output every 40 μs). Any frequencies above anti-aliasing filters on the front end.
12.5 kHz (such as the odd harmonics of the square wave Digital Synchronous Detection
modulation) alias back into the passband of the ADC; however, Rather than implementing synchronous detection in the
the synchronous demodulation stage rejects these frequencies hardware (see the Circuit Note CN-0312), this circuit takes the
as long as they do not fall right on top of the modulation time-sampled data and uses an FPGA to implement digital
frequency. To avoid aliases of the modulation waveform folding synchronous detection. Figure 4 shows a representation of the
back into its fundamental, select a modulation frequency digital synchronous detection block implemented in the FPGA.
according to the following relationship: The FPGA generates the ac excitation signal to drive the LEDs,
FSAMPLE and a numerically generated sine wave locks to this signal in a
FMODULATION 
2  n  0.5 digital phase-locked loop. The input signal is multiplied with
the digital sine wave and with a 90° shifted version, resulting
where: in two low frequency demodulated signals proportional to the
FMODULATION is the modulation frequency. in-phase and quadrature components of the input signal at the
FSAMPLE is the ADC effective output data rate. modulation frequency. As shown in Figure 4, the magnitude is
n is an integer (corresponding to the harmonics of the the root of the sum of the squares of these two components. For
modulation frequency). more information on this demodulation technique, see the
Learn More section.
PROGRAMMABLE
GAIN TIA FPGA
SAMPLING RATE
= 25kSPS
AD7175-2 SAMPLE CHANNEL
CHANNEL REFERENCE CHANNEL
SELECT
ADA4528-1
ISAMPLE
PROGRAMMABLE SPI
GAIN TIA LPF QSAMPLE
SAMPLE 24 SPI
BITS DMA
90° IREF
QREF
HPF
REF
BEAM
SPLITTER
SEQUENCER LPF
ADA4528-1 PHASE
CONVERSION
COMPLETE
R G B
SPI
LED SELECT
LED DRIVERS DPLL
LED CLOCK
fCLOCK ~ 1.02kHz
12568-004
Figure 4. System Block Diagram Including FPGA Synchronous Detector
Power Supplies CIRCUIT EVALUATION AND TEST
The EVAL-CN0363-PMDZ board is powered from an external A complete set of documentation for the EVAL-CN0363-PMDZ
6 V to 12 V dc supply. The analog portion of the circuit is board including schematics, layout drawings, Gerber files, and
supplied by AVDD = 5 V from an ADP7102 low dropout bill of materials can be found in the CN-0363 Design Support
regulator. The digital portion of the circuit is supplied by Package at www.analog.com/CN0363-DesignSupport.
IOVDD = 3.3 V developed from an ADP1720 low dropout
The CN-0363 evaluation software communicates with the
regulator. Alternatively, IOVDD can be supplied from the
FPGA development board to capture and analyze data from the
PMOD connector, VCC, via a link option.
EVAL-CN0363-PMDZ circuit board.
The 2.5 V reference voltage is supplied by the internal 2.5 V
Equipment needed
reference of the AD7175-2 ADC.
 EVAL-CN0363-PMDZ circuit evaluation board
Circuit Performance Measurements
 6 V to 12 V dc, 500 mA power supply or wall wart
To verify the noise performance of the system, acquire data with  FPGA development board (such as ZedBoard) and a 12 V
all of the LEDs disabled. The synchronous detector still operates power supply
at the LED clock frequency, but no light synchronous to this  8 GB SD card, supplied with EVAL-CN0363-PMDZ
clock is detected; therefore, it removes all dc and ac signals.
 USB keyboard and mouse combination
Table 1 shows the noise-free bit performance.
 HDMI monitor (HD only)
Table 1. Noise-Free Bit Performance1  CN-0363 evaluation software (see the CN-0363 User Guide)
ADC Output Final Filtered Output  Distilled water and test liquid samples
Reference Sample Reference Sample
Getting Started
Channel Channel Channel Channel
Gain ADC ADC Output Output Detailed operation of the evaluation hardware and software is
1 MΩ 12.46 12.85 15.91 15.50 available in the CN-0363 User Guide.
33 kΩ 15.58 15.59 18.77 18.85 HDL software and drivers are provided in the software link to
1
Sample rate = 25 kSPS, excitation frequency = 1020 Hz, output filter
support various FPGA development platforms, such as the
bandwidth = 100 Hz. Avnet ZedBoard.
COMMON VARIATIONS The development platforms require an SD card, which is

supplied with the CN-0363 hardware. The SD card has been
Changing the values of the feedback resistors on the photodiode properly partitioned, but must be updated with the latest
amplifiers changes the amplifier gains, which is an easy way to images. The procedure is described the CN-0363 User Guide.
customize the circuit for a specific application with different
light levels. However, the compensation capacitor must also be Functional Diagram
changed to maintain the same bandwidth and to guarantee that Figure 5 shows a functional block diagram of the test setup.
the amplifier is stable. EVAL-CN0363-PMDZ
For systems measuring extremely low levels of light, the cutoff
frequency of the synchronous detector’s output low-pass filter BEAM
SPLITTER
can be set to a much lower frequency for the highest
LED
performance at the expense of long measurement cycle times.
Because the light output of the LEDs changes with temperature,
the system makes measurements as a ratio of the sample and the
reference channels. The photodiodes have a gain tolerance of up J2–
6V TO 12V DC
J2+ POWER SUPPLY
to ±11%; therefore, even ratiometric variations include some
PMOD
drift as the LED output changes with time and temperature.
The addition of an optical feedback network to control the
PMOD
LED light output reduces light variations with temperature
HDMI
and makes possible accurate single-ended measurements. MONITOR
Rather than modulate the LEDs with a square wave, a DDS

KEYBOARD/
or PWM in the FPGA can be used to generate a sine wave ZEDBOARD MOUSE
modulation. Sine wave modulation reduces the harmonic
content of the signal, makes filtering easier, and results in lower
POWER
12568-005
noise. SUPPLY
Figure 5. Evaluation System Functional Diagram
Setup For a simple way to verify this theory without resorting to
Set up the system as follows: harmful chemicals, measure the concentration of dye used for
food coloring. Figure 6 shows experimental results from
1. Connect the PMOD cable between the EVAL-CN0363-
different concentrations of Yellow #5 dye when measured with
PMDZ and the ZedBoard, and connect a 6 V to 12 V dc
the EVAL-CN0363-PMDZ.
power supply to the J2 power connector. Do not turn on
0.7
the supply at this time.
2. Connect a USB keyboard/mouse, HDMI monitor, and 0.6
power supply to the ZedBoard. Do not turn on the supply
at this time. 0.5
ABSORBANCE (A.U.)
Test 0.4
Initialize the system as follows:

0.3
1. Turn on the power to the EVAL-CN0363-PMDZ board.
2. Turn on the power to the ZedBoard. 0.2
3. Allow the system to boot.

0.1
4. If needed, enter the appropriate keyboard commands
described in the CN-0363 User Guide. 0
12568-006
0 0.0002 0.0004 0.0006 0.0008 0.0010 0.0012 0.0014
Calibration VOLUME CONCENTRATION (ml/ml)
The system requires an initial calibration to compensate for Figure 6. Absorbance Line for Yellow #5 Dye Under 465 nm
(Dominant Wavelength) Light
misalignment between the LEDs, beam splitter, and
photodiodes, as well as to compensate for any mismatch in the Yellow solutions strongly absorb blue light; therefore, the
response of the photodiodes. To calibrate the system, fill the two measurements were taken using the blue (465 nm dominant
containers with distilled water and insert them into the square wavelength) LED as the source. The x-axis shows the volume
holes in the PCB. It is also recommended that the photodiodes concentration (which is in terms of milliliters of dye per
be shielded from ambient light during the calibration procedure. milliliter of water, hence unitless), and the y-axis shows the
Start the automatic calibration procedure in the software; from absorbance. As predicted by Beer-Lambert’s law, the absorbance
the Menu bar, open the Calibration dialog box, and click varies linearly with concentration.
Calibrate. The full calibration procedure process takes a few Analyzing a Sample
seconds, and the progress bar indicates the current step. When Click the Analyze Sample button in the Automated Data
the calibration is complete, the calibration values are updated. Collection tab (see Figure 7) to perform an automated sample
Calibration removes the zero offset and sets the proper gain for analysis that cycles through all three colors and calculates the
each channel. The calibration data also includes a multiplication absorbance factor for each. The analysis takes a few seconds,
factor, K, that expresses the relative relationship between the and a progress bar is updated to indicate the current step. When
reference and sample channel values at full-scale excitation. the process is complete, the absorbance values are displayed. It
The software calculates the K multiplier for each LED color, so that is then possible to either try to match the sample to an existing
sample from the sample library or to save the sample into the
VREFERENCE _ CHANNEL
K 1 sample library for future use.
VSAMPLE _ CHANNEL
where K is the calculated calibration constant.
After performing a calibration, the software uses the calibration
constants in all subsequent measurements.
In the field of spectroscopy, absorbance is defined as the
logarithmic ratio of the light reaching the material under test to the
light transmitted through the material. Beer-Lambert’s law states
that the amount of light transmitted through a material decreases
exponentially with increasing path length and concentration. By
defining absorbance as a logarithm, absorbance is directly
proportional to the concentration of the material (given a
12568-007
constant path length).

V  Figure 7. Automated Data Collection Tab Display
Absorbance  log 10  REFERENCE K 
 VSAMPLE 
Current/Absorbance Measurement and Manual Settings absorbance of multiple samples to each other. Samples can also
The Current/Absorbance Measurement tab gives direct be removed from the library by selecting the sample and then
manual access to the LED and gain controls, and allows the user clicking Remove. A sample that has been removed from the
to view the raw data (see Figure 8). The following parameters library cannot be restored.
can be set: Excitation Frequency, Excitation Current, LED A photo of the EVAL-CN0363-PMDZ board is shown in Figure 10.
(Red, Green, or Blue), Reference Channel Gain, and Sample
Channel Gain.
If these values are modified, the initial default values can be
restored by running the automatic calibration procedure.
12568-009
Figure 9. Sample Library Tab Display
12568-008
Figure 8. Current/Absorbance Measurement Tab Display
Sample Library
The Sample Library tab (see Figure 9) allows the user to
manage and compare previously saved sample data. On the left-
hand side is a list of all samples. On the right-hand side are the
absorbance values for the currently selected samples.
12568-010
It is possible to select multiple samples by holding down the
CTRL key. This feature can be used to directly compare the
Figure 10. Photo of EVAL-CN0363-PMDZ
CN-0363 Design Support Package: AD7175-2 Data Sheet
Orozco, Luis. “Synchronous Detectors Facilitate Precision, Low- AD8615 Data Sheet
Level Measurements.” Analog Dialogue 48-11, November 2014.
AD5201 Data Sheet
Orozco, Luis. "Programmable-Gain Transimpedance Amplifiers
Maximize Dynamic Range in Spectroscopy Systems." Analog
Dialogue 47-05, May 2013. ADG633 Data Sheet
Kester, Walt, Scott Wurcer, and Chuck Kitchin. High Impedance ADG733 Data Sheet
Sensors, Practical Design Techniques for Sensor Signal ADG704 Data Sheet
Conditioning, Section 5. 1999.
ADG819 Data Sheet
Skoog, Douglas A., F. James Holler, and Stanley R. Crouch.
“An Introduction to Spectrometric Methods.” Instrumental REVISION HISTORY
Analysis. USA: Brooks/Cole, Cengage Learning, 2007. 5/15—Revision 0: Initial Version

CN12568-0-5/15(0)
Circuit Note
CN-0365
High Temperature, 16-Bit, 600 kSPS
Circuits from the Lab® reference designs are engineered and AD7981
PulSAR ADC
analog, mixed-signal, and RF design challenges. For more High Temperature, Low Power, Dual
AD8634
information and/or support, visit www.analog.com/CN0365. Operational Amplifier
ADR225 High Temperature, Low Power Reference
16-Bit, 600 kSPS, Low Power Data Acquisition System for

High Temperature Environments
EVALUATION AND DESIGN SUPPORT This circuit uses the AD7981, a low power (4.65 mW at
Evaluation Boards 600 kSPS), high temperature PulSAR® ADC, driven directly
CN-0365 Circuit Evaluation Board (EVAL-CN0365-PMDZ) from the AD8634 high temperature, low power op amp. The
System Demonstration Platform (EVAL-SDP-CB1Z) AD7981 ADC requires an external voltage reference between
PMOD to SDP Interposer Board (SDP-PMD-IB1Z) 2.4 V and 5.1 V, and in this application, the voltage reference
Design and Integration Files chosen is the micropower ADR225 precision 2.5 V reference,
Schematics, Layout Files, Bill of Materials which is also qualified for high temperature operation and has
a very low quiescent current of 60 μA maximum at 210°C.
All of the ICs in this design have packaging specially designed
A growing number of applications require data acquisition systems for high temperature environments, including monometallic
that must operate reliably at very high ambient temperature wire bonds. In addition, this reference design describes the
environments, such as downhole oil and gas drilling, avionics, selection of the passive components, printed circuit board (PCB)
and automotive. The circuit shown in Figure 1 is a 16-bit, 600 kSPS materials, and construction techniques to enable operation at
successive approximation analog-to-digital converter (ADC) these extreme temperatures. A complete design support package
system using devices rated, characterized, and guaranteed at including bill of materials, schematic, assembly, and layout files
175°C. Because many of these harsh environment applications is also available.
are battery-powered, the signal chain has been designed for low
power consumption while still maintaining high performance.
+5V
1/2
VREF = 2.5V AD8634
+5V 49.9Ω
2 6 3
VS OUTPUT 8 1
0.1µF 47µF 2
ADR225 4
GND –2.5V VDD = 2.5V VIO = 1.8V TO 5V

4
10Ω
+5V 0.1µF
47µF
1/2 0.1µF
VREF AD8634 1 2 10
0.1µF
5
VIN+ 8 7 85Ω 3 REF VDD VIO 9
6 IN+ SDI
GND 8
4 AD7981
2.7nF SDK
–2.5V ADC 7 PMOD
SDO 3-WIRE INTERFACE TO SDP BOARD
IN– 6
4 GND CNV
12605-001
Figure 1. High Temperature Data Acquisition System (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
CIRCUIT DESCRIPTION This headroom requirement necessitates the negative supply,
Analog to Digital Converter which was chosen to be −2.5 V.
The heart of this circuit is the AD7981, a 16-bit, low power, single The AD8634 is available in an 8-lead SOIC rated for 175°C and
supply ADC that uses a successive approximation architecture an 8-lead FLATPACK rated for 210°C.
(SAR) and is capable of sampling up to 600 kSPS. As shown in fIN +5V
KICKBACK AD7981
Figure 1, the AD7981 uses two power supply pins: a core supply, VPEAK REXT tCONV
85Ω
VDD, and a digital input/output interface supply, VIO. The
1/2 tACQ
AD8634 CEXT CDAC
VIO pin allows a direct interface with any logic between 1.8 V 2.7nF
and 5.0 V. The VDD and VIO pins can also be tied together to
12605-003
–2.5V
save on the number of supplies needed in the system, and they
are independent of power supply sequencing. Figure 3. SAR ADC Front End Amplifier and RC Filter
The AD7981 powers down automatically between conversions The RC filter between the ADC driver and AD7981 attenuates
to save power. Therefore, the power consumption scales linearly the kickback injected at the input of the AD7981 and band
with the sampling rate, making the ADC well suited for both limits the noise coming to its input. However, too much band
high and low sampling rates (even as low as a few Hz) and limiting can increase settling time and distortion. The
enables very low power consumption for battery-powered calculation of the optimum RC value is primarily based on the
systems. Additionally, oversampling techniques can be used to input frequency and throughput rate. For the example shown,
increase the effective resolution for low speed signals. R = 85 Ω and C = 2.7 nF are the optimum values yielding a
The AD7981 has a pseudo differential analog input structure cutoff frequency of 693 kHz. Details of the calculations can be
that samples the true differential signal between the IN+ and found in the Analog Dialogue article, Front-End Amplifier and
IN− inputs and rejects the signals common to both inputs. The RC Filter Design for a Precision SAR Analog-to-Digital Converter.
IN+ input can accept the unipolar, single-ended input signal In this circuit, the ADC driver is in unity gain buffer configuration.
from 0 V to VREF, and the IN− input has a restricted range of Adding gain to the ADC driver reduces the bandwidth of the
GND to 100 mV. The pseudo differential input of AD7981 driver and lengthens the settling time. In this case, the throughput
simplifies the ADC driver requirement and lowers power of the ADC may need to be reduced or an additional buffer as a
dissipation. The AD7981 is available in a 10-lead MSOP rated driver can be used after the gain stage.
for 175°C. A simplified connection diagram is shown in Voltage Reference
Figure 2.
The ADR225 2.5 V voltage reference uses only 60 μA maximum
2.5V TO 5.0V 2.5V
of quiescent current at 210°C and has very low drift of 40 ppm/°C
typical, making it an ideal device for this low power data
acquisition circuit. The ADR225 has an initial accuracy of ±0.4%
REF VDD VIO 1.8V TO 5.0V and can operate over a wide supply range of 3.3 V to 16 V.
0V TO VREF
SDI
IN+
AD7981 SCK 3- OR 4-WIRE INTERFACE The voltage reference input of the AD7981, like other SAR ADCs,
IN– (SPI, DAISY CHAIN, CS)
SDO has a dynamic input impedance and must therefore be driven
GND CNV
12605-002
by a low impedance source with efficient decoupling between

the REF pin and GND, as shown in Figure 4. The AD8634 is
Figure 2. AD7981 Connection Diagram well suited as a reference buffer in addition to its ADC driver
ADC Driver application.
The input of AD7981 can be driven directly from low impedance Another advantage of using a reference buffer is that the noise
sources; however, high source impedances significantly degrade on the voltage reference output can be further reduced by adding
the ac performance, especially total harmonic distortion (THD). a low pass RC filter. In this circuit, a 49.9 Ω resistor and 47 μF
Therefore, it recommended to use an ADC driver or op amp, capacitor give a cutoff frequency of approximately 67 Hz.
such as the AD8634, to drive the input of the AD7981 as shown +5V
1/2
in Figure 3. At the start of the acquisition time, the switch closes, +5V
AD8634
and the capacitive DAC injects a voltage glitch (kickback) on 49.9Ω
VREF 47µF
the ADC input. The ADC driver helps to settle this kickback as ADR225 47µF
well as to isolate it from the signal source.
–2.5V
The low power (1.3 mA/amplifier) AD8634 dual precision op amp
is suited for this task because its excellent dc and ac specifications AD7981
are a good fit for sensor signal conditioning and elsewhere in the
12605-004
signal chain. While the AD8634 has rail-to-rail outputs, the input
requires 300 mV headroom from the positive and negative rails. Figure 4. SAR ADC Reference Buffer and RC Filter
During conversions, current spikes as high as 2.5 mA can occur
on the AD7981 reference input. A high value reservoir capacitor
is placed as close as possible to the reference input to supply that AuAl IMC VOIDING
current and to keep the reference input noise low. Typically, a
low ESR, 10 μF or more, ceramic capacitor is used; however, for
high temperature applications, ceramic capacitors are not available.
12605-006
For this reason, a low ESR, 47 μF tantalum capacitor was chosen
that has minimal impact on the performance of the circuit.
Figure 6. Au Ball Bond on Al Pad, After 500 Hours at 195°C
Digital Interface
To avoid these failures, Analog Devices uses an over pad
The AD7981 offers a flexible serial digital interface compatible
metallization (OPM) process to create a gold bond pad surface
with SPI, QSPI, and other digital hosts. The interface can be
for the gold bond wire to attach. This monometallic system
configured for a simple 3-wire mode for the lowest input/output
does not form intermetallics and has been proven reliable in
count, or 4-wire mode that allows options for the daisy-chained
qualification testing with over 6000 hours soak at 195°C, as
readback and busy indication. The 4-wire mode also allows
shown in Figure 7.
independent readback timing from the CNV (convert input),
which enables simultaneous sampling with multiple converters.
The PMOD interface used on this reference design implements the Au BALL BOND
simple 3-wire mode with SDI tied high to VIO. The VIO voltage
is supplied externally from the SDP-PMOD interposer board.
Power Supplies OPM LAYERS
12605-007
This reference design requires external, low noise power
supplies for the +5 V and −2.5 V rails. Because the AD7981 is
low power, it can be supplied directly from the reference buffer, Figure 7. Au Ball Bond on OPM Pad, After 6000 Hours at 195°C
as shown in Figure 5, thereby eliminating the need for an Although Analog Devices has shown reliable bonding at 195°C,
additional power supply rail, saving power and board space. the plastic package is rated for operation only up to 175°C due
+5V 2.5V
to the glass transition temperature of the molding compound.
10Ω In addition to the 175°C rated products used on this circuit,

1/2 210°C rated models are also available in a ceramic FLATPACK
AD8634 47µF
REFERENCE 0.1µF package. Known good die (KGD) are also available for systems
BUFFER –2.5V
that require custom packaging.
REF VDD VIO Analog Devices has a comprehensive reliability qualification
AD7981 program for high temperature products that includes high
12605-005
temperature operating life (HTOL), with the devices biased at

Figure 5. Supplying ADC Reference from Reference Buffer the maximum operating temperature. High temperature
products are data sheet specified for a minimum of 1000 hours
IC Packaging and Reliability
at the maximum rated temperature. Full production testing is
Devices in the Analog Devices high temperature portfolio the last step required to guarantee performance for each device
go through a special process flow that includes design, that is manufactured. Each device in the Analog Devices high
characterization, reliability qualification, and production test. temperature portfolio is production tested at elevated
Part of this process is special packaging designed specifically temperature to ensure that performance is met.
for extreme temperatures. A special material is used for the
175°C plastic packages in this circuit.
One of the major failure mechanisms in high temperature
packaging is the bond wire-to-bond pad interface, particularly
when gold (Au) and aluminum (Al) metals are mixed, as is typical
in plastic packages. Elevated temperature accelerates the growth of
AuAl intermetallic compounds. It is these intermetallics that are
associated with bond failures, such as brittle bonds and voiding,
which can occur in a few hundred hours, as shown in Figure 6.
Passive Components Performance Expectations
Passive components chosen must be rated for high temperatures. The AD7981 is specified for 91 dB SNR typical with a 1 kHz
For this design, 175°C+ thin film, low TCR resistors were used. input tone and a 5 V reference. However, when using low
COG/NPO capacitors were used for low value filter and decoupling reference voltages, as is common in low power/low voltage
applications and have a very flat coefficient over temperature. systems, some degradation in SNR is expected. From the
High temperature rated tantalum capacitors are available in AD7981 data sheet typical performance curves, approximately
larger values than ceramic capacitors and are commonly used 86 dB of SNR is expected at room temperature with a 2.5 V
for power supply filtering. The SMA connector used on this reference. This SNR value compares well with the performance
board is rated for 165°C; therefore, it must be removed for long achieved when the circuit was tested at room temperature with
duration testing at elevated temperatures. Similarly, the insulation approximately 86 dB SNR, as shown in Figure 8.
material on the 0.1” header connectors (J2 and P3) is only rated
for short durations at high temperature and must also be removed
for prolonged high temperature testing.
PCB Layout and Assembly
The PCB for this circuit is designed so that the analog signals
and digital interface are on opposites sides of the ADC, with no
switching signals running under the IC or near analog signal
paths. This design minimizes the amount of noise that is
coupled into the ADC die and supporting analog signal chain.
The pinout of the AD7981, with all its analog signals on the left
side and all its digital signals on the right side, eases this task.
The voltage reference input, REF, has a dynamic input
impedance and must be decoupled with minimal parasitic
12605-008
inductances, which is achieved by placing the reference
decoupling capacitor as close as possible to the REF and GND Figure 8. AC Performance with 1 kHz Input Tone, 580 kSPS, 25°C
pin and making the connection to the pin with a wide, low
impedance trace. The layout of this board was purposely When this circuit is evaluated over temperature, SNR performance
designed with components only on the top side of the board, to only degrades to approximately 84 dB at 175°C, as shown in
facilitate testing over temperature where heat is applied from Figure 9. THD remains better than −100 dB, as shown in Figure 10.
the bottom of the board. For further layout recommendations, The FFT summary for the circuit at 175°C is shown in Figure 11.
86.5
see the AD7981 data sheet.
For high temperature circuits, special circuit materials and 86.0
assembly techniques must be used to ensure reliability. FR4
is a common material used for PCB laminates; however, 85.5
commercial grade FR4 has a typical glass transition temperature

85.0
SNR (dB)
of approximately 140°C. Above 140°C, the PCB begins to break

down, delaminate, and cause stress on components. A widely 84.5
used alternative for high temperature assemblies is polyimide,
which typically has a glass transition temperature of greater 84.0
than 240°C. A 4-layer polyimide PCB was used in this design.

83.5
The PCB surface is also a concern, especially when used with
solders containing tin, because of the tendency of the solder to 83.0
12605-009
0 25 50 75 100 125 150 175 200

form intermetallics with copper traces. A nickel-gold surface TEMPERATURE (°C)
finish is commonly used, where the nickel provides a barrier, Figure 9. SNR over Temperature, 1 kHz Input Tone, 580 kSPS
and the gold provides a good surface for the solder joint
bonding. High melting point solder must also be used with a
good margin between the melting point and maximum
operating temperature of the system. SAC305 lead free solder
was chosen for this assembly. With a melting point of 217°C,
there is a margin of 42°C from the highest operational
temperature of 175°C.
–98
–99 This circuit uses the EVAL-CN0365-PMDZ circuit board, the
SDP-PMD-IB1Z interposer board, and the EVAL-SDP-CB1Z
–100
system demonstration platform (SDP) board. The interposer
board and the SDP board have 120-pin mating connectors. The
–101
THD (dB)
interposer board and the EVAL-CN0365-PMDZ board have

–102 12-pin PMOD matching connectors, allowing quick setup and
evaluation of the circuit performance. The EVAL-CN0365-
–103 PMDZ board contains the circuit to be evaluated, as described
in the CN-0365, and the SDP evaluation board is used with the
–104
CN-0365 Evaluation Software.
–105 Equipment Needed
12605-010
0 25 50 75 100 125 150 175 200
TEMPERATURE (°C) The following equipment is needed:
Figure 10. THD over Temperature, 1 kHz Input Tone, 580 kSPS
 EVAL-CN0365-PMDZ board
 System Demonstration Platform (EVAL-SDP-CB1Z)
 PMOD to SDP Interposer Board (SDP-PMD-IB1Z)
 CN-0365 Evaluation Software
 Function generator/signal source, such as the Audio
Precision SYS-2522 used in these tests
 Power supplies: +5 V and −2.5 V
 Power supply: +6 V wall wart (EVAL-CFTL-6V-PWRZ)
 PC operating Windows® XP (SP2), Windows Vista or
Windows 7 Business/Enterprise/Ultimate editions (32-bit/
64-bit systems) with USB port and USB cable
Getting Started
To get started, take the following steps:
12605-011
1. Download the CN-0365 Evaluation Software to the PC

Figure 11. AC Performance with 1 kHz Input Tone, 580 kSPS, 175°C from ftp://ftp.analog.com/pub/cftl/CN0365.
2. Install the software prior to connecting the SDP board to
the USB port of the PC, to ensure that the SDP board is
recognized when it connects to the PC.
3. Unzip the downloaded file.
4. Run the setup.exe file.
5. Follow the on-screen prompts to finish the installation. It is
recommended to install all software components to the
default locations.
Functional Block Diagram Test
Figure 12 shows the functional diagram of the test setup. Launch the evaluation software. The software communicates to
Setup the SDP board if the Analog Devices System Development
Platform drivers are listed in Windows Device Manager. After
To set up the circuit, take the following steps:
USB communications are established, the evaluation software
1. Connect the EVAL-CFTL-6V-PWRZ (+6 V dc power can be used to test, view, and save circuit performance metrics.
supply) to the SDP-PMD-IB1Z interposer board via the dc
Further details on the operation of the software can be found in
barrel jack.
the UG-340 and at the Evaluating 14-/16-/18-Bit ADCs from the
2. Connect the SDP-PMD-IB1Z interposer board to the
8/10 LEAD PulSAR® Family wiki page.
EVAL-SDP-CB1Z SDP board via the 120-pin CON A
connector. For testing over temperature in an environmental chamber,
3. Connect the EVAL-SDP-CB1Z SDP board to the PC via extension harnesses (not supplied) can be used for the analog
the USB cable. input, power supply, and PMOD connections. These harnesses
4. Connect the EVAL-CN0365-PMDZ evaluation board to must be as short as possible, and best practices must be used to
the SDP-PMD-IB1Z interposer board via the 12-pin avoid noise. The SMA connector used on this board is rated for
header PMOD connector. 165°C; therefore, it must be removed for long duration testing at
5. Connect the +5 V (VS+) and −2.5 V (VS−) power supplies elevated temperatures. Similarly, the insulation material on the
to the EVAL-CN0365-PMDZ P3 header. The VDD voltage 0.1” header connectors (J2 and P3) is only rated for short
(2.5 V) does not need an external connection in the default durations at high temperature and must also be removed for
configuration because it is generated on-board. prolonged high temperature testing.
6. Connect the signal source to the EVAL-CN0365-PMDZ A photo of the EVAL-CN0365-PMDZ board is shown in
via the SMA connector. Figure 13.
7. Set the Audio Precision SYS-2522 (or equivalent signal
generator) for a 1 kHz frequency and a 2.5 V p-p sine wave
with a 1.25 V dc offset.
DC +6V SUPPLY
POWER SUPPLIES OR
WALL WART
+5V –2.5V GND
P3
VIN
AUDIO PMOD USB PC WITH
PRECISION J1 J2 INTERPOSER SDP FFT
SYS-2522 BOARD BOARD ANALYSIS
EVAL-CN0365-PMDZ SOFTWARE
12-PIN 120-PIN 12605-012

CONNECTOR CONNECTOR
Figure 12. Circuit Test Setup for Measuring AC Performance

12605-013
Figure 13. Photo of EVAL-CN0365-PMDZ Circuit Board
CN-0365 Design Support Package: CN-0365 Circuit Evaluation Board (EVAL-CN0365-PMDZ)
www.analog.com/CN0365-DesignSupport System Demonstration Platform (EVAL-SDP-CB1Z)
System Demonstration Platform (SDP) SDP-PMOD Interposer Board (SDP-PMD-IB1Z)
UG-340 User Guide AD7981 Data Sheet
Evaluating 14-/16-/18-Bit ADCs from the 8/10 LEAD PulSAR® AD8634 Data Sheet
Family Wiki Page
ADR225 Data Sheet
High Temperature Products from Analog Devices
Watson, Jeff and Gustavo Castro, “High Temperature Electronics REVISION HISTORY
Pose Design and Reliability Challenges,” Analog Dialogue, 6/15—Revision 0: Initial Version
Volume 46, April 2012.
Watson, Jeff and Maithil Pachchigar, “Harsh Environments
Conquered—Lower Power, Precision, High Temperature
Components for Extreme Temperature Applications,” MS-
2707, Analog Devices.
Walsh, Alan, “Front-End Amplifier and RC Filter Design for a
Precision SAR Analog-to-Digital Converter,” Analog Dialogue,
Vol. 46, December 2012.
Walsh, Alan “Voltage Reference Design for Precision Successive-
Approximation ADCs,“ Analog Dialogue, Vol. 47, June 2013.
MT-021 Tutorial, Successive Approximation ADCs, Analog Devices
Mystery of "AGND" and "DGND," Analog Devices.

CN12605-0-6/15(0)
Circuit Note
CN-0370
Serial-Input, Voltage Output, Unbuffered
Circuits from the Lab® reference designs are engineered and AD5542A
16-Bit DAC
analog, mixed-signal, and RF design challenges. For more Rail-to-Rail Input/Output, Zero Input
ADA4500-2
information and/or support, visit www.analog.com/CN0370. Crossover Distortion Amplifier
Ultralow Noise, High Accuracy, 2.5 V
ADR4525
Voltage Reference
16-Bit, Single-Supply LED Current Driver with Less than ±1 LSB Integral and
Differential Nonlinearity
EVALUATION AND DESIGN SUPPORT and differential nonlinearity and has a 0.1 Hz to 10 Hz noise of
Circuit Evaluation Boards
less than 45 nA p-p for a full-scale output current of 20 mA.
CN-0370 Circuit Evaluation Board (EVAL-CN0370-PMDZ) The innovative output driver amplifier eliminates the crossover
System Demonstration Platform (EVAL-SDP-CB1Z) nonlinearity normally associated with most rail-to-rail input op
PMOD to SDP Interposer Board (SDP-PMD-IB1Z) amps that can be as high as 4 LSBs or 5 LSBs for a 16-bit system.
Design and Integration Files This industry-leading solution is ideal for pulse oximetry
Schematics, Layout Files, Bill of Materials applications where 1/f noise superimposed on the LED
CIRCUIT FUNCTION AND BENEFITS brightness levels affects the overall accuracy of the
measurement.
The circuit in Figure 1 is a complete single-supply, low noise
LED current source driver controlled by a 16-bit digital-to- Total power dissipation for the three active devices is less than
analog converter (DAC). The system maintains ±1 LSB integral 20 mW typical when operating on a single 5 V supply.
VPMOD
VPMOD
3.3V TO 5.5V 10µF VPMOD VEXT
VPMOD ADR4525
+
2.5V
VIN VOUT
10µF 0.1µF 0.1µF

GND
1/2 VLED
ADA4500-2
IOUT
SERIAL
INTERFACE REFS REFF VDD 1/2
CS ADA4500-2 D
SCLK AD5542A VOUT
DIN G
LDAC S
DGND AGND AGND
VOUT
RLIMIT
124Ω
13447-001
AGND
Figure 1. ±1 LSB Linear 16-Bit LED Current Source Driver (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
Devices engineers. Standard engineering practices have been employed in the design and construction
of each circuit, and their function and performance have been tested and verified in a lab environment
whatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) Fax: 781.461.3113 ©2015 Analog Devices, Inc. All rights reserved.
CIRCUIT DESCRIPTION A typical rail-to-rail input amplifier uses two differential pairs
In a typical pulse oximetry application, an LED is pulsed from a (PNP and NPN, or PMOS and NMOS) to achieve rail-to-rail
high level of current (for example, 3/4 scale) to a lower level of input swing (see the MT-035 Tutorial). One differential pair is
current (for example, 1/4 scale). The on-time of these pulses is active at the low range of the input common-mode voltage, and
typically in the order of several hundred microseconds. Peak- the other pair is active at the high end. This classic complementary
to-peak 1/f noise superimposed on the LED brightness levels dual differential pair topology introduces crossover distortion
during the on-time affects the accuracy of the overall during the transition between one differential pair to the other.
measurement and must be minimized. The change in offset voltage causes nonlinearity when the
amplifier is used as a DAC buffer.
Figure 1 shows the single-supply signal chain that consists of a
voltage reference, a DAC, a DAC output buffer, and a current The ADA4500-2 uses an integrated charge pump in its input
source. structure to achieve rail-to-rail input swing without the need for
a second differential pair. Therefore, it does not exhibit
The DAC is the AD5542A 16-bit, serial input, voltage output crossover distortion. Using a zero crossover distortion amplifier
segmented R-2R CMOS DAC. The output voltage of the DAC is in this single-supply system provides wide dynamic output
dependent on the reference voltage, as shown in the following range while maintaining linearity over the entire input
equation: common-mode range. Details of the operation of the
VREF  D ADA4500-2 can be found in the ADA4500-2 data sheet.
VOUT 
2N The output impedance of the DAC is constant (typically 6.25 kΩ)
where: and code independent. The output buffer must therefore have a
D is the decimal data word loaded in the DAC register. high input impedance and low input bias current to minimize
N is the number of bits. errors. The ADA4500-2 is a suitable candidate with high input
impedance and 2 pA maximum of input bias current at room
For a reference of 2.5 V and N = 16, the equation simplifies to
temperature, and 190 pA maximum of input bias current over
the following:
temperature. This results in 1.2 μV worst-case error due to input
2. 5  D 2. 5  D bias current flowing through the 6.25 kΩ DAC impedance,
VOUT  
216 65,536 which is significantly less than 1 LSB.
This gives a VOUT of 1.25 V at mid scale, and 2.5 V at full scale. The output of the DAC is buffered and used to drive the power
The LSB size is 2.5 V/65,536 = 38.1 μV. MOSFET (IRLMS2002TRPBF). The MOSFET converts the DAC
output voltage into current that drives the LED. The MOSFET
One LSB at 16 bits is also 0.0015% of full scale or 15 ppm full in the circuit is able to handle currents up to 6.5 A; however, the
scale. current is limited to 20 mA, which is the maximum rated current
The DAC reference pin is driven by an 2.5 V ADR4525 voltage of the LED supplied on the EVAL-CN0370-SDPZ board. The
reference buffered with the ADA4500-2. The ADR4525 voltage board has provisions to easily change the full-scale current to
reference provides a high precision, low noise (1.25 μV p-p, the LED by changing the RLIMIT resistor. The maximum current
0.1 Hz to 10 Hz), and stable reference to the DAC. The can be calculated by
ADR4525 uses an innovative core topology to achieve high IMAX = 2.5 V/RLIMIT
accuracy while offering industry-leading temperature stability
and noise performance. The low output voltage temperature Jumper options allow the LED to be connected to either the
coefficient (2 ppm/°C maximum) and low long-term output PMOD voltage (VPMOD) or an external voltage (VEXT).
voltage drift of the device also improve system accuracy over The VEXT option is required to provide sufficient headroom
time and temperature variations. The initial room temperature for the MOSFET when operating with VPMOD = 3.3 V. For
error of the ADR4525B is ±0.02% maximum, which is example, if VOUT = 2.5 V, VDS = 0.7 V, and VLED = 0.7 V, then
approximately 13 LSBs at 16 bits. VEXT must be greater than 2.5 V + 0.7 V + 0.7 V = 3.9 V.
The dual ADA4500-2 is selected as the DAC output buffer as well An alternative that allows 3.3 V supply operation is to limit the
as the voltage reference buffer. The ADA4500-2 is a high precision full-scale output voltage to approximately 1.9 V and only use
amplifier with maximum offset voltage of 120 μV, offset drift of 76% of the DAC output range. The RLIMIT resistor must be
less than 5.5 μV/°C, 0.1 Hz to 10 Hz noise of 2 μV p-p, and changed to approximately 95 Ω to maintain 20 mA full-scale
maximum input bias current of 2 pA. Its innovative rail-to-rail output current at 1.9 V output.
input structure eliminates crossover distortion and therefore The AD5542A is available in a 10-lead MSOP or 10-lead LFCSP.
makes it an excellent choice as a DAC buffer. The ADR4525 is available in an 8-lead SOIC, and the
ADA4500-2 is available in an 8-lead MSOP or 8-lead LFCSP.
10
Integral Nonlinearity (INL) and Differential Nonlinearity
(DNL) Measurements
5
INL is the deviation in LSB of the actual DAC transfer function
from an idealized transfer function. DNL is the difference
0
INL ERROR (LSB)

between an actual step size and the ideal value of 1 LSB. This
system solution provides a 16-bit resolution with ±1 LSB DNL
–5
and INL. Figure 2 and Figure 3 show the DNL and INL
performance of the circuit.
–10
0.6
–15
0.4
13447-004
–20
0.2 0 10000 20000 30000 40000 50000 60000 70000
DNL ERROR (LSB)
CODE
0
Figure 4. DAC Nonlinearity when Using Op Amp Buffer with Traditional
Rail-to-Rail Input Stage
–0.2 Noise Measurements

The targeted 0.1 Hz to 10 Hz noise for the complete system was
–0.4 less than 14 μV p-p measured at VOUT. The noise of the three
13447-002
components can be combined in a root-sum-squares (RSS)

–0.6 manner to estimate the total system noise. The 0.1 Hz to 10 Hz
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
values are
CODE  AD5542A: 0.134 μV p-p
Figure 2. Differential Nonlinearity (DNL)  ADR4525: 1.25 μV p-p
0.6
 ADA4500-2 (reference buffer): 2 μV p-p
0.4  ADA4500-2 (DAC buffer): 2 μV p-p
0.2 The RSS value of the above contributors is 3.1 μV p-p.

The true noise of the circuit is measured by using a noise
INL ERROR (LSB)
0
measuring box with a gain of 10,000 combined with a 0.1 Hz
–0.2 to 10 Hz filter. Figure 5 shows the noise test setup.
–0.4 The EVAL-SDP-CB1Z System Development Platform (SDP)
and SDP-PMD-IB1Z interposer boards were removed from the
–0.6
setup, and the supply was taken from a 4.5 V battery.
–0.8
13447-003
0.1Hz TO 10Hz
±15V POWER
–1.0 NOISE MEASURING OSCILLOSCOPE
SUPPLY
BOX
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
CODE AGND VOUT

Figure 3. Integral Nonlinearity (INL) 13447-005
Note that the DNL and INL measurements exclude the 100 codes 4.5V BATTERY EVAL-CN0370-PMDZ
(approximately 4 mV) from the lower end of the range. This is

Figure 5. Test Setup for Measuring 0.1 Hz to 10 Hz Noise with Gain of 10,000
because the MOSFET leakage current causes the output voltage
to become nonlinear in this region. The noise output of the box with the input shorted and the
Figure 4 shows the nonlinearity introduced using an op amp noise with the circuit connected were measured and were
with a traditional rail-to-rail input stage. This plot shows the 7.81 μV p-p and 9.6 μV p-p, respectively, as shown in Figure 6
crossover distortion when the active differential pair changes and Figure 7. The noise of the two systems is uncorrelated and
from the PNP pair to the NPN pair. The error swings from therefore combines in an RSS manner, and the system noise is
+4 LSB to −15 LSB in this region. calculated as follows:
System Noise  (9.6)2  (7.81)2  5.58 μV pp
The corresponding noise current driving the LED is 5.58 μV ÷

124 Ω = 45 nA for a full-scale current of 20 mA.
Board Layout Considerations
It is important to carefully consider the power supply and
ground return layout on the board. The printed circuit board
must have separate analog and digital sections. If the circuit is
used in a system where multiple devices require an analog
ground to digital ground connection, make the connection at
only one point. Power supplies to all components must be
bypassed with at least 0.1 μF capacitors. These bypass capacitors
must be as physically close as possible to the device, with the
capacitor ideally right up against the device. Choose the 0.1 μF
capacitor to have low effective series resistance (ESR) and low
13447-006
2 effective series inductance (ESL), such as ceramic capacitors.
CH1 20.0mV/DIV 1.00s/DIV
This 0.1 μF capacitor provides a low impedance path to ground
Figure 6. Output Noise with Input to Noise Measuring Box Shorted Measures for transient currents. The power supply line must also have as
78.1 mV p-p (7.81 μV p-p Referenced to Input)
large a trace as possible to provide a low impedance supply
path. Use proper layout, grounding, and decoupling techniques
to achieve optimum performance (see the the MT-031 Tutorial,
Grounding Data Converters and Solving the Mystery of AGND
and DGND and the MT-101 Tutorial, Decoupling Techniques).
A complete design support package including layout files,
schematics, and bill of materials, is available at
www.analog.com/CN0370-DesignSupport.
COMMON VARIATIONS
For a lower power consumption solution (at lower speed), use
the ADA4505-1/ADA4505-2/ADA4505-4 as the output buffer.
13447-007
2 The ADA4505-1/ADA4505-2/ADA4505-4 are micropower,

CH1 20.0mV/DIV 1.00s/DIV zero crossover distortion amplifiers with low input bias current.
Figure 7. Output Noise with EVAL-CN0370-PMDZ Connected Measures The ADR441 and ADR421are suitable candidates to provide the
96 mV p-p (9.6 μV p-p Referenced to Input)
2.5 V reference. They feature high accuracy, low noise and
accept input voltages up to 18 V.
The AD5063 is a 16-bit, unbuffered voltage output DAC that
allows bipolar mode operation in a dual-supply application.
This circuit uses the EVAL-CN0370-PMDZ circuit board and Connect the 120-pin connector on the SDP-PMD-IB1Z
the EVAL-SDP-CB1Z SDP board with the SDP-PMD-IB1Z interposer board to the connector marked CON A on the
interposer board. The SDP board and the interposer boards EVAL-SDP-CB1Z SDP board. Use nylon hardware to secure the
have 120-pin mating connectors, allowing quick setup and two boards firmly, using the holes provided at the ends of the
evaluation of the circuit performance. The EVAL-CN0370-PMDZ 120-pin connectors. Connect the EVAL-CN0370-PMDZ to the
board is connected via the PMOD connector J3. The EVAL- J3 PMOD connector.
CN0370-PMDZ contains the circuit to be evaluated, as described With power to the supply off, connect a 6 V wall wart power
in this circuit note. The SDP board and the interposer board are supply to the J1 connector. Connect the USB cable supplied
used with the CN-0370 evaluation software to capture the data with the SDP board to the USB port on the PC. Do not connect
from the EVAL-CN0370-PMDZ circuit board. The software the USB cable to the mini USB connector on the SDP board at
user guide is available at www.analog.com/wiki-CN0370. this time.
Equipment Needed Test
The following equipment is needed: Apply power to the interposer board then connect the USB cable
 PC with a USB port and Windows® XP, Windows Vista from the PC to the USB mini connector on the SDP board and
(32-bit), or Windows 7 (32-bit) launch the evaluation software. The software communicates
 EVAL-CN0370-PMDZ circuit evaluation board with the EVAL-CN0370-PMDZ if the EVAL-SDP-CB1Z System
 EVAL-SDP-CB1Z SDP board Development Platform is listed in Windows Device Manager.
 SDP-PMD-IB1Z interposer board After USB communications are established, the SDP board can
 CN-0370 evaluation software (download from be used to write date to the EVAL-CN0370-PMDZ circuit
ftp://ftp.analog.com/pub/cftl/CN0370/) evaluation board.
 Power supply: 6 V wall wart or EVAL-CFTL-6V-PWRZ Figure 9 shows a photograph of the EVAL-CN0370-PMDZ
 Agilent 34401A multimeter or equivalent circuit evaluation board.
 GPIB to USB cable (required only when making linearity Information and details regarding test setup and how to use
measurements on the circuit) the evaluation software for data capture can be found in the
Getting Started CN-0370 Software User Guide.
Download the CN-0370 evaluation software and install it on the Information regarding the SDP board is available in the SDP
PC. User Guide (UG-277).
Figure 8 shows the functional block diagram of the test setup.
13447-009
6V
SUPPLY
Figure 9. EVAL-CN0370-PMDZ Circuit Evaluation Board

EVAL-CN0370-PMDZ J1 EVAL-SDP-CB1Z
PMOD J3 J4 CON A
SDP-PMD-IB1Z
AGND VOUT USB
GPIB USB
13447-008
MULTIMETER PC
CN-0370 Design Support Package: AD5542A Data Sheet
Kester, Walt. The Data Conversion Handbook, Chapter 3 and ADR4525 Data Sheet
Chapter 7. Analog Devices, 2005.
REVISION HISTORY
AN-1212 Application Note. Single-Supply Low Noise LED
Current Source Driver Using a Current Output DAC in the
Reverse Mode. Analog Devices.
Circuit Note CN-0348. 16-Bit Single-Supply Buffered Voltage
Output Digital-to-Analog Conversion with Less Than ±1 LSB
and Differential Nonlinearity. Analog Devices.
MT-015 Tutorial. Basic DAC Architectures II: Binary DACs.
Analog Devices.
MT-016 Tutorial. Basic DAC Architectures III: Segmented DACs.
Analog Devices.
MT-035 Tutorial. Op Amp Inputs, Outputs, Single-Supply, and

CN13447-0-9/15(0)
Circuit Note
CN-0373
2.5 kV, Signal and Power Isolated, Dual
ADM3252E
Channel, RS-232 Line Driver/Receiver
2.5 kV, Signal and Power Isolated, ±15 kV
ADM2587E ESD Protected, Full/Half-Duplex, RS-485
Circuits from the Lab® reference designs are engineered and Transceiver
analog, mixed-signal, and RF design challenges. For more ADuM3160 Full/Low Speed, 2.5 kV, USB Digital Isolator
2.5 kV, Isolated Switch Regulator With
ADuM3070
Integrated Feedback
ADP190 Logic Controlled, High-Side Power Switch
ADP7102 20 V, 300 mA, Low Noise, CMOS LDO
Isolated USB to Isolated RS-485/Isolated RS-232 Interface
EVALUATION AND DESIGN SUPPORT the ground connection between bus and digital pins, thereby
Circuit Evaluation Boards removing possible ground loops within the system.
CN-0373 Circuit Evaluation Board (EVAL-CN0373-EB1Z) The TIA/EIA RS-485 bus standard is one of the most widely used
Design and Integration Files physical layer bus designs in industrial and instrumentation
Schematics, Layout Files, Bill of Materials applications. RS-485 offers differential data transmission
between multiple systems, often over very long distances.
RS-485 communication offers additional robustness through
The circuit shown in Figure 1 provides a completely isolated differential communication when compared to the RS-232
connection between the popular USB bus and an RS-485 or standard.
RS-232 bus. Both signal and power isolation ensures a safe USB
TIA/EIA RS-232 devices are widely used in industrial machines,
device interface to an industrial bus or debug port, allowing
networking equipment, and scientific instruments. In modern
TIA/EIA-485/232 bus traffic monitoring and the convenience of
personal computers, which are often used for debugging network
sending and receiving commands to and from a PC that is not
problems, USB has displaced RS-232 from most of its peripheral
equipped with an RS-485 or RS-232 port.
interface roles, and many computers do not come equipped
Isolation in this circuit increases system safety and robustness with RS-232 ports. The circuit in Figure 1 offers a robust and
by providing protection against electrical line surges and breaks compact solution for both RS-232 and RS-485 interfaces.
Rev. 0
VISO
+3.3V VISO = +3.3V
L3
T2 D5 47µH
64µH
C2 VIN VOUT
47µF
R19 C12 ADP190
C15 16.5kΩ 0.1µF
47µF D8
J1
GND2
VIN = 6V VOUT = 5V
VIN VOUT X1 VREG
ADP7102 ADuM3070 C16 10nF 100nF
SENSE C11 R18 VDD2
0.1µF ADM2587E
1µF 549Ω J2
X2 VCC VISOIN RS-485
NC FB VFB GND2 BUS
EN/ D6 A
UVLO LED R16 RXD
PG R20 10kΩ
EP GND VDDA OC 100kΩ RE B
0.1µF GND1 GND2 Z

12MHz DE
GND1
OSC
Y
TXD
GND1 GND1 GND2
VISOOUT
VISO = +3.3V GND485
18pF 18pF
FERRITE
600Ω GND1 GND2 0.1µF 10µF
GND2 GND2
4.7µF 0.1µF GND485

VISO = +3.3V GND2 GND485
FERRITE GND2 VISO = +3.3V

600Ω
OSCI
OSCO
VPHY
VPLL
BDBUS1
4.7µF 0.1µF VIN
PWREN# VOUT
GND2 ADP190
FT2232H BCBUS0
VISO = +3.3V
BDBUS0
GND2
VBUS1 VBUS2 DM
ADBUS1
DP VCC VISO
C3
VCCIO(20)
VCCIO(42)
VCCIO(56)
ADuM3160 VCCIO(31) ADBUS3 10µF 0.1µF + 0.1µF 0.1µF 10µF

VDD1 VDD2
VREGIN
0.1µF ADM3252E V+ 10V

ADBUS0 GND232
C1+
0.1µF PDEN SPD ADBUS2 + C1
0.1µF J3/J5
C1– 16V RS-232
ROUT1 BUS
GND1 SPU PIN ROUT2 TOUT1
TIN1 TOUT2
VBUS
UD– DD– TIN2 RIN1
J4 R5
USB D+ RIN2
USB GND2 GND2
CABLE UD+ DD+
MINI R7 0.1µF C2+
TO PC D– + C2
0.1µF GND232
0.1µF 0.1µF
C2– 16V
GND GND1 GND2
0.1µF V– C4
GND GNDISO
GND2 + 0.1µF
FERRITE GND2 GND232 16V
600Ω
GND1 GND2
12925-001
GND1
ISOLATION ISOLATION
BARRIER BARRIER
Figure 1. Isolated USB to FTDI Isolated RS-232/Isolated RS-485 Circuit (Simplified Schematic, All Connections Not Shown)
CIRCUIT DESCRIPTION and scientific instruments. Applications for RS-485 include

The circuit in Figure 1 provides highly integrated and robust process control networks; industrial automation; remote
isolation of fully TIA/EIA-485/232 compliant transceivers. The terminals; building automation, such as heating, ventilation,
ADM3252E 2.5 kV rms isolated RS-232 and the ADM2587E air conditioning (HVAC) and security systems; motor control;
2.5 kV rms isolated RS-485 solutions are the smallest available and motion control.
in the industry. The ADuM3160 provides market-leading USB In these real-world systems, lightning strikes and power source
port 2.5 kV rms isolation, and is easily integrated with low and fluctuations can cause damage to communications ports by
full speed USB-compatible peripheral devices. The FTDI generating large transient voltages. Isolation in the Figure 1
FT2232H (USB to UART converter) facilitates transmission via circuit increases system safety by providing protection against
UART to RS-485 or RS-232 bus ports. TIA/EIA RS-232 devices these electrical line surges.
are widely used in industrial machines, networking equipment,
EVAL-CN0373-EB1Z
12925-002
Figure 2. EVAL-CN0373-EB1Z Board
Figure 2 shows a photo of the isolated USB to FTDI isolated configuration, where data can be transmitted via the Y and Z pins,
RS-232/isolated RS-485 circuit. It is possible to transmit from and received via the A and B pins. Connecting the LK5 and LK6
the USB port to both RS-485 and RS-232 ports simultaneously, jumpers places the ADM2587E inputs/outputs in a half duplex
if required, or to just one port. configuration, which is where bus data can only be transmitted
The ADuM3160 provides 2.5 kV rms digital isolation of the or received, but not simultaneously.
data signals on the D+ and D− USB bus input to the FTDI The ADM3252E is a high speed, 2.5 kV, fully isolated, dual channel
FT2232H (USB to UART converter). The isolated USB output RS-232/V.28 transceiver device that is operational from a single
DD− and DD+ signals are connected to the DM and DP pins of 3.3 V or 5 V power supply. The RS-232 interface supports full-
the FTDI, respectively. The FTDI FT2232H can transmit data duplex communication and provides CTS and RTS for hardware
via UART to RS-232/RS-485 depending on which PC virtual handshaking via the J5 five-way connector or the J3 connector.
COM port (VCP) is chosen. The ADuM3160 VBUS1 power is J3 provides an RS-232 cable connector for connecting to
supplied via the USB cable connection. The ADuM3070 industrial equipment.
provides a regulated isolated power source. Power (+6 V) and The ADM3252E transmitter inputs (TINx) accept TTL/CMOS
ground for the ADuM3070 are connected via the J1 barrel input levels from the ADBUS0 and ADBUS2 output pins of
socket connector. The ADuM3160 VBUS2 pin is supplied with the FTDI. The TINx inputs are inverted and coupled across the
3.3 V isolated power by the ADuM3070. The ADuM3070 3.3 V isolation barrier, where they are transmitted as EIA/TIA-232E
output also supplies the primary power for the ADM3252E bus signals via the J3 or J5 connector. The ADM3252E receiver
2.5 kV rms isolated RS-232 and the ADM2587E 2.5 kV rms inputs (RINx) accept EIA/TIA-232E signal levels from the J3 or
isolated RS-485 transceiver. J5 connector. The RINx inputs are inverted and coupled across
The ADM2587E 2.5 kV rms isolated RS-485 transceiver is the the isolation barrier to appear at the ROUTx pins. The ROUTx pins
industry-leading signal and power isolated solution. This are connected to the ADBUS1 and ADBUS3 inputs to the FTDI.
transceiver is capable of operating at 3.3 V or 5 V. Data transmits Two separate ADP190 circuits are used as soft start circuitry
on the TxD pin, and it is received on the RxD pin. Both the to power the ADM2587E and ADM3252E after the FTDI
driver and receiver outputs can be enabled or disabled, that is, FT2232H has fully powered up. Jumper LK7 links the FTDI
put into a high impedance state, by changing the logic levels FT2232H PWREN# pin to the EN pin of the ADP190 circuits
on the DE and RE pins, respectively. via the 74AHC1G14W5-7 inverter. The ADP190 EN pin must
The FTDI output pin BDBUS0 is connected to the TxD data be high to turn on the power switch; drive EN low to turn off
input pin of the ADM2587E. The FTDI output pins BCBUS0, the power switch. Connecting LK7 in Position A (Position B
PWREN#, and BDBUS1 are connected to the DE, RE, and RxD disconnected) means that the ADP190 EN pin is always high/
input pins of the ADM2587E, respectively. The DE and RE pin enabled. Connecting LK7 in Position B (Position A disconnected)
state can also be configured via the LK1 and LK2 jumpers. For means that the ADP190 EN pin is triggered via the inverted
each link, Position A connects the logic pin to 3.3 V, Position B PWREN# signal.
connects the logic pin to GND, and Position C connects the The FTDI FT2232H data sheet provides a comprehensive listing
logic pin to the FTDI output pins. of the pin functions for RS-232 communications. The LK3 and
The ADM2587E can transmit and receive bus data via the A, B, LK4 jumpers allow handshaking options for RS-232. When LK3
Y, and Z RS-485 inputs/outputs. An RS-485 bus cable can be is connected, ADBUS4 (DTR#) is connected to ADBUS5 (DSR#).
connected via the J2 five-way connector. Disconnecting the When LK4 is connected, ADBUS4 (DTR#) is connected to
LK5 and LK6 jumpers places the ADM2587E in a full duplex ADBUS6 (DCD#).
Apply 6 V to the J1 barrel socket connector to power the EVAL-
CN0373-EB1Z board. The voltage can be checked on the
VCC_REG test point at the output of the ADP7102 regulator.
The ADP7102 output voltage should measure 5 V. The 5 V is
routed to the ADuM3070 and T2 transformer, which supply the
3.3 V outputs to power the RS-485, RS-232, and FTDI circuits.
Check that the ISO_VCC test point measures 3.3 V.
A complete transmit and receive path can be tested by connecting
the RS-232 and RS-485 outputs to an Analog Devices ezLINX™
iCoupler® Isolated Interface Development Environment board.
Alternatively, a USB to RS-232/RS-485 transmit test can be
performed by using the Tera Term open source terminal emulator
program. It is possible to transmit from the USB port to both
RS-485/RS-232 ports simultaneously, if required, or to just
one port.
12925-004
Connect a USB cable from the laptop/PC to the J4 connector.
Attach an oscilloscope probe to the ISOTxD test point next to
Figure 4. Tera Term COM5 for USB Transmission to the RS-232 Port on the
the ADM3252E transceiver, as shown in Figure 3. Open the PC EVAL-CN0373-EB1Z Board
application software and select COM5, then click OK, as shown
in Figure 4.
Load the RS-232 data to be transmitted by clicking Send under
the File menu. Choose any large data size file for continuous
test transmission and click Send, as shown in Figure 5.
12925-005
OSCILLOSCOPE Figure 5. Tera Term COM5 Data for USB Transmission to the RS-232 Port on
the EVAL-CN0373-EB1Z Board
6.0V Observe the isolated RS-232 signal on an oscilloscope by

POWER J1
SUPPLY ADM2587E
probing the ISOTxD test point on the EVAL-CN0373-EB1Z
Y board (see Figure 6).
PC/LAPTOP
TERA TERM FT2232H Z

J2
COM5 RS-232 RS-485
TERA TERM
ISOTxD
COM6 RS-485
ADM3252E
J5
RS-232 J3
J4 USB RS-232
12925-003
Figure 3. Test Setup for the EVAL-CN0373-EB1Z Board

12925-006
Figure 6. ISOTxD Signal for the RS-232 Port on the EVAL-CN0373-EB1Z Board
A similar test can be performed for the ADM2587E transceiver.
Connect a USB cable from the laptop/PC to the J4 connector.
Attach an oscilloscope probe to the Y and Z test points next to
the ADM2587E transceiver as shown in Figure 3. Open a
second Tera Term emulator window, and select COM6 for
RS-485 transmission, as shown in Figure 7.
12925-008
Figure 8. Tera Term COM6 Data for USB Transmission to the RS-485 Port on
the EVAL-CN0373-EB1Z Board
Observe the isolated RS-485 signals on an oscilloscope by

probing the Y and Z test points, or the differential bus signal
by using the oscilloscope Y − Z Math function, as shown in
Figure 9.
12925-007
Figure 7. Tera Term COM6 for USB Transmission to the RS-485 Port on the
EVAL-CN0373-EB1Z Board
Load the RS-485 data to be transmitted by clicking Send under

the File menu. Choose any large data size file for continuous
test transmission and click Send, as shown in Figure 8.
12925-009
Figure 9. Math Y – Z Waveform for the RS-485 Port on the
EVAL-CN0373-EB1Z Board
CN-0373 Design Support Package: ADM2587E Data Sheet
www.analog.com/CN0373-DesignSupport ADM3252E Data Sheet
ezLINX™ iCoupler® Isolated Interface Development ADuM3160 Data Sheet
Environment, ezLINX Board Quick Start Guide.
ADuM3070 Data Sheet
Marais, Hein. AN-960 Application Note. RS-485/RS-422
ADP190 Data Sheet
Circuit Implementation Guide. Analog Devices, Inc.
ADP7102 Data Sheet
Clark, Sean and Ronn Kliger. AN-740 Application Note.
iCoupler® Isolation in RS-232 Applications. ezLINX™ iCoupler® Isolated Interface Development
Analog Devices, Inc. Environment (EZLINX-IIIDE-EBZ)
UG-400 User Guide. ezLINX™ iCoupler® Isolated Interface REVISION HISTORY
Development Environment. Analog Devices, Inc.

CN12925-0-4/15(0)
Circuit Note
CN-0376
8-Channel, Low Noise, Low Power, 24-Bit,
AD7124-4
Circuits from the Lab® reference designs are engineered and Sigma-Delta ADC with PGA and Reference
tested for quick and easy system integration to help solve today’s ADuM5010 2.5 kV rms, Isolated DC-to-DC Converter
information and/or support, visit www.analog.com/CN0376. ADuM1441 Micropower Quad-Channel Digital Isolator
36 V, 1 A, Synchronous, Step-Down
ADP2441
DC-to-DC Regulator
Channel-to-Channel Isolated Temperature Input (Thermocouple/RTD) for

PLC/DCS Applications
Circuit Evaluation Boards The circuit shown in Figure 1 provides a dual-channel, channel-
CN-0376 Circuit Evaluation Board (EVAL-CN0376-SDPZ) to-channel isolated, thermocouple or RTD input suitable for
System Demonstration Platform (EVAL-SDP-CB1Z) programmable logic controllers (PLC) and distributed control
Design and Integration Files systems (DCS). The highly integrated design utilizes a low
Schematics, Layout Files, Bill of Materials power, 24-bit, Σ-Δ analog-to-digital converter (ADC) with a
rich analog and digital feature set that requires no additional
signal conditioning ICs.
Each channel can accept either a thermocouple or a RTD input.
The entire circuit is powered from a standard 24 V bus supply.
Each channel measures only 27 mm × 50 mm.
DIGITAL
P2 INTERFACE
SDP
PMOD
DUPLICATE CHANNEL OTHER
FIELD SUPPLY
VREF +24V GND
ADuM5010
REFOUT AVDD AVDD FERRITE ADP2441
VDD 3.3V
VISO VDDP DC-TO-DC
AIN0 (IOUT) 1µF CONVERTER
3kΩ IEXC IEXC 16.9kΩ
10µF 10µF
P1 RREF 1nF 10nF REFIN1(+) VSEL GNDP
1 10kΩ
IEXC 3.92kΩ 3kΩ 1nF
3kΩ IOVDD GNDISO
(4-WIRE) REFIN1(–) FERRITE
(3-WIRE) AD7124-4
THERMOCOUPLE 3kΩ
AIN+ 1nF 10nF AIN1 ADuM1441
ADC
RTD 3kΩ 1nF VDD2 VDD1
AIN– AIN3 0.1µF
VREF GND2 GND1 0.1µF
3kΩ
EN2 EN1
AIN4 (IOUT/VBIAS) DIGITAL
3kΩ VREF INTERFACE
CS VOA VIA
RETURN
DIN VOB VIB
AIN5 SDP
NTC SCLK VOC VIC PMOD
10kΩ DOUT VID VOD OTHER
AIN6
5.62kΩ 1 AVSS DGND
13011-001
10.1% TOLERANCE
Figure 1. PLC/DCS Channel-to-Channel Isolated Temperature Input (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0
CIRCUIT DESCRIPTION Terminal Connections
The AD7124-4 24-bit, Σ-Δ ADC with programmable gain array Figure 2 shows the terminal connections for each of the two
(PGA) and voltage reference provides the complete set of input channels. These terminals correspond to P1 and P2 in the
features to implement a flexible input capable of connection to hardware (see Figure 1). The thermocouple as well as 2-, 3-, or
either thermocouple or RTD sensors. Features include on-chip 4-wire RTD connections are shown.
reference, PGA, excitation currents, bias voltage generator, and IEXC
flexible filtering with enhanced 50 Hz and 60 Hz rejection (4-WIRE)

(2-WIRE/3-WIRE)
options. The AD7124-4 is in a small 5 mm × 5 mm LFCSP THERMOCOUPLE
AIN+
package, making it ideal in channel-to-channel isolated designs RTD
where space is a premium. It also includes multiple diagnostic AIN–
functions that are available to the user. (2-WIRE)
13011-002
(3-WIRE/4-WIRE)
The ADuM5010 isolated dc-to-dc converter provides 3.3 V RETURN
isolated power via integrated isoPower® technology. The Figure 2. Terminal Connections (Per Channel)
ADuM1441 isolates the serial peripheral interface (SPI) for the
AD7124-4. The ADuM1441 micropower isolator consumes Input Filtering
only 4.8 µA per channel when idle, resulting in an energy As shown in Figure 3, the input common-mode noise filtering is
efficient solution. provided by R1, C1 and R2, C2, and has a 50 kHz cutoff frequency,
approximately. Differential noise filtering is provided by R1, R2,
The ADP2441 36 V, step-down, dc-to-dc regulator accepts an
and C3 and has a 2.5 kHz cutoff frequency, approximately. It is
industrial standard 24 V supply, with wide tolerance on the
particularly important to filter out any interference at the Σ-Δ
input voltage. The ADP2441 steps the input voltage down to
modulator frequency (307 kHz in full-power mode). It is suggested
3.3 V to power all of the controller-side circuitry.
to adjust the cutoff of these filters to meet system bandwidth
System Overview requirements, with the cutoff of the common-mode filters being
Channel-to-channel isolation is advantageous in automation approximately 10× the cutoff of the differential filter.
systems, because faults on a particular input channel have no
negative impact on other channels in the system. However, AIN0 (IOUT)
channel-to-channel isolated input modules present a significant 3kΩ
1nF 10nF REFIN1(+)
design challenge in terms of complexity, space constraints, and IEXC
RREF
3.92kΩ 1 3kΩ 1nF
system cost. (4-WIRE) 3kΩ REFIN1(–)
(2-WIRE/3-WIRE)
Both thermocouple or RTD inputs are commonly used in THERMOCOUPLE R1 3kΩ
AIN+ C3 AIN1
industrial automation systems; therefore, it is advantageous to RTD
C1 1nF
10nF
AD7124-4
C2 1nF
design a temperature input module that handles both. This AIN– R2 3kΩ 3kΩ AIN3
flexibility minimizes the design effort required for the two input (2-WIRE) AIN4 (IOUT/VBIAS)
module variants, and also offers flexibility to the module user. (3-WIRE/4-WIRE) 3kΩ
VREF
RETURN RRETURN
The AD7124-4 significantly reduces the design complexity, NTC AIN5
providing a system-on-chip capable of performing all the 10kΩ
AIN6
necessary measurement functions for both thermocouple and 5.62kΩ 1
RTD sensors. 13011-003
10.1% TOLERANCE
Each channel of the circuit in Figure 1 measures only 27 mm by Figure 3. Front-End Filtering and Circuitry (Simplified)
50 mm, and this area can be further reduced by using both sides
of the printed circuit board (PCB) for populating components. Input Protection
This small size is achieved because the AD7124-4 is in a small To protect the input from an overvoltage condition, 3 kΩ resistors
5 mm × 5 mm LFCSP package and integrates almost all the were placed on every input path to the AD7124-4. This resistor
required functions except the isolation and additional front-end value limits the current from a 30 V dc overvoltage to less than
filtering and protection. The isolation circuit consumes only 10 mA.
87 mm2 for both the data and power isolation together, with a Consider the condition for 30 V connected between AIN+ and
minimum combined width of 12.5 mm. AIN−. Looking in from AIN+, the 30 V sees R1 (3 kΩ), followed
by internal ESD protection diodes, followed by 3 kΩ looking
out from AIN3 in parallel with 3 kΩ looking out from AIN4.
Ignoring the internal ESD protection diodes, the total resistance
seen between AIN+ and AIN− is 3 kΩ + 3 kΩ||3 kΩ = 4.5 kΩ.
The current through the AD7124-4 is therefore limited to
30 V ÷ 4.5 kΩ = 6.7 mA.
RTD Input To achieve the desired accuracy, the RTD itself must be
The circuit in Figure 1 can be connected to 2-, 3-, or 4-wire linearized in the software by the host controller, as described in
RTDs. A resistance of up to 3.92 kΩ can be measured, making it the Circuit Note CN-0383.
suitable for Pt100 and Pt1000 RTDs. Current excitation is used, Thermocouple Measurement
and the resistance measurement is a ratiometric measurement As shown in Figure 3, a thermocouple is connected between the
between the RTD and a precision 3.92 kΩ reference resistor AIN+ and AIN− terminals. The AIN4 pin provides a bias voltage
(RREF). As shown in Figure 3, the RTD measurement is made for the thermocouple of 3.3 V ÷ 2 = 1.65 V. The thermocouple
between AIN1 and AIN3, using REFIN1+ and REFIN1− as the voltage is measured between AIN1 and AIN3, and because the
reference input for the measurement. The excitation currents thermocouple signals are very small, a PGA gain of 32 or 64 is
are set as follows: typically recommended.
• 2-wire mode: only the excitation on AIN0 is active, set at A 10 kΩ NTC thermistor is used for cold junction
250 µA. compensation. A reference voltage excitation, VREF, is taken
• 3-wire mode: both the excitation currents on AIN0 and from REFOUT, and a precision, low-drift 5.62 kΩ resistor is
AIN4 are active, each set at 100 µA. placed in series to ground. The NTC resistance value can be
• 4-wire mode: only the excitation on AIN0 is active, set at calculated by
250 µA.
VNTC
R NTC = × 5.62 kΩ
A high-side current sense technique is used. For low values of VREF − VNTC
lead resistance to the RTD, this technique reduces the effect of
where:
any current mismatch in 3-wire mode. See the Circuit Note
VNTC is the voltage measured between AIN1 and AIN3.
CN-0383 for more details on the 3-wire RTD configuration.
VREF is the reference voltage from the AD7124-4 REFOUT.
The reference resistor (RREF) was chosen to be 3.92 kΩ, which
Any temperature difference between the terminal block and
allows measurement of a Pt1000 RTD up to 850°C (the RTD
the NTC temperature sensor directly impacts the resulting
resistance is 3.9048 kΩ at 850°C). The value of RREF must be
temperature reading for the thermocouple input. For this
selected based on the highest expected resistance for the RTD.
reason, the NTC thermistor must be placed as close to the
The accuracy of the RREF resistor has a direct impact on the
terminal block as possible to maximize the thermal coupling.
measurement accuracy; therefore, a precision, low drift resistor
must be used. To achieve the desired accuracy, the thermocouple and NTC
must be linearized in the software by the host controller, as
The excitation current must be set to 250 µA in 4-wire mode
described in the Circuit Note CN-0384.
and 100 µA in 3-wire mode. For 4-wire mode, assume an RTD
value of 3.92 kΩ. The excitation current coming from AIN0 Diagnostics
passes through; RREF + RRTD + RRETURN = 3.92 kΩ + 3.92 kΩ + The AD7124-4 provides a number of system level diagnostics,
3 kΩ = 10.84 kΩ. Therefore, the voltage at AIN0 is equal to including
250 µA × 10.84 kΩ = 2.71 V. The AD7124-4 specifies an output
• Reference detection
compliance of AVDD − 0.35 V on the excitation current outputs,
which corresponds to 3.3 V – 0.35 V = 2.95 V. Because 2.95 V > • Overvoltage/undervoltage detection on the input
2.71 V, the 250 µA excitation current functions correctly even • CRC on SPI communications
for the maximum RTD resistance. • CRC on the memory map
• SPI read/write checks
See the Circuit Note CN-0381 for more details on the 4-wire
RTD configuration. These diagnostics allow a high level of fault coverage for the
In 3-wire mode, the lead compensation excitation current from input channels.
AIN4 also flows through the 3 kΩ return resistor, producing an Isolation
additional voltage at AIN0 of 250 µA × 3 kΩ = 0.75 V, thereby The data channels are isolated using the ADuM1441, a quad-
making the total voltage at AIN0 equal to 2.71 V + 0.75 V = channel, micropower isolator, resulting in an energy efficient
3.46 V, which violates the headroom requirement. Therefore, in solution. The ADuM1441 is in a small 5 mm × 6.2 mm, 16-lead
3-wire mode, the excitation currents must each be reduced to QSOP package (30 mm2).
100 µA to allow sufficient headroom.
The ADuM5010, a complete isolated switching converter
The PGA gain can be used to increase the measurement utilizing isoPower technology, provides power isolation for the
resolution. For a Pt100 RTD, a gain of 8 is recommended circuit. The ADuM5010 is in a small 7.4 mm × 7.5 mm, 20-lead
(because Pt100 values are 10× smaller than Pt1000 values). SSOP package (56.25 mm2).
Figure 4 shows details of the ADuM5010 circuitry. Ferrite beads 2 Mbps. If the interface is active 1/8th of the time, the power
are used on the secondary side of the supply to suppress any consumption for the ADuM1441 is (552 μA × 0.125) + (7.2 μA ×
potential electromagnetic interference (EMI) emissions. The 0.875) = 75.3 μA total.
ferrite beads (Murata BLM18HK102SN1) are specifically chosen The measured power consumption for an input channel operating
for their high impedance from 100 MHz to 1 GHz. Decoupling in full power mode, gain = 32, internal reference, and TC bias
capacitors of 10 μF and 0.1 μF are also used. Both the ferrite beads enabled was 7.9 mA from the controller-side 3.3 V supply.
and the capacitors use short traces to the ADuM5010 pins to
minimize parasitic inductance and resistance. Power Supply Circuit
ADuM5010 The evaluation board is powered by a 4.5 V to 36 V dc power
ISOLATED
3.3V FERRITE 3.3V supply and uses an on-board switching regulator to provide the
VISO VDDP
10µF R2 3.3 V supply to the system, as shown in Figure 5. The EVAL-
0.1µF 16.9kΩ 0.1µF 10µF
VSEL GNDP SDP-CB1Z System Demonstration Platform (SDP) board
R1
13011-004
10kΩ
GNDISO
provides a regulated 3.3 V for the digital interface.
FERRITE
The ADP2441 includes programmable soft start, regulated
Figure 4. isoPower Circuit with Ferrite Beads and Decoupling Capacitors
output voltage, switching frequency, and power good. These
The stitching capacitance is kept to a minimum size because the features are programmed externally via tiny resistors and
ferrite beads significantly reduce the emissions. The PCB area capacitors. The ADP2441 also includes protection features, such
between the ADuM5010 supply, the GND pins, and the ferrite as undervoltage lockout (UVLO) with hysteresis, output short-
beads is kept clear of any ground planes or traces to minimize circuit protection, and thermal shutdown.
the capacitive coupling of any high frequency noise into the
A 300 kHz switching frequency maximizes the efficiency of the
ground plane. See the AN-0971 Application Note for additional
ADP2441. Due to the high switching frequency of the ADP2441,
information on controlling radiated emissions from isoPower
using shielded ferrite core inductors is recommended because
devices.
of their low core losses and low EMI.
The R1 and R2 feedback resistors are chosen to select a 3.3 V
In the Figure 5 circuit, the switching frequency is set to
output as per the ADuM5010 data sheet.
approximately 300 kHz using a 294 kΩ external resistor. The
Power Consumption per Channel inductor value of 22 μH (Coilcraft LPS6235-223MLC) was
The ADuM5010 typically consumes 3.3 mA from the controller- chosen using the downloadable ADP2441 Buck Regulator
side supply. The efficiency of the ADuM5010 is only 27% at full Design Tool. This tool selects the best component values based
load; therefore, minimizing the current drawn from field side on the required operating conditions (4.5 V to 36 V input, 3.3 V
significantly impacts the energy efficiency of the channel. output, 1 A output current).A current of 1 A was selected to
power additional circuits on the host controller side if required.
The AD7124-4 consumes ~994 μA (full power mode, gain = 32,
TC bias, diagnostics and internal reference enabled). The A complete set of documentation for the EVAL-CN0376-SDPZ
AD7124-4 power can be significantly reduced by using the circuit evaluation board including schematic, assembly, layout,
mid power or low power modes. Gerbers, and bill of materials is available at
www.analog.com/CN0376-DesignSupport.
For the ADuM1441, the field side consumes a total of
approximately 7.2 μA when idle and 552 μA when operating at
10nF 0.1µF
COILCRAFT
LPS6235-223MLC FERRITE
+3.3V 22µH BST VCC AGND 330Ω 4.5V
SW VIN TO
DIODE 36V
FUSE
10µF 40V 0.2A
61.9kΩ ADP2441
2.2µF TVS FIELD
SMBJ36CA SUPPLY
0.6V FB 36V
FERRITE
COMP 330Ω
13.7kΩ PGND GND
1nF
SS/TRK FREQ
32.4kΩ 10nF 294kΩ

13011-005
Figure 5. Power Supply Circuit (Simplified Schematic: All Connections Not Shown)
Testing Results COMMON VARIATIONS
For detailed performance analysis of the thermocouple, 3-wire If more channels are needed, the AD7124-8 can be used. The
and 4-wire RTD circuits, see the Circuit Note CN-0381, Circuit AD7124-8 has 8 differential or 16 single-ended inputs. The
Note CN-0383, and Circuit Note CN-0384 for in depth analysis AD7792 can also be considered as a lower cost option, but with
and measurement results. reduced features and performance.
Figure 6 shows a histogram for the EVAL-CN0376-SDPZ using Alternate options for the data isolation are to use a SPIsolator™
the 25 SPS post filter, with AIN+ shorted to AIN−, gain = 32, and such as the ADuM3151, which supports up to 17 MHz SPI
TC bias enabled. The data corresponds to 17.85-bit noise-free transmission as well as containing three general-purpose, low
code resolution. speed, isolated channels.
45
An NTC thermistor is used for cold junction compensation in
40 the circuit shown in Figure 1. Another option is to use the
35 ADT7320 digital temperature sensor, which is 0.25°C accurate.
(see the Circuit Note CN-0172).
30
OCCURRENCES
25
20
15
10
5
13011-006
0
8389570
8389580
8389590
8389600
8389610
8389620
8389630
8389640
8389665
CODES
Figure 6. Histogram of Codes for the AIN+ and AIN- Shorted Inputs
(25 SPS, Post Filter Selected, Gain = 32, TC Bias Enabled)
The circuit shown in Figure 1 uses the EVAL-CN0376-SDPZ The EVAL-CN0376-SDPZ evaluation board connects to the
evaluation board and the EVAL-SDP-CB1Z SDP controller board. EVAL-SDP-CB1Z SDP board through a 120-pin mating
connector found on both boards. The CN-0376 Evaluation
The EVAL-CN0376-SDPZ evaluation board features PMOD-
Software and the SDP board allow the data to be analyzed
compatible headers for integration with external controller boards.
using a PC.
The CN-0376 Evaluation Software communicates with the SDP
Apply a voltage in the range of 4.5 V to 36 V (24 V nominal)
board to configure and capture data from the EVAL-CN0376-
to the P3 connector. Ensure that the P8 jumper is set to EXT
SDPZ evaluation board.
(default), which powers the board via the P3 supply input.
Equipment Needed
External controllers can also be used to communicate with and
The following equipment is needed: power the evaluation board using the PMOD headers for SPI
 PC with a USB port and Windows® Vista (32-bit) or communication. If desired, set the P8 jumper to VCC_PMOD
Windows 7 (32-bit) to power the board from 3.3 V via the PMOD connector.
 EVAL-CN0376-SDPZ circuit evaluation board Precision voltage and resistance sources can be used as input to
 EVAL-SDP-CB1Z SDP controller board the analog front end to evaluate system performance. Similarly,
 CN-0376 Evaluation Software thermocouple or RTD simulators can be used.
 Precision voltage and resistance source, or alternately a Figure 8 shows a photo of the EVAL-CN0376-SDPZ circuit
thermocouple or RTD simulator. evaluation board.
 Power supply: 4.5 V to 36 V dc at 100 mA
Getting Started
Install the CN-0376 Evaluation Software, which is available
for download at ftp://ftp.analog.com/pub/cftl/CN0376/. Follow
the on-screen prompts to install and use the software. More
information is available in the CN-0376 Software User Guide.
Test Setup Functional Block Diagram
Figure 7 shows a functional block diagram of the test setup.
13011-008
4.5V TO
36V SUPPLY PC
AT 100mA
Figure 8. Photo of EVAL-CN0376-SDPZ Circuit Evaluation Board
USB
PT100, PT1000 P1 P3
THERMOCOUPLE
120 CON A
SDP OR
CON B
PRECISION
VOLTAGE OR P2
EVAL-SDP-CB1Z
13011-007
RESISTANCE
EVAL-CN0376-SDPZ
LEARN MORE Circuit Note CN-0206. Thermocouple Temperature Measurement
CN-0376 Design Support Package: System with Less Than 500 µA Current Drain. Analog Devices.
www.analog.com/CN0376-DesignSupport Circuit Note CN-0209. Fully Programmable Universal Analog
SDP-B User Guide Front End for Process Control Applications. Analog Devices.
CN-0376 Software User Guide Circuit Note CN-0325. PLC/DCS Universal Analog Input Using
Either 4 or 6 Pin Terminal Block. Analog Devices.
Duff, Matthew and Joseph Towey. Two Ways to Measure
Temperature Using Thermocouples Feature Simplicity, Accuracy, Circuit Note CN-0381. Completely Integrated 4-Wire RTD
and Flexibility. Analog Dialogue 44-10, Analog Devices. Measurement System Using a Low Power, Precision, 24-Bit,
Sigma-Delta ADC. Analog Devices.
Cantrell, Mark. Application Note AN-0971. Recommendations
for Control of Radiated Emissions with isoPower Devices. Circuit Note CN-0382. Isolated 4 mA to 20 mA/HART Temperature
Analog Devices. and Pressure Industrial Transmitter using a Low Power, Precision,
24-Bit, Sigma-Delta ADC. Analog Devices.
Kester, Walt. “Temperature Sensors,” Chapter 7 in Sensor Signal
Conditioning. Analog Devices, 1999. Circuit Note CN-0383. Completely Integrated 3-Wire RTD
Measurement System Using a Low Power, Precision, 24-Bit,
McCarthy, Mary. AN-615 Application Note. Peak-to-Peak Sigma-Delta ADC. Analog Devices.
Resolution Versus Effective Resolution. Analog Devices.
Circuit Note CN-0384. Completely Integrated Thermocouple
McNamara, Donal. AN-892 Application Note. Temperature Measurement System Using a Low Power, Precision, 24-Bit,
Measurement Theory and Practical Techniques. Analog Devices. Sigma-Delta ADC. Analog Devices.
Looney, Mike. AN-0970 Application Note. RTD Interfacing Data Sheets and Evaluation Boards
and Linearization Using an ADuC706x Microcontroller.
CN-0376 Circuit Evaluation Board (EVAL-CN0376-SDPZ)
Analog Devices.
System Demonstration Platform (EVAL-SDP-CB1Z)
Cantrell, Mark. MS-2644 Technical Article. Ultralow Power
Opening Applications to High Speed Isolation. Analog Devices. AD7124-4 Data Sheet
MT-031 Tutorial. Grounding Data Converters and Solving the ADuM1441 Data Sheet
Mystery of “AGND” and “DGND”. Analog Devices. ADuM5010 Data Sheet
MT-101 Tutorial. Decoupling Techniques. Analog Devices. ADP2441 Data Sheet
Circuit Note CN-0172. 3-Channel Thermocouple Temperature
REVISION HISTORY
Measurement System with 0.25 °C Accuracy. Analog Devices.

CN13011-0-7/15(0)
Circuit Note
CN-0381
Circuits from the Lab® reference designs are engineered and 4-Channel/8-Channel, Low Noise, Low
AD7124-4/
tested for quick and easy system integration to help solve today’s Power, 24-Bit, Sigma-Delta ADCs with PGA
AD7124-8
analog, mixed-signal, and RF design challenges. For more and Reference
information and/or support, visit www.analog.com/CN0381. 50 mA, High Voltage, Micropower Linear
ADP1720
Regulator
Completely Integrated 4-Wire RTD Measurement System Using a Low Power,

Precision, 24-Bit, Sigma-Delta ADC
EVALUATION AND DESIGN SUPPORT The AD7124-4/AD7124-8 establishes the highest degree of
Circuit Evaluation Boards signal chain integration, which include programmable low
AD7124-4 Evaluation Board (EVAL-AD7124-4SDZ) or drift excitation current sources. Therefore, the design of an
AD7124-8 Evaluation Board (EVAL-AD7124-8SDZ) RTD system is greatly simplified because most of the required
System Demonstration Platform (EVAL-SDP-CB1Z) RTD measurement system building blocks are included on-chip.
Design and Integration Files The AD7124-4/AD7124-8 gives the user the flexibility to
Schematics, Layout Files, Bill of Materials employ one of three integrated power modes, where the current
consumption, range of output data rates, and rms noise are
tailored with the power mode selected. The current consumed
The circuit shown in Figure 1 is an integrated 4-wire, resistance by the AD7124-4/AD7124-8 is only 255 μA in low power mode
temperature detector (RTD) system based on the AD7124-4/ and 930 μA in full power mode. The power options make the
AD7124-8 low power, low noise, 24-bit Σ-Δ ADC optimized for device suitable for non-power critical applications, such as
high precision measurement applications. With a two-point input/output modules, and also for low power applications such
calibration and linearization, the overall 4-wire system accuracy as loop powered smart transmitters where the complete
is better than ±1°C over a temperature range of −50°C to +200°C. transmitter must consume less than 4 mA.
Typical noise free code resolution of the system is 17.9 bits for
The device also has a power-down option. In power-down mode,
full power mode, sinc4 filter selected, at an output data rate of
the complete ADC along with its auxiliary functions are powered
50 SPS, and 17.3 bits for low power mode, post filter selected,
down so that the device consumes 1 μA typical. The AD7124-4/
and at an output data rate of 25 SPS.
AD7124-8 also has extensive diagnostic functionality integrated
The AD7124-4 can be configured for 4 differential or 7 pseudo as part of its comprehensive feature set.
differential input channels, while the AD7124-8 can be configured
for 8 differential or 15 pseudo differential input channels. The
on-chip programmable gain array (PGA) ensures that signals of
small amplitude can be interfaced directly to the ADC.
Rev. 0
of each circuit, and their function and performance have been tested and verified in a lab environment
GND ADP1720 GND GND GND

3.3V OUTPUT ADP1720
7V TO 9V IN GND 3.3V OUTPUT
IN GND
VIN
10µF 0.1µF
OUT GND OUT GND
4.7µF 4.7µF 4.7µF
EN GND EN GND
ADP1720ARMZ-R7
27kΩ 1.8V OUTPUT
ADJ GND
57.6kΩ
IN GND
4.7µF
OUT GND
4.7µF
EN GND
0.1µF 1µF
0.1µF
AVDD IOVDD
Pt100
REGCAPD
RL1
AIN0 0.1µF
REGCAPA
USB
RL2 1kΩ 0.1µF
AIN2 AD7124-4/
AD7124-8
0.01µF
0.1µF
RL3 1kΩ DOUT/RDY
AIN3
0.01µF DIN
RL4
SCLK AD7124
ADSP-BF527
LED
CS
1kΩ
REFIN1(+) SYNC POWER
5.11kΩ 0.01µF LED
REFERENCE 0.1% 0.1µF
RESISTOR ±15ppm/°C CLK
SDP-B STATUS
REFIN1(–)
1kΩ 0.01µF
REFERENCE
BUFFER 250Ω AVSS DGND
HEADROOM
13441-001
Figure 1. 4-Wire RTD Measurement Configuration
CIRCUIT DESCRIPTION For the circuit in Figure 1, a Pt100 RTD Class B sensor was used.
RTD Temperature Measurement Introduction Pt100 RTDs measure temperature from −200°C to +600°C. The
resistance of a Class B RTD is typically 100 Ω at 0°C and has a
RTDs are frequently used sensors for temperature measurements
typical temperature coefficient of ~0.385 Ω/°C (see Figure 2).
in industrial applications. An RTD is made from a pure metal
Using this information, the voltage generated across the Pt100
(examples include platinum, nickel, or copper), which has a
RTD can easily be calculated based on the current source selected.
predictable change in resistance as the temperature changes.
350
The most widely used RTDs are platinum Pt100 and Pt1000.
RTDs are capable of high accuracy and good stability when 300
compared with other types of temperature sensors. The error
250
due to the resistance of long wire lengths can be eliminated
RESISTANCE (Ω)
using the 4-wire connection. 200
To accurately measure the resistance, a voltage is generated

150
across the RTD by a constant current source. The AD7124-4/
AD7124-8 offers two such excitation current sources that are 100
register programmable from 50 μA to 1 mA. Errors in the current
source can be easily cancelled by referring the measurement to 50
13441-002
the voltage across a precision reference resistor that is driven with

the same current source, resulting in a ratiometric measurement. 0
–200 0 200 400 600
TEMPERATURE (°C)
Figure 2. Pt100 RTD Resistance vs. Temperature
How the Circuit Works The AD7124-4/AD7124-8 has diagnostic functions on-chip that
The AD7124-4/AD7124-8 provides an integrated solution for RTD can be used to detect faults in the SPI communication. These
measurements; it can achieve high resolution, low non-linearity, diagnostics include checks on the SPI read and write operations,
and low noise performance as well as very high 50 Hz and 60 Hz ensuring that only valid registers are accessed. An SCLK
rejection. The AD7124-4/AD7124-8 consists of an on-chip, low counter ensures that the correct number of SCLK pulses is used,
noise PGA that amplifies the small signal from the RTD with a while the CRC functionality checks for changes in bit values
gain programmable from 1 to 128, thus allowing direct interface during transmission. When any of these SPI communication
with the sensor. The gain stage has high input impedance and diagnostic functions are enabled and an associated error occurs,
limits the input leakage current to 3.3 nA typical for full power the corresponding flag is set in the error register. All enabled
mode and 1 nA typical for low power mode. The following flags are OR’ed together and control the ERR flag in the status
sections explain the different elements that make up the 4-wire register. This functionality is particularly useful if the status bits
RTD temperature measurement system. are appended to the ADC conversions.
Power Supplies Analog Inputs and Reference

The AD7124-4/AD7124-8 has separate analog and digital The AD7124-4 can be configured for 4 differential or 7 pseudo
power supplies. The digital power supply, IOVDD, is differential input channels, while the AD7124-8 can be
independent of the analog power supply and can be 1.65 V to configured for 8 differential or 15 pseudo differential input
3.6 V referenced to DGND. The analog power supply, AVDD, is channels.
referred to AVSS and has a range of 2.7 V to 3.6 V for low and The AD7124-4/AD7124-8 has on-chip diagnostics that can be
mid-power modes, and 2.9 V to 3.6 V for full power mode. The used to check that the voltage level on the analog pins are
circuit shown in Figure 1 operates on a single supply; therefore, within the specified operating range. The positive (AINP) and
AVSS and DGND are connected together, and only one ground negative (AINM) analog inputs can be separately checked for
plane is used. The AVDD and IOVDD voltages are generated overvoltages and undervoltages, as well as ADC saturation. An
separately using ADP1720 low dropout voltage regulators. The overvoltage is flagged when the voltage on the analog input
AVDD voltage is set to 3.3 V, and the IOVDD voltage is set to exceeds AVDD, while an undervoltage is flagged when the
1.8 V, using the ADP1720 regulators. Using separate regulators voltage on the analog input goes below AVSS.
ensures lowest noise.
For the circuit in Figure 1, three analog pins are used to
Serial Peripheral Interface (SPI) implement the 4-wire measurement: AIN0, AIN2, and AIN3.
SPI communications to the AD7124-4/AD7124-8 are handled AIN2 and AIN3 are configured as a fully differential input
by the Blackfin® ADSP-BF527 on the EVAL-SDP-CB1Z board, channel and are used for sensing the voltage across the RTD.
as shown in Figure 1. To access the registers of the AD7124-4/ The excitation current source used to excite the RTD is
AD7124-8, use the AD7124-4/AD7124-8 EVAL+ Software. generated from AVDD and is directed to AIN0. The analog pins
Figure 3 shows the main window of this software. Clicking the and their configuration are shown in greater detail in Figure 4.
4-WIRE RTD button configures the software for the 4-wire AD7124-4/
Pt100 AD7124-8
RTD measurement.
RL1
IOUT0 (AIN0)
RL2 1kΩ
AIN2
0.01µF
0.1µF
RL3 1kΩ
AIN3
0.01µF
RL4
1kΩ
REFIN1(+)
5.11kΩ 0.01µF
REFERENCE 0.1% 0.1µF
RESISTOR ±15ppm/°C
REFIN1(–)
1kΩ 0.01µF
REFERENCE
BUFFER 250Ω
13441-004
HEADROOM
13441-003
Figure 4. Analog Input Configuration for 4-Wire RTD Measurement

Figure 3. AD7124-4/AD7124-8 EVAL+ Software Configuration Window
Digital and Analog Filtering The value of the external precision resistor is chosen so that
For the circuit in Figure 1, the reference input used is REFIN1(±). the maximum voltage generated across the RTD equals the
The current through the RTD also flows through the precision reference voltage divided by the PGA gain.
reference resistor that generates the reference voltage. The voltage RREF = VRTD MAX/IEXC = 2.5096 V/500 μA = 5020 Ω
generated across this precision reference resistor is ratiometric Therefore, a 5.11 kΩ resistor is used, which gives a reference
to the voltage across the RTD; therefore, any variations seen in voltage of
the excitation current are removed. Because the buffers are
enabled, it is necessary to ensure that the headroom required 5.11 kΩ × Excitation Current = 5.11 kΩ × 500 μA = 2.555 V
for correct operation is met (AVDD − 0.1 V and AVSS + 0.1 V). The output compliance of the excitation current source must
The headroom of 0.125 V (500 μA × 250 Ω) is provided by the also be considered when making 4-wire RTD measurements
250 Ω resistor to ground, as shown in Figure 4. using the AD7124-4/AD7124-8. The output compliance is
dependent on the excitation current selected. For this circuit,
Differential (~800 Hz cutoff) and common-mode (~16 kHz
500 μA is selected, which has an output compliance voltage of
cutoff) filters are implemented at the analog inputs, as well as at
AVDD − 0.37 V. The AVDD supply voltage for this circuit is 3.3 V;
the reference inputs. This filtering is required to reject any
interference at the modulator frequency and also any multiples therefore, the output compliance level for the excitation current
of this frequency. source must be less than 2.93 V. From the previous calculations,
this specification is met, because the maximum voltage on the
The AD7124-4/AD7124-8 offers a great deal of on-chip digital AIN0 pin is the voltage across the precision reference resistor
filtering flexibility. Several filter options are available; the option plus the voltage across the RTD plus the voltage across the
selected has an effect on the output data rate, settling time, as headroom resistor.
well as 50 Hz and 60 Hz rejection. For this circuit note, the sinc4
VREF + VRTD + VHEADROOM = 2.555 V + 156.8 5 mV + 125 mV
filter and the post filter are implemented. The sinc4 filter is used
= 2.83685 V
because it has excellent noise performance across the range of
output data rates, as well as having excellent 50 Hz and 60 Hz The AD7124-4/AD7124-8 configuration for 4-wire RTD
rejection. The post filter provide simultaneous 50 Hz and 60 Hz measurements is as follows:
rejection, with a 40 ms settling time.  Differential input: AINP = AIN2, AINM = AIN3
Calibration  Excitation current: IOUT0 = AIN0 = 500 μA
The AD7124-4/AD7124-8 provides different calibration modes  Gain = 16
that can be used to eliminate offset and gain errors. For this  Precision reference resistor: 5.11 kΩ
circuit note, internal zero-scale calibration as well as internal  Digital filtering:
full-scale calibrations were used. o Sinc4 filter (full power mode)
o Post filter (low power mode)
4-Wire RTD Configuration
The circuit shown in Figure 1 is designed for precision 4-wire The general expression to calculate the RTD resistance, RRTD, when
RTD measurements using the AD7124-4/AD7124-8. For the the ADC is operating in bipolar differential mode is given by
4-wire RTD measurement, one excitation current source is (CODE  2 N  1 )  R REF
required. The AD7124-4/AD7124-8 provides two matched R RTD  (1)
G  2N  1
current sources; therefore, either one of these current sources
can be used to excite the RTD. The RTD produces a low-level where:
voltage signal, which can then be amplified by the on-board CODE is the ADC code output.
PGA of the AD7124-4/AD7124-8. The amplified voltage is then N is the resolution of the ADC (24, in this case).
converted to a precision digital representation using the 24-bit RREF is the reference resistor.
Σ-Δ ADC. G is the selected gain.
For this 4-wire RTD circuit, a Class B RTD is used. If the on-chip From the specification of the Class B RTD, the resistance changes
excitation current is programmed to 500 μA, at a maximum by approximately 0.385 Ω/°C. This relationship can be used as a
temperature of 600°C, the voltage generated across the RTD is quick method to obtain an approximate temperature of the RTD.
approximately 156.85 mV. To ensure that the maximum range of This method has inaccuracies due to the temperature coefficient
the AD7124-4/AD7124-8 is used, the PGA gain is programmed of the RTD changing slightly over the temperature range; however,
to a gain of 16. The PGA amplifies the maximum RTD sensor it can be a useful method to check the temperature quickly.
output voltage to 2.5096 V. To calculate the approximate temperature, use Equation 2.
RRTD  100
Temperature (C)  (2)
0.385
The RTD transfer function known as the Callender-Van Dusen 4-Wire RTD Measurements and Results
equation is made up of two distinct polynomial equations to For the circuit shown in Figure 1, data was gathered for
provide a more accurate result. Equation 3 is used for temperatures different digital filter and power mode configurations of the
greater than 0°C, and Equation 4 is for temperatures less than 0°C. AD7124-4/AD7124-8, with the sinc4 filter operating in full
The equation for temperature t ≤ 0°C is power mode, and the post filter operating in low power mode.
RRTD(t) = R0[1 + At + Bt2 + C(t − 100°C)t3] (3) Choosing the configuration for sinc4 filter, full power mode,
and 50 SPS allows the user to operate the AD7124-4/AD7124-8
The equation for temperature t ≥ 0°C is
for best performance relative to speed and noise. Figure 5 shows
RRTD(t) = R0(1 + At + Bt2) (4) the noise distribution when a 4-wire RTD is connected as shown
where: in Figure 1 at ambient temperature. The corresponding rms noise
t is the RTD temperature (°C). is typically 199.37 nV, which is approximately 17.9 noise free bits.
RRTD(t) is the RTD resistance (Ω). The noise performance of the AD7124-4/AD7124-8 for inputs
R0 is the RTD resistance at 0°C (in this case, R0 = 100 Ω). shorted using the same filter, gain, power mode, and output
A = 3.9083 × 10−3. data rate was 100 nV rms or 18.7 noise free bits. The increase in
B = −5.775 × 10−7. the noise comes directly from the RTD connection across the
C = −4.23225 × 10−12. input channel (AIN2, AIN3).
90
There are many different ways to determine the temperature as
a function of the RTD resistance given the transfer function in 80
1000 SAMPLES
Equation 3 and Equation 4. The direct mathematical method is 70
chosen, due to its accuracy. Taking Equation 3, the temperature
60
can be calculated as
OCCURANCES 50
 r 
A A  4 B  1 
2

 40
 R 0 
TRTD (C )  (5) 30
2B
20
where r is the RTD resistance, and the other variables are as
defined previously. 10
13441-005
This method works well for temperatures greater than or equal 0
11256419
11256427
11256435
11256443
11256451
11256459
11256467
11256475
to 0°C. To calculate the RTD temperature for temperatures
below 0°C, a best fit polynomial expression is required, and the
polynomial used in this circuit note is a fifth-order polynomial CODES
shown in Equation 6. Figure 5. Histogram of Codes for RTD at Ambient Temperature, Sinc4 Filter,
Full Power Mode, 50 SPS
TRTD (°C) = −242.02 + 2.2228 × r + (2.5859 × 10−3)r2 −
(48260 × 10−6)r3 − (2.8183 × 10−3)r4 + For the 4-wire RTD configuration where the sinc4 filter and full
(1.5243 × 10−10)r5 (6) power mode were selected, the temperature of the RTD was swept
As an example, if the code read back from the AD7124-4/ from −50°C to +200°C. For each temperature, the corresponding
AD7124-8 with the temperature set to 25°C is 11270065, voltage across the RTD was measured using the AD7124-4/
converting this code to a resistance using Equation 1 gives AD7124-8 as described previously. This voltage was then converted
to a resistance, which was then linearized, and converted to a
(11270065  2 23 )  R REF temperature as described in the 4-Wire RTD Configuration
R RTD   109 .704 Ω
G  2 23 section. Figure 6 shows the resulting error between the set
Linearization using Equation 5 gives a temperature of 24.921°C. temperature and the measured temperatures of the RTD after
linearization. For each RTD temperature setting, the AD7124-4/
As a second example, if the code read back from the AD7124-4/ AD7124-8 is kept at 25°C. As shown in Figure 6, the error of the
AD7124-8 with the temperature set to −25°C is 10757779, RTD temperature measured is well within the error window of
converting this code to a resistance gives the Pt100 Class B RTD after linearization. Figure 6 also shows the
(10757779  2 23 )  R REF deviation of the RTD error across different AD7124-4/AD7124-8
R RTD   90 .200 Ω temperature settings. For each AD7124-4/AD7124-8 temperature
G  2 23
setting, an internal zero-scale and full-scale calibration is carried
Linearization using Equation 6 gives a temperature of −24.982°C. out. As shown in Figure 6, the error of the RTD is well within
the expected error of the Class B RTD for all temperature settings
of the AD7124-4/AD7124-8.
2.5 100
2.0 AD7124-4/AD7124-8 90
TEMPERATURE
1000 SAMPLES
–40ºC
1.5 80
+25ºC Pt100
1.0 +105ºC 70
OCCURANCES
0.5 60
ERROR (°C)
0 50
–0.5 40
–1.0 30
–1.5 20
13441-008
13441-006
–2.0 10
–2.5 0
–50 –25 0 25 50 75 100 125 150 175 200
11271570
11271585
11271600
11271615
11271630
11271645
11271659
11271674
11271689
11271704
11271719
Pt100 TEMPERATURE (°C)
Figure 6. Temperature Accuracy Measurement, Sinc4 Filter,

Full Power Mode, 50 SPS CODES
Figure 7 shows the error in measured RTD temperature for a one Figure 8. Histogram of Codes for RTD at Ambient Temperature, Post Filter,
Low Power Mode, 25 SPS
time, internal zero-scale and full-scale calibration carried out at
25°C. From the plot, it can be seen that carrying out a one time The temperature of the RTD was swept from −50°C to +200°C.
calibration at 25°C or calibrating at each individual temperature For each of the set RTD temperatures, the corresponding voltage
of the AD7124-4/AD7124-8 gives the same performance. across the RTD was measured using the AD7124-4/AD7124-8
2.5 as described previously. The voltage was then converted to a
AD7124-4/AD7124-8 resistance, which was then linearized and converted to a
2.0
TEMPERATURE
–40ºC
temperature as described in the 4-Wire RTD Configuration
1.5
+25ºC Pt100 section. Figure 9 shows the resulting error between the set and
1.0 +105ºC measured temperatures of the RTD after linearization. For each
0.5 RTD temperature setting, the AD7124-4/AD7124-8 is kept at
ERROR (°C)
0 25°C. As shown in Figure 9, the error of the RTD temperature

measured is well within the error window of the Pt100 Class B
–0.5
RTD. Figure 9 also shows the deviation of the RTD error across
–1.0
different AD7124-4/AD7124-8 temperature settings. For each
–1.5 AD7124-4/AD7124-8 temperature setting, an internal zero-scale
and full-scale calibration was carried out. As shown in Figure 9,
13441-007
–2.0
–2.5 the error of the RTD is well within the expected error of the Class B
–50 –25 0 25 50 75 100 125 150 175 200 RTD for all temperature settings of the AD7124-4/AD7124-8.
Figure 7. Temperature Accuracy Measurement, Sinc4 Filter, Full Power Mode, AD7124-4/AD7124-8
50 SPS, One Time 25°C Calibration Only TEMPERATURE
–40ºC
2
The second AD7124-4/AD7124-8 configuration tested was the +25ºC
+105ºC Pt100
low power mode, where the post filter and 25 SPS output data 1
rate were selected. The 25 SPS filter provides simultaneous 50 Hz
ERROR (°C)
and 60 Hz rejection and allows the user to trade off settling time 0
with power supply rejection. Figure 8 shows the resulting noise
distribution when a 4-wire RTD is connected as shown in –1
Figure 1 at ambient temperature. The corresponding rms noise is
typically 774 nV, equating to approximately 16.8 noise free bits. –2
The noise performance of the AD7124-4/AD7124-8 for inputs
13441-009
shorted with the same filter, gain, power mode, and output data –3
rate is typically 360 nV rms or 17.3 noise free bits. The increase –50 –25 0 25 50 75 100 125 150 175 200
in the noise between the two measurements comes directly from
Figure 9. Temperature Accuracy Measurement, Post Filter,
the RTD connection across the input channel (AIN2, AIN3).
Figure 10 shows the error in measured RTD temperature for a one TERMINAL BLOCK
J6
time, internal zero-scale and full-scale calibration carried out at
25°C. From the plot, it can be seen that carrying out a one time AIN0 IOUT0
Pt100
calibration at 25°C or calibrating at each individual temperature
AIN1
of the AD7124-4/AD7124-8 gives similar performance. RL1
1.50 AIN2
RL2
1.25 AD7124-4/AD7124-8
TEMPERATURE
–40ºC AIN3
1.00 Pt100 RL3
+25ºC
0.75 RL4
+105ºC AIN4
0.50 EVAL-AD7124-4SDZ/
AIN5 EVAL-AD7124-8SDZ
ERROR (°C)
0.25
EVALUATION BOARD
0
REFIN+
–0.25 RREF
5.11kΩ
–0.50 REFIN–
–0.75
RHEADROOM
TERMINAL BLOCK
–1.00 250Ω J11
13441-010
–1.25
–1.50 AGND
–50 –25 0 25 50 75 100 125 150 175 200 Pt100
Pt100 TEMPERATURE (°C) PSW
RL1
Figure 10. Temperature Accuracy Measurement, Post Filter,
AIN6
Low Power Mode, 25 SPS, 25°C One Time Calibration Only RL2
COMMON VARIATIONS AIN7

RL3
Multiple 4-Wire RTDs RL4
13441-011
The AD7124-4/AD7124-8 can be used as a measurement system
for multiple 4-wire RTDs. The AD7124-4 can be used to connect Figure 11. AD7124-4 4-Wire RTD Configuration Using Two 4-Wire RTDs
two 4-wire RTDs, while the AD7124-8 can be used to connect
The performance of the 4-wire RTD configuration shown in
up to five 4-wire RTDs. The same reference input can be used
Figure 11 was evaluated to ensure that the expected performance
for all the RTDs, and one current source can be used to excite
was achieved when more than one RTD was connected. For this
all the RTDs. The current is directed to the top side of each of
measurement, the temperature of both 4-wire RTDs were swept
the RTDs in turn when the RTD temperature measurement is
from −50°C to +200°C. For each temperature setting, the voltage
required. The cross multiplexer on the AD7124-4/AD7124-8
across each RTD was recorded. Figure 12 shows the error in
allows multiple channels to be configured separately, where
each. As shown in the results, switching the same current from
each channel can be configured for different setups.
Channel 0 to Channel 1 has no effect on settling; both RTDs are
The steps needed to measure an RTD voltage are well within the expected error window for the Class B RTD.
1. Set the external reference to REFIN1±. 1.50
AD7124-4/AD7124-8
2. Enable the IOUT0 current to the RTD to be measured. 1.25
TEMPERATURE Pt100
3. Enable the analog input channel that has the RTD 1.00 25ºC (AIN2, AIN3)
25ºC (AIN6, AIN7)
connected across its input. 0.75
0.50
As an example, two 4-wire RTDs were connected to the AD7124-4
ERROR (°C)
0.25
as shown in Figure 11. One 4-wire RTD is connected across the
0
AIN2 and AIN3 analog input pins (Channel 0 configuration),
–0.25
where the excitation current comes from AIN0, and a second
–0.50
4-wire RTD is also shown connected across the AIN6 and AIN7
–0.75
analog input pins (Channel 1 configuration), where AIN1 is used
–1.00
for the excitation current. Temperature measurements were
13441-012
–1.25
then carried out on each RTD in turn using the following steps: –1.50
–50 –25 0 25 50 75 100 125 150 175 200
1. IOUT0 is directed to AIN0. The voltage is measured on
Channel 0 (AIN2, AIN3); therefore, Channel 0 must be
Figure 12. RTD Temperature Error Recorded for Two Different
enabled. All other channels are disabled for this measurement. RTD Measurement Configurations
2. Disable Channel 0, enable Channel 1, and direct the IOUT0
current to AIN1. The voltage is then measured on Channel 1
(AIN6, AIN7).
CIRCUIT EVALUATION AND TEST Configuring the Hardware
Equipment Needed To configure the hardware, take the following steps:
The following equipment is needed for the 4-wire RTD 1. Set all links on the EVAL-AD7124-4SDZ/EVAL-AD7124-
measurement system: 8SDZ evaluation board to the default positions, as
 EVAL–AD7124-4SDZ or EVAL-AD7124-8SDZ evaluation described in the EVAL-AD7124-4SDZ/EVAL-AD7124-
board 8SDZ user guide.
2. Power the board with a 7 V or 9 V power source connected
 EVAL-SDP-CB1Z System Demonstration Platform (SDP)
to J5.
 AD7124-4/AD7124-8 EVAL+ Software
3. Connect the RTD, the precision reference resistor, and the
 Power supply: 7 V or 9 V wall wart
resistor for headroom, as shown in Figure 14.
 Class B Pt100 4-wire RTD
 A PC running Windows® XP (SP2), Windows Vista, or TERMINAL BLOCK
J6
Windows 7 (32-bit or 64-bit) Pt100
AIN0
Software Installation RL1
AIN1
A complete software user guide for the AD7124-4/AD7124-8
and the SDP board can be found in the EVAL–AD7124-4SDZ/ AIN2
RL2
EVAL-AD7124-8SDZ user guide and the SDP User Guide.
AIN3
Software is required to interface with the hardware. This software RL3
can be downloaded from ftp://ftp.analog.com/pub/evalcd/AD7124. RL4
AIN4
If the setup file does not automatically run, double click EVAL-AD7124-4SDZ/
setup.exe from the file. Install the evaluation software before AIN5 EVAL-AD7124-8SDZ
EVALUATION BOARD
connecting the evaluation board and SDP board to the USB
REFIN+
port of the PC to ensure that the evaluation system is correctly RREF
5.11kΩ
recognized when connected to the PC. REFIN–
After the evaluation software installation is complete, connect the RHEADROOM

TERMINAL BLOCK
250Ω J11
EVAL-SDP-CB1Z (via Connector B) to the EVAL-AD7124-4SDZ/
EVAL-AD7124-8SDZ and then connect the EVAL-SDP-CB1Z to
AGND
the USB port of the PC using the supplied cable. When the
evaluation system is detected, proceed through any dialog boxes PSW
that appear to complete the installation.
13441-014
Setup and Test
Figure 13 shows a functional block diagram of the test setup. Figure 14. EVAL–AD7124-4SDZ/EVAL-AD7124-8SDZ Evaluation Board
Connector for 4-Wire RTD Measurement
7V TO 9V SUPPLY PC Run the AD7124-4/AD7124-8 EVAL+ Software, and the

260mA LIMIT
window shown in Figure 15 appears.
USB
Pt100
J4/J5
120
J1 CON A
J6
EVAL-AD7124-4SDZ/
REFERENCE EVAL-AD7124-8SDZ
AND
HEADROOM EVAL-SDP-CB1Z
RESISTORS
J11
13441-013
Figure 13. Test Setup Functional Diagram
The EVAL-AD7124-4SDZ /EVAL-AD7124-8SDZ evaluation

board is required to test the circuit. In addition, the following
sensor and resistors are required to ensure proper operation:
13441-015
 4-wire Pt100 RTD, Class B

 5.11 kΩ precision resistor Figure 15. AD7124-4 EVAL+ Software Window
 250 Ω resistor needed for buffer headroom

To configure the AD7124-4/AD7124-8 for 4-wire RTD
measurements, click the 4-WIRE RTD demo mode button
(see Figure 15). Clicking the 4-WIRE RTD button configures
the ADC software as follows:
 Channel_0
o AINP_0 = AIN2
o AINM_0 = AIN3
o Setup0
o Enabled = TRUE
 Setup_0
o PGA_0 = 16
o AIN_BUFP, AIN_BUFM both = ENABLED
o BIPOLAR = ENABLED
13441-016
o FS_0 = 384
o FILTER_MODE_0 = SINC4 Figure 16. Register Map Internal Full-Scale and Zero-Scale Calibration
 ADC_Control
The board and device are now configured for 4-wire RTD
o MODE = Continuous Conversion
measurements. Click SAMPLE to start gathering samples from
o POWER_MODE = FULL
the AD7124-4/AD7124-8. The Waveform tab and the Histogram
 IO_CONTROL_1 tab show the data gathered from the AD7124-4/AD7124-8.
o IOUT0 Channel Enable = AIN1
o IOUT0 Select = 500 μA
One additional step is required before the AD7124-4/AD7124-8
is configured for 4-wire RTD measurements: an internal full-
scale and zero-scale calibration of the AD7124-4/AD7124-8.
This calibration can be performed via the Register Map tab,
as shown in Figure 16.
1. Click the ADC_Control register.
2. Select Low Power mode.
3. Perform an internal full-scale calibration.
a. Click the Mode bitfield of the ADC control register
b. In the Mode bitfield, select the internal full scale
calibration option.
c. Check the calibration performed by clicking the
Gain0 register from the register tree, and check that
the coefficients have changed.
4. Perform an internal zero-scale calibration.
a. Click the Mode bitfield of the ADC control register.
b. In the Mode bitfield, select the internal zero-scale
calibration option.
c. Check the calibrations performed by clicking the
Offset0 register in the register tree, and check that the
coefficients have changed.
5. When calibrations are complete, change the power mode to
the required mode of operation, and ensure that the ADC is
set to continuous conversion mode by selecting Continuous
from the drop-down box in the Mode bit field of the
ADC_Control register.
CN-0381 Design Support Package: EVAL-AD7124-4SDZ
www.analog.com/CN0381-DesignSupport EVAL-AD7124-8SDZ
EVAL-AD7124-4 User Guide (UG-855) System Demonstration Platform (EVAL-SDP-CB1Z)
EVAL-AD7124-8 User Guide (UG-856) AD7124-4 Data Sheet
SDP User Guide AD7124-8 Data Sheet
Kester, Walt. “Temperature Sensors,” Chapter 7 in Sensor Signal ADP1720 Data Sheet
Conditioning. Analog Devices, 1999.
REVISION HISTORY
McCarthy, Mary. AN-615 Application Note. Peak-to-Peak
McNamara, Donal. AN-892 Application Note. Temperature
Measurement Theory and Practical Techniques. Analog Devices.
Circuit Note CN-0376. Channel-to-Channel Isolated
Temperature Input (Thermocouple/RTD) for PLC/DCS
Applications. Analog Devices.
Circuit Note CN-0382. Ultralow Power Industrial Temperature and
Pressure, 4 mA to 20 mA/HART Transmitter. Analog Devices.
Circuit Note CN-0383. Completely Integrated 3-Wire RTD

CN13341-0-7/15(0)
Circuit Note
CN-0383
AD7124-4/
tested for quick and easy system integration to help solve today’s Power, 24-Bit, Sigma-Delta ADCs with
AD7124-8
analog, mixed-signal, and RF design challenges. For more PGA and Reference
50 mA, High Voltage, Micropower
ADP1720
Linear Regulator
Completely Integrated 3-Wire RTD Measurement System Using a Low Power,

Precision, 24-Bit Sigma-Delta ADC
Circuit Evaluation Boards signal chain integration, which includes programmable low
AD7124-4 Evaluation Board (EVAL-AD7124-4SDZ) or drift excitation current sources. Therefore, the design of an
AD7124-8 Evaluation Board (EVAL-AD7124-8SDZ) RTD system is greatly simplified because most of the required
System Demonstration Platform (EVAL-SDP-CB1Z) RTD measurement system building blocks are included on-chip.
Design and Integration Files The AD7124-4/AD7124-8 gives the user the flexibility to
Schematics, Layout Files, Bill of Materials employ one of three integrated power modes, where the current
consumption, range of output data rates, and rms noise are
tailored with the power mode selected. The current consumed
The circuit shown in Figure 1 is an integrated 3-wire resistance by the AD7124-4/AD7124-8 is only 255 µA in low power mode
temperature detector (RTD) system based on the AD7124-4/ and 930 µA in full power mode. The power options make the
AD7124-8 low power, low noise, 24-bit Σ-Δ analog-to-digital device suitable for non-power critical applications, such as
converter (ADC) optimized for high precision measurement input/output modules, and also for low power applications,
applications. With a two-point calibration and linearization, such as loop-powered smart transmitters where the complete
the overall 3-wire system accuracy is better than ±1°C over a transmitter must consume less than 4 mA.
temperature range of −50°C to +200°C. Typical noise free code
The device also has a power down option. In power-down mode,
resolution of the system is 17.9 bits for full power mode, sinc4 filter
the complete ADC along with its auxiliary functions are powered
selected, at an output data rate of 50 SPS, and 16.8 bits for low
down so that the device consumes 1 µA typical. The AD7124-4/
power mode, post filter selected, at an output data rate of 25 SPS.
AD7124-8 also has extensive diagnostic functionality integrated
The AD7124-4 can be configured for 4 differential or 7 pseudo as part of its comprehensive feature set.
differential input channels, while the AD7124-8 can be configured
for 8 differential or 15 pseudo differential channels. The on-chip
programmable gain array (PGA) ensures that signals of small
amplitude can be interfaced directly to the ADC.
Rev. 0
Analog Devices beliable for direct,indirect,special,incidental,consequential or punitive damages due Tel: 781.329.4700 www.analog.com

3.3V OUTPUT ADP1720
IN GND
VIN
10µF 0.1µF
OUT GND OUT GND
4.7µF 4.7µF 4.7µF
EN GND EN GND
ADP1720ARMZ-R7
27kΩ 1.8V OUTPUT
ADJ GND
57.6kΩ
IN GND
4.7µF
OUT GND
4.7µF
EN GND
0.1µF 1µF
0.1µF
AVDD IOVDD
REGCAPD
AIN0 0.1µF
Pt100 REGCAPA
USB
RL1 1kΩ 0.1µF
AIN2 AD7124-4/
AD7124-8
0.01µF
0.1µF
RL2 1kΩ DOUT/RDY
AIN3
0.01µF DIN
RL3 SCLK AD7124
ADSP-BF527
LED
AIN1 CS
SYNC POWER
1kΩ
REFIN1(+)
LED
5.11kΩ 0.01µF CLK
0.1% 0.1µF SDP-B STATUS
±15ppm/°C
REFIN1(–)
1kΩ 0.01µF
AVSS DGND
13369-001
Figure 1. 3-Wire RTD Measurement Configuration
CIRCUIT DESCRIPTION 350
RTD Temperature Measurement Introduction 300
RTDs are frequently used sensors for temperature measurements

250
in industrial applications. An RTD is made from a pure metal
RESISTANCE (Ω)
(examples include platinum, nickel, or copper), which has a 200

predictable change in resistance as the temperature changes.
The most widely used RTDs are platinum Pt100 and Pt1000. 150
RTDs are capable of high accuracy and good stability when

100
compared with other types of temperature sensors. The resistance
of long wire lengths can be compensated for with a 3-wire 50
connection.
13369-002
To accurately measure the resistance, a voltage is generated across 0

–200 0 200 400 600
the RTD by a constant current source. The AD7124-4/AD7124-8 TEMPERATURE (°C)
offers two such excitation current sources that are register Figure 2. RTD Resistance vs. Temperature
programmable from 50 µA to 1 mA. Errors in the current
For the circuit in Figure 1, a Class B Pt100 RTD sensor was used.
source can be easily cancelled by referring the measurement to
Pt100 RTDs measure temperature from −200°C to +600°C. The
the voltage across a precision reference resistor that is driven
resistance of a Class B RTD is typically 100 Ω at 0°C and has a
with the same current source, thereby resulting in a ratiometric
typical temperature coefficient of ~0.385 Ω/°C (see Figure 2).
measurement result.
Using this information, the voltage generated across the Pt100
RTD can easily be calculated based on the current source selected.
How the Circuit Works the CRC functionality checks for changes in bit values during
The AD7124-4/AD7124-8 provides an integrated solution for transmission. When any of these SPI communication diagnostic
RTD measurement. It can achieve high resolution, low non- functions are enabled and an associated error occurs, the
linearity and low noise performance as well as very high 50 Hz corresponding flag is set in the error register. All enabled flags
and 60 Hz rejection. The AD7124-4/AD7124-8 consists of an are OR’ed together and control the ERR flag in the status register.
on-chip, low noise PGA that amplifies the small signal from the This functionality is particularly useful if the status bits are
RTD with a gain programmable from 1 to 128, thus allowing appended to the ADC conversions.
direct interface with the sensor. The gain stage has high input Analog Inputs and Reference
impedance and limits the input leakage current to 3.3 nA
The AD7124-4 can be configured for 4 differential or 7 pseudo
typical for full power mode and 1 nA typical for low power
differential channels, while the AD7124-8 can be configured for
mode. The following section explain the different elements that
8 differential or 15 pseudo differential channels.
make up the 3-wire RTD temperature measurement system.
The AD7124-4/AD7124-8 has on-chip diagnostics that can be
Power Supplies used to check that the voltage level on the analog pins are within
The AD7124-4/AD7124-8 has separate analog and digital power the specified operating range. The positive (AINP) and negative
supplies. The digital power supply, IOVDD, is independent of the (AINM) analog inputs can be separately checked for overvoltages
analog power supply and can be from 1.65 V to 3.6 V referenced and undervoltages, as well as ADC saturation. An overvoltage is
to DGND. The analog power supply, AVDD, is referred to AVSS flagged when the voltage on the analog input exceeds AVDD, while
and has a range of 2.7 V to 3.6 V for low and mid power modes, an undervoltage is flagged when the voltage on the analog input
and 2.9 V to 3.6 V for full power mode. The circuit shown in goes below AVSS.
Figure 1 operates from a single supply; therefore, AVSS and
For the circuit shown in Figure 1, four analog pins are used to
DGND are connected together, and only one ground plane is
implement the 3-wire measurement: AIN0, AIN1, AIN2, and
used. The AVDD and IOVDD voltage are generated separately
AIN3. AIN2 and AIN3 are configured as a fully differential
using ADP1720 voltage regulators. The AVDD voltage is set to input channel and are used for sensing the voltage across the
3.3 V and the IOVDD voltage is set to 1.8 V using the ADP1720 Pt100. The excitation current source used to excite the RTD
regulators. Using separate regulators ensures the lowest noise.
is generated from AVDD and is directed to AIN0. An identical
Serial Peripheral Interface (SPI) current is directed to AIN1 and flows through the RL2 lead
SPI communications to the AD7124-4/AD7124-8 is handled by resistance, thereby generating a voltage that cancels the voltage
the Blackfin® ADSP-BF527 on the EVAL-SDP-CB1Z, as shown in dropped across the RL1 lead resistance. The analog pins and
Figure 1. To access the registers of the AD7124-4/AD7124-8, use their configuration are shown in greater detail in Figure 4.
the AD7124-4/AD7124-8 EVAL+ Software. Figure 3 shows the
main window of this software. Clicking 3-WIRE RTD configures
the software for the 3-wire RTD measurement. Pt100
AIN0
RL1 1kΩ
AIN2
0.01µF
0.1µF
RL2 1kΩ
AIN3
0.01µF
RL3
AIN1
1kΩ
REFIN1(+)
5.11kΩ 0.01µF
0.1% 0.1µF
±15ppm/°C
REFIN1(–)
1kΩ
13369-004
0.01µF
Figure 4. Analog Inputs for 3-Wire RTD Measurement

13369-003
With the PGA enabled, the analog input buffers are automatically
Figure 3. AD7124-4/AD7124-8 EVAL+ Software Configuration Screen enabled. The PGA allows voltages on the input pins to be as low
The AD7124-4/AD7124-8 has diagnostic functions on-chip that as AVSS; therefore, headroom resistors are not required for the
can be used to detect faults in the SPI communication. These analog input pins. The reference buffers are also enabled. These
diagnostics include checks on the SPI read and write operations, buffers require headroom. Because the reference resistor is on the
ensuring that only valid registers are accessed. An SCLK counter high side, the headroom requirements for the reference resistor
ensures that the correct number of SCLK pulses are used, while are met; therefore, additional headroom resistors are not required.
For the circuit shown in Figure 1, the reference input used is To ensure that the maximum range of the AD7124-4/AD7124-8
REFIN1(±). The current through the Pt100 also flows through is used, the PGA gain is programmed to 16, which amplifies the
the precision reference resistor that generates the reference voltage. maximum RTD sensor output voltage to 2.5096 V. To ensure a
The voltage generated across this precision reference resistor is true ratiometric configuration for this 3-wire circuit, the
ratiometric to the voltage across the Pt100; therefore, any errors reference voltage to the ADC is generated using an external
because of variations in the excitation current are removed. precision resistor using the same excitation current as that used
Digital and Analog Filtering for the Pt100. Using this configuration means that any deviation
in the value of the excitation current is seen across the Pt100 as
Differential (~800 Hz cutoff) and common-mode (~16 kHz well as the reference resistor, and therefore does not alter the
cutoff) filters are implemented at the analog inputs as well as accuracy of the system.
at the reference inputs. This filtering is required to reject any
interference at the modulator frequency and also any multiples Using the excitation current of 500 µA and the amplified voltage
of this frequency. of the ADC, the reference resistor value is
The AD7124-4/AD7124-8 offers a great deal of on-chip digital VRTD MAX/IEXC = 2.51 V/500 µA = 5020 Ω
filtering flexibility. Several filter options are available; the option Therefore, a 5.11 kΩ resistor is chosen, which gives a reference
selected has an effect on the output data rate, settling time, as voltage of
well as 50 Hz and 60 Hz rejection. For this circuit note, the sinc4 VREF = RREF × IEXC = 5.11 kΩ × 500 µA = 2.555 V
filter and the post filter are implemented. The sinc4 filter is used
because it has excellent noise performance across the range of The output compliance of the excitation current source must
output data rates, as well as excellent 50 Hz and 60 Hz rejection. also be considered when making 3-wire RTD measurements
The post filter is used to provide simultaneous 50 Hz and 60 Hz using the AD7124-4/AD7124-8. The output compliance is
rejection with a 40 ms settling time. dependent on the excitation current selected. For this circuit,
500 µA is selected, which has an output compliance voltage of
Calibration AVDD − 0.37 V. The AVDD supply voltage for this circuit is 3.3 V,
The AD7124-4/AD7124-8 provides different calibration modes which means that the output compliance level for the excitation
that can be used to eliminate offset and gain errors. For this current source must be less than 2.93 V. From the previous
circuit note, internal zero-scale calibration as well as internal calculations, this specification is met because the maximum
full-scale calibration were used. Note that these calibrations voltage on the AIN0 pin is the voltage across the precision
remove only the ADC gain and offset errors, not gain and offset reference resistor plus the voltage across the RTD:
errors created by the external circuitry. VREF + VRTD = 2.555 V + 156.85 mV = 2.71185 V
3-Wire RTD Configuration The AD7124-4/AD7124-8 configuration for the 3-wire RTD
The circuit shown in Figure 1 is designed for precision 3-wire measurement is as follows:
RTD measurement using the AD7124-4/AD7124-8. For the • Differential input: AINP = AIN2, AINM = AIN3
3-wire RTD measurement, two precision excitation current
• Excitation current: IOUT0 = AIN0 = 500 µA
sources are required that provide an easy way to cancel the lead
• Excitation current: IOUT1 = AIN1 = 500 µA
resistance errors produced by RL1 and RL2. Note that the RL3
• Gain = 16
lead resistance does not affect the measurement accuracy. For
the 3-wire RTD configuration shown in Figure 1, the reference • 5.11 kΩ precision reference resistor
resistor is placed on the high side of the RTD. For this setup, one • Digital filtering (sinc4 and post filter)
excitation current flows through both the reference resistor and The general expression to calculate the RTD resistance (R),
the RTD; the second current flows through lead-resistance RL2 where the ADC is operating in bipolar mode, is given by
and develops a voltage that cancels the voltage dropped across
RL1. Because only one excitation current generates the reference (CODE − 2N − 1 ) × RREF
RRTD = (1)
voltage to REFIN1±, and also generates the voltage across the G × 2N − 1
RTD, the current source accuracy, mismatch, and mismatch
drift has a minimal effect on the ADC transfer function. where:
CODE is the ADC code.
A low level voltage is generated across the Pt100 RTD by the N is the resolution of the ADC (24, in this case).
excitation current. This low level voltage can then be amplified RREF is the reference resistor.
by the on-board PGA of the AD7124-4/AD7124-8, and is then G is the selected gain.
converted to a precision digital representation using the 24-bit
Σ-Δ ADC. For this 3-wire RTD configuration, both excitation From the specification of the Class B RTD, the resistance changes
currents are programmed to 500 µA. For a maximum RTD by approximately 0.385 Ω/°C. This relationship can be used as a
temperature of 600°C, the voltage generated across the RTD quick method to get an approximate temperature of the RTD. This
using the 500 µA excitation current is approximately 156.85 mV. method has inaccuracies due to the temperature coefficient of
the RTD changing slightly over the temperature range; however, Converting this code to a resistance gives
it can be a useful method to quickly check the temperature.
(10757779 − 223 ) × RREF
To calculate the approximate temperature, use Equation 2, RRTD = = 90.200 Ω
G × 223
where the resistance of the RTD is 100 Ω at 0°C.
Linearization using Equation 6 gives a temperature of −24.982°C.
RRTD − 100
Temperature (°C) = (2) 3-Wire RTD Measurements and Results
0.385
For the circuit shown in Figure 1, data was gathered for different
The RTD transfer function known as the Callender-Van Dusen
digital filter and power mode configurations of the AD7124-4/
equation is made up of two distinct polynomial equations.
AD7124-8, namely the sinc4 filter operating in full power mode
Equation 3 is used for temperatures greater than 0°C, and
and the post filter operating in low power mode.
Equation 4 for temperatures less than 0°C.
Choosing the configuration for sinc4 filter, full power mode for
The equation for temperature t ≤ 0°C is
an output data rate of 50 SPS allows the user to operate the
RRTD(t) = R0[1 + At + Bt2 + C(t − 100°C)t3] (3) AD7124-4/AD7124-8 for best performance in relation to speed
The equation for temperature t ≥ 0°C is and noise. Figure 5 shows the noise distribution when a 3-wire
RTD is connected as shown in Figure 1 at ambient temperature.
RRTD(t) = R0(1 + At + Bt2) (4)
The corresponding rms noise is typically 199.37 nV rms equating
where: to approximately 17.9 noise free bits. The noise performance of
t is the RTD temperature (°C). the AD7124-4/AD7124-8 for inputs shorted when the same filter,
RRTD(t) is the RTD resistance at temperature (t). gain, and output data rate are selected is typically 100 nV rms or
R0 is the RTD resistance at 0°C (in this case, R0 = 100 Ω). 18.7 noise free bits. The increase in the noise comes directly from
A = 3.9083 × 10−3. the RTD connected across the input channel (AIN2, AIN3).
B = −5.775 × 10−7. 160
C = −4.23225 × 10−12. 1000 SAMPLES
140
There are many different ways to determine the temperature as
a function of the RTD resistance given the transfer function in 120
Equation 3 and Equation 4. For this circuit note, the direct

OCCURRENCES
100
mathematical method is chosen because of its accuracy. Using
Equation 3, the temperature can be calculated as 80

60
r 
−A+ A2 − 4 B1 − 

 R0  40
TRTD (°C) = (5)
2B 20
13369-005
where r is the RTD resistance, and the other variables are as
0
defined previously.
11270217
11270222
11270228
11270233
11270238
11270243
11270249
11270254
This method works well for temperatures greater than or equal
to 0°C. To calculate the RTD temperature for temperatures CODES
below 0°C, a best fit polynomial expression is required. The Figure 5. Histogram of Codes for RTD at Ambient, Sinc4 Filter,
polynomial used in this note is a fifth-order polynomial, Full Power Mode, 50 SPS
shown in Equation 6.
For the 3-wire RTD configuration where the sinc4 filter and
TRTD (°C) = −242.02 + 2.2228 × r + (2.5859 × 10 )r −
−3 2
full power mode were selected, the temperature of the RTD
(48260 × 10−6)r3 − (2.8183 × 10−3)r4 + was swept from −50°C to +200°C. For each temperature, the
(1.5243 × 10−10)r5 (6) corresponding voltage across the RTD was measured using the
As an example, the code read back from the AD7124-4/ AD7124-4/AD7124-8 as outlined previously. This voltage was
AD7124-8 for the temperature set to 25°C is 11270065. then converted to a resistance, linearized, and converted to a
Converting this code to a resistance using Equation 1 gives temperature as outlined in the 3-Wire RTD Configuration
section. Figure 6 shows the resulting error between the set
(11270065 − 223 ) × RREF
RRTD = = 109.704 Ω temperature and the measured system temperature of the RTD
G × 223 after linearization. For each RTD temperature setting, the
Linearization using Equation 5 gives a temperature of 24.921°C. AD7124-4/AD7124-8 is kept at 25°C. As shown in Figure 6,
the error of the RTD temperature measured is well within the
As a second example, the code read back from the AD7124-4/
error window of the Pt100 Class B RTD. Figure 6 also shows the
AD7124-8 for the temperature set to −25°C is 10757779.
deviation of the RTD error across different AD7124-4/AD7124-8
temperature settings. For each AD7124-4/AD7124-8 temperature directly from the RTD connection across the input channel
setting, an internal zero-scale and full-scale calibration is carried (AIN2, AIN3).
out. As shown in Figure 6, the error of the RTD is well within 120
the expected error of the Class B RTD for all temperature settings 1000 SAMPLES
of the AD7124-4/AD7124-8. 100
1.50
1.25 AD7124-4/AD7124-8 80
OCCURRENCES
TEMPERATURE
1.00 –40ºC Pt100
+25ºC
0.75 60
+105ºC
0.50
ERROR (°C)
0.25 40
0
–0.25 20
13369-008
–0.50
–0.75 0
11270511
11270403
11270417
11270430
11270444
11270457
11270471
11270484
11270498
11270525
11270538
–1.00
13369-006
–1.25
–1.50 CODES
–50 –25 0 25 50 75 100 125 150 175 200
Figure 8. Histogram of Codes for RTD at Ambient, Post Filter,
Figure 6. Temperature Accuracy Measurement, Sinc4 Filter,
Full Power Mode, 50 SPS For this AD7124-4/AD7124-8 configuration where the post
Figure 7 shows the error in measured RTD temperature for a filter and low power mode were selected, the temperature of the
one time, internal zero-scale and full-scale calibrations carried RTD was swept from −50°C to +200°C. For each of the set RTD
out at 25°C. The plot shows that carrying out a one time temperatures, the corresponding voltage across the RTD was
calibration at 25°C or calibrating at each individual temperature measured using the AD7124-4/AD7124-8 as outlined previously.
of the AD7124-4/AD7124-8 gives similar performances. This voltage was then converted to a resistance, which was then
linearized and converted to a temperature as outlined in the 3-Wire
1.50
1.25 AD7124-4/AD7124-8 RTD Configuration section. Figure 9 shows the resulting error
1.00
TEMPERATURE
–40ºC
between the set and measured temperatures of the RTD after
Pt100
0.75
+25ºC linearization. For each RTD temperature setting, the AD7124-4/
0.50
+105ºC AD7124-8 is kept at 25°C. As shown in Figure 9, the error of the
RTD temperature measured is well within the error window of
ERROR (°C)
0.25
0
the Pt100 Class B RTD. Figure 9 also shows the deviation of the
–0.25
RTD error across different AD7124-4/AD7124-8 temperature
–0.50
settings. For each AD7124-4/AD7124-8 temperature setting,
–0.75
an internal zero-scale and full-scale calibration is carried out.
–1.00
Figure 9 shows that the error of the RTD is well within the
expected error of the Class B RTD for all temperature settings
13369-007
–1.25
–1.50
of the AD7124-4/AD7124-8.
–50 –25 0 25 50 75 100 125 150 175 200 1.50
Pt100 TEMPERATURE (°C) AD7124-4/AD7124-8
1.25
TEMPERATURE
Figure 7. Temperature Accuracy Measurement, Sinc4 Filter, 1.00 –40ºC Pt100
Full Power Mode, 50 SPS, One Time 25°C Calibration Only +25ºC
0.75
+105ºC
The second AD7124-4/AD7124-8 configuration tested was the 0.50
low power mode, where the post filter and 25 SPS output data
ERROR (°C)
0.25
rate were selected. The 25 SPS filter gives simultaneous 50 Hz 0
and 60 Hz rejection and allows the user to trade off settling –0.25
time with power supply rejection. Figure 8 shows the resulting –0.50
noise distribution when a 3-wire RTD is connected as shown in –0.75
Figure 1 at ambient temperature. The corresponding rms noise –1.00
is typically 774 nV rms equating to approximately 16.8 noise

13369-009
–1.25
free bits. The noise performance of the AD7124-4/AD7124-8 –1.50

–50 –25 0 25 50 75 100 125 150 175 200
for inputs shorted with the same filter, gain, power mode, and Pt100 TEMPERATURE (°C)
output data rate is typically 360 nV rms or 17.3 noise free bits. Figure 9. Temperature Accuracy Measurement, Post Filter,
The increase in the noise between the two measurements comes Low Power Mode, 25 SPS
Figure 10 shows the error in measured RTD temperature for a IOUT1 is connected to AIN1. The average of these two voltage
one time, internal zero-scale and full-scale calibration carried measurements is then used in the overall calculation of the RTD
out at 25°C. The plot shows that carrying out a one time resistance, and subsequently the temperature is calculated using
calibration at 25°C or calibrating at each individual temperature Equation 1 through Equation 6. The chopping method greatly
of the AD7124-4/AD7124-8 gives similar performances. reduces any effects of excitation current mismatch and mismatch
1.50 drift. However, there is an impact on the throughput rate since
1.25 AD7124-4/AD7124-8
TEMPERATURE
two measurements are required.
1.00 –40ºC Pt100
+25ºC
0.75
+105ºC 250µA
0.50 AIN0
Pt100
ERROR (°C)
0.25
0 RL1 1kΩ
AIN2
–0.25 0.01µF
0.1µF
–0.50
RL2 1kΩ
AIN3
–0.75
0.01µF
–1.00
RL3
–1.25 13369-010 AIN1
–1.50 250µA
–50 –25 0 25 50 75 100 125 150 175 200 1kΩ
500µA REFIN1(+)
5.11kΩ 0.01µF
Figure 10. Temperature Accuracy Measurement, Post Filter, 0.1%
±15ppm/°C
0.1µF
Low Power Mode, 25 SPS, 25°C One Time Calibration Only REFIN1(–)
REFERENCE 1kΩ
13369-011
250Ω 0.01µF
COMMON VARIATIONS BUFFER
HEADROOM
Current Source Mismatch and Mismatch Drift

Figure 11. AD7124-4/AD7124-8 Configuration for 3-Wire RTD Measurement
In the Figure 1 circuit, the precision reference resistor was Using the Current Chopping Measurement Technique
placed on the high side. The high-side configuration works well
Measurement data using the excitation current chopping method
for systems using a single RTD. When multiple RTDs are used,
was gathered, and the corresponding Pt100 temperature error
it is better to place the precision resistor on the low side because
recorded as shown in Figure 12. For all RTD temperatures
only a single reference resistor is required. With the reference
measured, the temperature error is within the error band of the
resistor on the low side, better excitation current matching is
Pt100 RTD for different ambient temperatures of the AD7124-4/
required. Two different techniques can be used to minimize the
AD7124-8. These results show that chopping the excitation
errors due to mismatches in the currents:
current gives results that are comparable to the data gathered
• Chopping the excitation currents with the high-side precision reference resistor configuration.
• Calibration by measuring the excitation currents 1.50
1.25 AD7124-4/AD7124-8
Chopping the Excitation Currents TEMPERATURE
–40ºC
1.00 Pt100
The crosspoint multiplexer on the AD7124-4/AD7124-8 allows 0.75
+25ºC
+105ºC
easy implementation of the chopping configuration. Figure 11 0.50
shows the 3-wire RTD configuration with the precision 5.11 kΩ
ERROR (°C)
0.25
reference resistor connected to the low side of the Pt100 RTD. 0
For this configuration, the current source used as well as the –0.25
gain must be reconsidered. Both IOUT0 and IOUT1 are set to –0.50
250 µA. Selecting this current ensures that the circuit complies –0.75
with the output compliance of the current sources as well as the –1.00
reference voltage generated across the precision resistor. To
13369-012
–1.25
ensure that the full range of the ADC is used, the gain of the –1.50
–50 –25 0 25 50 75 100 125 150 175 200
PGA was set to 32. A resistor is required on the low side of the Pt100 TEMPERATURE (°C)
reference resistor because the reference buffers are enabled and
Figure 12. Temperature Accuracy Measurement for Chopping Configuration,
require headroom (100 mV). Sinc4 Filter, Full Power Mode, Calibration at Each Temperature
To chop the currents, a measurement of the RTD voltage is taken Calibration by Measuring the Excitation Currents
when IOUT0 is connected to AIN0, and IOUT1 is connected
The configuration for calibrating the 3-wire system by
to AIN1, as shown in Figure 11. A second measurement of the
measuring the excitation currents is shown in Figure 13. For
voltage across the RTD is then taken when the currents are
this configuration, the precision reference resistor is connected
swapped, that is, when IOUT1 is connected to AIN0, and
to the low side of the RTD. This configuration is similar to that Lead Resistance Considerations
used for chopping the currents, where both the currents are set For the 3-wire RTD measurement, the accuracy of the lead
to 250 µA, and the PGA gain is set to 32. However, the main resistance compensation depends on the resistance of each of
difference is that an additional differential input channel is the leads being equal (specifically, RL1 = RL2). The voltage
required. The additional input channel enables the measurement dropped across RL3 does not affect the voltage measured across
of the two excitation currents. The measurement is implemented the RTD element; therefore, RL3 does not introduce error in the
by measuring the voltage drop across the precision reference measurement for the circuits described in this circuit note.
resistor with respect to the internal reference when each of the
excitation currents is individually enabled. The measured voltage The nominal resistance of 24 AWG copper wire is 0.026 Ω/foot.
is then converted to a current based on the value of the precision A 50 foot length has a 1.3 Ω lead resistance. A 10% error in
reference resistor value, which is subsequently used to calculate matching produces a 0.13 Ω error in the RTD measurement,
the ratio of the currents, and then used to calibrate the mismatch. assuming perfectly matched compensation and excitation
currents. The RTD temperature coefficient is approximately
0.385 Ω/°C; therefore, the 0.13 Ω lead resistance mismatch
250µA
measurement error translates into approximately (0.13 Ω) ÷
AIN0
Pt100 (0.385 Ω/°C) = 0.337°C error due to lead resistance mismatch.
RL1 1kΩ Therefore, for accurate 3-wire measurements, the matching
AIN2
0.01µF
characteristics of the connecting cables must be known precisely.
0.1µF
RL2 1kΩ Assuming perfect lead resistance matching, mismatches in the
AIN3
0.01µF
excitation currents (IOUT0 and IOUT1) produce an error that
RL3 is proportional to the total lead resistance. For instance, a 0.5%
AIN1 mismatch in the excitation currents (typical specification for the
250µA
AD7124-4/AD7124-8) produces a corresponding 0.5% error in
1kΩ
500µA REFIN1(+) the RTD resistance measurement. The nominal Pt100 RTD
5.11kΩ
0.1%
0.01µF
0.1µF resistance temperature coefficient is 0.385 Ω/°C, which is
±15ppm/°C
REFIN1(–) equivalent to a temperature change of 2.6°C/Ω. A 0.5% error in
REFERENCE
BUFFER 250Ω
1kΩ 0.01µF the resistance measurement gives an RTD measurement error of
HEADROOM
0.005 × 2.6°C/Ω = 0.013°C/Ω. For a lead resistance of 10 Ω
AIN4 (~400 feet of 24 AWG copper wire), the error due to the
mismatch in currents is only 0.13°C.
13369-013
AIN5
The previous discussion illustrates that, in most practical

Figure 13. AD7124-4/AD7124-8 Configuration for 3-Wire RTD Measurement
Calibration by Measuring the Excitation Currents
applications, the mismatch in the lead resistances creates much
more error than the 0.5% mismatch in excitation currents. As
Figure 14 shows the calibrated temperature error in the RTD previously mentioned, the mismatch error in the excitation
measurements. The results show that the RTD error is within the currents can be minimized by using either the chopping mode
expected error band of the RTD, where the error in measurement or by measuring the individual excitation currents.
is close to the error profile of the RTD itself. To ensure accurate
results, calibration of the currents must take place at regular
intervals over time.
1.50
1.25 AD7124-4/AD7124-8
TEMPERATURE
1.00 –40ºC Pt100
+25ºC
0.75
+105ºC
0.50
ERROR (°C)
0.25
0
–0.25
–0.50
–0.75
–1.00
13369-014
–1.25
–1.50
–50 –25 0 25 50 75 100 125 150 175 200
Figure 14. Temperature Accuracy Measurement for Excitation Current

Calibration, Sinc4 Filter, Full Power Mode, Calibration at Each Temperature
CIRCUIT EVALUATION AND TEST The EVAL-AD7124-4SDZ/EVAL-AD7124-8SDZ evaluation
Equipment Needed board is required to test the circuit. In addition, the following
sensor and resistors are required for proper operation:
The following equipment is required for the 3-wire RTD
measurement system: • 3-wire Pt100 RTD, Class B
• 5.11 kΩ precision resistor
• The EVAL–AD7124-4SDZ or EVAL-AD7124-8SDZ
• 250 Ω resistor for buffer headroom (not needed for this
evaluation board
configuration, but included for completeness because it
• The EVAL-SDP-CB1Z System Demonstration Platform
may be required if a Pt1000 RTD is used with a gain of 1)
(SDP)
• AD7124-4/AD7124-8 EVAL+ Software To configure the hardware, take the following steps:
• Power supply: 7 V or 9 V wall wart • Set all links on the EVAL-AD7124-4SDZ/EVAL-AD7124-
• Class B Pt100 3-wire RTD 8SDZ to the default board positions as outlined in the
• A PC running Windows® XP (SP2), Windows Vista, or EVAL-AD7124-4SDZ/EVAL-AD7124-8SDZ user guide.
Windows 7 (32-bit or 64-bit) • Power the board with a 7 V or 9 V power source connected
Software Installation to J5.
• Connect the RTD, precision reference resistor, and resistor
A complete software user guide for the AD7124-4/AD7124-8
for headroom as shown in Figure 16.
and the SDP board can be found in the EVAL-AD7124-4SDZ/
EVAL-AD7124-8SDZ user guide and the SDP User Guide. TERMINAL BLOCK
J6
Software is required to interface with the hardware. This software
can be downloaded from ftp://ftp.analog.com/pub/evalcd/AD7124. AIN0
If the setup file does not run automatically, double-click setup.exe AIN1
Pt100
from the file. Install the evaluation software before connecting
the evaluation board and SDP board to the USB port of the PC RL1
AIN2
to ensure that the evaluation system is correctly recognized

AIN3
when connected to the PC. RL2 EVAL-AD7124-4SDZ/
RL3
After the evaluation software installation is complete, connect AIN4 EVAL-AD7124-8SDZ
EVALUATION BOARD
the SDP board (via Connector A) to the EVAL-AD7124-4SDZ/
AIN5
EVAL-AD7124-8SDZ and then connect the SDP board to the
USB port of the PC using the supplied cable. When the evaluation REFIN+
system is detected, proceed through any dialog boxes that appear RREF
5.11kΩ
to complete the installation. REFIN–
Setup and Test RHEADROOM

250Ω
TERMINAL BLOCK
J11
Figure 15 shows a functional block diagram of the test setup for
the 3-wire RTD configuration. AGND
PSW
7V TO 9V SUPPLY PC
260mA LIMIT
13369-016
USB
Pt100
Figure 16. EVAL-AD7124-4SDZ/EVAL-AD7124-8SDZ Evaluation Board
J4/J5 Connector for 3-Wire RTD Measurement
120
J1 CON A Run the AD7124-4/AD7124-8 EVAL+ Software. Figure 17
J6
shows a screenshot of the main window of the software.
EVAL-AD7124-4SDZ/
RREF EVAL-AD7124-8SDZ
EVAL-SDP-CB1Z
J11
13369-015
is configured for 3-wire RTD measurements: an internal full-
scale and zero-scale calibration of the AD7124-4/AD7124-8.
This calibration can be performed via the Register Map tab, as
shown in Figure 18.
1. From the register tree, select the ADC_Control register.
2. Select Low Power mode.
3. Perform an internal full-scale calibration.
b. In the Mode bitfield, select the internal full-scale
calibration option.
c. Check that the calibration performed by selecting the
Gain0 register from the register tree, and check that
13369-017
the coefficients have changed.
Figure 17. AD7124-4/AD7124-8 EVAL+ Software Main Window 4. Perform an internal zero-scale calibration.
To configure the AD7124-4/AD7124-8 for 3-wire RTD b. In the Mode bitfield, select the internal zero-scale
measurements, click the 3-WIRE RTD demo mode button (see calibration option.
Figure 17). Clicking this button configures the ADC software c. Check that the calibration performed by selecting the
for optimized performance. Some of the register settings are as Offset0 register from the register tree, and check that
follows: the coefficients have changed.
1. Channel_0 5. When calibrations are complete, change the power mode to
a. AINP_0 = AIN2 the required mode of operation, and ensure that the ADC is
b. AINM_0 = AIN3 set to continuous conversion mode by selecting Continuous
c. Setup0 from the drop-down box in the Mode bitfield of the
d. Enabled = TRUE ADC_Control register.
2. Setup_0
a. PGA_0 = 16
b. AIN_BUFP, AIN_BUFM both = ENABLED
c. BIPOLAR = ENABLED
d. FS_0 = 384
e. FILTER_MODE_0 = SINC4
3. ADC_Control
a. MODE = Continuous Conversion
b. POWER_MODE = FULL
4. IO_CONTROL_1
a. IOUT0 Channel Enable = AIN0
b. IOUT0 Select = 500 μA
c. IOUT1 Channel Enable = AIN1
d. IOUT1 Select = 500 μA
13369-018
Figure 18. Register Map Internal Full-Scale and Zero-Scale Calibration
The board and device are now configured for 3-wire RTD
measurements. Click SAMPLE to start gathering samples from
the AD7124-4/AD7124-8. The Waveform tab and the Histogram
tab show the data gathered from the AD7124-4/AD7124-8.
SDP User Guide System Demonstration Platform (EVAL-SDP-CB1Z)
AN-892 Application Note. Temperature Measurement Theory ADP1720 Data Sheet
and Practical Techniques. Analog Devices.
REVISION HISTORY
McCarthy, Mary. AN-615 Application Note. Peak-to-Peak
Circuit Note CN-0376. Channel-to-Channel Isolated
Circuit Note CN-0381. Completely Integrated 4-Wire RTD
Circuit Note CN-0382. Ultralow Power Industrial Temperature and
Pressure 4 mA to 20mA/HART Transmitter. Analog Devices.
property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab
reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability,
noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that
may result from their use. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so.

CN13369-0-7/15(0)
Circuit Note
CN-0384
AD7124-4/
tested for quick and easy system integration to help solve today’s Power, 24-Bit, Sigma-Delta ADCs with
AD7124-8
analog, mixed-signal, and RF design challenges. For more PGA and Reference
50 mA, High Voltage, Micropower Linear
ADP1720
Regulator
Completely Integrated Thermocouple Measurement System Using a Low Power,

Precision, 24-Bit, Sigma-Delta ADC
Circuit Evaluation Boards signal chain integration, which includes programmable low
AD7124-4 Evaluation Board (EVAL-AD7124-4SDZ) or drift excitation current sources, bias voltage generator, and
AD7124-8 Evaluation Board (EVAL-AD7124-8SDZ) internal reference. Therefore, the design of a thermocouple
System Demonstration Platform (EVAL-SDP-CB1Z) system is simplified when the AD7124-4/AD7124-8 is used
Design and Integration Files because most of the required system building blocks are
Schematics, Layout Files, Bill of Materials included on-chip.
The AD7124-4/AD7124-8 gives the user the flexibility to
employ one of three integrated power modes, where the current
The circuit shown in Figure 1 is an integrated thermocouple consumption, range of output data rates, and rms noise are
measurement system based on the AD7124-4/AD7124-8 low tailored with the power mode selected. The current consumed
power, low noise, 24-bit, Σ-Δ analog-to-digital converter (ADC), by the AD7124-4/AD7124-8 is only 255 μA in low power mode
optimized for high precision measurement applications. and 930 μA in full power mode. The power options make the
Thermocouple measurements using this system show an overall device suitable for non-power critical applications, such as
system accuracy of ±1°C over a measurement temperature range input/output modules, and also for low power applications,
of −50°C to +200°C . Typical noise free code resolution of the such as loop-powered smart transmitters where the complete
system is approximately 15 bits. transmitter must consume less than 4 mA.
The AD7124-4 can be configured for 4 differential or 7 pseudo The device also has a power-down option. In power-down
differential input channels, while the AD7124-8 can be configured mode, the complete ADC along with its auxiliary functions are
for 8 differential or 15 pseudo differential channels. The on-chip powered down so that the device consumes 1 μA typical. The
low noise programmable gain array (PGA) ensures that signals AD7124-4/AD7124-8 also has extensive diagnostic functionality
of small amplitude can be interfaced directly to the ADC. integrated as part of its comprehensive feature set.
Rev. 0
toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. Continuedonlastpage) Fax: 781.461.3113 ©2015 Analog Devices, Inc. All rights reserved.

3.3V OUTPUT ADP1720
IN GND
VIN
10µF 0.1µF
OUT GND OUT GND
4.7µF 4.7µF 4.7µF
EN GND EN GND
ADP1720ARMZ-R7
27kΩ 1.8V OUTPUT
ADJ GND
57.6kΩ
IN GND
4.7µF
OUT GND
4.7µF
EN GND
0.1µF 1µF
THERMOCOUPLE
CONNECTOR 0.1µF
1kΩ AVDD IOVDD
+ AIN2
T-TYPE
THERMOCOUPLE 0.01µF REGCAPD
0.1µF
0.1µF
1kΩ REGCAPA
– AIN3
USB
0.01µF
AD7124-4/ 0.1µF
AD7124-8
COLD IOUT1 (AIN1)
JUNCTION
1kΩ DOUT/RDY
AIN6
RTD Pt100 0.01µF DIN
4-WIRE 0.1µF
CONFIGURATION SCLK AD7124
ADSP-BF527
LED
1kΩ
AIN7 CS
0.01µF SYNC POWER
LED
1kΩ CLK
REFIN1(+) SDP-B STATUS
5.11kΩ 0.01µF
0.1% 0.1µF
±15ppm/°C
REFIN1(–)
1kΩ 0.01µF
REFERENCE AVSS DGND
BUFFER 250Ω
HEADROOM
13470-001
Figure 1. AD7124-4/AD7124-8 Thermocouple Measurement Configuration Including RTD Cold Junction Compensation
CIRCUIT DESCRIPTION The junction is placed where the temperature is to be measured,

Temperature Measurement Introduction and is referred to as the measurement junction. The other end
of the thermocouple is connected to a precision voltage
Thermocouples are one of the most frequently used sensors for
measurement unit, and this connection is referred to as the
temperature measurements in industrial applications because of
reference junction, or alternately the cold junction. The
their low cost, ruggedness, repeatability, as well as wide operating
temperature difference between the measurement junction and
temperature range and fast response time. Thermocouples are
the cold junction generates a voltage that is proportional to the
especially useful for making measurements at high temperatures
difference between the temperatures of the two junctions. The
(up to 2300°C for C-type thermocouples).
signal generated is typically from several microvolts to tens of
A thermocouple consists of the junction of two wires of millivolts and is dependent on the temperature difference. In
different metal types, as shown in Figure 2. the circuit shown in Figure 1, a T-type thermocouple is used.
METAL A T-type thermocouples are capable of measuring temperatures
TO SIGNAL of −200°C to +400°C with an output range of approximately
CONDITIONING
METAL B
AND ADC INPUT −8.6 mV to +17.2 mV. It is important for the signal chain to
present a high impedance and low leakage to the thermocouple
to achieve the highest accuracy.
13470-002
MEASUREMENT REFERENCE
JUNCTION JUNCTION T-type thermocouples have a sensitivity of approximately
Figure 2. Thermocouple Connection Showing Measurement and 40 μV/°C. Therefore, by using the integrated PGA of the
Reference Junctions AD7124-4/AD7124-8, the small thermocouple voltage levels
can be easily sensed and accurately converted to a digital How the Circuit Works
representation. The thermocouple response is approximately The AD7124-4/AD7124-8 provides an integrated solution for
linear over a small portion of the range (0°C to 60°C), as shown thermocouple measurements. The AD7124-4/AD7124-8 can
in Figure 3. For accurate measurements over a wide temperature achieve high resolution, low nonlinearity, and low noise
range, a linearization routine must be applied to the measured performance as well as high 50 Hz and 60 Hz rejection. The
value to ensure accurate temperature values. device consists of an on-chip, low noise PGA that amplifies the
20 small signal from thermocouple with a gain programmable
T-TYPE THERMOCOUPLE from 1 to 128, thus allowing direct interface with the sensor.
15 The gain stage has high input impedance and limits the input
THERMOCOUPLE EMF (mV)
leakage current to 3.3 nA typical for full power mode and 1 nA

10 typical for low power mode. The following sections discuss the
different elements used to develop a thermocouple temperature
5
measurement system based on the AD7124-4/AD7124-8.
0
APPROXIMATELY Power Supplies
LINEAR REGION
The AD7124-4/AD7124-8 has separate analog and digital power
–5 supplies. The digital power supply, IOVDD, is independent of the
analog power supply and can be 1.65 V to 3.6 V referenced to
–10 DGND. The analog power supply, AVDD, is referred to AVSS and
13470-003
–300 –200 –100 0 100 200 300 400

TEMPERATURE (°C)
has a range of 2.7 V to 3.6 V for low power mode and mid power
Figure 3. T-Type Thermocouple Output Voltage vs. Temperature
mode, and 2.9 V to 3.6 V for full power mode. The circuit shown
in Figure 1 operates from a single supply; therefore, AVSS and
T-type thermocouples are formed by joining copper and DGND are connected together, and only one ground plane is
constantan metals. Other combinations of metals form other used. The AVDD and IOVDD voltages are generated separately
types of thermocouples with various ranges and sensitivities. using ADP1720 low dropout voltage regulators. The AVDD voltage
For instance, J-type thermocouples are made by joining iron is set to 3.3 V and the IOVDD voltage is set to 1.8 V using the
and constantan and have a range of 0°C to 760°C with a ADP1720 regulators. Using separate regulators ensures the
sensitivity of 55 μV/°C. K-type thermocouples are made by lowest noise.
joining chromel and alumel and have a range of −200°C to
+1260°C with a sensitivity of 39 μV/°C. Serial Peripheral Interface (SPI)
Cold Junction Compensation (CJC) SPI communication to the AD7124-4/AD7124-8 is handled by

the Blackfin® ADSP-BF527 on the EVAL-SDP-CB1Z board, as
The voltage generated by a thermocouple must be converted to shown in Figure 1. To access the registers of the AD7124-4/
temperature. Converting the voltage measured to an accurate AD7124-8, use the AD7124-4/AD7124-8 EVAL+ Software.
temperature can be difficult because the thermocouple voltage Figure 4 shows the main window of this software. Clicking
is small, the temperature-voltage relationship is nonlinear, and THERMOCOUPLE configures the software for a T-type
the cold junction temperature must also be accurately measured. thermocouple measurement.
The output voltage of the thermocouple represents the difference
between the temperature of the thermocouple and the cold
junction temperature. The cold junction temperature must be
known to ensure an accurate absolute temperature reading from
the thermocouple. The cold junction temperature is measured
with another temperature sensitive device, typically a thermistor,
diode, resistance temperature detector (RTD), or semiconductor
temperature sensor. The temperature-sensing device used for this
circuit is a 4-wire RTD. The cold junction measurement error
contributes directly to the absolute temperature error; therefore,
a high accuracy cold junction temperature measurement is
required. The technique of measuring and compensating for
the cold junction temperature is referred to as cold junction
13470-004
compensation, or CJC.
Figure 4. AD7124-4/AD7124-8 EVAL+ Software Configuration Screen
THERMOCOUPLE
The AD7124-4/AD7124-8 has diagnostic functions on-chip that CONNECTOR
AVDD
can be used to detect faults in the SPI communication. These 1kΩ
+ AIN2
T-TYPE
diagnostics include checks on the SPI read and write operations, THERMOCOUPLE 0.01µF
0.1µF
ensuring that only valid registers are accessed. An SCLK counter
1kΩ
ensures that the correct number of SCLK pulses are used, while – AIN3
0.01µF AD7124-4/
the CRC functionality checks for changes in bit values during AD7124-8
transmission. When any of these SPI communication diagnostic COLD IOUT1 (AIN1)
JUNCTION
functions are enabled and an associated error occurs, the 1kΩ
AIN6
corresponding flag is set in the error register. All enabled flags RTD Pt100 0.01µF
4-WIRE 0.1µF
are OR’ed together and control the ERR flag in the status register. CONFIGURATION
1kΩ
This functionality is particularly useful if the status bits are AIN7
0.01µF
appended to the ADC conversions.
Analog Inputs 1kΩ
REFIN1(+)
The AD7124-4 can be configured for 4 differential or 7 pseudo 5.11kΩ 0.01µF
0.1% 0.1µF
differential input channels, while the AD7124-8 can be configured ±15ppm/° C
REFIN1(–)
for 8 differential or 15 pseudo differential input channels. 1kΩ 0.01µF
REFERENCE AVSS
The AD7124-4/AD7124-8 has on-chip diagnostics that can be BUFFER 250Ω
13470-005
HEADROOM
used to check that the voltage level on the analog pins are
within the specified operating range. The positive (AINP) and
Figure 5. Analog Input Configuration for Thermocouple Measurement Using
negative (AINM) analog inputs can be separately checked for 4-Wire RTD for Cold Junction Compensation
overvoltages and undervoltages, as well as ADC saturation. An
overvoltage is flagged when the voltage on the analog input For this circuit, the cold junction circuit utilizes the reference input,
exceeds AVDD, while an undervoltage is flagged when the REFIN1(±). The current through the 4-wire RTD used for the
voltage on the analog input goes below AVSS. cold junction measurement also flows through the precision
reference resistor that generates the reference voltage. The voltage
For the circuit shown in Figure 1, two analog input pins are generated across this precision reference resistor is ratiometric
used to connect the thermocouple (AIN2, AIN3), and three to the voltage across the RTD; therefore, any variations seen in
analog pins are needed for the cold junction compensation the excitation current are removed. Because the reference buffers
(AIN1, AIN6, AIN7). AIN2 and AIN3 are configured as a fully are enabled, it is necessary to ensure that the headroom required
differential input channel and measure the voltage generated by for correct operation is met (AVDD − 0.1 V and AVSS + 0.1 V).
the thermocouple. For this circuit, the thermocouple is floating The headroom of 0.125 V (500 μA × 250 Ω) is provided by the
as shown in Figure 1. To bias the thermocouple to a known level, 250 Ω resistor to ground, as shown in Figure 5.
the VBIAS voltage generator is enabled on AIN2 and biases the
thermocouple to Digital and Analog Filtering
Differential (~800 Hz cutoff) and common-mode (~16 kHz
 AVDD  AVSS 
VBIAS  AVSS    cutoff) filters are implemented at the analog inputs as well as at
 2 
the reference inputs. This filtering is required to reject any
The thermocouple measurement is an absolute measurement; interference at the modulator frequency and also any multiples
therefore, a voltage reference is needed, and the AD7124-4/ of this frequency.
AD7124-8 internal 2.5 V reference is used.
The AD7124-4/AD7124-8 offers a great deal of on-chip digital
For the cold junction compensation, one excitation current filtering flexibility. There are several filter options available; the
source is used to excite the RTD. This current is generated from option selected has an effect on the output data rate, settling
AVDD and is directed to AIN1. The analog pins and their time, as well as 50 Hz and 60 Hz rejection. For this circuit note,
configuration are shown in greater detail in Figure 5. the sinc4 filter and the post filter are implemented. The sinc4
filter is used because it has excellent noise performance across
the range of output data rates, as well as excellent 50 Hz and
60 Hz rejection. The post filter is used to provide simultaneous
50 Hz and 60 Hz rejection with a 40 ms settling time.
Calibration The AD7124-4/AD7124-8 full system configuration for the
thermocouple measurement is as follows:
The AD7124-4/AD7124-8 provides different calibration modes
that can be used to eliminate offset and gain errors. For this  Thermocouple measurement (T-type)
circuit note, internal zero-scale calibration as well as internal o Differential input (AINP = AIN2, AINM = AIN3)
full-scale calibrations were used. o Gain = 128
Thermocouple Configuration o Internal 2.5 V reference
o Digital filtering (sinc4 and post filter)
The circuit shown in Figure 1 is designed for precision T-type
 Cold junction compensation measurement (4-wire RTD)
thermocouple measurement using the AD7124-4/AD7124-8.
o Differential input (AINP = AIN6, AINM = AIN7)
Thermocouple measurements require cold junction compensation.
o Excitation current: IOUT1 = AIN1= 500 μA
As shown in Figure 1, a 4-wire Pt100 RTD is used for this purpose.
o Gain = 16
Using the configuration shown in Figure 1, one precision excitation
o 5.11 kΩ precision reference resistor
current source is required to excite the RTD as part of the cold
o Digital filtering (sinc4 and post filter)
junction compensation measurement. The RTD is connected
to analog inputs AIN6, AIN7. The bottom side of the RTD is Thermocouple Temperature Calculation
connected to a precision reference resistor, which applies an Once the previous procedure is implemented, the next step is to
external reference voltage to the device. The precision reference work through the thermocouple and cold junction calculations.
resistor is connected between reference input pins REFIN1(±). Different approaches can be used for the linearization/
This configuration represents a ratiometric configuration, where compensation, which include
any deviation in the excitation current is seen by both the RTD
and the reference resistor, and is therefore removed from the  Look-up table: requires memory for storage, but also
measurement. provides a quick, accurate conversion.
 Software linear approximation: does not require storage
The thermocouple itself is connected to the AIN2, AIN3 analog except for the conversion polynomial coefficients. Requires
inputs. One of the inputs is biased using the internal bias voltage
processing time to solve the multiple order polynomial.
generator of the ADC. The thermocouple voltage is in the range
However, it also yields a very accurate result. This is the
of −8 mV to +17.2 mV, which represents a temperature range of
method used for this circuit.
−200°C to +400°C. This low level voltage is amplified by the on-
board PGA of the AD7124-4/AD7124-8, which is converted to The software linear approximation requires two inputs: the
a precision digital representation using the 24-bit Σ-Δ ADC. To voltage measured across the thermocouple, and the cold
ensure that the full range of the ADC is utilized, the PGA gain junction temperature.
is set to 128. This thermocouple measurement is made with The analog input channel (AIN2, AIN3) is used to measure the
respect to the internal low drift 2.5 V reference. voltage across the thermocouple. The formula used to convert
A 4-wire Pt100 Class B RTD is used for the cold junction the code representation to a voltage is Equation 1, which assumes
measurement. The excitation current for the Pt100 RTD is a bipolar configuration of the ADC. The AD7124-4/AD7124-8
programmed to 500 μA. software automatically converts the codes to a voltage based on
the configuration implemented.
The value of the external precision resistor is chosen so that the
maximum voltage generated across the RTD equals the reference (CODETC  2 N 1 )  VREF
VTC  (1)
voltage divided by the selected gain. The Circuit Note CN-0381 2 N 1  Gain
discusses in detail the following required steps:
where:
 Selecting a precision reference resistor VTC is the thermocouple (TC) voltage.
 Selecting an appropriate PGA gain for RTD measurement CODETC is the thermocouple (TC) code.
 Headroom resistor selection N is the resolution of ADC, 24.
 Excitation current output compliance VREF is the reference used for measurement. For this circuit, the
internal reference is used for the thermocouple measurement.
Gain is the chosen gain for TC mode, 128.
The 4-wire RTD used for the cold junction requires its own The thermoelectric voltage can then be used to calculate the
linearization. The general expression to calculate the RTD overall thermocouple temperature. This step involves a power
resistance (R) where the ADC is operating in bipolar mode is series polynomial given by Equation 4. For this circuit, a sixth-
given by order polynomial was used, where the T-type thermocouple
polynomial coefficients were taken from the NIST website.
(CODE  2N  1 )  RREF
RRTD  (2) T = a0 + a1V + a2V2 + a3V3 + … + anVn (4)
G  2N  1
where:
where:
V is the thermoelectric voltage (microvolts).
RRTD is the resistance of the RTD.
ax is the type dependent polynomial coefficient.
CODE is the ADC code.
T is the temperature (°C).
N is the resolution of ADC, 24.
n is the order of polynomial.
RREF is the reference resistor.
G is the selected gain, 16. Thermocouple Measurements and Results
The steps involved in converting the RTD voltage to a temperature For the circuit shown in Figure 1, data was gathered for
and the linearization are outlined in the Circuit Note CN-0381. different digital filter and power mode configurations of the
AD7124-4/AD7124-8.
The following steps are required to calculate the thermocouple
temperature: The first configuration was with the sinc4 filter, full power mode,
with an output data rate of 50 SPS. These conditions optimize
 Convert the cold junction temperature to a voltage the AD7124-4/AD7124-8 for best performance in relation to
 Calculate the thermoelectric voltage speed and noise. Figure 6 shows the noise distribution when
 Convert the thermoelectric voltage to a temperature a thermocouple is connected between the AIN2, AIN3 input
representation channel as shown in Figure 1 at ambient temperature. The
The cold junction temperature must be converted to a voltage. corresponding rms noise is typically 70 nV rms or approximately
The cold junction temperature is converted using a polynomial 16.4 noise free bits. The noise performance of the AD7124-4/
generated by National Institute of Standards and Technology AD7124-8 for inputs shorted under the same conditions is
(NIST) and is outlined in Equation 3. typically 48 nV rms or 17 noise free bits. The increase in the
noise comes directly from the thermocouple that is connected
VCJ = a0 + a1T + a2T2 + … + anTn (3) across the input channel (AIN2, AIN3).
where: 180
VCJ is the thermoelectric voltage. 1000 SAMPLES
160
ax is the thermocouple type dependent polynomial coefficient.
140
T is the cold junction temperature (°C).
n is the order of the polynomial. 120
OCCURRENCES
The cold junction temperature-to-voltage conversion accuracy can 100
be increased by increasing the order of the polynomial. However, 80

the higher the order, the more processing is required. Therefore,
60
a trade-off is required when carrying out this conversion. For the
calculations implemented for this circuit, an eighth-order 40
polynomial was used. 20

13470-006
The cold junction temperature voltage must be added to the 0

differential voltage measured across the thermocouple. The
8383705
8383724
8383744
8383763
8383782
8383801
8383821
8383840
8383859
8383879
8383898
8383917
8383936
8383956
8383975
8383994
resulting voltage is an approximation of the thermoelectric

voltage generated by the temperature sensing junction of the CODES
thermocouple. Figure 6. Histogram of Codes for Thermocouple at Ambient, Sinc4 Filter,
Full Power Mode, 50 SPS
120
For the thermocouple configuration where the sinc4 filter and full
1000 SAMPLES
power mode were selected, the temperature of the thermocouple
100
was swept from −50°C to +200°C, while the cold junction was held
at −40°C, +25°C, and +105°C. For each of the set thermocouple
80
temperatures, the corresponding voltage across the thermocouple
OCCURRENCES
was measured using the AD7124-4/AD7124-8 as previously
60
outlined. Also recorded was the cold junction temperature using
the 4-wire RTD. The voltage of the thermocouple along with the
40
voltage representation of the cold junction temperature were
used to calculate the temperature of the thermocouple. Figure 7
20
shows the resulting error measured between the set temperature
13470-008
value and measured temperatures of the thermocouple after
0
linearization, for cold junction temperatures of −40°C, +25°C,
8383171
8383220
8383269
8383317
8383366
8383415
8383464
8383512
8383561
8383610
8383659
and +105°C. Internal zero-scale and full-scale calibrations were
performed at each cold junction temperature. As shown in CODES
Figure 7, the error between the calculated and set temperature Figure 8. Histogram of Codes for Thermocouple and Cold Junction
of the thermocouple is well within the root sum square combined Temperature at Ambient, Post Filter, Low Power Mode, 25 SPS
error window of the T-type thermocouple and Pt100 RTD, as
For this AD7124-4/AD7124-8 configuration (with the post filter
shown in the plot. The T-type thermocouple has a maximum
and low power mode selected), the temperature of the RTD was
error of 1°C, or 0.75%, and from the IEC751 Standard, the
swept from −50°C to +200°C. For each of the set thermocouple
Pt100 error is ±(0.3 + 0.005 × |T|).
temperatures, the corresponding voltage across the thermocouple
3
COLD JUNCTION was measured using the AD7124-4/AD7124-8, as outlined
TEMPERATURE
T-TYPE + RTD previously. Also recorded was the cold junction temperature
2 –40ºC ERROR
+25ºC using the 4-wire RTD. The voltage of the thermocouple along
+105ºC with the voltage representation of the cold junction temperature
1
were used to calculate the temperature of the thermocouple.
ERROR (°C)
0 Figure 9 shows the resulting error between the set and measured
temperatures of the thermocouple after linearization for cold
–1 junction temperatures of −40°C, +25°C, and +105°C. As shown
in Figure 9, the error between the calculated and set temperature
–2 of the thermocouple is well within the root sum square combined
error window of the T-type thermocouple and Pt100 RTD, as
13470-007
–3 shown in the plot. The T-type thermocouple has a maximum

–50 0 50 100 150 200
error of 1°C or 0.75%, and the Pt100 error is ±(0.3 + 0.005 × |T|)
THERMOCOUPLE TEMPERATURE SET (°C)
from the IEC751 Standard.
Figure 7. Thermocouple Temperature Accuracy Measurement, Sinc4 Filter,
Full Power Mode, 50 SPS 3
COLD JUNCTION
TEMPERATURE
The second configuration tested was with the post filter, low 2
–40ºC T-TYPE + RTD
ERROR
power mode, and a 25 SPS output data rate that gives simultaneous +25ºC
+105ºC
50 Hz and 60 Hz rejection, allowing the user to trade off settling 1
time with rejection. Figure 8 shows the noise distribution when
ERROR (°C)
a thermocouple is connected between the AIN2, AIN3 input 0

channel as shown in Figure 1 at ambient temperature. The
corresponding rms noise is typically 220 nV rms equating to –1
approximately 14.7 noise free bits. The noise performance of the
AD7124-4/AD7124-8 for inputs shorted when the same filter, –2
gain, and output data rate are selected is typically 170 nV rms
13470-009
or 15.1 noise free bits. The increase in the noise comes directly –3
from the thermocouple that is connected across the input –50 0 50 100 150 200
THERMOCOUPLE TEMPERATURE SET (°C)
channel (AIN2, AIN3).
Figure 9. Thermocouple Temperature Accuracy Measurement, Post Filter,
THERMOCOUPLE
COMMON VARIATIONS CONNECTOR
AVDD IOVDD
1kΩ
Cold Junction Measurement Alternative T-TYPE + AIN2
THERMOCOUPLE 0.01µF REGCAPD
The EVAL–AD7124-4SDZ/EVAL-AD7124-8SDZ evaluation 0.1µF
1kΩ REGCAPA
boards have a thermistor on board as part of the overall board – AIN3
design. This thermistor is a KTY81/110 and has a typical resistance 0.01µF AD7124-4/
AD7124-8
of 1 kΩ at +25°C, 500 Ω at −40°C, and 1.7 kΩ at +105°C. The
COLD IOUT1 (AIN1)
thermistor can be used for measuring the cold junction JUNCTION
1kΩ
AIN6 DOUT/RDY
temperature. Thermistors are cheaper than 4-wire RTDs, but THERMISTOR 0.01µF DIN
are not as accurate. When implementing a thermistor for cold KTY81-110
1kΩ AT 25°C
0.1µF
1kΩ SCLK
junction measurements, care must be taken to ensure that the AIN7
CS
cold junction measurement works as expected. The following 0.01µF
SYNC
steps outline some decisions that need consideration:
1kΩ
REFIN1(+) CLK
1. Choose the precision reference resistor value. 2kΩ 0.01µF
2. Choose the appropriate gain. 0.1% 0.1µF
±15ppm/° C
3. Choose the excitation current. REFIN1(–)
1kΩ 0.01µF
4. Check the output voltage compliance range of the REFERENCE AVSS DGND
BUFFER 250Ω
excitation current.
13470-010
HEADROOM
5. Check the resistance value of the thermistor for the
different cold junction temperatures. Figure 10. Thermistor Cold Junction Configuration for Thermocouple
Measurements
Taking all of these steps into consideration, the settings for
implementing this thermistor when measuring the cold junction Using the setup configuration shown in Figure 10, the reference
temperature as part of the overall temperature measurement to the AD7124-4/AD7124-8 is always approximately 1 V based
system requires the following register configurations: on the 500 μA current and the 2 kΩ precision reference resistor.
The performance of the system when the thermistor is used for
 Thermocouple measurement settings as outlined cold junction compensation was recorded where the cold junction
previously (T-type) was held at 25°C, and the temperature of the thermocouple
o Differential input (AINP = AIN2, AINM = AIN3) swept from −50°C to +200°C. The sinc4 filter in full power mode
o Gain = 128 and the post filter in low power mode were used. Figure 11 shows
o Internal 2.5 V reference the worst-case error recorded between the set temperature of
o Digital filtering (sinc4 and post filter) the thermocouple, and the calculated temperature using the
 Cold junction compensation measurement (thermistor) linearization technique for both filter types and power modes.
o Differential input (AINP = AIN4, AINM = AIN5) The worst case error recorded was ±1°C.
o Excitation current: IOUT0 = AIN1 = 500 μA 3
o Gain = 1 FULL POWER, SINC4 FILTER
T-TYPE + RTD
LOW POWER, POST FILTER ERROR
o 2 kΩ precision reference resistor (the thermistor 2
resistance varies from 500 Ω at −40°C to 1.7 kΩ at
+105°C; it is also required to evaluate the headroom 1
with this resistance)
ERROR (°C)
–1
–2
13470-011
–3
–50 0 50 100 150 200
THERMOCOUPLE TEMPERATURE (°C)
Figure 11. Thermocouple Temperature Accuracy Measurement Using

Thermistor for Cold Junction Compensation at 25°C
THERMOCOUPLE
Bias Voltage CONNECTOR
AVDD IOVDD
1kΩ
In Figure 1, the internal VBIAS voltage is supplied to the + AIN0
T-TYPE
REGCAPD
thermocouple via the AINP or AINM pins. This configuration THERMOCOUPLE 0.01µF
0.1µF
REGCAPA
for the VBIAS voltage works well when the anti-alias filters are 1kΩ
– AIN1 (IOUT0)
implemented using the component values shown in Figure 1. If 0.01µF
filters with very large R and C values are used (for example, for THERMOCOUPLE AD7124-8
EMC filtering), VBIAS must be taken from a separate dedicated CONNECTOR
1kΩ
pin and then applied externally to the thermocouple. This T-TYPE + AIN2
THERMOCOUPLE 0.01µF
removes any inaccuracies in the measurements caused by 0.1µF
potential common-mode noise that can be converted to –
1kΩ
AIN3
differential-mode noise. 0.01µF
THERMOCOUPLE
Multiple Thermocouple Measurement System CONNECTOR DOUT/RDY
1kΩ
The AD7124-4 and AD7124-8 can be used for multiple T-TYPE
+ AIN4 DIN
thermocouple measurements. Thermocouple measurements THERMOCOUPLE 0.01µF SCLK

0.1µF
CS
require –
1kΩ
AIN5
SYNC
0.01µF
 Two analog pins configured differentially to measure the
voltage across the thermocouple THERMOCOUPLE CLK
CONNECTOR
 Two analog pins configured differentially to measure the 1kΩ
T-TYPE + AIN6
voltage at the cold junction terminal THERMOCOUPLE 0.01µF
0.1µF
 One single analog pin to steer the excitation current to the 1kΩ
– AIN7
cold junction compensation circuitry 0.01µF
THERMOCOUPLE
Using this information, the AD7124-4 allows two thermocouples CONNECTOR
to be connected and measured with respect to the same cold 1kΩ
+ AIN8
T-TYPE
junction, as shown in Figure 12. The AD7124-8 allows up to six THERMOCOUPLE 0.01µF
0.1µF
different thermocouple measurements with respect to the same 1kΩ
– AIN9
cold junction, as shown in Figure 13.
0.01µF
THERMOCOUPLE
CONNECTOR THERMOCOUPLE
AVDD IOVDD CONNECTOR
1kΩ
+ AIN0 1kΩ
T-TYPE
THERMOCOUPLE 0.01µF REGCAPD + AIN10
T-TYPE
0.1µF THERMOCOUPLE 0.01µF
REGCAPA
1kΩ 0.1µF
– AIN1 (IOUT0) 1kΩ
0.01µF – AIN11
AD7124-4 0.01µF
THERMOCOUPLE
CONNECTOR
COLD IOUT0 (AIN12)
1kΩ JUNCTION
+ AIN2 1kΩ
T-TYPE AIN13
THERMOCOUPLE 0.01µF
0.1µF THERMISTOR 0.01µF
KTY81-110 0.1µF
1kΩ DOUT/RDY 1kΩ AT 25°C
– AIN3 1kΩ
0.01µF AIN14
DIN
0.01µF
SCLK
COLD IOUT0 (AIN4)
JUNCTION CS
1kΩ 1kΩ
AIN5 SYNC REFIN1(+)
THERMISTOR 0.01µF 2kΩ 0.01µF
KTY81-110 0.1µF 0.1% 0.1µF
1kΩ AT 25°C CLK ±15ppm/° C
1kΩ
AIN6 REFIN1(–)
0.01µF 1kΩ 0.01µF
REFERENCE AVSS DGND
BUFFER 250Ω
13470-013
HEADROOM
1kΩ
REFIN1(+)
2kΩ 0.01µF
0.1% 0.1µF Figure 13. AD7124-8—Six Thermocouple Measurement System
±15ppm/° C
REFIN1(–)
Including Cold Junction Compensation
1kΩ 0.01µF
REFERENCE AVSS DGND
BUFFER 250Ω
13470-012
HEADROOM
Figure 12. AD7124-4—Two Thermocouple Measurement System

Including Cold Junction Compensation
CIRCUIT EVALUATION AND TEST The EVAL–AD7124-4SDZ/ EVAL-AD7124-8SDZ evaluation
Equipment Needed board is needed to test the circuit. In addition, the following
sensor and resistors are required for proper operation:
The following equipment is required for the thermocouple
measurement system:  T-type thermocouple
 2 kΩ precision resistor
 EVAL–AD7124-4SDZ/EVAL-AD7124-8SDZ evaluation
 250 Ω resistor needed for buffer headroom
board
 EVAL-SDP-CB1Z System Demonstration Platform (SDP) Configuring the Hardware
 AD7124-4/AD7124-8 EVAL+ Software To configure the hardware, do the following:
 Power supply: 7 V or 9V wall wart
 Set all links on the EVAL-AD7124-4SDZ/EVAL-AD7124-
 T-type thermocouple
8SDZ to the default board positions as outlined in the
 A PC running Windows® XP (SP2), Windows Vista, or
evaluation board user guide.
Windows 7 (32-bit or 64-bit)
 Power the board with a 7 V or 9 V power source connected
Software Installation to J5.
A complete software user guide for the EVAL–AD7124-4SDZ/  Connect the thermocouple, precision reference resistor,
EVAL-AD7124-8SDZ and SDP boards can be found in the and resistor for headroom as shown in Figure 15.
EVAL–AD7124-4SDZ/EVAL-AD7124-8SDZ user guide and
TERMINAL BLOCK
the SDP User Guide, respectively. J6
500µA
Software is required to interface with the hardware, and can be AIN0
downloaded from ftp://ftp.analog.com/pub/evalcd/AD7124 . If

IOUT0 (AIN1)
the setup file does not automatically run, double-click setup.exe
EVAL-AD7124-4SDZ/
from the file. Install the evaluation software before connecting AIN2
EVAL-AD7124-8SDZ
the evaluation board and SDP board to the USB port of the PC EVALUATION BOARD
AIN3
to ensure that the evaluation system is correctly recognized
when connected to the PC. AIN4
After the evaluation software installation is complete, connect the

AIN5
SDP board (via Connector A) to the evaluation board, and then
connect the evaluation board to the USB port of the PC using the REFIN(+)
supplied cable. When the evaluation system is detected, proceed RREF
through any dialog boxes that appear to complete the installation. 5.11kΩ REFIN(–)
Setup and Test RHEADROOM

250Ω TERMINAL BLOCK
Figure 14 shows the functional block diagram of the test setup. To J11
allow quick setup for thermocouple measurements, the on-board AGND

thermistor is used to implement the cold junction measurements. PSW
7V TO 9V SUPPLY PC COLD
260mA LIMIT – JUNCTION
T-TYPE
THERMOCOUPLE R28
500µA USB THERMISTOR
AIN4
J4/J5 +
AIN5
THERMOCOUPLE
J6 120 CONNECTOR
REFIN1(+) J1 CON A
13470-015
A2
REFERENCE REFIN1(–)
AND
HEADROOM Figure 15. Evaluation Board Connector for Thermocouple Measurement
RESISTORS
AGND J11 EVAL-SDP-CB1Z
THERMISTOR
TC AIN2 +
COMNNECTION ANI3 A2
– EVAL-AD7124-4SDZ/
EVAL-AD7124-8SDZ
13369-014
Configuring the Software  IO_CONTROL_1 (excitation for RTD)
Run the AD7124-4/AD7124-8 EVAL+ Software. Figure 16 o IOUT1 Channel Enable = AIN1
shows a screenshot of the main window of the software. o IOUT1 Select = 500 μA
 IO_CONTROL_2 (biasing the thermocouple)
o VBIAS2 = True
is configured for thermocouple measurements: an internal full-
scale and zero-scale calibration of the AD7124-4/AD7124-8 is
required for the thermocouple channel. This can be performed
via the Register Map tab, as shown in Figure 17.
1. From the register tree, select the ADC_Control register.
2. Enable Channel 0 only.
3. Select low power mode.
4. Carry out an internal full-scale calibration.
b. Select internal full-scale calibration.
13470-016 c. Check that the calibration has been performed by
Figure 16. AD7124-4/AD7124-8 EVAL+ Software Main Window selecting the Gain0 register from the register tree, and
check that the coefficients have changed.
To configure the AD7124-4/AD7124-8 for thermocouple
5. Carry out an internal zero-scale calibration.
measurements, click the THERMOCOUPLE demo mode button
in the main window, as shown in Figure 16. Clicking this button
b. Select internal zero-scale calibration.
configures the ADC software for optimized performance. Some
c. Check that the calibration has been performed by
of the register settings are as follows:
selecting the Offset0 register in the register tree, and
 Channel_0 (thermocouple) check that the coefficients have changed.
o AINP_0 = AIN2
o AINM_0 = AIN3
o Setup = Setup0
o Enabled = TRUE
 Channel_1 (thermistor cold junction measurement)
o AINP_1 = AIN4
o AINM_0 = AIN5
o Setup = Setup1
o Enabled = TRUE
 CONFIG_0 (thermocouple)
o PGA_0 = 128
o BIPOLAR = ENABLED
o REF_SEL = Internal Reference
13470-017
 CONFIG_1 (thermistor cold junction measurement)
o PGA_0 = 1 Figure 17. Register Map Internal Full-Scale and Zero-Scale Calibration
A calibration is not required for the thermistor channel because
o BIPOLAR = ENABLED
the gain error at a gain of 1 is factory calibrated.
o REF_SEL = External Reference
 FILTER_0 (thermocouple) The board and device are now configured for thermocouple
o Filter = Sinc4 measurements, which includes cold junction compensation
o FS_0 = 384 measurement using the thermistor positioned on the evaluation
 FILTER_1 (thermistor cold junction) board. Click SAMPLE to start gathering samples from the
o Filter = Sinc4 AD7124-4/AD7124-8. The Waveform tab and the Histogram
o FS_0 = 384 tab show the data gathered from the AD7124-4/AD7124-8.
 ADC_Control For more accurate cold junction measurements, a 4-wire RTD can
o MODE = Continuous Conversion be connected, as outlined in the previous sections. To use a 4-wire
o POWER_MODE = FULL POWER RTD, the current from AIN1 must be disconnected from the
o REF_EN = Enabled thermistor and connected to the 4-wire RTD, as shown in Figure 1.
SDP User Guide System Demonstration Platform (EVAL-SDP-CB1Z)
AN-892 Application Note. Temperature Measurement Theory ADP1720 Data Sheet
and Practical Techniques. Analog Devices.
REVISION HISTORY
Mary McCarthy. AN-615 Application Note. Peak-to-Peak
CN-0376 Circuit Note. Channel-to-Channel Isolated
CN-0381 Circuit Note. Completely Integrated 4-Wire RTD
CN-0382 Circuit Note. Isolated 4 mA to 20 mA/HART Temperature
and Pressure Industrial Transmitter Using a Low Power, Precision,
24-Bit Sigma-Delta ADC. Analog Devices.
CN-0383 Circuit Note. Completely Integrated 3-Wire RTD
property by application or use of the Circuits from the Lab reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab
reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability,
noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that
may result from their use. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so.

CN13470-0-7/15(0)
Circuit Note
CN-0387
Fast Responding, 45 dB Range, 0.5 GHz to
Circuits from the Lab® reference designs are engineered and ADL6010
43.5 GHz Envelope Detector
analog, mixed-signal, and RF design challenges. For more 1 MSPS, Ultralow Power, 12-Bit ADC in
AD7091R
information and/or support, visit www.analog.com/CN0387. 10-Lead LFCSP and MSOP
GaAs MMIC, SPDT, Nonreflective Switch,
HMC547
DC to 28 GHz
Calibration-Free Return Loss Measurement System

EVALUATION AND DESIGN SUPPORT The design is implemented on a single circuit board using a
Circuit Evaluation Boards nonreflective RF switch; a microwave RF detector; and a 12-bit,
CN-0387 Return Loss Measurement Evaluation Board precision analog-to-digital converter (ADC). To evaluate the
(EV-VSWR-SDZ) circuit over the widest possible frequency range, a dual-port
System Demonstration Platform (EVAL-SDP-CB1Z) directional coupler with SMA connectors was used instead of a
Design and Integration Files narrow-band, surface-mount directional coupler.
Schematics, Layout Files, Bill of Materials The circuit measures return loss of up to 20 dB over an input
power range of 25 dB (return losses in excess of 20 dB can be
measured over a smaller input power range).
The circuit shown in Figure 1 accurately measures return loss in
A unique feature of the circuit is that it calculates return loss
a wireless transmitter from 1 GHz to 28 GHz without any need
using a simple ratio of the digitized voltages from the RF
for system calibration.
detector, thereby eliminating the need for system calibration.
RF POWER
AMPLIFIER BIDIRECTIONAL COUPLER
MARKI MICROWAVE C10-0226 LOAD/ANTENNA
EVALUATION BOARD
–5V
VNEG
HMC547 74LV04AD GPIO OUTPUT

RF SWITCH CONTROL LOGIC NEGATIVE LOGIC
50Ω 50Ω INPUTS INVERTER CIRCUIT
+5V
VPOS
3 +5V
ADL6010 GND
VIN POWER DETECTOR AVDD
RFCM
4
VOUT
RFIN SDP INTERFACE
200Ω AD7091R SPI BOARD PC
5 LINEARIZER 2
12-BIT ADC
RFCM
6 340Ω
1
COMM
13680-001
GND GND GND
Figure 1. Voltage Standing Wave Ratio (VSWR) Evaluation Board Measurement Setup (All Connections and Decoupling Not Shown)
Rev. A
of each circuit, and their function and performance have been tested and verified in a lab environment at
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause Tel: 781.329.4700 www.analog.com
CIRCUIT DESCRIPTION Then converting to dBm,
An RF signal between 1 GHz and 28 GHz is fed through an RF   VOUT − c 
2

coupler (Marki Microwave C10-0226) to a matched 50 Ω load    
 m  
or antenna as shown in Figure 1. The forward and reverse PIN dBm = 10 × log 1000 ×   (4)
 R 
coupled ports are connected to the HMC547, a single-  
pole/double-throw (SPDT) nonreflective switch. The switch  
input is toggled between the forward and reverse coupled ports, If the ADC is included, the equation becomes
while terminating the opposite port in 50 Ω, so that both
coupled ports always see a 50 Ω load.   CODE − c ' 
2

   
 m' 
The output port of the RF switch drives the ADL6010, a PIN dBm = 10 × log 1000 ×  
 (5)
microwave RF detector that can operate from 500 MHz to  R 
43.5 GHz. The output voltage level of the detector is directly  
 
proportional to the amplitude of the input signal. The ADL6010
is a linear-in-V/V detector, having a nominal slope of 2.1 V/V. where:
m’ is the slope of the detector and ADC combined signal chain.
The AD7091R 12-bit ADC samples the power detector output c’ is the intercept of the detector and ADC combined signal chain.
voltage at a rate of 1 MSPS. (Lower sampling rates can also be
used, resulting in lower power consumption in the ADC). The return loss is the difference between the forward and
reverse power in dBm:
The AD7091R converts the analog voltage to a digital code. The
EVAL-SDP-CB1Z (SDP-B) interface board then uses serial   CODE F − c '  
2
  
peripheral interface (SPI) communications to control the ADC   m'  
and sends results to a PC for system evaluation and return loss  1000 × 
PFdBm − PRdBm = 10 × log  R  (6)
calculation. The VSWR, return loss, and reflection coefficient   CODE R − c '  
2
are then calculated using the ratio between the forward and    
 1000 ×  m'  
reverse coupled voltages sampled by the ADC. 
 R 
Return Loss Calculation
 (CODE F − c ' ) 2 
The following derivation shows the relationship between the ⇒ PFdBm − PR = 10 × log   (7)
dBm  (CODE − c ' ) 2 
ratio of forward and reverse voltages and the return loss of the  R 
system. This relationship is fundamental to the calibration-free Because c’ is close to zero, and because CODEF and CODER are
nature of the system. generally much greater than c’, the formula reduces to
The system transfer function of the detector in its linear
 CODEF 2 
operating region can be expressed using the familiar straight- PFdBm − PR = 10 × log  
2 
(8)
 CODER 
dBm
line equation,
y = mx + c The derivation in this section shows that return loss can be
where: calculated without the need for calibration, because the formula
m is the slope. does not include the slope (m’) or intercept (c’) of the signal
c is the intercept. chain.
Using actual circuit parameters, RF Switch

The HMC547 is a nonreflective SPDT RF switch with a frequency
VOUT = m × VIN + c (1)
range of dc to up to 28 GHz. As shown in the Figure 2 block
As noted previously, m is nominally 2.1, but can vary with diagram, the switch internally terminates either input at 50 Ω,
frequency and from device to device. The value of c is typically while the other input is fed to the RFC output. The switch has a
close to zero. fast switching time of typically 6 ns. The A and B logic inputs of
Rewriting Equation 1 in terms of VIN, this switch are controlled by negative voltage logic of −5 V high
and 0 V low. A recommended control circuit is included in the
VOUT − c
⇒ VIN = (2) HMC547 data sheet. The circuit consists of a 5.1 V Zener diode
m level shifter that drives 74LV04AD inverters. The inverters are
Converting this equation to power, powered between −5 V and 0 V, rather than 0 V and +5 V. The
2 complete power supply circuit is shown in the detailed schematic
V − c 
  contained in the CN-0387 Design Support Package, available at
m 
⇒ PIN =  (3) www.analog.com/CN0387-DesignSupport.
R
N/C GND RF2 GND
Analog-to-Digital Converter
16 15 14 13
VDD 1 10 VDRIVE
HMC547
REFIN/REFOUT 2 9 SDO
N/C 1 12 N/C
AD7091R
VIN 3 TOP VIEW 8 SCLK
(Not to Scale)
50Ω REGCAP 4 7 CS
GND 2 11 A
GND 5 6 CONVST
RFC 3 10 B NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
13680-005
50Ω FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED
GND 4 9 N/C
PAD TO THE SUBSTRATE, GND.
Figure 5. AD7091R Analog-to- Digital Converter

5 6 7 8
PACKAGE The AD7091R is a 12-bit successive approximation register
13680-002
N/C GND RF1 GND BASE
GND
(SAR) ADC, which has a throughput rate of up to 1 MSPS.
Figure 2. HMC 547 Top View
Although a highly accurate external reference voltage can be
used, it is not required in this application. In this circuit, the
Power Detector internal reference of 2.5 V is used, which yields an LSB size of
The ADL6010 power detector has a linear-in-V/V characteristic, LSB = (2.5 V)/212 = 610 µV
which is key to this application. To power this device, apply a
+5 V dc voltage to the VPOS pin and round to the COMM pin, Because the output voltage of the ADL6010 can reach a
as shown in Figure 3. maximum voltage of approximately 3 V, it is necessary to
attenuate this voltage using a 200 Ω/340 Ω resistor divider
ADL6010 between the detector and the ADC, as shown in Figure 1. This
RFCM 4 3 VPOS divider provides a nominal attenuation of 1.6.
RFIN 5 LINEARIZER 2 VOUT

Directional Coupler
A directional coupler couples a portion of the forward or
RFCM 6 1 COMM
13680-003
reverse signals to the power detector for measurement. In

general, couplers have 4 ports as shown in Figure 6.
Figure 3. ADL6010 RF/Microwave Detector Functional Diagram
1 2
INPUT OUTPUT
As shown in Figure 4, the output voltage varies with frequency. SIGNAL
RF DIRECTIONAL COUPLER
SIGNAL
This variation in transfer function vs. frequency does not
degrade the performance of the circuit in any way because the 4 3
return loss calculation relies on a ratiometric calculation at a 50Ω TERMINATED PORT/

ISOLATED PORT
specific frequency.
13680-006
COUPLED
10 OUTPUT PORT
Figure 6. Directional Coupler
In the Figure 6 configuration, the input signal is coupled to

1
Port 4, and Port 3 is terminated at 50 Ω for nonreflective
OUTPUT VOLTAGE (V)
0.5GHz
coupling of the signal. If Port 4 is terminated in 50 Ω instead of
1.0GHz Port 3, the reflected signal is coupled to Port 3.
0.1 5.0GHz
10.0GHz
15.0GHz In this circuit, instead of using the 50 Ω termination connected
20.0GHz
25.0GHz
directly to the port as shown previously, both ports are fed to
0.01 30.0GHz the RF switch inputs. Therefore, the coupler can be regarded as
35.0GHz
40.0GHz being bidirectional, because the 50 Ω termination is applied by
43.5GHz
the HCM547 internally to Port 3 or Port 4, depending on the
13680-004
0.001 state of the switch.

–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20
PIN (dBm) The RF coupler chosen for this circuit was the Marki Microwave
Figure 4. Transfer Function at Frequencies from 500 MHz to 43.5 GHz
C10-0226 stripline coupler. This coupler has 10 dB coupling,
meaning that the coupled signal is 10 dB less than the input
signal. A directional coupler with SMA connectors was used in
this circuit to demonstrate operation over the widest possible
frequency range. A surface-mount coupler can also be used;
however, such devices generally have a narrower frequency range.
Data Analysis When the RF switch receives the signal to toggle the switch, the
The EVAL-SDP-CB1Z system demonstration platform (SDP) switch position changes, and the forward or reverse coupled
board is used in conjunction with evaluation software, to port signal is fed to the power detector. In the return loss
capture the data being sampled by the ADC. calculation step, 500 forward samples and 500 reverse samples
are averaged, and the return loss is calculated from the ratio of
The software calculates the return loss using Equation 8, which
averaged forward and reverse voltages.
was derived previously. The reflection coefficient and VSWR
are derived from this equation. The ADC samples at a rate of 1 MSPS. Therefore, it takes 500 µs
to measure 500 samples. Toggling the switch position using a
 CODEF 2  general-purpose input/output (GPIO) of the SDP-B interface
PFdBm − PR = 10 × log  
2 
(8)
 CODER  takes approximately 400 µs between forward and reverse cycles.
dBm
The timing diagram is shown in Figure 9.

Figure 7 shows the result display panel of the software GUI.
500µs 400µs 500µs 750µs
500 SAMPLES 500 SAMPLES REPEAT
13680-009
FORWARD TOGGLE REVERSE MEAN
SAMPLING SWITCH SAMPLING CALCULATION
Figure 9. Timing Diagram Representation
The return loss, reflection coefficient, and VSWR are calculated

using the resultant average of forward and reverse voltage
measurements. To allow results to be clearly read before
updating, 50 sample results are averaged before displaying on
the GUI results panel.
Complete documentation for the EVAL-VSWR-SDZ board,
including schematics, layouts, Gerber files, and bill of materials, is
available for download in the CN-0387 Design Support Package
13680-007
at www.analog.com/CN0387-DesignSupport.
Figure 7. CN-0387 Evaluation Software Display
COMMON VARIATIONS
Detector Sampling Strategy
As previously noted, a wideband connectorized directional
To accurately measure the return loss of the system, the forward coupler was used in this circuit to enable operation over the
and reverse voltages must be measured with a short time delay widest possible frequency range. Surface-mount directional
between the forward and reverse measurements. Figure 8 shows couplers or printed circuit directional couplers can also be used;
the sampling sequence performed when sampling continuously. however, these devices tend to have narrower frequency ranges.
Directional couplers with higher coupling factors can also be
used, which tend to have lower insertion loss. However, it is
TOGGLE SWITCH
recommended that the circuit be dimensioned to maximize
measurement range. For example, if the maximum system
MEASURE power is +35 dBm, using a 20 dB directional coupler sets the
500 FORWARD SAMPLES
maximum power to the detector at approximately +15 dBm,
which is at the upper limit of the input range.
TOGGLE SWITCH
MEASURE
500 REVERSE SAMPLES
CALCULATE
RETURN LOSS
13680-008
Figure 8. Sampling Sequence
CIRCUIT EVALUATION AND TEST 2. Connect the input and output coupled ports of the RF
Equipment Needed coupler to the RF1 and RF2 3.5 mm SMA connections of the
evaluation board, respectively, using suitably rated RF cables.
The following equipment is needed to perform the evaluations
3. Connect the coupler input port to the 50 Ω output of the
described in this circuit note:
signal generator.
• The EV-VSWR-SDZ evaluation board. 4. Connect the output of the coupler to a 50 Ω termination or
• A suitably rated broadband RF Coupler. For this a suitably rated RF attenuator termination.
evaluation, the Marki Microwave C10-0226 was used. 5. Connect the EVAL-SDP-CB1Z SDP interface board to the
However, any coupler with suitable specifications and with EV-VSWR-SDZ evaluation board.
a 3.5 mm SMA type connector can be used. 6. Connect the SDP interface board to a PC via the USB cable
• The EVAL-SDP-CB1Z SDP-B board. provided.
• A signal generator (with output frequency within the range 7. Connect the power supply from the dc supply to the power
of 500 MHz to 28 GHz). and ground of the banana sockets of the evaluation board.
• A suitable power supply unit with 6 V dc output voltage. 8. Download and install the CN-0387 Evaluation Software
• The CN-0387 Evaluation Software, which can be onto the PC that is connected to the SDP-B control board.
downloaded from ftp://ftp.analog.com/pub/cftl/CN0387/. 9. After the software is installed properly, run the executable.
• An SMA attenuator and 50 Ω termination. 10. Set the output frequency of the signal generator to 2 GHz
and set the power level to 15 dBm output. Then turn on the
• A PC running Windows® 7 connected to the SDP-B board
output of the signal generator.
via a USB cable (supplied with the EVAL-SDP-CB1Z).
11. In the software display, select Continuous, and then click
Setup and Test Capture. The software continuously repeats measurements;
To set up and test the VSWR measurement system, set LK6 in when each measurement is gathered, the GUI display updates
Position B and put LK22 in place, and then take the following with the value of the return loss and the corresponding values
steps: of VSWR and reflection coefficient.
1. Turn on all test equipment and wait until all equipment Functional Block Diagram of Test Setup
boots up. Figure 10 shows the functional block diagram of the test setup.
6V POWER SUPPLY UNIT
SIGNAL
GENERATOR
BIDIRECTIONAL
COUPLER
EVAL-SDP-CB1Z
EV-VSWR-SDZ
13680-010
PC
Figure 10. Functional Block Diagram of Test Setup
Test Results Power Detector Measured Power
20
Measurements were gathered manually by adjusting the RF input
power levels. Return loss in different output configurations was 15
measured over the power range of the ADL6010. 10
RF simulations were also run using the Keysight Advanced 5
Design System (ADS). This software is an electronic design 0
POUT (dBm)
simulation tool for RF and microwave applications. Simulations –5
were performed to verify that RF input trace insertion loss and
–10
reflection were within certain limits and to simulate the
–15
performance of the directional coupler.
–20
The Marki Microwave C10-0226 directional coupler was
–25
13680-012
provided with a simulation model file, an .s4p file. This file
contains information that describes the S-parameters of the –30
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20
coupler and can be readily used in ADS within a simulation. PIN (dBm)
Simulations were performed over a frequency range from dc up
Figure 12. Input Power vs. Measured Coupled Output Power
to the upper frequency limit of the coupler of 26.5 GHz, and the
input power was set to 0 dBm for each simulation. Figure 12 shows how the measured power changes with input
Return Loss Measurement power. A calibration routine was performed at 2 GHz to obtain
accurate power measurement at the forward coupled port, at
While testing the EV-VSWR-SDZ evaluation board, a 9 dB each power level. As the input power rises, the measured power
attenuator termination was connected to the coupler output to reaches the detector limit of 15 dBm. Similarly, as input power
verify that the expected attenuation levels were measured at a is reduced, the lower limit of the detector is reached and
chosen frequency as compared to the simulated results. measurement accuracy reduces.
25
Open Circuit Configuration
0
20
MEASURED RETURN LOSS (dB)
–5
15 –10
–15
POWER (dBm)
FORWARD POWER
10 REVERSE POWER
–20
–25
5
–30
13680-011
0 –35
13680-013
0
5
–5
10
15
20
25
30
35
–30
–25
–20
–15
–10
–40
FORWARD POWER (dBm)
0 5 10 15 20 25 30
Figure 11. Return Loss Measurement FREQUENCY (GHz)
Figure 13. Coupler Forward and Reverse Power vs. Frequency—Open Circuit
As shown in Figure 11, within the input power range of 0 dBm
to 25 dBm, the return loss measured remains nearly constant at Figure 13 shows that the return loss is close to 0 dB as forward
20 dB. This value is the summation of the forward and reverse and reverse power levels are close in value, compared to the
attenuations as previously outlined (9 dB + 9 dB), and the forward previous 50 Ω termination case.
insertion loss of the coupler at 2 GHz using the Marki Microwave This open-circuit simulation shows how the majority of the signal
C10-0226. After the input power at the forward coupled port is reflected back through the coupler in the opposite direction
reaches approximately 27 dBm, the return loss reduces significantly. to the forward wave. The difference in amplitude between the
This reduction occurs because the coupled power at the forward forward and reflected waves is a result of the insertion loss of
coupled port is close to +15 dBm (with 10 dB coupling), which the coupler across the frequency range. This graph highlights
is the upper power limit of the ADL6010. As input power is that exact return loss and VSWR measurements vary with the
reduced, the measured return loss begins to reduce due to the coupler used, due to non-ideal coupler impedance matching
reflected power at the reverse coupled port dropping below the across frequency.
lower limit of −30 dBm. Figure 11 illustrates the power range
over which the ADL6010 can operate to measure a return loss
of 20 dB.
–3dB
Additionally, a threshold return loss can be set to indicate ATTENUATOR
whether there is a mismatch occurring in the system, which is –3dB
FORWARD
much greater than the coupler return loss. 2
INPUT
50 Ω Output Termination Circuit Configuration SIGNAL
0 –3dB
REFLECTED
–10
13680-016
–20 RETURN LOSS
–6dB
POWER (dBm)
–30 Figure 16. Coupler with 6 dB Attenuation
–40 The 6 dB attenuation is due to the 3 dB coupler attenuating both

FORWARD POWER the incident signal and reflected signal by 3 dB. As shown in
REVERSE POWER
–50 Figure 16, the signal first attenuates by 3 dB in the forward
direction before being reflected and attenuated by a further
–60
3 dB. The measured reflected signal is the result of the
13680-014 accumulated forward and reverse attenuations.
–70
0 5 10 15 20 25
FREQUENCY (GHz)
Calibration Structure Trace Insertion Loss
Figure 14. Coupler Forward and Reverse Power vs. Frequency—50 Ω Termination The RF trace insertion loss was simulated using the layout file
of the EV-VSWR-SDZ evaluation board. This layout file was
Figure 14 shows the Marki Microwave C10-0226 RF coupler
imported into the ADS tool to run a simulation, to determine
forward insertion loss and reflected signal for a 50 Ω terminated
the losses of the RF traces on the board.
output with a 0 dBm power level applied to the forward port of
RF1
the coupler. The coupler is specified to operate from 2 GHz to CALIBRATION STRUCTURE
26.5 GHz. Therefore, the coupler begins to operate as expected

beyond 2 GHz in Figure 14. The simulation uses an ideally
matched transmission line of 50 Ω output impedance on the
coupler. The return loss at any frequency is the difference
between the forward and reverse power. The graph shows that
return loss varies with frequency. However, within this frequency
a
range, the return loss is close to 20 dB, which is acceptable
because return loss values greater than 20 dB are taken to be
2a
negligible.
3 dB Output Attenuator Circuit Configuration a
0
–5
–10
POWER LOSS (dBm)
–15
–20 13680-017
FORWARD POWER RF2
REVERSE POWER
–25 Figure 17. Calibration Structure
–30 The calibration structure shown in Figure 17 on the board

section was used in the simulation. This structure was included
–35
in the board design to measure the losses from the SMA
13680-015
–40 connector to the switch (Distance A). As shown, the length of

0 5 10 15 20 25 30
the calibration structure is exactly twice the distance from
FREQUENCY (GHz)
RF1/RF2 to the HMC547 switch (U10). To measure these RF
Figure 15. Coupler Forward and Reverse Power vs. Frequency—3 dB Attenuator
trace losses at a particular frequency, the signal is applied to one
In Figure 15, the return loss is relatively stable at 6 dB until up of the calibration structure connectors and is then measured on
to approximately 15 GHz, after which the loss of the coupler the opposite connector.
increases and the attenuation increases.
The ADS simulation tool was run on this structure from dc to
26.5 GHz to simulate the insertion loss of the RF traces.
0
As shown in Figure 18, the insertion loss of the calibration
–0.1 structure reaches a maximum attenuation of approximately
–0.2 −0.4 dB at a frequency of 26.5 GHz.
–0.3 This insertion loss is considered to be within the acceptable
–0.4 limits for the evaluation board. If this insertion loss is
LOSS (dB)
–0.5
significant, it limits the range of measurement.
–0.6 A photograph of the EV-VSWR-SDZ board connected to the
–0.7
EVAL-SDP-CB1Z board is shown in Figure 19.
–0.8 An electrically equivalent replacement part for the HMC547LC3
will be available in June 2016.
–0.9
13680-018
–1.0
0 5 10 15 20 25 30
FREQUENCY (GHz)
Figure 18. Calibration Structure Loss—Frequency vs. Power
13680-019
Figure 19. EV-VSWR-SDZ Board Connected to EVAL-SDP-CB1Z Board
CN-0387 Design Support Package: HMC547LC3 Data Sheet and Evaluation Board
www.analog.com/CN0387-DesignSupport ADL6010 Data Sheet and Evaluation Board
EVAl-SDP-CB1Z System Demonstration Platform User Guide AD7091R Data Sheet and Evaluation Board
(UG-277)
REVISION HISTORY
EVAL-AD7091RSDZ Evaluation Board User Guide (UG-409)
ADIsimRF Design Tool
Changes to Setup and Test Section ................................................. 5
Ardizzoni, John. A Practical Guide to High-Speed Printed-Circuit-
Board Layout. Analog Dialogue 39-09, September 2005. 10/15—Revision 0: Initial Version
Circuit Note CN-0366. A 40 GHz Microwave Power Meter with
a Range from −30 dBm to +15 dBm. Analog Devices.
Circuit Note CN-0178. Software-Calibrated, 50 MHz to 9 GHz,
RF Power Measurement System. Analog Devices.
Mystery of "AGND" and "DGND." Analog Devices.
MT-073 Tutorial. High Speed Variable Gain Amplifiers (VGAs).
Analog Devices.

CN13680-0-10/15(A)
Instrumentation Anthology Circuits from the Lab Reference Designs
NOTES

CN15481-0-2/17(0)

Instrumentation Anthology Circuits From The Lab

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Circuits from the Lab

Circuits from the Lab® Reference Designs for Instrumentation

INTRODUCTION Built and verified for function and performance by applications

Anthology | Page 2 of 215

Anthology | Page 4 of 215

High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion

using the AD5764, a quad, 16-bit, serial input, bipolar voltage 4

this precision 16-bit DAC are a reference voltage source,

and an optional short-circuit current setting resistor leading to +5V

CIRCUIT DESCRIPTION SDO 4

A precision voltage reference must be used in order for the NC = NO CONNECT

Table 1. Precision 5.0 V References

tantalum bead type. The 0.1 µF capacitor must have low

©2009 Analog Devices, Inc. All rights reserved. Trademarks and

Interfacing the ADL5370 I/Q Modulator to the AD9779A

AD9779A ADL5370 1.8

OUT2_P QBBP 10 100 1k 10k

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Interfacing the ADL5375 I/Q Modulator to the AD9779A

CIRCUIT FUNCTION AND BENEFITS CIRCUIT DESCRIPTION

2.0 A simulated filter example is shown in Figure 3 with a third-

AD9779A LPI ADL5375-05 MAGNITUDE

C1I C2I 100Ω

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Precision, Unipolar, Inverting Conversion Using the AD5547/AD5557 DAC

Figure 1. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 V to –VREF (Simplified Schematic)

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Precision, Unipolar, Noninverting Configuration for the AD5547/AD5557 DAC

Figure 1. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 V to +VREF (Simplified Schematic)

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Precision, Bipolar, Configuration for the AD5547/AD5557 DAC

R1A RCOMA VREFA ROFSA RFBA

WR LDAC RS MSB A0, A1 C8 1µF

Figure 1. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF (Simplified Schematic)

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

AD5390/AD5391/AD5392 Channel Monitor Function

Figure 1. Efficient Channel Monitoring Circuit (Simplified Schematic)

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Converting a Single-Ended Signal with the

CIRCUIT FUNCTION AND BENEFITS CIRCUIT DESCRIPTION

CF greater than +5 V and the negative supply should be a few

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

DC-Coupled, Single-Ended-to-Differential Conversion Using the AD8138 Low

*MOUNT AS CLOSE TO THE AD7356 AS POSSIBLE.

2/09—Revision 0: Initial Release

©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and

Driving the AD7366/AD7367 Bipolar SAR ADC in Low-Distortion DC-Coupled

1kΩ 15pF VSS

©2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and

Using the AD8352 as an Ultralow Distortion Differential RF/IF Front End

0.1µF VOP 0.1µF 33Ω

0.1µF VON 0.1µF

Figure 2. Single-Ended Input to the AD8352 Driving the AD9445 ADC

3.5 V by an internal network. Input ac-coupling can be –120

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and

Stable, Closed-Loop Automatic Power Control for RF Applications

412Ω +5V ATTENUATOR

*SEE COMMON VARIATIONS SECTION

1 MHz to 8 GHz precision demodulating logarithmic amplifier. 1

–10 0 changing input envelope.

AD8318 WITH PULSED VSET T

Figure 2. ADL5330 Output Power vs. AD8318 Setpoint Voltage,

©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and