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the dynamic logic family. This architecture has embedded a 3. In chip Design, scan circuitry can be added to the
pull-down network (PDN) into the overlap-based DFF. The basic flip-flop design with nearly zero hit in
pull-down network can be any embedded Logic function performance
such as LUT, Multiplexer, inverter etc. If the PDN is
replaced by a single nMOS transistor, the design operates IV. CONCLUSION
as a single DFF. Further, O. Sarbishei et al. (2010) have
constructed a 4-bit Shift Regsiter based on the design of In this Review Paper, we have studied various
flip-flop and compared their work with earlier existing Flip-flop architectures with embedded logic in the design.
state-of-art design[9]. We have attempted to identify the advantage and
The major advantage of the SDFF has been the disadvantage of each design. The static designs offer a
capability to incorporate complex logic functions good alternative when speed is not a concern. Semi-
efficiently. Although SDFF has the potential of offering dynamic & Dynamic Flip flop architectures such SDFF,
improved efficiency in terms of speed and area, but it does DDFF, DRFF etc can incorporate logic structures
not consider the power consumption criterion. As discussed efficiently into the designs but they yield poor performance
earlier, an efficient logic structure incorporating logic in terms of power dissipation. Conditional
functions must consider all three viz. speed, area and power Charging/discharging Flip-flop are efficient when it comes
into account. In subsequent years, attempts are being made to delay and power consideration. However, their
to design a flip-flop, which can incorporate logic efficiently performance degrades if large logic structures are
in terms of all three; power, speed and area. embedded into the design. So far, The Dual Dynamic Node
Kalarikkal Absel et al. (2013) propose a Low- Hybrid Flip-flop designs seem to offer the best
Power solution, Dual Dynamic Node Pulsed Flip-Flop with performance when all the three performance parameters i.e
efficient embedded logic. The design is shown in Figure 9. area(or, number of transistors), power dissipation and
This design incorporates a PDN driven by the data-input speed(ie delay considerations) are considered.
instead of a transistor doing similar job. Due to this, charge We conclude that there is still a lot of scope for
sharing issue is also addressed to a great extent which research work to be done towards developing more
otherwise becomes a serious issue when large logic is efficient flip-flop designs incorporating logic functions.
embedded in the design[10]. Design of memories and processors using such Embedded-
Logic flip flops would optimize the on-chip area, delay &
power consumption and hence improve the overall
performance of the sequential circuits.
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