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Figure 1 Seven level inverter based APF.
The principle characteristic of the cascaded topology is suitable for active filter
applications in high and medium voltage systems. The proposed control scheme uses p-q theory
for reference compensation current estimation and Neuro controller for dc bus control at LV cell
and carrier based pulse width modulation techniques for gating signal generation. The control
scheme is simulated using MATLAB/SIMULINK.
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Va,Ia
Discrete, [B]
Ts = 5e-005 s.
Goto1
Out1 Ia Conn1
Isabc pow ergui
Out2 Ib LOAD CURRENTS
Out3 Ic
Vsabc
Out4 Va Conn2
Out5 Vb
Out6
i
Vc +
-
Conn1 Conn3
A +
i
Conn2 -
B
i NONLINEAR DIODE RECTIFIER LOAD
Conn3 +
C -
3-PHASE AC SOURCE
Out1 ta1
Out2 ta2
Out3 ta3
i
-
VA
If aref
TO PHASE-A
Out4 ta4 [A]
+
Out5 ta5
ILabc2 Out6 ta6 Goto
Out7 ta7
Out8 ta8
Out9 tb1
VB
Out10 tb2
[B] Out11 tb3
If bref Out12 tb4
TO PHASE-B
From Out13 tb5
Out14 tb6
Out15 tb7
VC
[A] Out16 tb8
Out17 tc1 A
From1 If abc Out18 tc2
Out19 tc3
If cref Out20 tc4
TO PHASE-C C VSI OUTPUT
Out21 tc5
-
Out22 tc6
Out23 tc7
Out24 tc8
B
time
REFERENCE COMPENSATION CURRENT ESITIMATOR
3-PHASE SEVEN LEVEL INVERTER
CSFSHPWM Clock
To Workspace
Fig. 2 Simulation model of MV test system with proposed 7-level SHAPF compensation.
The proposed ACSLISAF compensation consists of an asymmetric cascaded seven level
inverter (ACSLI) and its overall control system including p-q theory, Carrier switching
frequency sub-harmonic PWM technique and NeuroController.
4.1 Three Phase ACSLI model
Each phase of ACSLI consists of two H-bridge cells (LV cell and HV cell) in series and
each H-bridge cell is constructed using 4 thyristor switches with anti-parallel diodes. The two
H-bridges have separate energy storage devices on DC side. The DC voltages selected for LV
and HV cells are 1.5 kV and 3 kV. Since VHV is two times VLV, it can produce seven levels in
its output wave form. On DC side of 3 kV cell a DC source is used as storage device and a
capacitor of 4000 μF is used on the DC side of 1.5 kV cell. The DC-bus capacitor value is taken
large enough to minimize the variation of its voltage based on the general principle that
capacitor time constant to be ten times than that of fundamental period. The ACSLI is
connected at the point of common coupling through an interfacing inductor (Lf) and capacitor
(Cf) whose values are Lf = 2 mH, Cf=100 μF to filter the noise.
4.2 Control Strategy of ACSLI
The control strategy of ACSLI includes p-q theory for reference compensation current
estimation and carrier based PWM techniques for gating signal generation and NeuroController
for voltage regulation at LV cell capacitor.
4.2.1 p-q theory for estimating reference compensating currents
The simulation details of subsystem blocks for calculating various parameters are
described in the following sections.
4.2.1.1 ClarkTransformation
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Fig.4 Block Diagram for Clark Transformation and p calculation.
Fig 5 Clark transformation block diagram for both Vα, Vβ, Iα and Iβ
4.2.1.2: Calculation of :
According to p-q theory real and imaginary power can be separated into two parts:
Real power:
Imaginary power:
Where 𝑝̃ and 𝑞̃ are average power due to component 𝑖𝑎𝑝 ̅̅̅̅ and 𝑖𝑎𝑞
̅̅̅̅ respectively. 𝑝 ̃ and 𝑞̃ are
oscillating power due to components 𝑖𝑎𝑝 ̃ and 𝑖𝑎𝑞 ̃ respectively. And 𝑖 − (𝑖𝑎𝑝 ̃ + 𝑖𝑎𝑞 ̃ ) will
produces a purely sinusoidal waveform.But in order to achieve unity power factor APF
must compensate for 𝑞̃ from component 𝑖𝑎𝑞 ̃ .Thus 𝑖 − (𝑖𝑎𝑝 ̃ + 𝑖𝑎𝑞 ̃ + 𝑖𝑎𝑞
̅̅̅̅ ) will produce
purely sinusoidal waveform with unity power factor. Thus, inverse transformation 𝑖𝑎𝑝 ̅̅̅̅
will produce reference current𝑖𝑠∗ for each phase.𝑖̅̅̅̅
𝑎𝑝 can be deduced from 𝑝̅ which is filtered out
using low pass filter from p.
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Fig.7 𝒑̅ from p using low pass filter
4.2.1.3: Reference Current Calculation:
Reference currents are calculated from inverse Clark transformation.
TABLE II Choice of bipolar sigmoid transfer function as activation function for hidden
layer
Number of Number of epochs with Number of epochs with logsig
hidden neurons tansig activation function activation function
1 Performance goal not met Performance goal not met
2 Performance goal not met Performance goal not met
3 ≈ 400 ≈ 410
4 ≈ 100 ≈ 200
5 ≈ 320 ≈ 420
6 ≈ 360 ≈ 460
7 ≈ 400 ≈ 480
8 ≈ 420 ≈ 485
7
NOT Ta 7
8
Ta 8
OR
Ta 6 6
NOT
Ta 5 5
<=
AND
3 Ta 3
NOT
time 2
4 Ta 4 Clock
To Workspace
NOT
1 Ta 1
1 AND
2 Ta 2
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1
0.8
0.6
Magnitude(pu) 0.4
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
0.8
0.6
0.4
Magnitude(pu)
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
0.8
0.6
0.4
Magnitude(pu)
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
0.8
0.6
0.4
magnitude(pu)
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
10
1
0.8
0.6
MAgnitude(pu) 0.4
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
0.8
0.6
0.4
Magnitude(pu)
0.2
-0.2
-0.4
-0.6
-0.8
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
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0.8
0.6
0.4
0.2
Magnitude(pu)
-0.2
-0.4
-0.6
-0.8
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(sec)
0.8
0.6
0.4
0.2
Magnitude(pu)
-0.2
-0.4
-0.6
-0.8
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time (sec)
Fig. 18. Variable switching frequency (optimal) reference signals and carrier waves.
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5. RESULTS AND DISCUSSION
The Specifications of the elements used in Simulink model are given in Table III.
Table III: Specifications of elements
System parameters
Source voltage(peak) Vsa,Vsb,Vsc 4500V
Source frequency f 50Hz
Source impedance L 15mH
Diode rectifier load 0.1mH
inductance
Diode rectifier load 20Ω
resistance
Seven level SAF parameters
DC HV bus Voltage Vdchv 3 kV
DC LV bus Voltage Vdclv 1.5 kV
DC LV bus capacitor 4000µF
AC side inductance 2mH
AC side capacitance 100µF
250
200
150
100
load current(A)
50
-50
-100
-150
-200
-250
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)
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250
200
150
100
source current(A)
50
-50
-100
-150
-200
-250
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)
Figure 21. Harmonic spectrum of line current without filter for phase-a.
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600
400
200
Current(Amp)
0
-200
-400
-600
-800
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
time(sec)
600
400
200
Filter current(A)
-200
-400
-600
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)
4000
3000
2000
Voltage(Volts)
1000
-1000
-2000
-3000
-4000
-5000
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time(sec)
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Figure 25. Harmonic spectrum of source current (phase-a) with SAF.
The THD in source current for different carrier based PWM techniques are obtained and are
presented in Table IV. From Table IV it is observed that VSF-PWM is more superior in
compensating harmonics in load current compared to all other carrier based PWM techniques
mentioned.
Table. IV Source current THD comparison for different carrier based PWM techniques.
% THDi
Carrier based PWM Ia Ib Ic
technique
Without SAF 12.39 12.39 12.39
With SAF(PD-PWM) 3.33 3.55 3.49
With SAF(PD-PWM-O) 3.50 3.69 3.54
With SAF(POD-PWM) 3.59 3.31 3.49
With SAF(POD-PWM-O) 3.30 3.51 3.46
With SAF(APOD-PWM) 3.28 3.55 3.44
With SAF(APOD-PWM-O) 3.36 3.49 3.56
With SAF(VSF-PWM) 3.21 3.29 3.35
With SAF(VSF-PWM-O) 3.52 3.77 3.68
6. CONCLUSIONS
The asymmetric cascaded seven level inverter based shunt active power filter is suitable
for power line conditioning of medium voltage power systems. The p-q theory based
reference current estimating technique worked effectively and the sinusoidal PWM method
effectively produced the gating signals to the inverter switches to produce seven level output
voltage. The seven level APF system including the proposed control method reveal that the
cascaded active power filter effectively compensates the harmonics. The measured total
harmonic distortion of the source currents is 3.51 % that is in compliance with IEEE
519-1992 and IEC 61000-3 standards for harmonics. Also the performance of SAF with VSF-
PWM is superior when compared with other carrier based sinusoidal PWM techniques.
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