Hef4538b PDF

HEF4538B
Dual precision monostable multivibrator

Rev. 10 — 1 April 2016 Product data sheet
1. General description
The HEF4538B is a dual retriggerable-resettable monostable multivibrator. Each
multivibrator has an active LOW trigger/retrigger input (nA), an active HIGH
trigger/retrigger input (nB), an overriding active LOW direct reset input (nCD), an output
(nQ) and its complement (nQ), and two pins (nREXT/CEXT, and nCEXT, always
connected to ground) for connecting the external timing components CEXT and REXT.
Typical pulse width variation over the specified temperature range is 0.2 %.
The multivibrator may be triggered by either the positive or the negative edges of the input
pulse and will produce an accurate output pulse with a pulse width range of 10 s to
infinity. The duration and accuracy of the output pulse are determined by the external
timing components CEXT and REXT. The output pulse width (tW) is equal to REXT  CEXT.
The linear design techniques in LOCMOS (Local Oxide CMOS) guarantee precise control
of the output pulse width. A LOW level at nCD terminates the output pulse immediately.
The trigger inputs’ Schmitt trigger action makes the circuit highly tolerant of slower rise
and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits

 Tolerant of slow trigger rise and fall times
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Specified from 40 C to +85 C and 40 C to +125 C
 Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number Package
Name Description Version
HEF4538BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4538B
4. Functional diagram
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Fig 1. Functional diagram
HEF4538B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 10 — 1 April 2016 2 of 17

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Fig 2. Logic diagram (one multivibrator)
5. Pinning information
5.1 Pinning
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Fig 3. Pin configuration

5.2 Pin description

Table 2. Pin description
Symbol Pin Description
1CEXT, 2CEXT 1, 15 external capacitor connection (always connected to ground)
1REXT/CEXT, 2REXT/CEXT 2, 14 external capacitor/resistor connection
1CD, 2CD 3, 13 direct reset input (active LOW)
1B, 2B 4, 12 input (LOW-to-HIGH triggered)
1A, 2A 5, 11 input (HIGH-to-LOW triggered)
1Q, 2Q 6, 10 output
1Q, 2Q 7, 9 complementary output (active LOW)
VSS 8 ground supply voltage
VDD 16 supply voltage
6. Functional description
Table 3. Function table
Inputs Outputs
nA nB nCD nQ nQ
 L H
H  H
X X L L H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = positive-going transition;  = negative-going transition;
= one HIGH level output pulse, with the pulse width determined by CEXT and REXT;
= one LOW level output pulse, with the pulse width determined by CEXT and REXT.


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(1) Positive edge triggering.

(2) Positive edge re-triggering (pulse lengthening).
(3) Negative edge triggering.
(4) Reset (pulse shortening).
(5) T = REXT  CEXT.
Fig 4. Timing diagram
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Fig 5. Connection of the external timing components REXT and CEXT
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground)
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI < 0.5 V or VI > VDD + 0.5 V - 10 mA
VI input voltage 0.5 VDD + 0.5 V
IOK output clamping current VI < 0.5 V or VI > VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C

Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground)
Symbol Parameter Conditions Min Max Unit
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 package [1] - 500 mW
P power dissipation per output - 100 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min Max Min Max Min Max Min Max
VIH HIGH-level IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - V
input voltage 10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 V
input voltage 10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level IO < 1 A 5V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage 10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level IO < 1 A 5V - 0.05 - 0.05 - 0.05 - 0.05 V
output voltage 10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA
output current VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

Table 6. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min Max Min Max Min Max Min Max
IOL LOW-level VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
II input leakage nA, nB 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
current nREXT/CEXT 15 V - 0.3 - 0.1 - 1.0 - 1.0 A
CI input - - - - 7.5 - - - - pF
capacitance
Table 7. Typical static characteristics

VSS = 0 V; VI = VSS or VDD; Tamb = +25 C.
Symbol Parameter Conditions VDD Typ Unit
IDD supply current active state 5V [1] 55 A
10 V 150 A
15 V 220 A
CI input capacitance nREXT/CEXT - 15 pF
[1] Only one monostable is switching: for the specified current during the output pulse (output nQ is HIGH).
10. Dynamic characteristics

Table 8. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 11.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW nA, nB to nQ; 5V 193 ns + (0.55 ns/pF) CL - 220 440 ns
propagation see Figure 6 10 V 74 ns + (0.23 ns/pF) CL - 85 190 ns
delay
15 V 52 ns + (0.16 ns/pF) CL - 60 120 ns
nCD to nQ; see Figure 6 5V 98 ns + (0.55 ns/pF) CL - 125 250 ns
10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns
15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns
tPLH LOW to HIGH nA, nB to nQ; 5V 173 ns + (0.55 ns/pF) CL - 200 460 ns
propagation see Figure 6 10 V 79 ns + (0.23 ns/pF) CL - 90 180 ns
delay
15 V 52 ns + (0.16 ns/pF) CL - 60 120 ns
nCD to nQ; see Figure 6 5V 98 ns + (0.55 ns/pF) CL - 125 250 ns
10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns
15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns
tt transition time see Figure 6 5V 10 ns + (1.00 ns/pF) CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns
trec recovery time nCD to nA, nB; 5V - 20 40 ns
see Figure 7 10 V - 10 20 ns
15 V - 5 10 ns

Table 8. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25 C; for test circuit see Figure 11.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
trtrig retrigger time nQ, nQ to nA, nB; 5V 0 - - ns
see Figure 7 10 V 0 - - ns
15 V 0 - - ns
tW pulse width nA LOW; minimum width; 5 V 90 45 - ns
see Figure 7 10 V 30 15 - ns
15 V 24 12 - ns
nB HIGH; 5V 50 25 - ns
minimum width; 10 V 24 12 - ns
see Figure 7
15 V 20 10 - ns
nCD LOW; 5V 55 25 - ns
minimum width; 10 V 25 12 - ns
see Figure 7
15 V 20 10 - ns
nQ or nQ; 5V 218 230 242 s
REXT = 100 k; 10 V 213 224 235 s
CEXT =2.0 nF;
see Figure 7 15 V 211 223 234 s
nQ or nQ ; 5V 10.3 10.8 11.3 ms

REXT = 100 k; 10 V 10.2 10.7 11.2 ms
CEXT = 0.1 F;
see Figure 7 15 V 10.1 10.6 11.1 ms
nQ or nQ; 5V 1.01 1.09 1.11 s

REXT = 100 k; 10 V 0.99 1.04 1.09 s
CEXT = 10 F;
see Figure 7 15 V 0.99 1.04 1.09 s
tW pulse width nQ or nQ variation over 5V - 0.2 - %

variation temperature range; 10 V - 0.2 - %
see Figure 8
15 V - 0.2 - %
nQ or nQ variation over - 1.5 - %
VDD voltage range
5 V to 15 V; see Figure 9
nQ or nQ variation 5V - 1 - %
between monostables in 10 V - 1 - %
the same device;
REXT = 100 k; 15 V - 1 - %
CEXT = 2 nF to 10 F
REXT external timing 5 - [2] k
resistor
CEXT external timing 2000 - no pF
capacitor limits
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] The maximum permissible resistance REXT, which holds the specified accuracy of tW (nQ, nQ output), depends on the leakage current
of the capacitor CEXT and the leakage of the HEF4538B.

11. Waveforms
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Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output levels that occur with the output load.
Fig 6. Waveforms showing propagation delays
Table 9. Measurement points

Supply voltage Input Output
VDD VM VM
5 V to 15 V 0.5VDD 0.5VDD

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Measurement points are given in Table 9.

Set-up and recovery times are shown as positive values but may be specified as negative values.
Logic levels: VOL and VOH are typical output levels that occur with the output load.
Fig 7. Waveforms showing minimum nA, nB, and nQ pulse widths and set-up, recovery and retrigger times

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a. REXT = 100 k; CEXT = 100 nF b. REXT = 100 k; CEXT = 2 nF

(1) VDD = 5 V.
(2) VDD = 10 V.
(3) VDD = 15 V.
tW = 0 % at VDD = 10 V and Tamb = 25 C
Fig 8. Typical normalized change in output pulse width as a function of ambient temperature
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Tamb = 25 C; tW = 0 % at VDD = 10 V; REXT = 100 k REXT = 100 k; CEXT = 100 nF; CL = 50 pF;
(1) CEXT = 2 nF. one monostable multivibrator switching only
(2) CEXT = 100 nF. (1) VDD = 15 V.

(2) VDD = 10 V.
(3) VDD = 5 V.
Fig 9. Typical normalized change in output pulse Fig 10. Total supply current as a function of the
width as a function of the supply voltage output duty factor

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Test data is given in Table 10.

Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 11. Test circuit for measuring switching times
Table 10. Test data

Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD  20 ns 50 pF

12. Package outline
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Fig 12. Package outline SOT109-1 (SO16)

13. Abbreviations
Table 11. Abbreviations
Acronym Description
DUT Device Under Test
14. Revision history

Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4538B v.10 20160401 Product data sheet - HEF4538B v.9
Modifications: • Type number HEF4538BP (SOT38-4) removed.
Modifications: • Figure 8 and Figure 9 updated to show output pulse width over full temperature range.
HEF4538B v.4 20090206 Product data sheet - HEF4538B_CNV v.3
HEF4538B_CNV v.3 19950101 Product specification - HEF4538B_CNV v.2
HEF4538B_CNV v.2 19950101 Product specification - -

15. Legal information
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Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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In no event shall NXP Semiconductors be liable for any indirect, incidental,
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17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016. All rights reserved.

For more information, please visit: http://www.nxp.com
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Date of release: 1 April 2016
Document identifier: HEF4538B

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HEF4538B

Dual precision monostable multivibrator

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

2. Features and benefits

Fig 1. Functional diagram

Product data sheet Rev. 10 — 1 April 2016 2 of 17

Fig 2. Logic diagram (one multivibrator)

Fig 3. Pin configuration

Product data sheet Rev. 10 — 1 April 2016 3 of 17

5.2 Pin description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;

Product data sheet Rev. 10 — 1 April 2016 4 of 17

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(1) Positive edge triggering.

Fig 5. Connection of the external timing components REXT and CEXT

Product data sheet Rev. 10 — 1 April 2016 5 of 17

Table 4. Limiting values …continued

8. Recommended operating conditions

Product data sheet Rev. 10 — 1 April 2016 6 of 17

Table 6. Static characteristics …continued

Table 7. Typical static characteristics

10. Dynamic characteristics

Product data sheet Rev. 10 — 1 April 2016 7 of 17

Table 8. Dynamic characteristics …continued

nQ or nQ ; 5V 10.3 10.8 11.3 ms

nQ or nQ; 5V 1.01 1.09 1.11 s

tW pulse width nQ or nQ variation over 5V - 0.2 - %

Product data sheet Rev. 10 — 1 April 2016 8 of 17

Measurement points are given in Table 9.

Table 9. Measurement points

Product data sheet Rev. 10 — 1 April 2016 9 of 17

Measurement points are given in Table 9.

Product data sheet Rev. 10 — 1 April 2016 10 of 17

a. REXT = 100 k; CEXT = 100 nF b. REXT = 100 k; CEXT = 2 nF

(2) CEXT = 100 nF. (1) VDD = 15 V.

Product data sheet Rev. 10 — 1 April 2016 11 of 17

Test data is given in Table 10.

Table 10. Test data

Product data sheet Rev. 10 — 1 April 2016 12 of 17

12. Package outline

287/,1( 5()(5(1&(6 (8523($1

Fig 12. Package outline SOT109-1 (SO16)

Product data sheet Rev. 10 — 1 April 2016 13 of 17

14. Revision history

Product data sheet Rev. 10 — 1 April 2016 14 of 17

15. Legal information

15.1 Data sheet status

Product data sheet Rev. 10 — 1 April 2016 15 of 17

16. Contact information

Product data sheet Rev. 10 — 1 April 2016 16 of 17

© NXP Semiconductors N.V. 2016. All rights reserved.

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