EC6411 CircuitsSimulation LAB

EC6411 – CIRCUITS & SIMULATION LAB
Ex.No: 1
VOLTAGE SHUNT FEEDBACK AMPLIFIER
AIM:
i) To design and construct the voltage shunt feedback amplifier with voltage divider
bias circuit and to study the effect of negative feedback.
ii) To calculate the input impedance, output impedance and bandwidth and also plot
the frequency response.
APPARATUS REQUIRED:
S.NO COMPONENTS RANGE/TYPE QUANTITY
1 Transistor BC 547 1
2 Resistors 100KΩ, 50 KΩ, 5.6 KΩ, 22 KΩ, 1each
1KΩ
3 Capacitors 0.1µF, 22µF 1each

4 AFO 2MHz 1
5 RPS (0-30)V, DC 1
6 CRO 20 MHz 1
7 Bread board - 1
8 Connecting wires - As required
9 BNC cable - 2
THEORY:
A fraction of output voltage is applied in parallel with input voltage through the
feedback amplifier network. The voltage shunt feedback connection decreases both the input and
output resistance of amplifier and Overall Gain. Thus Rif =Ri /1+AVβ and Rof =Ro/1+AV β.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Set the biasing voltage, VCC=+12V1 using RPS.
3. Set the input voltage, 50mv sinusoidal using AFO.
4. Varying the frequency of AFO obtain corresponding output voltage using CRO
DEPARTMENT OF ECE RMKCET

5. Calculate the voltage gain Av.

6. Plot the frequency response and plot the bandwidth curve.
PIN DIAGRAM
PIN SPECIFICATIONS
B- Silicon C- AF power transistor Maximum voltage- 50V Operating frequency- 500KHz

Power- (0-5)w Current- (0-1)A
CIRCUIT DIAGRAM
VOLT AGE SHUNT FEEDBACK AMP LIFIER
VCC=12V
A.WIT H FEEDBACK
R1
Rc
100K Rf 5.6K C2
50K Q1 0.1U
C1
BC547
0.1U
Vout
Vin
FREQ = (0-30MHz)
VAMPL = 1Vpp R2 Re
Ce
22K 1.2K
FREQ = (0-2MHz) 22U
VCC=12V
B.WIT HOUT FEEDBACK
R1
Rc
100K 5.6K C2
Q1 0.1U
C1
BC547
0.1U
Vout
VAMPL = 1Vpp Vin
R2 Re FREQ = (0-30MHz)
FREQ = (0-2MHz) Ce
22K 1.2K
22U

DESIGN:
Given Vcc=12v, Vce=5v, Ic=1mA
Step 1: To find Rc & Re

Applying KVL to output loop,
Vcc=Vce+Ic(Rc+Re)
12=5+0.001((Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ
Step 2: To find R1 & R2
Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
Step 3: To find Ce, C1 & C2
Choose C1 & C2 = 0.1µf & Ce= 0.01Re
1
Ce  = 31µf
2  50  0.110^ 6100
Choose Ce=22µf

MODEL GRAPH
TABULAR COLUMN
A.WITHOUT FEEDBACK Vi=________volts
Frequency in Hz Output voltage Vo in volts Gain Av=Vo/Vi Gain in Db =20log AV

B.WITH FEEDBACK Vi=________volts

Frequency in Hz Output voltage Vo in volts Gain Av=Vo/Vi Gain in dB =20log AV
RESULT:
Thus the voltage shunt feedback amplifier is designed and the frequency response is
obtained.
Without feedback bandwidth = KHz
With feedback bandwidth = KHz

EC6411-CIRCUITS & SIMULATION LAB
Ex.No: 2
VOLTAGE SERIES FEEDBACK AMPLIFIER
AIM:
i)To design and construct the voltage series feedback amplifier with voltage divider
bias circuit and to study the effect of negative feedback.
ii)Also calculate the input impedance, output impedance and bandwidth and plot the
frequency response.
APPARATUS REQUIRED:

2 Resistors 100KΩ, 5.6 KΩ,22 KΩ, 1.2KΩ 2each
870 KΩ, 47 KΩ 1each
3 Capacitors 0.1µF, 4.7µF 2each
4 AFO 2MHz 1
5 RPS (0-30)V, DC 1
6 CRO 20 MHz DUAL 1
7 Bread board - 1
9 BNC cable - 2
THEORY:
A fraction of output voltage is applied in series with input voltage through the feedback
amplifier network. The voltage series feedback connection increases the input resistance and
decreases the output resistance of amplifier and Overall Gain. Thus, Rif =Ri *1+AVβ and
Rof =Ro/1+AV β
PROCEDURE:
4. Varying the frequency of AFO, obtain corresponding output voltage using CRO.

PIN DIAGRAM
PIN SPECIFICATIONS
B- Silicon
C- AF power transistor
Maximum voltage- 50V
Operating frequency- 500KHz
Power- (0-5)w
Current- (0-1)A
CIRCUIT DIAGRAM
VOLT AGE SERIES FEEDBACK AMPLIFIER VCC=12V

A.WIT HOUT FEEDBACK
R1 R3
Rc1 Rc2
100K 5.6K C2 100K 5.6K C3
Q1 0.1U Q2 0.1U
C1
BC547 BC547 Vout

0.1U
Vin FREQ = (0-30MHz)
VAMPL = 1Vpp R2 Re1 R4 Re2

Ce1 Ce2
22K 1.2K 22K 1.2K
FREQ = (0-2MHz) 4.7U 4.7U
B.WIT H FEEDBACK VCC=12V
R1 R3
Rc1 Rc2
100K 5.6K C2 100K 5.6K C3
Q1 0.1U Q2 0.1U
C1
BC547 BC547 Vout

0.1U
Vin Re1 FREQ = (0-30MHz)
VAMPL = 1Vpp R2 1.2K R4 Re2

Ce2
22K 22K 1.2K
FREQ = (0-2MHz) 4.7U
Rf 1
47K
0 Rf 2
870K

DESIGN:
Vcc=Vce+Ic(Rc+Re)
12=5+10((Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ
Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
Choose C1 & C2 = 0.1µf & XCe= 0.01Re
1
Ce 
2  50  0.110^ 6100 = 31µf
Choose Ce=22µf

MODEL GRAPH
TABULAR COLUMN

RESULT:
Thus the voltage series feedback amplifier is designed and the frequency response is
obtained.

Ex.No: 3
CURRENT SERIES FEEDBACK AMPLIFIER
AIM:
i)To design and construct the current series feedback amplifier with voltage divider bias
circuit.
ii)To study the effect of negative feedback, also calculate input impedance, output
impedance and bandwidth and also Plot the frequency response.
APPARATUS REQUIRED:
2 Resistors 2.2KΩ, 1KΩ, 100 KΩ, 22 KΩ 1each
3 Capacitors 0.1µF, 4.7µF,0.1 µF 1 each
4 AFO (0-10)MHz 1
5 RPS (0-30)V, DC 1
6 CRO (0.20) MHz DUAL 1
7 Bread board - 1
9 BNC cable - 2
THEORY:
A fraction of output voltage is applied in series with input voltage through the feedback
amplifier network. The cuurent series feedback connection increases the input resistance and the
output resistance of amplifier and Overall Gain. Thus, Rif =Ri *1+AVβ and Rof =Ro *1+AV β
PROCEDURE:
4. Varying the frequency of AFO, obtain corresponding output voltage using CRO.

PIN DIAGRAM
PIN SPECIFICATIONS
B- Silicon C- AF power transistor Maximum voltage- 50V
Operating frequency- 500KHz Power- (0-5)w Current- (0-1)A
CIRCUIT DIAGRAM
CURRENT SERIES FEEDBACK AMPLIFIER

VCC=12V
A.WITHOUT FEEDBACK
R1
Rc
100K 5.6K C2
Q1 0.1U
C1
BC547
0.1U
Vout
VAMPL = 1Vpp Vin
FREQ = (0-2MHz) Ce
22K 1.2K
4.7U
B.WIT H FEEDBACK VCC=12V
R1
Rc
100K 5.6K C2
Q1 0.1U
C1
BC547
0.1U
Vout
VAMPL = 1Vpp Vin
FREQ = (0-2MHz)
22K 1.2K

DESIGN:
Vcc=Vce+Ic(Rc+Re)
12=5+10((Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ
Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
1
Ce 
2  50  0.110^ 6100 = 31µf
Choose Ce=22µf

MODEL GRAPH
TABULAR COLUMN

RESULT:
Thus the current series feedback amplifier with voltage divider bias circuit is design and
plotted the output response.

EC6411- CIRCUITS & SIMULATION LAB
Ex.No: 4
RC PHASE SHIFT OSCILLATOR
AIM:
To design a transistorized RC phase shift oscillator at the frequency 200Hz. Assume R=2.2kΩ,
C=0.1uf.
APPARATUS:
2 Resistors 5.6KΩ, 1KΩ, 100 KΩ, 1each
22 KΩ ,2.2 KΩ
3 Capacitors 22 µF, 1
0.1 µF 3
4 RPS (0-30)V DC 1
5 CRO 20 MHz DUAL 1
6 Bread board - 1
8 BNC cable - 2
THEORY:
The RC phase shift oscillator circuit consists of a conventional single transistor amplifier with
voltage divider bias and RC phase shift network. The phase shift network consist of three
sections is 60° so that the total phase shift produced by this RC network is 180°.The frequency of
oscillation is given by
1
fo =
2RC 6 + 4K

Where R1=R2=R3=R; k=Rc/R
C1=C2=C3=C
When the circuit is switched on the voltage divider bias provides necessary biasing to the
circuit. In the feedback network due to leed and lag of resistors and capacitors, it produces
oscillations of frequency determined by fo the output Vo of amplifier is feedback to the
network. This network produces a phase shift of 180° and voltage Vi appears at output, which is
applied to input of transistor amplifier and the feedback fraction m=Vi /Vo. The feedback
network produces 180° and amplifier stage produces 180° phase shift because of common
emitter configuration. Thus the total feedback around the circuit is 360° this is the required
condition for oscillation.
PROCEDURE:
2. Set the biasing voltage, VCC=+12V using RPS.
3. To vary the value of resistance ‘R’ to get the perfect sinusoidal waveform.
4. Note the time period and amplitude using CRO.
5. Calculate the frequency of sine wave and compare it with theoretical frequency.
6. Plot the waveform on the graph.
PIN DIAGRAM
PIN SPECIFICATIONS
B- Silicon C- AF power transistor Maximum voltage- 50V
Operating frequency- 500KHz Power- (0-5)w

Current- (0-1)A
CIRCUIT DIAGRAM
R C PHASE SHIFT OSCILLATOR VCC=12V
R1
Rc
100K 5.6K Cf 1 Cf 2 Cf 3
Q1 0.1u 0.1u 0.1u

AMPLIFIER V
CIRCUIT
BC547
Rf 1 Rf 2 Rf 3
2.2K 2.2K 2.2K
R2 Re
Ce FEEDBACK
22K 1.2K
22U
DESIGN:
AMPLIFIER STAGE
Vcc=Vce+Ic(Rc+Re)
12=5+10((Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ

Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
1
Ce 
2  50  0.110^ 6100 = 31µf
Choose Ce=22µf
FEEDBACK STAGE
Given R=R1=R2=R3=2.2kΩ,
C=C1=C2=C3=0.1µf f=?
1
f 
2RC 4k  6
Rc
k ?
R

MODEL GRAPH
TABULAR COLUMN
X- Y-
SIGNAL TIME/DIV. VOLT/DIV. TIME AMPLITUDE FREQ.
AXIS AXIS
OUTPUT
RESULT:
Hence the required transistorized RC phase shift oscillator is designed and waveform is
plotted
Theoretical frequency = Hz
Practical frequency = Hz

Ex.No: 5
COLPITTS OSCILLATOR
AIM:
To design a colpitts oscillator of frequency 10KHZ C1=0.1µF, C2=0.01µF and plot the
waveforms.
APPARATUS REQUIRED:
1 Transistor BC547 1
2 Resistors 100kΩ, 5.6 kΩ 1each
22kΩ, 1.2kΩ 1
3 Capacitors 0.1µF, 0.01 µF 1each
22 µF 1
4 Inductor 22.8mH 1
5 RPS (0-30)V DC 1
6 CRO (0-30)MHz DUAL 1
7 Bread board - 1
9 BNC cable - 2
THEORY:
The colpitts oscillator uses two capacitors and placed across a common inductor L at the
centre of capacitors is taped. The tank circuit is made up of C1, C2 and L. The frequency of
oscillation is given by
1 C1 C2
f  ; where Ceq 
2 LCeq C1  C2

When the circuit is turned ON. the capacitors are charged. When the capacitors are
fully charged it discharges through coil L and hence feedback V appears across C2. The voltage
developed across C1. A phase shift of 180° is produced by C1=C2 voltage divider in this way,
feedback is properly phased to produce the continuous undammed oscillators.
PROCEDURE:
2. Set the biasing voltage, VCC=+12V using RPS. By varying the value of C1, C2 and L the
frequency of oscillation can be varied.
PIN DIAGRAM
PIN SPECIFICATION
B- Silicon
Power- (0-5)w
Current- (0-1)A

CIRCUIT DIAGRAM
COLP IT T S VCC=12V
OSCILLAT OR
R1
Rc
100K 5.6K Cc2
Q1 0.1U
AMPLIFIER Cc1 V
CIRCUIT
BC107
0.1U
R2 Re
Ce
22K 1.2K
22U
0
C1 C2
0.1U 0.01U
0 TANK CIRCUIT
L 27.8mH
DESIGN:
AMPLIFIER STAGE
Vcc=Vce+Ic(Rc+Re)
12=5+10(Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ
Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
1
Ce 
2  50  0.110^ 6100 = 31µf
Choose Ce=22µf
FEEDBACK STAGE
Given F=10kHz.
Assume C1=0.1µf & C2=0.01µf, find L=?
1
f 
2 LCeq
C1C 2
Ceq  ?
C1  C 2

MODEL WAVEFORM
TABULAR COLUMN
SIGNAL X-AXIS Y-AXIS TIME/DIV VOLT/DIV TIME AMPLITUDE FREQ.
OUTPUT
RESULT:
Thus the Colpitts oscillator was designed and the output was obtained.
Theoretical frequency= Hz

Ex.No: 6 HARTLEY OSCILLATOR
AIM:
To design a Hartley oscillator of frequency 8KHz. Assume L=10mH, C=0.1µF
APPARATUS REQUIRED:
2 Resistors 5.6KΩ,1 KΩ 1 each
100 KΩ,22 KΩ
3 Capacitors 0.01 µF,22 µF 1each
4 DIB 200 µF 2
5 RPS (0-30)V DC 1
7 Bread board - 1
9 BNC cable - 2
THEORY:
The Hartley oscillator consists of two inductors 4 and L2 are placed across a common
capacitors C and the centre of the inductor’s tapped. The tank circuit is made up of L1, L2 and C.
The frequency of oscillator is given by
1
f 
2 CLeq
Leq  L1  L 2

When the circuit is turned ON. The capacitor is charged. When the capacitors
fully charged. It discharges through coils L1 and feedback V appears across L2. The voltage
developed across L1, A phase shift of 180° is produced by L1=L2 voltage divider in this way,
feedback is properly phased to produce the continuous undammed oscillators
PROCEDURE:
3. By varying the value of L1, L2 and C the frequency of oscillation can be varied.
PIN DIAGRAM
PIN SPECIFICATION
B- Silicon
Power- (0-5)w
Current- (0-1)A

CIRCUIT DIAGRAM
VCC=12V
HART LEY
OSCILLAT OR
R1
Rc
100K 5.6K Cc2
Q1 0.1U
AMPLIFIER Cc1 V
CIRCUIT
BC107
0.1U
R2 Re
Ce
22K 1.2K
22U
0
L1 200uH L2 10mH
0 TANK CIRCUIT
C
0.1uF
DESIGN:
Given Vcc=12v, Vce=5v, Ic=1Ma
AMPLIFIER STAGE
Vcc=Vce+Ic(Rc+Re)
12=5+10(Rc+Re)
Rc+Re = 7kΩ
Choose Re=1kΩ
Rc+1kΩ=7kΩ
Rc= 6kΩ
Choose Rc=5.6kΩ

Vr1 R1

Vr2 R 2
Vr2=Vbe + Vre
Vr2=0.7+1=1.7v
Vr1=Vcc-Vr2=12-1.7v=10.3v
R1 10 .3  10 .3 
  R1  R 2 
R 2 1.7  1.7 
Choose R1=100kΩ
R2 = 0.165x100kΩ
Choose R2=22kΩ
1
Ce 
2  50  0.110^ 6100 = 31µf
Choose Ce=22µf
FEEDBACK STAGE
Given F=10kHz.
Assume C=0.1µf , L1=200µH, f=5kHz, L2=?
1
f 
2 CLeq
Leq  L1  L 2  ?

MODEL WAVEFORM
TABULAR COLUMN
SIGNAL X-AXIS Y-AXIS TIME/DIV VOLT/DIV TIME AMPLITUDE FREQ
OUTPUT
RESULT:
Thus the Hartley’s oscillator is designed and output is obtained.

Ex.No: 7 WIEN BRIDGE OSCILLATOR
AIM:
To design Wien bridge oscillator and to compare theoretical and practical frequency.
APPARATUS REQUIRED:
2 Resistor 68K(2), 100K(2), 16K(2), 12K(2), -
1K(2), 47K(1), 4.7K(1),
3 Capacitor .01uf(2), 10uf(2) -
4 CRO (0-20MHz) Dual 1

5 RPS 0-30v DC 1
6 Bread board - 1
8 BNC cable - 1
THEORY:
The Wien bridge oscillator is also a RC oscillator used for audio frequency range. The feedback
network does not provide any phase shift it is a lead lag network, which is called Wien bridge circuit. The
amplifier is the two stage common emitter transistor configurations. Each stage contributes 180° phase
shift. Hence the total phase shifts due to the amplifier becomes 360° which is necessary as per the
oscillator conditions. The frequency of oscillations is given by
1
f 
2 R1 R2 C1C 2
When R1  R2  R and C1  C 2  C
1
f 
2RC

CIRCUIT OPERATION:
The bridge consists of R&C in series with R&C in parallel. The feedback is applied from the
collector of Q2 through the coupling capacitor to the bridge circuit. The resistance R4 serves the dual
purpose of emitter resistance of the transistor Q1 and also the element of the Wien bridge. The two stage
amplifier provides a gain much more than three, and it is necessary to reduce it. To reduce the gain the
negative feedback is used without bypassing the resistance R4. The negative feedback can accomplish the
gain stability and can control the output magnitude also the negative feedback reduces the distortion and
therefore the output obtained is a pure sinusoidal in nature. The amplitude stability can be improved using
a non linear resistor R4. Due to this the loop gain depends on RC amplitude of the oscillations. This
reduces the loop gain and hence signal amplitude gets reduced and controlled.
PROCEDURE:
3. By varying the value of R and C the frequency of oscillation can be varied.
6. Plot the waveforms on the graph.
CIRCUIT DIAGRAM:

MODEL WAVEFORM
TABULAR COLUMN
SIGNAL X-AXIS Y-AXIS TIME/DIV VOLT/DIV TIME AMPLITUDE FREQ
OUTPUT
RESULT:
Thus the Wien bridge oscillator circuit was designed and output was verified with theoretical
frequency.

Ex.No: 8
INTEGRATOR AND DIFFERENTIATOR
AIM:
To design and construct the integrator and differentiator circuits and obtain the output
response for various input frequency range.
APPARATUS REQUIRED:
1 Resistor 10KΩ 1
2 Capacitor 0.1µF 1
4 AFO 1 MHz 1
5 Bread board - 1
7 BNC cable - 2
THEORY:
INTERGRATOR:
A circuit in which the output voltage is directly proportional to the integral of input is
known as integrator (i.e) Output α input It is a sample RC series circuit which output is taken
across the capacitor C. For good integrator.
i) The time constant RC of the circuit should be very large compared to the time period of the
input waves
ii) The value of „R‟ should be ten or more times larger than Xc

DIFFERENTIATOR:
A circuit in which the output voltage is directly proportional to the derivative of the
input is known as “Differentiator”. (i.e) Output α (input).
It is a series sample RC circuit which output is taken across the capacitor C, For a good
differentiator
i)The time constant RC of the circuit should be much smaller than the input period of the input
waves.
ii) The values of Xc should be ten (or) more times larger than(R).
PROCEDURE:
1. Give the connections as per the circuit diagram.
2. The input waveform is to be set using AFO with different frequency range.
3. The output waveform is to be observed using CRO.
4. Plot the waveforms on the graph.
CIRCUIT DIAGRAM
A.INTEGRATOR
10k
Vin Vout
C
V1 = 1Vpp
0.1U

MODEL GRAPH
TABULATION:
AMPLITUDE
SIGNAL X-AXIS Y-AXIS TIME/DIV. VOLT/DIV. TIME
INPUT
OUTPUT 1
OUTPUT 2
B.DIFFERENTIATOR
C
0.1U
v OUT
Vin R
10k
V2 = 1Vpp

MODEL GRAPH
Design:
Differentiator:
f = 1KHz
τ = RC = 1ms
If C = 0.1μF
Then R = 10KΩ
For T << τ, Choose R = 1KΩ and
For T >> τ, Choose R = 100KΩ
Integrator:
f = 1KHz
= RC = 1ms
If C = 0.1μF

Then R = 10KΩ
For T << τ, Choose R = 1KΩ and
For T >> τ, Choose R = 100KΩ
TABULATION:
AMPLITUDE
SIGNAL X-AXIS Y-AXIS TIME/DIV. VOLT/DIV. TIME
INPUT
OUTPUT 1
OUTPUT 2
RESULT:

Ex.No: 9
ASTABLE MULTIVIBRATOR
AIM:
To design and determine the period and frequency of oscillations of an astable multivibrator
with the component value R1=R2=150KΩ, RC1=RC2=3.3 KΩ.
APPARATUS REQUIRED:
2 Resistor 150 KΩ,3.2 KΩ 2each
3 Capacitor 0.01µf 2
4 CRO (0-20)MHZ DUAL 1
5 RPS (0-30)V DC 1
6 Bread board - 1
7 Connecting wires As required
8 BNC cable - 2
THEORY:
Astable multivibrator is also known as free running multivibrator. It is rectangular wave

shaping circuit having nonstable states. This circuit does not need an external trigger to change
state. It consists of two similar NPN transistors. They are capacitor coupled. It has 2 quasi-stable
states. It switches between the two states without any applications of input trigger pulses. Thus it
produces a square wave output without any input trigger. The time period of the output square
wave is given by, T = 1.38RC.
CIRCUIT OPERATION:
When VCC is applied, the collector current starts following in Q1 and Q2. In addition the
coupling capacitor C1 and C2 also start changing up. As the characteristics of two transistors say
Q1 will conduct more and more +Ve. The increasing positive output at point ‘A’ is applied to the

base of transistor Q2, through C1. These establishes a reverse bias Q2 and the collector current
starts decreasing. At the collector of Q2 is connected to the base of Q1 through C2 . Therefore
base of A1 becomes more negative Q1 is more forward biased. This further increased the
collector current in Q1 and cause a further decrease of collectors repeated until the circuit
devices Q1 to saturation and Q2 to cut off. This action occurs very rapidly and may be
considered practically instantaneous across the output of Q1 (ON state) is approximately zero
and that of Q2 is VCC time period T=1.4RC seconds.
PROCEDURE:
1. Connections are made as per the circuit diagram
2. Obtain the required waveform. Note down the time period and amplitude using CRO
3. Calculate the frequency of the waveform.
CIRCUIT DIAGRAM
MODEL GRAPH:

DESIGN PROCEDURE:
VCC = 10V; IC = 2mA; VCE (sat) = 0.2V; f = 1KHz; hfe =315
Vcc – Vce(sat)
RC = = 5.9 KΩ
Ic
R ≤ hfe RC = 315 * 5.9 * 103 = 1.85MΩ
R = 1.5MΩ
T = 1.38RC
C = T / (1.38R) = (1 * 10-3) / (1.38 * 1.5 * 106)= 0.48nF
TABULAR COLUMN:
AMPLITUDE TON TOFF Frequency
(in volts) (ms) (MS) (in HZ)
V01
V02
RESULT:
Thus the Astable Multivibrator is designed and output waveforms are plotted.

Ex.No: 10 MONOSTABLE MULTIVIBRATOR
AIM:
To design and construct monostable multivibrator. And calculate the time period of pulse.
APPARATUS REQUIRED:
2 Resistor 4KΩ, 4 KΩ, 2each
190 KΩ, 48.5 KΩ,
30.6 KΩ 1each
3 Capacitor 2000pf 1
4 Diode IN4007 1
6 RPS (0-30)V DC 1
7 Bread board - 1
9 BNC cable - 2
THEORY:
A multivibrator in which one transistor is always conducting and the other is non-conducting
is called a monostable multivibrator. It has only one stable state.
From the above circuit arrangements Q1 is at cut off and Q2 is saturated. This is the stable
state for the circuit and it will continue to stay in the stable until a triggering pulse is applied to
C2. When a negative pulse of short duration and sufficient magnitude is applied to the base of

Q1 through C2, the transistor Q1 starts the conducting and the positive potential at the collection
of Q1 and is coupled to the base of Q2 through capacitor C1. This decreases the forward bias on
Q2 and its collector current decreases. The increasing negative potential on the collector of Q2 is
applied to the base of Q1 through R3.This further increases the forward bias on Q1 and hence its
collector current with the set of action taking place Q1 is quickly driver to saturation and Q2 at
the cur off region.
PROCEDURE:
1. The connections are made as per the circuit diagram

2. The negative pulse is given to collector of first transistor
3. Obtain the required waveform
4. Note the time period and amplitude using CRO
5. Calculate the frequency of waveform
6. Plot the waveforms on graph.
CIRCUIT DIAGRAM

MODEL GRAPH
DESIGN PROCEDURE:
VCC = 12V; VBB = -2V; IC = 2mA; VCE (sat) = 0.2V; f = 1KHz; hfe =315
Vcc – Vce(sat)
RC = = 5.9 KΩ
Ic
IB2(min) = IC2 / hfe =
Select IB2 > IB2(min)
IB2 =
Vcc – Vce(sat)
R= = 1.13MΩ
IB2
T = 0.69RC
C = T / 0.69R =

VB1 =
= (since, V B1 is very less)
VBBR1 = VCE (sat) R2
R2 =10R1 (since, VBB = 2V and VCE (sat) = 0.2V)
Let R1 = 10KΩ, then R2 = 100KΩ
Choose C1 = 25pF.
TABULAR COLUMN:
INPUT OUTPUT
WIDTH
(ms) TON TOFF Voltage TON TOFF Voltage
(ms) (MS) (volts) (ms) (MS) (volts)
RESULT:

Ex.No: 11 SINGLE TUNED AMPLIFIER
AIM:
To design a Class-C tuned amplifier with the frequency of 2 KHz and obtain the frequency
response. Calculate the bandwidth.
APPARATUS REQUIRED:
S.No. Apparatus Range/Type Qty.
1. Transistor CL100 1
2. Resistor 10kΩ, 47kΩ 1 each
3. Capacitor 1µf 3
4. DRB - 1
5. DIB - 1
6. AFO (0-20MHz) 1
7. CRO (0-30MHz) dual 1
8. RPS DC-(0-30v) 1
9. Bread board - 1
10. Connecting Wires - 10
11. BNC cable - 2
THEORY:
If any amplifier amplifies a specific frequency or narrow band of frequencies those are
called tuned amplifiers. The amplifier is said to be Class-C tuned amplifier, if the Q-point and
the input signals are selected such that the output signal is obtained less than a half cycle for a
full wave input. Due to such a selection of a point transistor remains active for less than a half
cycle. Hence only that much point is produced at the output of remaining cycle of the input the

transistor remains cut-off and no signal is produced at the output. A parallel resonant circuit
acts as a load impedance. As collector current follows for less than a half cycle, the collector
current consists of a series and of pulses with harmonics of input signal. A parallel tuned
circuit acting as load and is tuned to the input frequency. Therefore it filters the harmonics and
produce a sine wave it is the fundamental frequency. The efficiency is high.
PROCEDURE

2. Switch on the RPS to bias the circuit with 12V.
3. Set the input sinusoidal signal with 1Vp-p using AFO.
4. Vary the input signal from 0-30MHz using AFO and obtain the corresponding
output voltage using CRO.
5. Calculate the gain in dB and plot the frequency response on the graph.
PIN DIAGRAM
PIN SPECIFICATION
C- Gallium Arsenide
L- High frequency power transistor
Power- (0-3)w
Current- (0-1)A

CIRCUIT DIAGRAM
CLASS- C TUNED AMPLIFIER VCC=12v
RC=47k
Cc2
1u
Q1
Cc1 RB=10k
CL100
1u 1k
L1 C1 R1 Vout
VAMPL = 1V Vin 6.33mH

1k FREQ = 0-30MHz
FREQ = 0-2MHz 1u
DESIGN
1
Given f =2kHz. f  ;
2 LC
Let C=1nF
L=?
MODEL GRAPH

TABULAR COLUMN:
Vi=________volts
Frequency in Output voltage Vo in volts Gain – Gain in dB

Hz Av=Vo/Vi
=20log AV
RESULT
The Class-C tuned amplifier has been designed with 2KHz frequency and frequency
response was plotted on the graph. The bandwidth is
Critical frequency(theoretical) = KHz
Critical frequency(practical) = KHz
Bandwidth = KHz

Ex.No: 12 CLIPPERS AND CLAMPERS
AIM:
To construct positive and negative clippers and clampers using diode.
APPARATUS REQUIRED:
1 Diode 1N4007 1
2 Resistor 1KΩ, 10 KΩ 1each
3 CRO (0-20)MHz, DUAL 1
4 RPS (0-30)V DC 1
5 Bread board - 1
7 BNC cable - 2
THEORY:
CLIPPERS:
The clipper circuits are used to clip off or removal off the position of signal voltage above
(or) below certain levels.
POSITIVE CLIPPERS:
A positive clipper is that which removes the positive portion of the input voltage. During the
positive half cycle of the input voltage, the diode is forward bias and conduct heavily therefore
the voltage across the diode and hence the load resistance is zero
 R1 
Output voltage (VO) =  Vin Where RL>R1
 R1  RL 

NEGATIVE CLIPPERS:
A negative clipper is that which removes the negative portion of the input voltage. The
diode is forward bias and conducts heavily. Therefore the voltage across the diode and hence
across the load resistance, is zero. Hence the output voltage during negative half cycle is zero.
During the positive half
cycle of input voltage the diode is reverse biased and behaves as an open. In this condition the
circuit behaves as voltag3e divider.
 R1 
Outputvoltage (VO)=  Vin Where RL>R1
 R1  RL 
CLAMPERS:
Clamper is a diode circuit which is used to add and subtract a dc level to an electrical signal.
POSITIVE CLAMPERS:
During the negative half cycle of the input signal the diode is forward biased it behaves as a
short. The charging time constant (τ=RC) is very small. So that the capacitor will charge to volts
very quickly (VO=V)
NEGATIVE CLAMPERS
During the positive half cycle of the input diode is forward signal biased. The charging
time constant (τ=RC) is very small. So that the capacitor will charge to volts very quickly.
PROCEDURE:
i) Give the connections as per the circuit.

ii) Given (or) set input waveform by AFO.
iii) O/P waveform is to be observed using CRO.
iv) Voltage and time period are noted.
v) Output waveforms are plotted with noted readings.

CLAMPER:
POSITIVE CLAMPER:
MODEL GRAPH:
NEGATIVE CLAMPER

MODEL GRAPH
CLIPPER:
SERIES POSITIVE CLIPPER:
MODEL GRAPH:

SERIES NEGATIVE CLIPPER:
MODEL GRAPH:
RESULT:

Ex.No: 13 STUDY OF PSPICE
AIM:
To study about the basics of PSPICE.
Introduction:
SPICE stands for Simulation Package with Integrated Circuit Emphasis. SPICE is as close to a
universally available package for doing numerical network analysis as one can find. In PSPICE
the program we run in order to draw circuit schematics is called CAPTURE. The program that
will let us run simulations and see graphic results is called PSPICE. You can run simulation from
the program where your schematic is. There are a lot of things we can do with PSpice, but the
most important things for you to learn are
 Design and draw circuits
 Simulate circuits
 Analyze simulation results (Probe for older versions)
For this course you will not need the full capacity of CAPTURE. The devices that we will use
are resistors, inductors, capacitors and various independent/dependent sources. It is good to
know that CAPTURE has extensive symbol libraries and includes a fully integrated symbol
editor for creating your own symbols or modifying existing symbols.
The main tasks in CAPTURE are
 Creating and editing designs
 Creating and editing symbols
 Creating and editing hierarchical designs
 Preparing your design for simulation
Procedure:
In this part we will create a simple DC circuit shown in Fig. 1‐1 just to let you know how to start
working

with PSpice. Your goal is to find the current value in the resistor labeled R1.
Proceed as follows to obtain the answer using PSpice.

1. Run the CAPTURE program.
2. Select File/New/Project from the File menu.
3. On the New Project window select Analog or Mixed A/D, and give a name to your project
then click OK.
4. The Create PSpice Project window will pop up, select Create a blank project, and then click
OK.
5. Now you will be in the schematic environment where you are to build your circuit.
6. Select Place/Part from the Place menu.
7. Click ANALOG from the box called Libraries:, then look for the part called R. You can do it
either by scrolling down on the Part List: box or by typing R on the Part box. Then click OK.
8. Use the mouse to place the resistor where you want and then click to leave the resistor there.
You
can continue placing as many resistors as you need and once you have finished placing the
resistors right‐click your mouse and select end mode.
9. To rotate the components there are two options:
 Rotate a component once it is placed: Select the component by clicking on it then
Ctrl‐R
 Rotate the component before it is placed: Just Ctrl‐R.
10. Select Place/Part from the Place menu.
11. Click SOURCE from the box called Libraries:, then look for the part called VDC. You can
do it either by scrolling down on the Part List: box or by typing VDC on the Part box, and
then click OK. Place the Source.
12. Repeat steps 10 ‐ 12 to get and place a current source named IDC.

13. Select Place/Wire and start wiring the circuit. To start a wire click on the component
terminal where you want it to begin, and then click on the component terminal where you
want it to finish. You can continue placing wires until all components are wired. Then
right‐click and select end wire.
14. Select Place/Ground from the Place menu, click on GND/CAPSYM. Now you will see the
ground
symbol.
15. Type 0 on the Name: box and then click OK. Then place the ground. Wire it if necessary.
16. Now change the component values to the required ones. To do this you just need to
double‐click on the parameter you want to change. A window will pop up where you will be
able to set a new value for that parameter.
17. Once you have finished building your circuit, you can move on to the next step – prepare it
for simulation.
18. Select PSpice/New Simulation Profile and type a name, this can be the same name as your
project, and click Create.
19. The Simulations Settings window will now appear. You can set up the type of analysis you
want PSpice to perform. In this case it will be Bias Point. Click Apply then OK.
20. Now you are ready to simulate the circuit. Select PSpice/Run and wait until the PSpice
finishes. Go back to Capture and see the voltages and currents on all the nodes.
21. If you are not seeing any readout of the voltages and currents then select PSpice/Bias
Point/Enable Bias Voltage Display and PSpice/Bias Point/Enable Bias Current Display. Make
sure that PSpice/ Bias
Point/Enable is checked.
DC Sweep
Compose the schematics shown in Fig. 1‐2. The type of analysis you need to set up is DC Sweep.
Make sure the sweep variable is Voltage source. Type in V1 as the name of the source. Make
sure the sweep type is linear and use 0V, 2V and 0.01V for the start value, end value and
increment, respectively. Run the simulation. We are interested in graphing the diode current
versus the diode voltage. Once the simulation has finished you will see a black window with no
graph in it. Select Trace/Add trace from the trace menu. You will see now a window with all the
variables you can add to your plot. Select I(D1). Note that the x‐axis variable is V_V1 and we
need to change it to V(D1:1). Select Plot/Axis settings...

from the Plot menu, Click on Axis Variable..., select V(D1:1). Now look for the value of
V(D1:1) when the current I(D1) is 1mA. Select Trace/Cursor/Display from the Trace menu. A
small window called probe cursor will appear. You have two cursors, A1 is controlled with the
left button of your mouse and A2 is controlled with the right button of your mouse. Use one of
them to find the point requested. Once you have the point, select Plot/Label/Mark from the Plot
menu The coordinates of the point will show up. Select Trace/Cursor/Display from the Trace
menu and now you can move the coordinates to a better place in case they are over the curve.
Click over the coordinates and hold the button down, move the mouse to place them in a better
place then release the button. You can add labels to the plot just to make sure people who see
your work know what you are showing. Select Plot/Label/Text from the Plot menu, type in the
label "Diode’s I‐V characteristic” and then place wherever you want on the plot by moving the
mouse and drop it by left clicking.
AC Sweep
Compose the schematics shown in Fig. 1‐3. Use the part VAC as your source. The type of
analysis you need to set up is AC Sweep. Check logarithmic in AC Sweep type and select
Decade. Use 1, 1000 and 10 for Start frequency, End frequency and Points/Decade, respectively.
Run the simulation. Now we are interested in plotting the output to input ratio (i.e., the transfer
function of the circuit). Select Trace/Add Trace from the Trace menu, select V(C1:2) then from
the right window select / and finally select (V1:+).
Use the cursor to find the point where the y‐axis value is 1/√2 (or –3dB). Mark that point and
now using Plot/Label/Line, Plot/Label/Arrow and Plot/Label/Text mark the limits of the region
from 1Hz to the point you found, something like this |← BW →|. This is the –3dB bandwidth of
your circuit.

Parametric Sweep
In the schematics of Fig. 1‐1, replace the DC voltage source V1 by a 0V‐120V square wave. You
may specify a period of 10ns, a 50% duty cycle and a 1ns rise time and fall time for the square
wave. Our goal is to find the values of R2 such that the current in R1 is 1A when V1 is 0V and
120V, respectively. (Note: a hand calculation of possible values of R2 may help you here. Also,
you should obtain two different R2 values for this part.)
First we need to define the sweep parameter, in this case it is the value of R2, so double‐click on
the value and change it to something like {Var} where Var can be any name. Now from the
library Special, get a part named Param and place it on the schematics and double‐click on it so
you can edit its properties. Click on the New Column and type the name Var without the {}, then
input the Value 50 and finally click OK. Now select the column Var and select Display, a new
window called Display Properties will appear, click on Name and Value then Ok. Close the
properties window. Set up a transient simulation from 0 to 100ns with a step size of 0.1ns. Once
you are in the setup window check the parametric sweep option and select Global Parameter,
type Var as the name and then select linear and type 10, 20 and 1 for the start value, end value
and increment, respectively. Perform the simulation.
RESULT:

Ex.No: 14 CLIPPERS & CLAMPERS
AIM:
To simulate the circuit Clippers and Clampers using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
1. Draw the circuit as per the circuit diagram.
2. Create a edit simulation title.
3. Select the type of analysis.
4. Create a new simulation file.
5. Simulate the file.
CIRCUIT DIAGRAM:
SERIS POSITIVE CLIPPER:
D1
0V 30.69e-21V
D1N4002
V V
V1 R1
VOFF = 0
VAMPL = 2 1k
FREQ = 300
0V
OUTPUT:

NETLIST:
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of pspiceev.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 10ms 0
.PROBE
.INC "clipper-SCHEMATIC1.net"
**** INCLUDING clipper-SCHEMATIC1.net ****
* source CLIPPER
D_D1 N00017 N00010 D1N4002
R_R1 0 N00017 1k
V_V1 N00010 0
+SIN 0 2 300 0 0 0
SERIES NEGATIVE CLIPPER:
D1
D1N4002
V V
V1 R1
VOFF = 0
VAMPL = 2 1k
FREQ = 300
0V

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 10ms 0
.PROBE
* source CLIPPER
D_D1 N00010 N00012 D1N4002
R_R1 0 N00012 1k
V_V1 N00010 0
+SIN 0 2 300 0 0 0

SHUNT POSITIVE CLIPPER:
R1
10K
V1
VOFF = 0
VAMPL = 2 D1N4002
FREQ = 300
D1
0V
OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 10ms 0
.PROBE

* source CLIPPER
D_D1 N00190 0 D1N4002
R_R1 N00190 N00010 10K
V_V1 N00010 0
+SIN 0 2 300 0 0 0
SHUNT NEGATIVE CLIPPER:
R1
0V
10K
V1
VOFF = 0
VAMPL = 2 D1
FREQ = 300
D1N4002
0V
OUTPUT:

NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 10ms 0
.PROBE
* source CLIPPER
D_D1 0 N00192 D1N4002
R_R1 N00192 N00255 10K
V_V1 N00255 0
+SIN 0 2 300 0 0 0
RESULT:

Ex.No: 15 TUNED COLLECTOR OSCILLATOR
AIM:
To simulate the Tuned Collector Oscillator using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
CIRCUIT DIAGRAM:
V1
7
L2
R1 1u C2
14k 220p
C1
Q1
70p
C5 V
L1 .026p Q2N2222
9.8m
C4 R2
R4 C3
6.3p 9k R3 R5
7 40n 10k
1k

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 2ms 0
.PROBE
.INC "tuned13-SCHEMATIC1.net"
**** INCLUDING tuned13-SCHEMATIC1.net ****
* source TUNED13
Q_Q1 N00036 N00147 N00028 Q2N2222
L_L1 N00139 N00142 9.8m

L_L2 N00036 N00095 1u
C_C1 N00036 N00057 70p
C_C2 N00036 N00045 220p
C_C3 0 N00028 40n
C_C4 0 N00147 6.3p
R_R1 N00042 N00045 14k
R_R2 0 N00042 9k
R_R3 0 N00028 1k
R_R4 0 N00139 7
R_R5 0 N00057 10k
V_V1 N00095 0 7
C_C5 N00142 N00147 .026p
RESULT:

Ex.No: 16A TWIN T OSCILLATOR
AIM:
To simulate the TWIN-T Oscillator using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
CIRCUIT DIAGRAM:
V1 R1
3.3k
9
Q1
Q2N3904
C1 R5
50n 100
V
R2 R3
18k
C3 18k
47n
C4 C2
0V
22n 22n
R4
1.5k
0A

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 100s 0
.PROBE
.INC "twinteee-SCHEMATIC1.net"
**** INCLUDING twinteee-SCHEMATIC1.net ****
* source TWINTEEE
Q_Q1 N00024 N00042 0 Q2N3904
R_R1 N000051 N00024 3.3k

R_R2 N00042 N00031 18k
R_R3 N00031 N00024 18k
R_R4 0 N00039 1.5k
R_R5 N00292 0 100
C_C1 N00031 N00292 50n
C_C2 N00039 N00024 22n
C_C3 0 N00031 47n
C_C4 N00042 N00039 22n
V_V1 N000051 0 9

Ex.No: 16B WEIN BRIDGE OSCILLATOR
AIM:
To simulate the WEIN BRIDGE Oscillator using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
CIRCUIT DIAGRAM:
5
V2
R1
R3 4.7k
R4
27k R6
39k
C1 4.7k
C2V
Q3 10u
Q4 10u
Q2N3904
Q2N3904
R7 R8 C3
3.3k 4.7k 10u
R2 R5
1k 22k

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 5s 0
.PROBE
.INC "wein1-SCHEMATIC1.net"
**** INCLUDING wein1-SCHEMATIC1.net ****
* source WEIN1
R_R1 N00034 N00091 4.7k
R_R2 0 N00031 1k

R_R3 N00085 N00091 27k
R_R4 N00045 N00091 39k
R_R5 0 N00045 22k
R_R6 N00142 N00091 4.7k
R_R7 0 N00144 3.3k
R_R8 0 N00085 4.7k
C_C1 N00034 N00045 10u
C_C2 N00085 N00142 10u
C_C3 0 N00085 10u
V_V2 N00091 0 5
Q_Q3 N00034 N00085 N00031 Q2N3904
Q_Q4 N00142 N00045 N00144 Q2N3904
RESULT:

Ex.No: 17 SINGLE TUNED AMPLIFIER
AIM:
To simulate the Single tuned Amplifier using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
5. To plot the frequency response of the amplifier use dB Magnitude of Voltage in
Advanced Markers.
CIRCUIT DIAGRAM:
10
V2
R3 R1
C3
55k 1k
Q1
C1
1u
R6
L1 VDB
1n 5k
Q2N2222 C5
2.8u
.009u
R4
19k
Q2
R7 C2
1k 1u
Q2N2222
1Vac R5
0Vdc R2 C4
10k
800 1u

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.AC DEC 100K 1 1000k
.PROBE
.INC "stuned-SCHEMATIC1.net"
**** INCLUDING stuned-SCHEMATIC1.net ****
* source STUNED
Q_Q1 N000031 N00048 N00030 Q2N2222
Q_Q2 N00030 N00052 N00094 Q2N2222

R_R1 N000031 N00055 1k
R_R2 0 N00094 800
R_R3 N00048 N00055 55k
R_R4 N00052 N00048 19k
R_R5 0 N00052 10k
R_R6 0 N00044 5k
R_R7 N00104 N00786 1k
C_C1 0 N00048 1n
C_C2 N00786 N00052 1u
C_C3 N000031 N00044 1u
C_C4 0 N00094 1u
L_L1 0 N00044 2.8u
C_C5 0 N00044 .009u
V_V1 N00104 0 DC 0Vdc AC 1Vac
V_V2 N00055 0 10
RESULT:

Ex.No: 18 STAGGER TUNED AMPLIFIER
AIM:
To simulate the Stagger Tuned Amplifier using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
Advanced Markers.
CIRCUIT DIAGRAM:
10
V2
R3 R1
C3
55k 1k
Q1
C1
1u
R6
L1 VDB
1n 5k
Q2N2222 C5
2.8u
.009u
R4 0A
19k
Q2
R7 C2
1k 1u
L2 C6 Q2N2222
1Vac R5
.88u .029u R2 C4
0Vdc 10k
800 1u

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.AC DEC 100k 1 1000000k
.PROBE
.INC "stuned-SCHEMATIC1.net"
**** INCLUDING stuned-SCHEMATIC1.net ****
* source STUNED
Q_Q1 N000031 N00048 N00030 Q2N2222

Q_Q2 N00030 N00052 N00094 Q2N2222
R_R1 N000031 N00055 1k
R_R2 0 N00094 800
R_R3 N00048 N00055 55k
R_R4 N00052 N00048 19k
R_R5 0 N00052 10k
R_R6 0 N00044 5k
R_R7 N00104 N00786 1k
C_C1 0 N00048 1n
C_C2 N00786 N00052 1u
C_C3 N000031 N00044 1u
C_C4 0 N00094 1u
L_L1 0 N00044 2.8u
C_C5 0 N00044 .009u
C_C6 0 N00786 .029u
L_L2 0 N00786 .88u
V_V2 N00055 0 10
RESULT:

Ex.No: 19 DOUBLE TUNED AMPLIFIER
AIM:
To simulate the Double Tuned Amplifier using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
Advanced Markers.
CIRCUIT DIAGRAM:
12.00V
R1 R2
10 40
C1
R4 L1 L2
1.25n
80k 1m .1m
C2
125p 12.00V K K1
V1 K_Linear
VDB
12.00V 12 COUPLING = .3
Q1
C4 4.615V
165.6mV
100n Q2N2222
0V 3.887nV
R3
V3
1Vac R5 150 C3
0Vdc 50k 10u
0V

OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
.lib "nom.lib"
.AC DEC 100k 1 1000k
.PROBE
.INC "double1-SCHEMATIC1.net"
**** INCLUDING double1-SCHEMATIC1.net ****
* source DOUBLE1
Q_Q1 N00033 N00028 N00075 Q2N2222
R_R1 N000051 N00043 10

R_R2 N000071 N00043 40
R_R3 0 N00075 150
R_R4 N00047 N00043 80k
R_R5 0 N00047 50k
L_L1 N00033 N000051 1m
L_L2 N00069 N000071 .1m
C_C1 N00069 N00043 1.25n
C_C2 N00033 N00043 125p
C_C3 0 N00075 10u
C_C4 N00111 N00028 100n
V_V1 N00043 0 12
Kn_K1 L_L1 L_L2 0.3
RESULT:

Ex.No: 20 ASTABLE MULTIVIBRATOR
AIM:
To simulate the circuit Astable multivibrator transistor bias using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
CIRCUIT DIAGRAM:
25Vdc
V1
R1 R2 R3 R4
C5 C6
1k 15k 15k 1k
.1u .1u
v c1 v c2
V
Q1 V
v b1
v b2
BC107A V
Q2 V BC107A
D1 D2
D1N4007 D1N4007
V1 = -4v C7 D3
0
V2 .01u
V2 = 4v R6
TD = 0s D1N4007
TR = 100ns 22k
TF = 100ns
PW = 500u 0 0
PER = 1ms

OUTPUT:
5.0V
2.5V
SEL>>
0V
V(Q2:c)
1.0V
0V
-1.0V
V(Q2:b)
10V
0V
-10V
V(Q1:c)
10V
0V
-10V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(Q1:b)
Time
NETLIST:
Q_Q1 VC2 VB2 N00027 BC107A
Q_Q2 VC1 VB1 N00022 BC107A
R_R1 VC1 N00035 1k
R_R2 VB2 N00035 15k
R_R3 VB1 N00035 15k
R_R4 VC2 N00035 1k
D_D3 VB2 N00502 D1N4007
C_C7 N00541 N00502 .01u
R_R6 0 N00502 22k
V_V2 N00541 0
+PULSE -4v 4v 0s 100ns 100ns 500u 1ms
V_V1 N00035 0 25Vdc

C_C5 VC1 VB2 .1u
C_C6 VB1 VC2 .1u
D_D1 N00022 0 D1N4007
D_D2 N00027 0 D1N4007
RESULT:

Ex.No: 20 BISTABLE MULTIVIBRATOR
AIM:
To simulate the circuit Bistable multivibrator transistor bias using ORCAD PSPICE
software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
CIRCUIT DIAGRAM:
0
V1
15Vdc
R3 R4
C3
2k C4 2k
1p
1p
R1 R2
VC1 100k 100k VC2

Q1
Q2 V
VB2
V
VB1
V
BC107A
BC107A V
C10 D12
.01u
V1 = -4v
V3 D1N4001
V2 = 4v 22k
TD = 0s C107
TR = 100ns 0
TF = 100ns R19
.01u
PW = 500us
PER = 1ms 22k
0
0

OUTPUT:
20V
10V
SEL>>
0V
V(Q1:c)
1.0V
0.5V
0V
V(Q1:b)
20V
10V
0V
V(Q2:c)
10V
0V
-10V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms 5.5ms 6.0ms 6.5ms 7.0ms 7.5ms 8.0ms
V(Q2:b)
Time
NETLIST:
** Creating circuit file "bist-SCHEMATIC1-fdg.sim.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN

BY SUBSEQUENT SIMULATIONS
*Libraries:
* Local Libraries :
.lib "nom.lib"
.TRAN 0 8ms 0
.PROBE

.INC "bist-SCHEMATIC1.net"
**** INCLUDING bist-SCHEMATIC1.net ****
* source BIST
Q_Q1 N00034 N00067 0 Q2N2222
Q_Q2 N00038 N00077 0 Q2N2222
R_R1 0 N00067 22k
R_R2 N00038 N00067 100k
R_R3 N00038 N00183 2k
R_R4 N00034 N00183 2k
R_R5 N00077 N00034 100k
R_R6 0 N00234 22k
C_C1 N00246 N00234 .01u
C_C2 N00077 N00034 1p
C_C3 0 N00067 .01u
D_D1 N00077 N00234 D1N4002
V_V1 N00246 0
+PULSE -4 4 0 100ns 100ns 500us 1ms
C_c4 N00038 N00067 1p
V_V2 N00183 0 15
RESULT:

Ex.No: 20 SCHMITT TRIGGER WITH PREDICTABLE HYSTERSIS
AIM:
To simulate the circuit Schmitt Trigger circuit using ORCAD PSPICE software and to plot
its hysersis curve.
SOFTWARE REQUIRED:
ORCAD PSPICE
CIRCUIT DIAGRAM:
NETLIST:
r_rin 1 2 50
r_rc1 0 3 50
r_r1 3 5 185
r_r2 5 8 760

r_rc2 0 6 100
r_re 4 8 260
r_rth2 7 0 85
c_cload 0 7 5pf
v_vee 8 0 dc -5
v_vin 1 0
+pwl 0 -8 1ms -1.0v 2ms -1.8v
r_rth1 8 7 125
q_q1 3 2 4 qstd
q_q2 6 5 4 qstd
q_q3 0 6 7 qstd
q_q4 0 6 7 qstd
.model qstd npn(is=1.0e-16 bf=100 br=0.1 rb=50 rc=10 tf=0.12ns tr=5ns
+ cje=0.4pf pe=0.8 me=0.4 cjc=0.5pf pc=0.8 mc=0.333 ccs=1pf va=50)
.TRAN .01ms 2ms
.probe
* plots the transient response
.END
PROCEDURE:
To Plot the hysteresis of Schmitt trigger the QSTD model can be used in PSPICE. As
QSTD model is not available in PSPICE library, for this experiment Netlist may be created and
executed in ORCAD capture.
1. Goto file menu in PSPICD A/D DEMO Student File New Text file

2. Type the above Netlist and save with the extension of “.cir” (circuit file)
3. To execute the circuit file, you can close the file and again open the file and click run.
4. Instead of using the DC sweep to look at the hysteresis, use the transient analysis, (Print
Step = .01ms and Final Time = 2ms) sweeping VIN from -1.8 volts to -1.0 volts and back
down to -1.8 volts, very slowly. This has two advantages:
it avoids convergence problems
it covers both the upward and downward transitions in one analysis
After the simulation, in the Probe window in PSpice , the X axis variable is initially set to be
Time. By selecting X Axis Settings from the Plot menu and clicking on the Axis Variable button,
you can set the X axis variable to be V(1). Then use Add on the Trace menu to display V(7), and
change the X axis to a user defined data range from -1.8V to -1.0V (Axis Settings on the Plot
menu). This plots the output of the Schmitt trigger against its input, which is the desired
outcome.
OUTPUT:
RESULT:

Ex.No: 23 MONOSTABLE BLOCKING OSCILLATOR
AIM:
To simulate the BLOCKING Oscillator using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
2. To choose transformer
Go to Part Place Analog XFRM
Double click on the transformer and give the Coupling coefficient as 1(maximum value is
1) and L1 =30H and L2=40H.
CIRCUIT DIAGRAM:
TX2
TX1
D1
V1 D1N4002 V
5
C1
R1 10n
R2
10
Q3 3k
Q2N2222
0V

OUTPUT:
NETLIST:
.TRAN 0 100ms 0
.PROBE
.INC "blocking1-SCHEMATIC1.net"
**** INCLUDING blocking1-SCHEMATIC1.net ****
* source BLOCKING1
K_TX1 L1_TX1 L2_TX1 1
L1_TX1 N00044 N00020 10H
L2_TX1 N00056 N00029 60H
K_TX2 L1_TX2 L2_TX2 1
L1_TX2 N00056 N00044 30H
L2_TX2 N00038 N00056 40H

Q_Q3 N000111 N00032 0 Q2N2222
R_R1 N000111 N00020 10
R_R2 N00032 N00038 3k
D_D1 N00029 N00119 D1N4002
V_V1 N00056 0 5
C_C1 0 N00119 10n
RESULT:

R.M.K COLLEGE OF ENGINEERING AND
TECHNOLOGY
R S M Nagar, Puduvoyal – 601 206
Department of Electronics and Communication Engineering
LAB MANUAL/ OBSERVATION BOOK
EC6411- CIRCUITS & SIMULATION LABORATORY

(REGULATION - 2013)
SECOND YEAR (IV – SEMESTER)
Prepared By
Mr.A.Manikandan, AP/ECE
&
Ms.N.G.Praveena, Asso. Prof/ECE
Name of the Student
Reg.No
Sec
SYLLABUS- EC6411/CIRCUITS & SIMULATION LAB
DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS:

1. Series and Shunt feedback amplifiers-Frequency response, Input and output impedance
calculation
2. RC Phase shift oscillator and Wien Bridge Oscillator
3. Hartley Oscillator and Colpitts Oscillator
4. Single Tuned Amplifier
5. RC Integrator and Differentiator circuits
6. Astable and Monostable multivibrators
7. Clippers and Clampers
8. Free running Blocking Oscillators
SIMULATION USING SPICE (Using Transistor):

1. Tuned Collector Oscillator
2. Twin -T Oscillator / Wein Bridge Oscillator
3. Double and Stagger tuned Amplifiers
4. Bistable Multivibrator
5. Schmitt Trigger circuit with Predictable hysteresis
6. Monostable multivibrator with emitter timing and base timing
7. Voltage and Current Time base circuits
CONTENT BEYOND SYLLABUS:

1. Clipper And Clamper using PSPICE
3. Monostable Multivibrators
List of Experiments
S.NO DATE NAME OF EXPERIMENT Date of MARKS SIGNATURE

Submission
1. Voltage Shunt Feedback Amplifier
2. Voltage Series Feedback Amplifier
3. Current Series Feedback Amplifier
4. RC Phase Shift Oscillator
5. Colpitts Oscillator
6. Hartley Oscillator
7. Wien Bridge Oscillator
8. RC Integrator And Differentiator
9. Astable Multivibrator
10. Monostable Multivibrator
12. Clippers And Clampers
USING PSPICE
13. STUDY OF PSPICE
14. Clippers And Clampers
15. Tuned Collector Oscillator
16. Twin -T Oscillator / Wein Bridge

Oscillator
18. Stagger Tuned Amplifiers
19. Double Tuned Amplifiers
20. Astable Multivibrators
21. Bistable Multivibrators
22. Schmitt Trigger with Predictable Hystersis
23. Monostable Blocking Oscillator

EC6411 CircuitsSimulation LAB

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EC6411 CircuitsSimulation LAB

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EC6411 – CIRCUITS & SIMULATION LAB

3 Capacitors 0.1µF, 22µF 1each

DEPARTMENT OF ECE RMKCET

5. Calculate the voltage gain Av.

B- Silicon C- AF power transistor Maximum voltage- 50V Operating frequency- 500KHz

B.WIT HOUT FEEDBACK

DEPARTMENT OF ECE RMKCET

Given Vcc=12v, Vce=5v, Ic=1mA

Step 1: To find Rc & Re

DEPARTMENT OF ECE RMKCET

DEPARTMENT OF ECE RMKCET

B.WITH FEEDBACK Vi=________volts

DEPARTMENT OF ECE RMKCET

S.NO COMPONENTS RANGE/TYPE QUANTITY

1. Connections are made as per the circuit diagram.

2. Set the biasing voltage, VCC=+12V1 using RPS.

3. Set the input voltage, 50mv sinusoidal using AFO.

5. Calculate the voltage gain Av.

6. Plot the frequency response and plot the bandwidth curve.

DEPARTMENT OF ECE RMKCET

Maximum voltage- 50V

Operating frequency- 500KHz

VOLT AGE SERIES FEEDBACK AMPLIFIER VCC=12V

100K 5.6K C2 100K 5.6K C3

BC547 BC547 Vout

Vin FREQ = (0-30MHz)

VAMPL = 1Vpp R2 Re1 R4 Re2

B.WIT H FEEDBACK VCC=12V

100K 5.6K C2 100K 5.6K C3

BC547 BC547 Vout

Vin Re1 FREQ = (0-30MHz)

VAMPL = 1Vpp R2 1.2K R4 Re2

DEPARTMENT OF ECE RMKCET

Given Vcc=12v, Vce=5v, Ic=1mA

Step 1: To find Rc & Re

Applying KVL to output loop,

Step 2: To find R1 & R2

Step 3: To find Ce, C1 & C2

Choose C1 & C2 = 0.1µf & XCe= 0.01Re

DEPARTMENT OF ECE RMKCET

A.WITHOUT FEEDBACK Vi=________volts

Frequency in Hz Output voltage Vo in volts Gain Av=Vo/Vi Gain in dB =20log AV

DEPARTMENT OF ECE RMKCET

B.WITH FEEDBACK Vi=________volts

Frequency in Hz Output voltage Vo in volts Gain Av=Vo/Vi Gain in dB =20log AV

Without feedback bandwidth = KHz

With feedback bandwidth = KHz

DEPARTMENT OF ECE RMKCET

S.NO COMPONENTS RANGE/TYPE QUANTITY

2 Resistors 2.2KΩ, 1KΩ, 100 KΩ, 22 KΩ 1each

3 Capacitors 0.1µF, 4.7µF,0.1 µF 1 each

6 CRO (0.20) MHz DUAL 1

8 Connecting wires - As required

1. Connections are made as per the circuit diagram.

2. Set the biasing voltage, VCC=+12V1 using RPS.

3. Set the input voltage, 50mv sinusoidal using AFO.

DEPARTMENT OF ECE RMKCET

5. Calculate the voltage gain Av.

6. Plot the frequency response and plot the bandwidth curve.

B- Silicon C- AF power transistor Maximum voltage- 50V

Operating frequency- 500KHz Power- (0-5)w Current- (0-1)A

CURRENT SERIES FEEDBACK AMPLIFIER

B.WIT H FEEDBACK VCC=12V

DEPARTMENT OF ECE RMKCET