Topics

p
ECE385 z Programmable Logic
DIGITAL SYSTEMS LABORATORY „ PLAs,
PLAs PLDs,
PLDs FPGAs
z Design Description Languages
z Introduction
I t d ti to t VHDL
Lecture „ Logic Value System of VHDL
„ Entity
E tit
Introduction to VHDL „ Architecture
„ Concurrent
C S
Statements

© Janak H H. Patel
Department of Electrical and Computer Engineering
y of Illinois at Urbana-Champaign
University p g

Programmable
g Logic
g PLDs and FPGAs
z Programmable Logic Arrays (PLAs) and PALs z Speed
„ Two-level AND-OR array with True and „ PLDs give predictable timing
timing, and give higher
Complemented inputs system clock frequency
‹ Primarily used in large chip designs „ FPGA clock frequency
q y is design
g dependent
p and
z Programmable Logic Devices (PLDs) usually much slower than PLDs
„ A variety of proprietary designs consisting of z Size
severall PLA lik
like bl
blocks
k andd programmable
bl „ PLDs can accommodate up to 10,000 gates
switches to interconnect them „ FPGAs can accommodate up to 25 million gates
z Field Programmable Gate Arrays (FPGAs) z Design
D i fl flexibility
ibilit
„ Thousands of identical macro-cells that can be „ FPGAs often come with large memory and
interconnected by y programmable
p g switches predefined function units
„ Each macro-cell is a Programmable Logic Gate z Manufacturers
‹ Truth Table is stored in a RAM, called the Look-up „ Xilinx, Altera, Lucent, Cypress, Lattice
T bl (LUT)
Table
3 4

Hardware Description
p Languages
g g VHDL
z Two Widely Used Languages z Uses 9 Signal Values (IEEE standard)
„ Verilog HDL „ A Signal Val
Value
emmust
st be enclosed in single q
quotes
otes
‹ C-language like syntax, easy to learn ‹ ‘0’ -- Forcing 0
„ VHDL ‹ ‘1’
1 -- Forcing 1
‹ VHSIC Hardware Description Language
‹ ‘X’ -- Forcing Unknown
‹ VHSIC - Very High Speed Integrated Circuits
‹ ‘-’
- -- Don
Don’tt Care
‹ Follows the structure of ADA programming
Language ‹ ‘Z’ -- High Impedance

‹ Originally intended as a Simulation Language for ‹ ‘U’

U -- Uninitialized
very large systems ‹ ‘L’ -- Weak 0
‹ Very Strongly Typed Language, for example, bit ‹ ‘H’ -- Weak 1
vector
t “0011” and d integer
i t ‘3’ are nott easily
il
interchangeable „ Bit Vectors are enclosed in double quotes
„ Verilog and VHDL each have about 50% share of „ An example
p of VHDL assignment
g statement
the commercial user base Y <=‘1’ when STATE =“0101” else ‘0’;
5 6
 Entities and Architectures 4-to-1 Multiplexer
p ((behavioral))
z Entity library IEEE; -- libraries needed for
„ External View: Pin
Pin-Out
Out description, Interface use IEEE.std_logic_1164.all; -- simple logic functions
description, Input-Output Port definition etc. entity mux is
port (sel: in std_logic_vector(1 downto 0);
z Architecture
Din: in std
std_logic_vector
logic vector (3 downto 0);
„ Internal View Dout: out std_logic);
‹ StructuralDescription - e.g. Gates and wires end entity mux;
‹ Behavioral
B h i l D
Description
i ti - e.g. functions
f ti andd processes, architecture my_mux_behavior of mux is
RTL description, if-then-else, Add, Subtract begin -- all comments are preceded by two dashes
Dout <
<= Din(3) when sel 11 else -- first evaluate this
sel=“11”
4 Din(2) when sel=“10” else -- next evaluate this
ENTITY mux Din(1) when sel=“01” else -- then evaluate this
Din
Din(0) when sel=“00” else -- then h evaluate
l this
h
2 ARCHITECTURE
Dout ‘X’; -- if all fails then X
sel end architecture my
y_mux_behavior; ;
(“when <condition> else” construct forces a priority structure in hardware synthesis)
7 8

4-to-1 Multiplexer (better behavioral) 4-to-1 Multiplexer

p using
gggates
library IEEE; s1bar s0bar
use IEEE.std_logic_1164.all; Din(3)

entity mux is
Din(2)
port (sel: in std_logic_vector(1 downto 0);
Din: in std
std_logic_vector
logic vector (3 downto 0); Dout =
Di (1)
Din(1)
Dout: out std_logic); Din(3)●sel(1)●sel(0) +
Din(2)●sel(1)●s0bar +
end entity mux; Din(0)
Din(1)
( )●s1bar●sel(0)
( )+
architecture behavior of mux is Din(0)●s1bar●s0bar
begin
with sel select
sel(1) sel(0)
Dout <= Din(3) when “11”, -- there is no specific order under
architecture structure of mux is
Din(2) when “10”, -- which conditions are evaluated signal s0bar, s1bar; std_logic; -- internal signals
Din(1)
i (1) when
h “01”
“01”, b i
begin
s0bar <= not(sel(0));
Din(0) when “00”, s1bar <= not(sel(1));
‘X’ when others; --“default case” must be included Dout <= (Din(3) and sel(1) and sel(0)) or
(Din(2) and sel(1) and s0bar) or
end architecture behavior; (Din(1) and s1bar and sel(0)) or
(Din(0) and s1bar and s0bar);
(“with <signal> select” construct results in better optimized hardware in synthesis) 9 end architecture structure; 10

4-to-1 Multiplexer
p ((Structural)) A Note about Libraries
library IEEE;
z In almost all designs from now on, we will use the
use IEEE.std_logic_1164.all;
entity mux is
following Libraries
port (sel: in std_logic_vector(1 downto 0); „ library IEEE;
Din: in std
std_logic_vector
logic vector (3 downto 0); „ use IEEE
IEEE.STD_LOGIC_1164.ALL;
STD LOGIC 1164 ALL;
Dout: out std_logic);
„ use IEEE.STD_LOGIC_ARITH.ALL;
end entity mux;
architecture structure of mux is „ use IEEE
IEEE.STD_LOGIC_UNSIGNED.ALL
STD LOGIC UNSIGNED ALL
signal s0bar, s1bar; std_logic; -- internal signals z These libraries permit use of predefined logic
g
begin -- ffollowingg three are concurrent signal
g assignments
g (CSAs)
( ) values logic operations like AND,
values, AND OROR, and
s0bar <= not(sel(0)); -- these are not executed sequentially
s1bar <= not(sel(1)); -- order of these CSAs is unimportant!
arithmetic operations like + (add) etc.
Dout <
<= (Din(3) and sel(1) and sel(0))or
(Din(2) and sel(1) and s0bar) or
(Din(1) and s1bar and sel(0)) or
(Din(0) and s1bar and s0bar);
end architecture structure;
11 12
 A Bit-Serial Logic
g Unit Behavioral of Logic
g Processor
architecture Behavioral of compute is
F2-F0 begin
with F select
F_A_B <= A_In and B_In when "000",
A_out A_In or B_In when "001",,
A in
A_in
One-bit wide F_A_B
A_In xor B_In when "010",
B_in Logic Unit '1' when "011",
“compute”
compute A In nand B_In
A_In B In when "100",
100 ,
B_out A_In nor B_In when "101",
entity compute is A_In xnor B_In when "110",
Port ( F : in std
std_logic_vector(2
logic vector(2 downto 0); '0' when others; -- must be included
A_In, B_In : in std_logic; A_Out <= A_In;
A_Out, B_Out : out std_logic; B_Out <= B_In;
F A B : out
F_A_B o t std
std_logic);
logic)
end entity compute; end architecture Behavioral;

13 14

Concurrencyy in VHDL Sequential

q Circuit Example
p
z Concurrent Signal Assignments (CSA) entity up_down_counter is
„ All statements in a VHDL description are e executed
ec ted port
t (
(clk,
lk enable,
bl up_down
d : in
i std_logic;
td l i
concurrently unless specified within a process asynch_clr: in std_logic;
„ Concurrency is useful in describing combinational Q: out std
std_logic_vector(7
logic vector(7 downto 0);
logic circuits end entity;

„ A concurrent statement is evaluated when any of

its arguments change its value enable
z A process executes only on specified triggers up
p_down
asynch_clr
8 bit Up-Down
8-bit U D C
Counter
t
„ A process declaration includes a sensitivity list
clk
„ A process executes only when one of the
arguments in the sensitivity list changes Q(7) Q(6) . . . . . Q(1)Q(0)
„ Processes are useful in describing g sequential
q
circuits and state transition diagrams
15 16

Counter Behavior Sequential

q Circuit Example-2
p
architecture counter_behavior of up_dn_counter is
signal count: std_logic_vector(7 downto 0); entity up_down_counter is
Begin -- count is an internal signal to this process port
t (
(clk,
lk enable,bl up_down
d : in
i std_logic;
td l i
process(clk, asynch_reset) -- sensitivity list
synch_clr: in std_logic;
begin
if (asynch
(asynch_reset=
reset=‘1’)1 ) then count <= “00000000”;00000000 ; Q: buf std
std_logic_vector(7
logic vector(7 downto 0);
elsif (rising_edge(clk)) then – synchronous state transitions -- ‘buf’ is same as ‘out’ but can be read inside the process
if (enable=‘1’) then
end entity;
if (up
(up_down
down=‘1’)
1 ) then count < <= count+
count+”00000001”;
00000001 ;
else count <= count-”00000001”;
end if; enable
end if;
; up
p_down
-- ‘end if’ is not permitted here to match ‘elsif’ synch_clr
8 bit Up-Down
8-bit U D C
Counter
t
end if;
end process;
p clk
Q <= count;
Q(7) Q(6) . . . . . Q(1)Q(0)
end architecture counter_behavior;

Note: We cannot use “Q <= Q + 1” since Q is defined as output only

17 18
 Counter Behavior-2 4-Bit Shift Register
g
architecture counter_behavior of up_dn_counter is
begin entity reg_4 is
process(clk, synch_reset) -- sensitivity list Port (Shift_In, Load, Shift_En, Clk : in std_logic;
begin D : in std_logic_vector(3 downto 0);
if (rising_edge(clk)
_ then Shift_Out : out std_logic;
g
if(synch_reset=‘1’) then Q <= “00000000”; Data_Out : out std_logic_vector(3 downto 0);
elsif (enable=‘1’) then --notice no ‘e’ in ‘elsif’ end entity reg_4;
if (
(up
p_down=‘1’) ) then Q <= Q + ’1’
else Q <= Q - ’1’;
end if; 4
if is not permitted here to match the “elsif”
end if”
-- “end elsif D
4
end if; Shift_In Data_Out
end if; -- notice it is ‘end if’ not ‘endif’ 4-Bit Register
end process; Load reg_4
“reg 4” Shift Out
Shift_Out
end architecture counter_behavior; Shift_En
Clk

19 20

Shift-Register
g Behavior Control Unit
architecture Behavioral of reg_4 is
signal reg_value: std_logic_vector(3 downto 0); entity control is
b i
begin Port ( Reset, LoadA, LoadB, Execute : in std_logic;
operate_reg: process (Load, Shift_En, Clk, Shift_In) Clk : in std_logic;
begin Shift_En,
_ Ld_A,
_ Ld_B
_ : out std_logic);
_
if (rising_edge(Clk)) then end entity control;
if (Shift_En = '1') then
g_value <= Shift_In & reg
reg g_value(3 ( downto 1); ) Input switches
-- operator “&” concatenates two bit-fields C
Control
l Bi
Bits
Reset
elsif (Load = '1') then Shift_En
< D; -- parallel load (lower priority than shift)
reg value <=
reg_value LoadA
Control
else LoadB (state machine) Ld_A
reg_value <= reg_value; --keep data unchanged Execute
end if;
Clk Ld_B
end if;
end process;
0
Data_Out
D t O t <<= reg_value;
l 0 1 d d d d 1
Shift_Out <= reg_value(0);
A B C D E F
end architecture Behavioral; 21 Reset Shift Shift Shift Shift Halt 22

Controller State Machine State Transitions

get_next_state: process (Execute, state)
architecture Behavioral of control is begin
type cntrl_state
cntrl state is (A, B, C, D, E, F); case state is
when A =>
-- User defined type “cntrl_state” has 6 symbolic values if (Execute = '1') then
signal state, next_state : cntrl_state; next_state <= B;
else
begin next_state <= A;
control_reg: process (Reset, Clk, LoadA, LoadB) end if;
begin when B => next_state <= C;
when C => next_state <= D;
if (Reset = '1') then when D => next_state <= E;
state <= A; when E => next_state <= F;
_
elsif (rising_edge(Clk)) then --wait at state F until 'Execute' = 0
when F =>
state <= next_state; if (Execute = '0') then
end if; next_state <= A;
else
end process;
p ; next state <= F;
next_state
-- Behavioral continued on next two slides for Next State and Output Functions end if;
-- “when others =>” default case is not needed here since there are
-- only six values for “state” and we have exhausted them all.
end case;
See Sequence Recognizer Example in Mano and Kime (ECE 290 Text Book) end process;
23 24
 Outputs
p ((Moore machine)) State Machine Encoding
g
get_cntrl_out: process (LoadA, LoadB, state)
begin z State Machine Encoding and Synthesis
case state is „ Synthesis
S nthesis automatically
a tomaticall picks the “best” encoding
when A =>
-- Enable Register-Loads only when in state A „ Or, you can specify the encoding for your state
Ld_A <= LoadA;
Ld_B <= LoadB; machine explicitly
Shift_En <= '0’; „ Examples of State Encodings (for 5 States)
when
h F => Ld
Ld_A
A <= '0'
'0'; Ld_B
Ld B <= '0'
'0'; ‹ ArbitraryBinary Encoding: 011,
011 101
101, 000
000, 111
111, 010
Shift_En <= '0'; ‹ Enumerated Binary: 000, 001, 010, 011, 100
when others => -- “others”
others are states B,C,D
B C D and E ‹ One
One-Hot:
Hot: 00001,
00001 00010,
00010 00100
00100, 01000
01000,10000
10000
Ld_A <= '0'; Ld_B <= '0';
Shift_En <= ‘1'; „ See VHDL example code from Xilinx
„ http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex9.html
p
end case;
end process;

end architecture Behavioral; -- started

d on page 23
25 26

Using
g “Components”
p Connecting
g Components
p
entity full_adder is architecture structural of ADDER4 is
port (x, y
p y, z : in std_logic);g component full_adder is
x y z
s, c : out std_logic); full_adder port(x,y,z:
t( i std_logic;
in td l i s,c: outt std_logic);
td l i ) -- reproduce
d the
h entity ddescription
end entity; end component full_adder; -- omit name “full_adder” for older simulators
c s
-- we will use the component full_adder to signal c0,c1,c2: std_logic; -- internal wires needed to connect full adders
-- build a 4-bit ripple carry adder carry sum
begin -- this illustrates how to instantiate and connect components
entity ADDER4 is FA0: full_adder port map(x =>A(0), y =>B(0), z =>c_in, s =>S(0), c =>c0);
port (A
(A,B
B : in std
std_logic_vector
logic vector (3 down to 0); FA1: full_adder p port map(x
p( =>A(1),
( ), y =>B(1),
( ), z =>c0,, s =>S(1),
( ), c =>c1); );
S : out std_logic_vector (3 down to 0); FA2: full_adder port map(x =>A(2), y =>B(2), z =>c1, s =>S(2), c =>c2);
c_in : in std_logic; FA3: full_adder port map(x =>A(3), y =>B(3), z =>c2, s =>S(3), c =>c_out);
c_out
t : out
t std_logic);
td l i ) end architecture structural ADDER4
end entity; A3 B3 A2 B2 A1 B1 A0 B0
x y x y x y x y c_in
A3 B3 A2 B2 A1 B1 A0 B0 c_out FA3 c2 c1 c0
c_out c z c FA2 z c FA1 z c FA0 z
ADDER4 c_in s s s s
S3 S2 S1 S0
S3 S2 S1 S0
27 28

Putting
g it all together
g Architecture of my_system
y_ y
architecture structural of my_system is
entity my_system component compute is -- entity description reproduced
6 port(A in B_in:
port(A_in, B in: in std std_logic;
logic; F2-F0
A_out
D 6 A_out, B_out, F_A_B: out std_logic; A_inentity
A F: in std_logic_vector(2 downto 0)); compute F_A_B
3 end component compute; B in
B_in B out
B_out

F Register Compute 6 component register_unit is

Unit Unit ... -- reproduce entity description here
2
B component router is
... -- reproduce entity description here
R component control is
LoadA ... -- reproduce
p entityy description
p here
Routing
R ti Control
C t l
LoadB
end component control;
Unit Unit
signal ...; –- declare all signals needed to interconnect components
Execute begin
Reset ... -- instantiate and connect all components in main body
computation_unit: compute
Clock port map(F=>F, A_in=> ..., B_in=>..., F_A_B=>...);
...
end architecture structural my_system;
29 30
 Summaryy
z VHDL is a design description language – not a
language that automatically designs for you!
„ The design process is very similar to the designing
with TTL chips and wires, but with much more
fl ibili and
flexibility d ffunctionality
i li
„ In VHDL you create your own “chips” (entities) and
connect the “pins”
pins (ports) with “wires”
wires (signals)
„ You cannot make bigger TTL chips out of smaller
chips,
p , but with VHDL you y can make biggergg and
more complex entities out of smaller entities (e.g. a
16-bit ALU out of 16 one-bit ALU slices)
ÎY mustt fi
ÎYou firstt design
d i on paper using i block
bl k
diagrams and interconnections, before you can
describe it in VHDL!

31