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By
MICROELECTRONICS TRACK 3
Bachelor of Science in
Electronics Engineering
EXERCISE I: LED AND PUSH BUTTON
The objective for this exercise is simple by knowing how to program so that
the LEDG0 on the FPGA board would light up and when the KEY0 is pressed, the
light on LEDG0 would turn off.
input CLOCK_50;
input [3:0] PB;
reg [9:0] state;
output [7:0] LEDG;
endmodule
Figure 1 The LEDG0 on the Photo is lit up and When the KEY0 is pressed, the LEDG0 would turn off
The exercise aims to design a Verilog program that controls the LEDG0
LED with the use of a push button specifically, the KEY1 push button. When KEY1
is pressed and LEDG0 LED is turned on, it will light up. However, when KEY0 is
pressed and LEDG0 is lit up, it will turn off.
TCL Script:
set_location_assignment PIN_R22 -to PB[0]
set_location_assignment PIN_R21 -to PB[1]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_U22 -to LEDG\[0\]
set_location_assignment PIN_U21 -to LEDG\[1\]
set_location_assignment PIN_V22 -to LEDG\[2\]
set_location_assignment PIN_V21 -to LEDG\[3\]
set_location_assignment PIN_W22 -to LEDG\[4\]
set_location_assignment PIN_W21 -to LEDG\[5\]
set_location_assignment PIN_Y22 -to LEDG\[6\]
set_location_assignment PIN_Y21 -to LEDG\[7\]
Photos:
This exercise aims to design a Verilog program that controls the blinking of
all the LEDs (LEDG0 – LEDG7) in the DE1 starter kit. The LEDs should blink every
half a second or 0.5 seconds at the same time.
input CLOCK_50;
input [3:0] PB;
reg [7:0] state;
reg [23:0] counter;
output [7:0] LEDG;
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
Photos:
Figure 5 All of the LEDG LEDs light up and blinking for 0.5 seconds
EXERCISE IV: LED PATTERN
This exercise aims to design a Verilog program that outputs the pattern below
using the LEDs.
The transition interval for each set is 0.5 seconds. A colored dot means that the
corresponding LED lights up.
input CLOCK_50;
input [3:0] PB;
reg [3:0] state_1;
reg [3:0] state_2;
reg [23:0] counter;
output [3:0] LEDG1;
output [7:4] LEDG2;
endcase
endcase
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
input CLOCK_50;
input [3:0] PB;
reg [3:0] state1;
reg [3:0] state2;
reg [23:0] counter;
output [3:0] LEDG1;
output [7:4] LEDG2;
parameter a0 = 4'b0000;
parameter a1 = 4'b1000;
parameter a2 = 4'b0100;
parameter a3 = 4'b0010;
parameter a4 = 4'b0001;
parameter b0 = 4'b0000;
parameter b1 = 4'b1000;
parameter b2 = 4'b1100;
parameter b3 = 4'b1110;
parameter b4 = 4'b1111;
parameter b5 = 4'b0001;
assign LEDG1 = state1;
assign LEDG2 = state2;
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
This exercise aims to design a Verilog program that outputs the number “4”
to the seven-segment display in the DE1 Starter Kit.
input CLOCK_50;
input [3:0] PB;
reg [6:0] number;
output [7:0] HEX0, HEX1, HEX2, HEX3;
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
Photos:
This exercise aims to design a Verilog program that outputs the numbers
letters “bESt” to the seven-segment display in the DE1 starter Kit.
input CLOCK_50;
input[2:0] PB;
reg[6:0] lettera, letterb, letterc, letterd;
output[7:0] HEX0, HEX1, HEX2, HEX3;
parameter O = 7'b0000011;
parameter T = 7'b0000110;
parameter Th = 7'b0010010;
parameter F = 7'b0000111;
begin
lettera <= 7'h7F;
letterb <= 7'h7F;
letterc <= 7'h7F;
letterd <= 7'h7F; end
else
begin
lettera <= F;
letterb <= Th;
letterc <= T;
letterd <= O; end
endmodule
TCL Script:
set_location_assignment PIN_D1 -to HEX1[6]
Photos:
This exercise aims to design a Verilog program that outputs 0000 to 9999 to
the seven-segment display in the DE1 Starter Kit with a 0.1 second interval.
input CLOCK_50;
input[3:0] PB;
output[7:0] HEX0, HEX1, HEX2, HEX3;
reg[22:0] counter;
reg[6:0] number0, number1, number2, number3;
parameter n1 = 7'b1111001;
parameter n2 = 7'b0100100;
parameter n3 = 7'b0110000;
parameter n4 = 7'b0011001;
parameter n5 = 7'b0010010;
parameter n6 = 7'b0000010;
parameter n7 = 7'b1111000;
parameter n8 = 7'b0000000;
parameter n9 = 7'b0010000;
parameter n0 = 7'b1000000;
endcase
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
Figure 11 The Counter counting from 0000 to 9999 in the four Seven-Segment Display with 0.1 second interval
EXERCISE IX: COUNTER WITH CONTROLS
This exercise aims to design a Verilog program that outputs 0000 to 9999 to
the seven-segment display in the DE1 Starter Kit with a 0.1 second interval when
the SW0 switch is off. When the SW0 is on, the output number will increment by 1
if SW1 is pressed and it will decrement by 1 if SW2 is pressed.
input CLOCK_50;
input[3:0] PB;
input[9:0] SW;
output[7:0] HEX0, HEX1, HEX2, HEX3;
reg[22:0] counter;
reg[6:0] number0, number1, number2, number3;
reg hold;
reg add;
reg sub;
reg rst;
parameter n1 = 7'b1111001;
parameter n2 = 7'b0100100;
parameter n3 = 7'b0110000;
parameter n4 = 7'b0011001;
parameter n5 = 7'b0010010;
parameter n6 = 7'b0000010;
parameter n7 = 7'b1111000;
parameter n8 = 7'b0000000;
parameter n9 = 7'b0010000;
parameter n0 = 7'b1000000;
initial
begin
number0 <= n0;
number1 <= n0;
number2 <= n0;
number3 <= n0;
rst = 0;
end
endcase
end
endcase
else if (counter == 5_000_000 && rst == 0 && hold ==
0 && sub == 1)
case (number0)
n9: begin
number0 <= n8;
rst <= 1;
end
n8: begin
number0 <= n7;
rst <=1;
end
n7: begin
number0 <= n6;
rst <=1;
end
n6: begin
number0 <= n5;
rst <=1;
end
n5: begin
number0 <= n4;
rst <=1;
end
n4: begin
number0 <= n3;
rst <=1;
end
n3: begin
number0 <= n2;
rst<=1;
end
n2: begin
number0 <= n1;
rst<=1;
end
n1: begin
number0 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
case (number1)
n9: begin
number1 <= n8;
rst<=1;
end
n8: begin
number1 <= n7;
rst<=1;
end
n7: begin
number1 <= n6;
rst<=1;
end
n6: begin
number1 <= n5;
rst<=1;
end
n5: begin
number1 <= n4;
rst<=1;
end
n4: begin
number1 <= n3;
rst<=1;
end
n3: begin
number1 <= n2;
rst<=1;
end
n2: begin
number1 <= n1;
rst<=1;
end
n1: begin
number1 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
case (number2)
n9: begin
number2 <= n8;
rst <=1;
end
n8: begin
number2 <= n7;
rst <=1;
end
n7: begin
number2 <= n6;
rst <=1;
end
n6: begin
number2 <= n5;
rst <=1;
end
n5: begin
number2 <= n4;
rst <=1;
end
n4: begin
number2 <= n3;
rst <=1;
end
n3: begin
number2 <= n2;
rst <=1;
end
n2: begin
number2 <= n1;
rst <=1;
end
n1: begin
number2 <= n0;
rst <=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
number2 <= n9;
case (number3)
n9: begin
number3 <= n8;
rst<=1;
end
n8: begin
number3 <= n7;
rst<=1;
end
n7: begin
number3 <= n6;
rst<=1;
end
n6: begin
number3 <= n5;
rst<=1;
end
n5: begin
number3 <= n4;
rst<=1;
end
n4: begin
number3 <= n3;
rst<=1;
end
n3: begin
number3 <= n2;
rst<=1;
end
n2: begin
number3 <= n1;
rst<=1;
end
n1: begin
number3 <= n0;
rst<=1;
end
n0: begin
number0 <= n9;
number1 <= n9;
number2 <= n9;
number3 <= n9;
end
endcase
end
endcase
end
endcase
end
endcase
endmodule
TCL Script:
set_location_assignment PIN_L1 -to CLOCK_50
Figure 12 When SW0 is turned ON, the Counter will count from 0000 to 9999 by 0.1 seconds interval. But When
SW0 is turned OFF, the counter pauses.
Figure 13 Increment of 1 if SW1 is turned ON while SW0 is turned off.
Figure 14 Decrement of 1 if SW2 is turned ON while SW0 is turned OFF
EXERCISE XI: VGA DISPLAY
input CLOCK_50;
output[3:0] VGA_R, VGA_G, VGA_B;
output VGA_HS, VGA_VS;
reg[9:0] counter_HS;
reg[8:0] counter_VS;
reg vga_HS, vga_VS, clk;
reg[3:0] VGA_R, VGA_G, VGA_B;
Photos:
Figure 15 The Default Screen Display of the FPGA Board connected to the Monitor Via the VGA port. This screen
will appear as a start-up configuration with no codes compiled and programmed to the board yet.
Figure 16 The output of the Verilog Code will all of the Possible Color Combination Was seen on the display.