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of a Digital System
involved in a human
temperature
measuring device
Design features:
1. Storing capability of eight
temperature readings and corresponding
time.
2. Programmable alarm for intimating the
user to take the temp reading.
3. Programmable timer which display the
real time.
Din[7:0]
sysclk D
I Yout[7:0]
reset
G
ret0 I
ret1 T En[3:0]
A
set
L
rwm One Hz
live T
H
autos Alarm_led
E
Ti/temp R
s0 M sc1
O
s1
M
s2 E sc0
s3 T
E
s4 Led_auto
R
s5
s6
Direction Pin Assignment on FPGA Functional Description
Name
Top Module:
module dtm
(Din,sysclk,resetn,onehtz,ret0,ret1,sc0,sc1,set,rwm,live,autos,autoled,titemp,En,Yout,s0,s1,
s2,s3,s4,s5,s6,aled);
input sysclk,resetn,ret0,ret1,rwm,live,autos,titemp,set,s0,s1,s2,s3,s4,s5,s6;
input [7:0]Din;
output onehtz,sc0,sc1,autoled,aled;
output [3:0] En;
wire[2:0]add;
output [7:0]Yout;
wire [15:0] H,out16,In;
wire [7:0] out8;
wire [11:0]B;
wire [15:0]U;
wire ret0t,ret1t,ret0a,ret1rw,rd,wr,autoled,auto,b,onehtz,sw,tt;
assign autoled=auto;
assign U={1'b0,add,B};
assign onehtz=b;
endmodule
TIMER
module timer(resetn,ret0,ret1,sysclk,scan0,scan1,b,H);
input resetn,sysclk,ret0,ret1;
output [15:0]H;
output b,scan0,scan1;
wire[7:0]min;
wire[7:0]hrs;
wire b;
wire un1,un2,un3,pro;
wire [3:0] TENS1,ONES1,TENS0,ONES0;
wire [15:0] H;
assign un2=scan0;
assign H={TENS1,ONES1,TENS0,ONES0};
endmodule
Clock_divider(timer)
1minute pulse
One Hz
module div11(cl1,out1);
input cl1;
output out1;
reg out1;
integer n;
always@(posedge cl1)
begin
n <= n+1;
if(n<3000000)
out1 = 1;
else if (n<6000000)
out1 =0;
else
n <=0;
end
endmodule
always@(posedge cl2)
begin
no <= no+1;
if(no<30)
out2 = 1;
else if (no<60)
out2 =0;
else
no <=0;
end
endmodule
//time dividers for setting the time( Time set clock dividers)
xor x (ac2,aa,ab);
muxes mu1 (in5,in300,ac1,ac3);
muxes mu2 (mi1,ac3,ac2,outm);
endmodule
module mhg(clkin,reset,HR,MN);
input clkin,reset;
output [7:0]HR,MN;
wire cn;
assign d1 = {B[6:3]};
assign d2 = {c1[2:0],B[2]};
assign d3 = {c2[2:0],B[1]};
add3t C1 (d1,c1);
add3t C2 (d2,c2);
add3t C3 (d3,c3);
always@(AI)
begin
case(AI)
0:BI = 4'b0000;
1:BI = 4'b0001;
2:BI = 4'b0010;
3:BI = 4'b0011;
4:BI = 4'b0100;
5:BI = 4'b1000;
6:BI = 4'b1001;
7:BI = 4'b1010;
8:BI = 4'b1011;
9:BI = 4'b1100;
default:BI=4'b0000;
endcase
end
endmodule
Memory Module
MEMORY 8*8
MEMORY 8*16
module memory16(Din,ad,rd,wr,Yout,clk);
input clk,rd,wr;
input [15:0]Din;
input [2:0] ad;
output [15:0]Yout;
wire [7:0] al;
decoder16 cas0 (ad,al);
ram16 cas1 (al,wr,rd,clk,Din,Yout);
endmodule
//A special algorithm called “add-3 shift” is used here for the
conversion of binary to BCD
//A special algorithm called “add-3 shift” is used here for the
conversion of binary to BCD
C is a combinational circuit which will generate the output as
per the input values. If the input is more than or equal to 5
,the logic will add 3 to the input and sum will be the output
otherwise(Input<5)output will be the same input. Let us try one
example.
module bbc8 (Dout,B);
input[7:0]Dout;
output[11:0]B;
wire [11:0] B;
wire [3:0]c1,c2,c3,c4,c5,c6,c7;
wire[3:0]d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,Dout[7:5]};
assign d2 = {c1[2:0],Dout[4]};
assign d3 = {c2[2:0],Dout[3]};
assign d4 ={c3[2:0],Dout[2]};
assign d5= {c4[2:0],Dout[1]};
assign d6= {1'b0,c1[3],c2[3],c3[3]};
assign d7={c6[2:0],c4[3]};
add3 C1 (d1,c1);
add3 C2 (d2,c2);
add3 C3 (d3,c3);
add3 C4 (d4,c4);
add3 C5 (d5,c5);
add3 C6 (d6,c6);
add3 C7 (d7,c7);
assign B={2'b00,c6[3],c7[3:0],c5[3:0],Dout[0]};
endmodule
Alarm Generating section
Timer Data
R/W R
Memory
W +
Clock Comparat
ors
Addr Alarm
LED
Mode
always@(AI)
begin
case(AI)
0:BI = 4'b0000;
1:BI = 4'b0001;
2:BI = 4'b0010;
3:BI = 4'b0011;
4:BI = 4'b0100;
5:BI = 4'b1000;
6:BI = 4'b1001;
7:BI = 4'b1010;
8:BI = 4'b1011;
9:BI = 4'b1100;
default:BI=4'b0000;
endcase
end
endmodule
We can store 8 times in 8 registers that we need for alarms.8 comparators are
also using for the comparison between the current time and stored time. Mode
will enable the data out from the different registers to comparator
For example if we select the mode 7 ,alarm will give for all times that we
stored in the registers.
DISPLAY SECTION
module ssdd (In,Out,sysclk,En);
input [15:0] In;
input sysclk;
output [3:0]En;
output [7:0]Out;
wire [31:0] T;
wire [1:0]sel;
wire t1;
decoder cas0 (In,T);
ds cas1 (sel,T,Out);
controller cas2(t1,{En,sel});
div1 cas3 (sysclk,t1);
endmodule
The controller provides the select lines for the Multiplexer and
enable signals (Active LOW) for the 4 seven segment LEDs.It
enable any one of the 4 LEDs and correspondingly gives the
select line status of the Mux. Actually ,we feel it like a
continuous display but one LED is ON at a time. Switching speed
is 4000Hz.
module controller(cont,ctrl);
input cont;
output[5:0]ctrl;
counter abcde1 (cont,ctrl[1:0]);
ctdecoder abcde2 (ctrl[1:0],ctrl[5:2]);
endmodule
module counter(inclk,oc);
input inclk;
output[1:0]oc;
reg[1:0]oc;
always@(posedge inclk)
oc <= oc+1;
endmodule
module ctdecoder(din1,dout1);
input[1:0]din1;
output[3:0]dout1;
reg[3:0]dout1;
always@(din1)
begin
case(din1)
0:dout1=4'b0111;
1:dout1=4'b1011;
2:dout1=4'b1101;
3:dout1=4'b1110;
endcase
end
endmodule
module decoder(I,D);
input [15:0]I;
output [31:0]D;
M
ult DISPLAY
Data from ipl
Decoder ex
er
Select
Lines
module ds(s,T,U);
input[1:0]s;
input[31:0]T;
output[7:0]U;
reg[7:0]U;
always@(s)
begin
case(s)
0 : U=T[31:24];
1 : U=T[23:16];
2 : U=T[15:8];
3 : U=T[7:0];
endcase
end
endmodule
module div1(clock,t1);
input clock;
output t1;
reg t1;
integer n;
always@(posedge clock)
begin
n <= n+1;
if(n<750)
t1 = 1;
else if (n<1500)
t1 =0;
else
n <=0;
end
endmodule
and a (u0,autos,clk);
countmtime ca1 (u0,auto);
endmodule