Lecture 10

Backgate Effect
Common Gate Stage

Jayant Charthad
Stanford University
jayantc@stanford

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 1

 The "Atoms" of Analog Circuit Design

Common Common Common

Source Gate Drain

• As we've seen from the discussion so far, a common source

stage is sufficient for building a simple amplifier
– How about the other two possible configurations?
• We'll find that common gate and drain stages can be
incorporated as valuable add-ons, for building "better" amplifiers
• Interestingly, many analog circuits can be decomposed into a
combination of the above three fundamental building blocks

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 2

 Bulk Connection

*Be aware:
•Ask the tech. folks
•Know what it means!

• In the EE114/214A (N-well) technology, only the PMOS device

has an isolated bulk connection

• Newer technologies* (e.g. 0.13µm CMOS) also tend to have

NMOS devices with isolated bulk ("tripple-well" process)
A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 3
 Aside: Modern Triple-Well Process
Different grounding (digital vs. analog)
helps reduce noise coupling

n+ p+ p+

Courtesy
Shoichi Masui

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 4

 Bulk Connection Scenarios

NMOS

VDD

PMOS

Can connect bulk to

source or VDD (see next slide)
A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 5
 PMOS Well Capacitance
• In the EE114/214A (N-well) technology, the PMOS transistor is
a 5-terminal device
– G, D, S, B, Substrate
• N-well forms a PN junction with the substrate
– Often "AC shorted" when N-well=VDD, Substrate=GND VDD
(cap shorted)

– Not shorted when we connect N-well to source!

• Resulting capacitance ~ 0.05 fF/µm2
• Not modeled in Spice! Must add extra diode manually in this
case

≈
A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 6
 Model for PMOS Well Capacitance

• Model available in ee114_hspice.sp

* well-to-substrate diode
* example instantiation (area = 10um*10um = 100pm^2)
* (anode) (cathode) (model) (area)
* d1 sub_node well_node dwell 100p

.model dwell d cj0=1e-4 m=0.5

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 7

 Well Area Estimation

Ldiff L Ldiff • Highly dependent

Well Contact on exact layout
Ldiff
• For the example on
the left, we have

Awell = ( 3Ldiff + L + 2X1+ X2)

W S G D
D
×(W + 2X1)
X1 X2 X1
• E.g. W/L=10µm/1µm
€
X1 Awell = (9 + 1+ 10 + 3)µm
Well
×(10 + 10)µm
= 460µm 2
EE114/214A Technology: X1=5µm, X2=3µm

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 8

€
 Small Signal Model With Well-Cap

Cgd
G D
+
vgs Cgs gm vgs ro
-
S

Cgb Csb Cdb

B

Cbsub (PMOS only)

SUB

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 9

 Backgate Effect (1)

VSB>0

• With positive VSB, depletion region around source grows

• Increasing amount of negative fixed charge in depletion region
tends to "repel" electrons coming from source
– Need larger VGS to compensate for this effect (I.e. Vt
increases)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 10

 Backgate Effect (2)

• This effect is usually factored in as an effective increase in Vt

• Detailed analysis shows

Vt = Vt 0 + γ ( 2φ f + VSB − 2φ f )
• A change in Vt also means a change in drain current
– Define small-signal backgate transconductance
∂I D ∂I
g mb = =− D
∂VBS ∂VSB

g mb ∂Vt ∂I D ∂VGS ∂Vt γ

=− = =
gm ∂VSB ∂Vt ∂I D ∂VSB 2 VSB + 2φ f

-1

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 11

 MOS “Level 1” Equations (Saturation)

KP W 2
I DS = ⋅ ⋅ (VGS − Vt ) ⋅ (1 + λVDS )
2 Leff
SPICE Parameter Names:
Vt = VTO + γ 2φ −
+V (
VSB
BS − 2φ )
' VTO
KP ≡ µC OX

2ε S qN bulk COX
GAMMA
€ ≡γ= '
COX KP
2kT N bulk
2φ = ln LAMBDA (l)
q ni
'
COX =
ε OX GAMMA (g)
tOX
PHI (2f)
Leff = Lmask − 2 X J −lateral
A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 12
Linear region (small VDS, before Saturation)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 13

 Modified Small Signal Model

New term
Cgd
G D
+
vgs Cgs gm vgs gmbvbs ro
-
S
-
vbs Cgb Csb Cdb
+
B

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 14

 Common Gate Stage

RL
RL
Vo Cgd+Cdb
Vo
VB
(we’ve
grounded) -(gm+gmb)vi ro

IB +
ii RS ii RS vi Cgs+Csb
-

Define: CS = C gs + Csb g' m = g m + g mb

“enhanced” gm’
due to both “gates”

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 15

 CG Current Transfer

(Ignore loading for the moment,

focus on current in and out)
io
io g' m
g'mvgs ro ≅ Input pole:
CS ii g' + sC + 1
m S
RS Relatively high freq.
due to 1/g’m
+ vgs - g' m RS 1
ii RS ≅ ⋅
1 + g' m RS 1 + s RS CS
All nodes grounded, 1 + g' m RS
therefore ii sees the
following) io
io 1
≅ for g' m RS >> 1
ii RS CS 1/g’ m ro ii 1 + s CS
g' m

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 16

 CG Input Impedance (1)

io
w.r.t.

+ v o v o v test
g'm vgs ro vo RL KCL@v o : 0 = + − − g'm v test
CS -
RL ro ro
⇒ v o ≅ g'm ( RL || ro )v test
w.r.t.
+ vgs -
Yin
vtest v test v o
KCL@v test : itest = g'm v test + −
ro ro
itest g' r 1
⇒ Yin = ≅ m o + (sCS + )
v test RL + ro Rs
v gs = −vtest
We can add in both effects of CS and RS
€ to above analysis. (typically 1/RS<<g’m)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 17

 CG Input Impedance (2)

Yin ≅
g' m ro & (R + r )#
$$1 + sC S L o !!
RL + ro % g' m ro "

• At low frequencies
1 1 & RL #
Rin = ≅ $1 + !
Yin g' m $% ro !"

• Two interesting cases

1
– RL<<ro: Rin ≅ (well known)
g' m
RL
– RL>>ro: Rin ≅ (not so well known…)
g' m ro

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 18

 CG Output Impedance
All resistive and
capacitive loading at w.r.t.
output node can be
added in parallel Rout vtest v gs
itest = + + g' m v gs
itest ro ro
v gs = −itest RS
g'm vgs ro vtest
CS

vtest
+ vgs - Rout = ≅ ro (1 + g' m RS )
RS itest

(Very high if g'mRS>>1 !)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 19

 CG Input-Output RC Time Constants

io

+
g'm vgs CL
CS
ro >>vo RL
-

+ vgs -
Yin
vitest
in
RS
For this specific configuration (and assumption):
Input and output are decoupled; “RC time constants” are
= 1/poles (see also lecture on Miller approx., slide 5)
Input RC: ~CS(1/g’m) (RS>>1/g’m)
Output RC: RLCL (ro>>RL)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 20

 CG Summary
• Current gain is unity up to very high frequencies
– Our "simple" device model predicts up to roughly fT
• Input impedance is very low
– At least when the output is also terminated with some
reasonable impedance
• Can achieve very high output resistance
• In summary, a common gate stage is ideal for turning a decent
current source into a much better one
– Seems like this is something we can use to improve our
common source stage
• Which is indeed nothing but a decent (voltage controlled)
current source

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 21

 Cascode Stage ― Preview of Cascading

• An important, extremely useful application of Common Gate

– http://web.mit.edu/klund/www/cascode.html
Ro
Vo
VBCAS io Low Frequency
Equivalent
M2 vo
ii
Vi G mvi Ro
M1
∂ io reminder
Gm ≡
∂ vi g'm 2 = gm 2 + gmb 2
i0
Gm = g m1 ⋅ ≅ g m1 Ro ≅ ro 2 (1 + g' m 2 ro1 )
ii
€
2
Gm Ro = g m1ro 2 (1 + g' m 2 ro1 ) ≅ g m1ro1 ⋅ g' m 2 ro 2 ~ (g m ro )

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 22

 High Frequency Benefits

vx g m1 & R#
= g m1Z x ≅ $
$ 1 + !!
R vg g 'm 2 % ro 2 "
VBCAS Vo

M2
• vx/vg is close to 1 for moderate values
of R
Cgd Zx – Mitigates Miller amplification of Cgd
Vx • Aside: Even if R is large, there is often
M1 a load capacitance that provides a low
Vi Vg
impedance termination to help maintain
this feature

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 23

 Example Revisited

5V • What we expect to see in

Spice after adding the
IB cascode device
Relatively small Vo – Bandwidth should increase
Rin (~1/g’mc) VBCAS (reduction in “Miller
MNC R
20/1 amplification” for Cgd1)
VB – You will analyze this
MN1
20/1 situation using a ZVTC
Ri
vi analysis in the next
VI
homework problem set
• We will return to a more
detailed analysis (including
non-dominant poles) later in
VB = 2.5V, VI = 1.394V, VBCAS= 3V this course
IB = 500µA, R = 5kW, Ri = 50kW

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 24

 Simulated Frequency Response

• 3-dB bandwidth increased from 32 MHz to 52 MHz

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 25

 Supply Headroom Issue

VDD
• Even if we adjust VBCAS
such that VDS1 is small,
R
adding a cascode reduces
Vo the available signal swing
• This can be a big issue
VBCAS when designing circuits
VDS2>VDSsat2 with VDD@1V
– Typically need each
Vi VDS1>VDSsat2
VDS>~0.2V

A. Arbabian, R. Dutton, B. Murmann EE114/214A L10- 26