Vol. 34, No.

9 Journal of Semiconductors September 2013

VLSI scaling methods and low power CMOS buffer circuit

Vijay Kumar SharmaŽ and Manisha Pattanaik
Department of Information Technology, ABV-Indian Institute of Information Technology & Management,
Gwalior-474015, India

Abstract: Device scaling is an important part of the very large scale integration (VLSI) design to boost up the
success path of VLSI industry, which results in denser and faster integration of the devices. As technology node
moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both
are increasing with the new technology generation and affecting the performance of the overall logic circuit. The
VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices.
In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of
those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating
the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate
(LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation
results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files.
The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm
technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of
the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that
causes large circuit reliability.

Key words: LPTG buffer; power dissipation; propagation delay; scaling; nanoscale CMOS; figure of merit
DOI: 10.1088/1674-4926/34/9/095001 EEACC: 2570

1. Introduction various scaling methods in low power design. The methodol-

The MOS transistor is the basic building block of inte-
grated circuits. Scaling of the MOS transistor improves its size,
cost and performance. Today’s fabricated integrated circuits
are many times faster and occupy much less area, like today’s
microprocessors that contain nearly one billion transistors on
a single chip. The role of supply voltage is vital for control-
ling the power consumption and hence reducing the power dis-
sipation. It is reducing for each new technology generation.
Threshold voltage of the device must be reduced proportion-
ally as supply voltage reduces to sustain the transistor’s output
performance. The reduction in threshold voltage increases the
leakage current drastically with each new technology genera-
tionŒ1 . As the leakage current increases with a new technol-
ogy generation, it will affect the overall logic circuit’s power
dissipation. Leakage current is the major problem in the deep
submicron region, so we need a powerful leakage reduction
technique to minimize the effect of threshold voltage scaling.
Scaling methods pay a significant role in reducing the
power dissipation from one technology node to another node.
There are various scaling methods used for VLSI circuits.
Most common are voltage scalingŒ2 , load scalingŒ3 , technol-
ogy scalingŒ4 and transistor sizing (width scaling)Œ5 . The pur-
pose of studying various scaling methods is to decide a suitable
method for scaling while keeping power dissipation and prop-
agation delay in mind. In this paper the work investigations are
carried out on the above said four scaling methods for a CMOS
buffer circuit.
The paper is organized as follows. Section 2 describes the
† Corresponding author. Email: vijay.buland@gmail.com
Received 15 February 2013, revised manuscript received 20 March 2013
ogy of the proposed approach is provided in Section 3 with
conventional design. The leakage reduction and robustness ca-
pability of the proposed approach is verified in Section 4. Fi-
nally, conclusions of this work are outlined in Section 5.
2. Scaling methods
2.1. Voltage scaling
A common and very effective method of reducing the
power dissipation of a circuit is to reduce its supply voltage.
The dynamic power dissipation component is directly propor-
2
tional to VDD that makes this technique so effectiveŒ6 . Power
reduction is possible through the voltage scaling at a constant
clock frequency. It is observed that a CMOS inverter will con-
tinue to operate correctly with a supply voltage which is as low
as the limit value shown in Eq. (1)Œ6
ˇ ˇ
VDD; min D jVtn j C ˇVtp ˇ : (1)
One MOS device is always in on condition in CMOS in-
verter for any input voltage. The term voltage scaling used here
is different from that of constant voltage scaling because here
all other parameters are kept constant instead of scaling them
by the same factor. This is the reason for propagation delay
increasing because only the supply voltage is reduced. This is
analytically observed from Eq. (2)Œ6 for propagation delay of
the CMOS inverter as
CL VDD CL VDD
D D ; (2)
l n COX .w= l/.VGS Vth /2
© 2013 Chinese Institute of Electronics

095001-1
J. Semicond. 2013, 34(9) Vijay Kumar Sharma et al.

Fig. 2. Total load capacitance CL at the output node.

Fig. 1. Load capacitance and its components.

where  is the propagation delay due to low to high and high

to low output voltage transition. Vth is the threshold voltages
of the MOS device. CL is the load capacitance and VDD is the
power supply voltage.
The circuits operate more slowly as the supply voltage de-
creases when assuming no other changes are made. This is the
drawback of this approach. Another drawback is that some cir-
cuit styles cannot function at low supply voltages. The prop-
agation delay increases with reducing the power supply volt- Fig. 3. Circuit model for analyzing the effect of transistor sizing.
age and can be compensating if the threshold voltage of the
transistor is reduced accordingly. However, a reduction in the
If RL is the summed resistance of the overall circuit at the
threshold voltage will cause an exponential increase in the de-
load terminal then propagation delay of the circuit is the mul-
vice sub-threshold leakage current. In turn, this increases the
tiply of load capacitance and load resistance.
static power of the device to unacceptable levelsŒ7 . This study
clearly justifies the need for leakage reduction techniques.
2.3. Transistor width scaling
2.2. Load scaling Transistor sizing is also known as channel width scal-
ing. Transistor width scaling effectively reduces power dissipa-
Load scaling is the other way to reduce the power dissi-
tionŒ9 . If the channel width of the transistor is increased, then
pation. Larger load capacitance draws more charge from the
it reduces the signal transition at the output and hence prop-
power supply during each switching and hence increases the
agation delay of the logic circuit. The small value of channel
dynamic power dissipationŒ8 . The larger capacitance reduces
width is utilized for optimization of power dissipation and chip
the speed of operation. Figure 1 shows the load capacitance and
area while the large value is used to optimize the propagation
its components at output node Vout .
delay of the logic circuit. For high performance calculation it
Here Cgd1 and Cgd2 are the overlap capacitances, Cg1
may be seen that finding a single critical path can degrade the
and Cg2 are the gate capacitances, Cdb1 and Cdb2 are the
performance of the entire circuit. However, in low power de-
drain/source diffusion capacitances, and Cint is the interconnect
sign the focusable target is on lower power dissipation while
capacitance which is due to parallel plate capacitance, fringing
taking propagation delay constraints and assuming the certain
capacitance and wire-wire capacitance.
active area for the logic circuit.
Therefore the capacitances are given as below:
Figure 3 shows the 2-gate circuit with the first gate driving
Cgate D Cg1 C Cg2 ; (3) the gate capacitance Cg and the parasitic capacitance CP to the
next gate.
Cdiff D Cdb1 C Cdb2 : (4) The input gate capacitance of both gates is given by NCref ,
where Cref is the gate capacitance of an MOS device with the
Total capacitance CL is then possible smallest aspect ratio. The propagation delay through
the first gate at a supply voltage Vref is given by Eq. (6)Œ10
CL D Cgate C Cdiff C Cint : (5)
 ˛ Vref
Total capacitance is depicted in Fig. 2.  DK 1C ; (6)
N .Vref Vth /2

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J. Semicond. 2013, 34(9)
Fig. 4. Scaling of an MOSFET by a factor of S .
where ˛ is the ratio of CP to Cref , and K stands for the condi-
tions independent of the device’s width and voltage.
2.4. Transistor’s technology scaling
CMOS technology has continued to scale down at a dra-
matic rate to opt high performance. In 1975, Moore predicted
that the number of transistors per square inch in an IC would
double every 18 months. In each new technology generation,
the overall lateral and vertical dimensions of the transistors are
scaled down by a factor. Figure 4 reflects the reduction of the
key dimensions of a typical MOSFET while increasing of the
doping densities.
The new technology generation has an impact on reducing
the power dissipation, as well as increasing the circuit’s speed
due to reduction of all capacitance effects. As today’s technol-
ogy scales below 45 nm, the transistor density will continue
to growŒ11 . A number of limitation factors like short channel
effects, sub-threshold conduction, body effect etc. arise in the
very deep submicron region for further scaling of the transis-
tors. In practice, there are two types of scaling strategies for
MOSFET devices: full scaling and constant voltage scaling.
Constant field scaling reduces both the drain voltage and
the drain current by a factor of S. Therefore, the power dis-
sipation of the transistor decreases by a factor of S 2 , while it
increases by the factor S in constant voltage scaling. This sig-
nificant reduction of the power dissipation is one of the most
attractive features of constant field scaling. However, the con-
stant field scaling causes the sub-threshold leakage currents to
grow exponentially and becomes an increasingly larger com-
ponent of the total power dissipationŒ12 .
3. Conventional and LPTG CMOS buffer
A conventional CMOS buffer consists of two inverters cas-
caded as shown in Fig. 5. The input and the output have a def-
inite delay time due to the device transitions in the CMOS cir-
cuits. The buffer circuit is generally used to drive large capac-
itive loads developed both by the next stage and the intercon-
nect capacitances too. So, while building buffers, both strong
NMOS and PMOS are used. This would help the device in
charging and discharging the buffers quicker than normal. But
these strong MOS devices in turn provide large capacitance and
affect the time delays of the previous stages of the circuits.
095001-3
Vijay Kumar Sharma et al.
Fig. 5. Conventional CMOS buffer.
From the above said scaling methods, various important
outcomes appear to explain them in the very deep submicron
region. As we are moving towards the very deep submicron re-
gion the supply voltage as well as threshold voltage must be
scaled in proper ratio to maintain the correct operation of the
logic circuitŒ13 . Power dissipation is the important term in the
deep submicron region because of reduction in threshold volt-
age and effects of various other parameters to increase the leak-
age current components. As the technology node scales down
below 65 nm node, many reliability problems are coming into
being as a resultŒ14 . The above discussions tell that power dis-
sipation and parameter variations are the main issues as tech-
nology scales down below 65 nm. To reduce the power dissipa-
tion a number of leakage reduction techniques are used. These
techniques have their own advantages and disadvantages. In
this section we have proposed a reliable leakage reduction tech-
nique for a CMOS buffer circuit.
Our proposed low power transmission gate (LPTG) ap-
proach is a circuit level approach for reducing the leakage
current and hence, leakage power directly affected the total
power dissipation of the logic circuit. This approach is very
effectively reducing both the active as well as the standby
mode leakage current. Through a literature survey we know
that many leakage reduction techniques are there in low power
design but one simple and effective technique called LEC-
TORŒ15 , is the single threshold voltage circuit level technique.
The drawback of this technique is its low output swing volt-
age. Our proposed approach gives full output swing voltage
as well as lower power dissipation as compared to LECTOR
technique. The proposed approach used the extra insertion of
transmission gates between the pull-up to output and output to
pull-down network for minimizing the leakage current. These
extra inserted transmission gates are called low power trans-
mission gates (LPTG). LPTG provides a high conducting path
when this block is on and a high resistive path when this block
is off. The LPTG circuit block contains one NMOS and one
PMOS transistor. The schematic of the CMOS LPTG buffer
circuit is shown in Fig. 12. Here con and conbar are the con-
trol signals which are complementary to each other. These sig-
nals are used for activation or deactivation of the LPTG blocks.
These signals depend on the output functionality of the buffer
circuit. These signals must be precisely defined to give the re-
J. Semicond. 2013, 34(9)
Fig. 6. Power dissipation for conventional buffer with voltage scaling.
liable and accurate performance of the circuit. If input voltage
is uniformly on/off periodic pulse with time period tp then con
and conbar are given as:
(
0; 0 < t < tp =2;
Vin .VDD / D
VDD ; tp =2 < t < tp ;
( increases by 114.66%. For 32 nm technology, the supply volt-
VDD ; 0 < t < tp =2;
Vcon .Vin / D
0; tp =2 < t < tp ;
( is concluded from the above results that the voltage scaling is
0; 0 < t < tp =2;
Vconbar .Vin / D
VDD ; tp =2 < t < tp :
These control signals also depend on the logic states of in-
put voltage. Control signals con and conbar are assigned with
appropriate potential based on the logic states of the input volt-
age.
4. Results and discussion
4.1. Voltage scaling for CMOS conventional buffer
HSPICE EDA tool is used for calculating power dissipa-
tion and propagation delay for the conventional CMOS buffer
at 65 nm, 45 nm and 32 nm technology nodes. For making
a fine comparison, other parameters except supply voltage of
these particular technology nodes are taken the same through-
out the scaling of supply voltage. The supply voltage range
for different technology nodes is precisely defined before an-
alyzing the logic circuit because it is related to reliability of
the circuit. The supply voltages for different technologies are
chosen so as to maintain the high noise margin with proper
output function while keeping the effective work of process
parameters. According to ITRS the nominal supply voltage for
65 nm is 1.0 V, for 45 nm it is 0.9 V, and for 32 nm node it
is 0.8 V. The supply voltage range is ˙20% of the nominal
value and it is 0.80 to 1.20 V for 65 nm technology node, 0.72
to 1.08 V for 45 nm technology node and 0.64 to 0.96 V for
32 nm technology node for precise and reliable operation of
the circuit. Figure 6 depicts the supply voltage scaling at dif-
ferent technology nodes.
Vijay Kumar Sharma et al.
Fig. 7. Propagation delay for convention buffer with voltage scaling.
It is observed from Fig. 6 that power dissipation is reduced
with the reduction of supply voltage but propagation delay in-
creases. For 65 nm technology, where supply voltage range is
0.80 to 1.20 V, % reduction in power dissipation is 86.73%
while propagation delay increases by 112.14%. For 45 nm tech-
(7) nology, where supply voltage range is 0.72 to 1.08 V, % reduc-
tion in power dissipation is 85.28% while propagation delay
age range is 0.64 to 0.96 V, % reduction in power dissipation
(8)
is 91.64% while propagation delay increases by 155.31%. It
more efficient when technology scaled in terms of power dissi-
(9) pation saving, while it is challenging to reduce the propagation
delay.
Figure 7 shows the decrease in propagation delay with cor-
responding increasing in supply voltage and technology node
of the conventional buffer. As the power dissipation increases
in direct proportion with the supply voltage, so a compromise
is to be made between the propagation delay and power dis-
sipation of the conventional buffer depending upon the appli-
cation requirements. A figure of merit is utilized to decide the
acceptable level of propagation delay in low power VLSI cir-
cuit design. Figure of merit is the product of leakage power
and propagation delay of the logic circuits. The supply voltage
scaling improves the figure of merit by 78.70% when scaling
from 0.96 to 0.64 V for 32 nm technology node.
4.2. Load scaling for CMOS conventional buffer
With the reduction in the load capacitance, both power dis-
sipation and propagation delay are reduced as shown in Figs. 8
and 9 at 65 nm, 45 nm and 32 nm technology nodes. For making
a fine comparison, other parameters, except load capacitance,
of these particular technology nodes are taken as the same for
scaling of load capacitance. The load capacitance range for dif-
ferent technology nodes are precisely defined before analyzing
the logic circuit because it is related to stability of the circuit.
The ranges of load capacitances are chosen so as to optimize
the power dissipation and propagation delay, while controlling
the good input output characteristics of the logic circuit.
Total power dissipation is the summation of dynamic and
static power dissipation, where dynamic power is directly pro-
095001-4
J. Semicond. 2013, 34(9)
Fig. 8. Power dissipation for conventional buffer with load scaling at
65 nm, 45 nm and 32 nm technology.
Fig. 9. Propagation delay for conventional buffer with load scaling at
different technologies.
portional to the load capacitance CL . It is concluded that power
dissipation is reducing as load capacitance is decreased, as
power dissipation directly depends on the load capacitance.
Figure 9 shows that reduction in the load capacitance is reduc-
ing the propagation delay. As load capacitance is decreased, the
output signal is changed rapidly and hence reduces the transi-
tion times at the output of conventional buffer. At 65 nm tech-
nology node the propagation delay is increasing with increase
in the load capacitance values.
The load capacitance scaling improves the figure of merit
by 71.54% when scaling from 2.0 to 0.1 fF for 32 nm technol-
ogy node.
4.3. Technology scaling for CMOS conventional buffer
The results for technology scaling are presented in Fig. 10
at different technology nodes. It is concluded that power dis-
sipation and propagation delay are increased with technology
scaling. The incremental change in power dissipation with
technology is due to leakage current components which are
more dominant at lower technology node. Sub-threshold and
gate leakage are the dominant components of leakage current
in the very deep sub-micron regionŒ13 . The energy efficiency
095001-5
Vijay Kumar Sharma et al.
Fig. 10. Power dissipation and propagation delay for conventional
buffer at different technologies.
of the logic circuit is evaluated by the figure of merit. The lower
value of figure of merit is desirable for energy efficient opera-
tion of the logic circuit. Figure 10 shows the power dissipation
and propagation delay curves at different technology nodes.
It is clear that as technology scaled down from 65 to 32 nm,
356.48% power dissipation and 18.64% propagation delay is
increased. Figure of merit increases with reduction of technol-
ogy node. It increases very rapidly below 45 nm technology
node. The technology scaling degrades the figure of merit by
516% when scaling from 65 nm to 32 nm technology node. A
good VLSI designer wants to minimize the figure of merit to
optimize the logic circuit design. It is the challenging task of
the designers in the very deep submicron region and it requires
the effective architecture, technique or algorithm to optimize
both power dissipation and propagation delay of the circuit.
4.4. Transistor width scaling for CMOS conventional
buffer
The results for width scaling at 32 nm technology node are
given in Fig. 11. The nominal supply voltage is 0.8 V at 32 nm
node. The nominal width of NMOS device is twice of the cor-
responding channel length and it is six times in PMOS device.
The width ratio of PMOS to NMOS device is increasing from 1
to 5. The power dissipation of conventional buffer is increased
by 438.47% while propagation delay reduces by 66.28% from
width ratio scaling of 1 to 5. It is inferred that with decreasing
width ratio of the transistors, the power dissipation decreases
with increment in the propagation delay penalty. By taking the
appropriate transistor’s sizing, the designer made his design
very valuable. The transistor’s width scaling improves the fig-
ure of merit by 44.90% when scaling from 5 to 1 for 32 nm
technology node.
4.5. LPTG CMOS buffer
The above discussions for a conventional CMOS buffer
are presented for different scaling methods. Technology scal-
ing is the prime requirement of the future nanoscale devices
due to scaling of the various device parameters. The limitation
of technology scaling is its poor figure of merit. We have pro-
posed a low power transmission gate CMOS buffer circuit for
improving the figure of merit of the technology scaling method.
J. Semicond. 2013, 34(9)
Fig. 11. Power dissipation and propagation delay for conventional
buffer with width ratio scaling.
Fig. 12. Schematic of LPTG CMOS buffer.
The generalized schematic of the LPTG CMOS buffer is shown
in Fig. 12. In the proposed design, eight extra transistors are
employed for providing the path resistance from power sup-
ply to ground. The area requirement is reduced by choosing a
fitting width scaling.
Comparison of the conventional buffer and the LPTG
CMOS buffer on power dissipation and propagation delay
performance at different technologies is shown in Fig. 13.
The LPTG approach reduces the power dissipation effectively
when moving towards low technology nodes. In the LPTG ap-
proach we used the MOS devices which have accurate and ef-
ficient turning on/off characteristic. The number of off MOS
devices between power supply to ground provides the greater
body bias of these MOS devices, thus reducing the power dis-
sipation. At 32 nm technology node LPTG approach reduces
95.16% power dissipation while increasing the propagation de-
lay by 226.19%. The increments in propagation delays are of
less concern because the LPTG approach has the better fig-
ure of merit. The figure of merit at 32 nm technology reduces
by 84.23%. Our proposed approach is more valuable in the
very deep nanoscale region as it reduces the figure of merit by
44.10% to 84.23% when moving from 65 nm to 32 nm tech-
nology node.
The graph clarifies that the power dissipation of the LPTG
095001-6
Vijay Kumar Sharma et al.
Fig. 13. Power dissipation (PD) and propagation delay for CMOS
buffer at different technologies.
Fig. 14. Power dissipation and propagation delay versus width ratio
for CMOS buffer.
buffer circuit is very low and less influenced at low technol-
ogy node in the very deep submicron region as compared to
the conventional buffer. On the basis of propagation delay, the
LPTG buffer circuit having the greater delay because of the
number of transistors used in the LPTG buffer, increases the
propagation delay of the circuit.
Now we consider the effect of width ratio variation of the
LPTG buffer circuit at 32 nm technology node while taking
power supply voltage 0.8 V. A width comparison of the con-
ventional CMOS buffer and LPTG CMOS buffer is shown in
Fig. 14. The LPTG CMOS buffer circuit reduces the power dis-
sipation by nearly 90.98% at width ratio 1. The sub-threshold
leakage current component directly affected the power dissipa-
tion of the CMOS buffer circuit while larger width ratio causes
larger chip area and proportionally reduces the speed of the
circuit. An important result is reduction of the propagation de-
lay with increment in width as compared to the conventional
CMOS buffer. At normal width calculation, the % change in
propagation delay is 196.83% while it is 259.83% at width ra-
tio 5. The LPTG approach diminishes normally 70.70% figure
of merit as width ratio varies from 1 to 5 as compared to the
conventional CMOS buffer.
The power dissipation and delay vs. temperature effects
are analyzed as explained in Fig. 15. The temperature range is
taken from 25 to 125 ıC. Power dissipation and propagation
J. Semicond. 2013, 34(9)
Fig. 15. Power dissipation and propagation delay versus temperature
for CMOS buffer.
Fig. 16. Power dissipation and propagation delay versus supply volt-
age for CMOS buffer.
delay for both circuits are increased with increasing the tem-
perature. The increment in power dissipation is due to ther-
mal voltage dependency of the leakage current. If we calcu-
late the % change of these two parameters then % saving of
power dissipation is decreasing while propagation delay in-
creases as temperature increasing. Leakage uncertainty is less
in the LPTG approach as compared to the conventional. The
LPTG approach is less affected, normally 64.10% figure of
merit with temperature varying from 25 to 125 ıC as compared
to the conventional CMOS buffer.
The effect of voltage scaling of ˙20% variations from
nominal value is analyzed for LPTG and conventional CMOS
buffer circuit. The output results are illustrated in Fig. 16 at
32 nm technology node. The rising rate of performance para-
meters are very slow in the LPTG approach with increasing in
VDD as compared to conventional circuit.
The ˙20% power supply voltage variations are less influ-
enced, normally 73.20% figure of merit as compared to con-
ventional CMOS buffer.
The summation of leakage current components under vari-
ous process, voltage and temperature variations are distributed
as shown in Fig. 17. These leakage current components are re-
sponsible for power dissipation and reliability issues in buffer
circuit.
Figure 17 is plotted by taking ˙10% variations in pro-
095001-7
Vijay Kumar Sharma et al.
Fig. 17. Histogram of leakage current variations for CMOS buffer.
cess, voltage and temperature parameters with Monte–Carlo
1000 runs at 32 nm node. The LPTG approach is less suscepti-
ble to the process variations as compared to conventional cir-
cuit. The value of mean and standard deviation of leakage cur-
rent components are 86.83 nA and 79.05 nA respectively for
conventional CMOS buffer while in LPTG CMOS buffer, these
are 72.86 nA and 31.50 nA respectively. The leakage current
uncertainty is 0.91 in conventional while it is 0.43 in LPTG
CMOS buffer. Thus our proposed approach mitigates 2.12X
reliability issues in CMOS buffer circuit.
5. Conclusion
Low power design is drawing a huge deal of awareness
in VLSI digital design, principally for portable high perfor-
mance systems. The quick switching of billions of transistors
dissipates tremendous power and overheats the chip, reducing
the reliability of the chip and necessitating expensive and large
cooling systems. In this article, scaling methods like voltage
scaling, load scaling, technology scaling and width scaling for
a nanoscale CMOS buffer circuit have been analyzed. Based
on the analysis of these scaling methods we proposed a reli-
able low power transmission gate approach which effectively
reduces the power dissipation and enhances the reliability. Dif-
ferent scaling variations are used to analyze the power dissi-
pation and propagation delay behavior in the CMOS buffer
circuit. The necessity of future nanoscale circuits is mitiga-
tion of the energy consumption per cycle. The least value of
figure of merit provides the energy efficient design at future
nanoscale nodes. Our proposed approach saves power dissipa-
tion by 95.16% with 84.20% progress in figure of merit in the
CMOS buffer at 32 nm technology node. The LPTG approach
decreases the leakage current uncertainty from 0.91 to 0.43 in
the CMOS buffer for reliable operation of the logic circuit in
the very deep submicron region.
References
[1] Agarwal A, Mukhopadhyay S, Raychowdhury A, et al. Leakage
power analysis and reduction for nanoscale circuits. IEEE Micro,
2006, 26(2): 68
[2] Liao W, He L, Lepak K M. Temperature and supply voltage
aware performance and power modeling at microarchitecture
level. IEEE Trans Computer-Aided Design of Integrated Circuits
and Systems, 2005, 24(7): 1042
J. Semicond. 2013, 34(9)
[3] Dhillon Y S, Diril A U, Chatterjee A, et al. Analysis and opti-
mization of nanometer CMOS circuits for soft-error tolerance.
IEEE Trans Very Large Scale Integration Syst, 2006, 14(5): 514
[4] Wong H, Iwai H. On the scaling issues and high- replacement
of ultrathin gate dielectrics for nanoscale MOS transistors. Mi-
croelectron Eng, 2006, 83(10): 1867
[5] Lin C H, Haensch W, Oldiges P, et al. Modeling of width-
quantization-induced variations in logic FinFETs for 22 nm and
beyond. Digest of Technical Papers, Symposium on VLSI Tech-
nology, 2011, 16
[6] Kang S M, Leblebici Y. CMOS digital integrated circuits analysis
and design. New Delhi: Tata McGraw-Hill, 2003
[7] Islam A, Hasan M. Leakage characterization of 10T SRAM cell.
IEEE Trans Electron Devices, 2012, 59(3): 631
[8] Nayan A N, Yasuhiro T, Toshikazu S. LSI implementation of
a low-power 4  4-bit array two-phase clocked adiabatic static
CMOS logic multiplier. Microelectron J, 2012, 43(4): 244
[9] Elkamma A N, Vemuru S R. Scaling of serially-connected MOS
transistors with constant area constraint. Midwest Symposium on
095001-8
Vijay Kumar Sharma et al.
Circuits and Systems, 2002, 1515
[10] Chandrakasan A P, Brodersen R W. Minimizing power consump-
tion in CMOS circuits. Proc IEEE, 1995, 83(4): 498
[11] Guo X, Ipek E, Soyata T. Resistive computation: Avoiding the
power wall with low-leakage, STT-MRAM based computing. In-
ternational Symposium on Computer Architecture, 2012: 371
[12] Ho Y, Chang C, Su C. Design of a subthreshold supply boot-
strapped CMOS inverter based on an active leakage-current re-
duction technique. IEEE Trans Circuits Syst II: Express Briefs,
2012, 59(1): 55
[13] Sharma V K, Pattanaik M, Raj B. ONOFIC approach: low power
high speed nanoscale VLSI circuits design. International Journal
of Electronics, 2013, (in press)
[14] Wang J, Gong N, Hou L, et al. Leakage current, active power, and
delay analysis of dynamic dual Vt CMOS circuits under P –V –T
fluctuations. Microelectronics Reliability, 2011, 51(9): 1498
[15] Hanchate N, Ranganathan N. LECTOR: a technique for leakage
reduction in CMOS circuits. IEEE Trans Very Large Scale Inte-
gration Syst; 2004, 12(2): 196