MICRO

1. DIFFERENTIATE RISC AND CISC

RISC
REDUCED INSTRUCTION SET COMPUTER
SMARTER SOFTWARE
MACHINE – ORIENTED
SIMPLE INSTRUCTION
MORE RAM REQUIRED
LOW CYCLES PER SECOND
LOAD AND STORE REGISTER –
REGISTER ARE INDEPENDENT
IT HAS A SINGLE – CLOCK
THE PERFORMANCE OF THE RISC
PROCESSORS DEPENDS TO THE
PROGRAMMER OR COMPILER
SPENDS MORE TRANSISTORS ON
MEMORY REGISTERS
EXAMPLE:
MOV AH,5;
MOV BH,3;
PROD AH,BH;
STORE AH;
CISC
COMPLEX INSTRUCTION SET COMPUTER
SMARTER HARDWARE
PROGRAMMER - ORIENTED
COMPLEX – DECODING LOGIC
LESS CHIP SPACE
HIGH CYCLES PER SECOND
LOAD AND STORE MEMORY – TO –
MEMORY IS INDUCED IN INTRUCTIONS
IT HAS MULTI – CLOCK
THE PERFORMANCE OF THE MACHINE
SLOWS DOWN DUE TO THE MULTIPLE
CLOCK TAKEN BY MULTIPLE
INSTRUCTIONS WILL BE DISSIMILAR
TRANSISTORS USED FOR STORING
COMPLEX INSTRUCTIONS
EXAMPLE:
MUL 5,3;

RISC is stands for REDUCED INSTRUCTION SET COMPUTER. The following are
characteristics of RISC: SMARTER SOFTWARE, MACHINE – ORIENTED, SIMPLE
INSTRUCTION (see:
https://drive.google.com/open?id=12pkQN48dPIJW7Xy5xLpW0piC60nVtc8l ), MORE
RAM REQUIRED (see: https://drive.google.com/open?id=1-1PybCI-
VpffYp8277oo8D42d_JyUbg-), LOW CYCLES PER SECOND, LOAD AND STORE
REGISTER – REGISTER ARE INDEPENDENT, IT HAS A SINGLE – CLOCK , THE
PERFORMANCE OF THE RISC PROCESSORS DEPENDS TO THE PROGRAMMER OR
COMPILER and SPENDS MORE TRANSISTORS ON MEMORY REGISTERS. For example:
MOV AH,5;
MOV BH,3;
PROD AH,BH;
STORE AH;
CISC is stands for COMPLEX INSTRUCTION SET COMPUTER. The following are the
characteristics of CISC: SMARTER HARDWARE, PROGRAMMER – ORIENTED, COMPLEX
– DECODING LOGIC (see:
https://drive.google.com/open?id=12pkQN48dPIJW7Xy5xLpW0piC60nVtc8l), LESS CHIP
SPACE (see: https://drive.google.com/open?id=1MZf5G_jJFUWhX47-
puCoaljIEOpZAZN3), HIGH CYCLES PER SECOND, LOAD AND STORE MEMORY – TO –
MEMORY IS INDUCED IN INTRUCTIONS, IT HAS MULTI – CLOCK , THE PERFORMANCE
OF THE MACHINE SLOWS DOWN DUE TO THE MULTIPLE CLOCK TAKEN BY MULTIPLE
INSTRUCTIONS WILL BE DISSIMILAR and TRANSISTORS USED FOR STORING
COMPLEX INSTRUCTIONS. For example:
MUL 5,3;
For better visualization, see
https://drive.google.com/open?id=1qx6o1u1bgjtqQjxadVioidiziT7SV-54.

2. COMPARE PROCESSOR AND THE CONTROLLER

PROCESSOR
REAL – TIME APPLICATION
IT HAS AN INTEGRATED CIRCUIT WHICH
HAS ONLY THE CPU INSIDE THEM
IT HAS NO RAM, ROM AND OTHER
PERIPHERAL ON THE CHIP
IT APPLIES IN DESKTOP, PCs LAPTOPS
AND ETC.
IT PERFORMS UNSPECIFIC TASKS.
REQUIRES HIGH AMOUNT OF
RESOURCES
HIGH CLOCK SPEED
MUCH EXPENSIVE COMPARE TO
CONTROLLER
CANNOT BE USED IN STAND ALONE
IT REQUIRES EXTERNAL CIRCUITS
CONTROLLER
REAL – TIME APPLICATION
IT HAS CPU.
IT HAS FIXED RAM, ROM AND OTHER
PERIPHERALS
MINICOMPUTER OR COMPUTER ON A
SINGLE CHIP.
IT PERFORMS SPECIFIC TASKS WHEREIN
INPUT AND OUTPUT ARE DEFINED.
REQUIRES SMALL RESOURCES
SLOW CLOCK SPEED
CHEAPER THAN PROCESSOR
CAN BE USED IN STAND ALONE
DOES NOT REQUIRE ANY EXTERNAL
CIRCUITS
HEART OF EMBEDDED SYSTEM

Processor is designed for REAL – TIME APPLICATION. IT HAS AN INTEGRATED

CIRCUIT WHICH HAS ONLY THE CPU INSIDE THEM. IT HAS NO RAM, ROM AND
OTHER PERIPHERAL ON THE CHIP. IT APPLIES IN DESKTOP, PCs LAPTOPS AND ETC.
IT PERFORMS UNSPECIFIC TASKS. IT REQUIRES HIGH AMOUNT OF RESOURCES, HIGH
CLOCK SPEED, MUCH EXPENSIVE COMPARE TO CONTROLLER AND CANNOT BE USED
IN STAND ALONE. To see the basic processor, see in
https://drive.google.com/open?id=1zg6VOPHpIefj0f_kXi3DoY5jIwbRyNPE
Controller is also designed for REAL – TIME APPLICATION. IT HAS CPU. IT HAS FIXED
RAM, ROM AND OTHER PERIPHERALS. IT IS ALSO CALLED AS MINICOMPUTER OR
COMPUTER ON A SINGLE CHIP. IT PERFORMS SPECIFIC TASKS WHEREIN INPUT AND
OUTPUT ARE DEFINED.IT REQUIRES SMALL RESOURCES, SLOW CLOCK SPEED, AND
CHEAPER THAN PROCESSOR. IT CAN BE USED IN STAND ALONE. IT DOES NOT
REQUIRE ANY EXTERNAL CIRCUITS AND IT IS THE HEART OF EMBEDDED SYSTEM.
For example: see
https://drive.google.com/open?id=1MCUTEmnhjpUsn1n9NG5p2Alm9HxoDTg2
For better visualization, see
https://drive.google.com/open?id=1jttmpHsggu_c7mDNeL03kPLgipQ7ndGn
3. DESCRIBE THE PIPELINING PROCESS FOR IMPROVING THE SPEED OF A
PROCESSOR
PIPELINING IS A TECHNIQUE USED TO SPEED UP THE EXECUTION OF A CPU BY
USING THE PROCESSOR RESOURCES IN A MORE EFFICIENT MANNER. The concept of
this is TO SPLIT THE PROCESSOR INSTRUCTIONS INTO A SERIES OF SMALL
INDEPENDENT STAGES. Each stage is designed to perform a certain part of the
instruction. At a very basic level, these stages can be broken down into:
FETCH UNIT - Fetch an instruction from the memory
DECODE UNIT - Decode the instruction be executed from the fetch unit
EXECUTE UNIT - Execute the instruction that has been decoded
WRITE UNIT - Write the result back to register or memory
(For better visualization, also
seehttps://drive.google.com/open?id=1cmPoEDBNH9VdKFeGQfWcHBQzXIIrCI4q )
On a non-pipelined CPU, when an instruction is being processed at a particular stage,
the other stages are at an idle state – which is very inefficient. In figure in
https://drive.google.com/open?id=1hvxykEN6feDzD2V2hdWqiq8ELF5bR7_4, when the
1st instruction is being decoded, the Fetch, Execute and Write Units of the CPU are not
being used and it takes 8 clock cycles to execute the 2 instructions. In short, the speed
is slow in non-pipelined.
However, when the processor is pipelined just liked in the figure
https://drive.google.com/open?id=19O-qV-mhbirQuK5Yz9c8wTkJwBTgfzBH, all the
stages work in simultaneously. When the 1st instruction is being decoded by the
Decoder Unit, the 2nd instruction is being fetched by the Fetch Unit. It only takes 5
clock cycles to execute 2 instructions on a pipelined CPU.
4. WHAT ARE THE DIFFERENCES BETWEEN SRAM AND DRAM

CHARACTERISTICS SRAM DRAM

STANDS FOR STATIC RANDOM ACCESS DYNAMIC RANDOM
MEMORY ACCESS MEMORY
DEFINITION IT IS A TYPE OF RAM AND IT IS A TYPE OF RAM AND
USUALLY USES LATCHES USES CAPASITORS TO
TO STORE CHARGE. SRAM STORE BITS IN THE
MAKES USE OF AN ARRAY FORM OF CHARGE. DRAM
OF 6 TRANSISTORS. MAKES USE OF SINGLE
TRANSISTOR AND
CAPACITOR FOR EACH
MEMORY CELL
SPEED FASTER SLOWER
SIZE BIGGER SMALLER
COST MORE EXPENSIVE PER BIT LESS EXPENSIVE PER BIT
ACCESS EASY HARDER
CONSTRUCTION DIFFICULT SIMPLE
POWER CONSUMPTION LESS MORE
EXECUTING DOES NOT NEEDED TO NEEDS REFRESHING
REFRESH
others SRAMS ARE USED IN DRAMS ARE USED FOR
CACHES BECAUSE OF MAIN MEMORY IN A PC
HIGHER SPEED BECAUSE OF HIGHER
DENSITIES.

SRAM is stands for STATIC RANDOM ACCESS MEMORY. IT IS A TYPE OF RAM AND
USUALLY USES LATCHES TO STORE CHARGE. SRAM MAKES USE OF AN ARRAY OF 6
TRANSISTORS. The following are characteristics of SRAM: FAST SPEED, BIGGER SIZE,
MORE EXPENSIVE PER BIT, EASY ACCESS, DIFFICULT CONSTRUCTION, LESS POWER
CONSUMPTION, DOES NOT NEEDED TO REFRESH AND USES CACHES.
DRAM is stands for DYNAMIC RANDOM ACCESS MEMORY. IT IS A TYPE OF RAM AND
USES CAPASITORS TO STORE BITS IN THE FORM OF CHARGE. DRAM MAKES USE OF
SINGLE TRANSISTOR AND CAPACITOR FOR EACH MEMORY CELL. The following are
characteristics of SRAM: SLOWER SPEED, SMALLER SIZE, LESS EXPENSIVE PER BIT,
HARD ACCESS, SIMPLE CONSTRUCTION, MORE POWER CONSUMPTION, NEEDED TO
REFRESH AND USES MAIN MEMORY.
To summarized, see
https://drive.google.com/open?id=1RUf5sVyUmsOGsdIBhWPKfJPL6z48qjnI.
 5. DESCRIBE THE CONVERSION PROCESS OF THE SOURCE CODE FROM THE
ARDUINO IDE TO THE ARDUINO DEVICE
After WRITING THE CODE is COMPILED using Arduino IDE, it should be UPLOADED to
the main microcontroller of the Arduino UNO using a USB CONNECTION. Since the
microcontroller doesn’t have a USB transceiver, it is needed to have converter of signals
between the SERIAL INTERFACE (UART INTERFACE) of the MICROCONTROLLER and
the HOST USB SIGNALS. To show better illustration, see
https://drive.google.com/open?id=1sZHjDmczkCxDOUCJKYxW8S9Uzp90kG4j.
6. WHAT IS MOORE’S LAW?
It is a prediction of Gordon Moore that states that every year, their invention or
innovation must BE DOUBLED THE NUMBER OF TRANSISTORS PER SQUARE INCH on
the integrated circuit.
7. WHAT ARE THE DIFFERENCES BETWEEN VIRTUAL AND PHYSICAL MEMORY

CHARACTERISTICS PHYSICAL MEMORY VIRTUAL MEMORY

DEFINITION PHYSICAL MEMORY ARE VIRTUAL MEMORY IS
THE RAM CHIPS STORED ON THE HARD
PURCHASED AND PLACED DRIVE. VIRTUAL MEMORY
IN A SLOT ON THE IS USED WHEN THE RAM
COMPUTER IS FILLED.
MOTHERBOARD.
ALLOCATION "FIRST IN, LAST OUT" INFORMATIONS ARE LAID
PROCESS ACROSS THE HARD DRIVE
IN FIXED SIZES
SIZE LIMITED TO THE SIZE OF LIMITED BY THE SIZE OF
THE RAM CHIPS THE HARD DRIVE

PHYSICAL MEMORY ARE THE RAM CHIPS PURCHASED AND PLACED IN A SLOT ON THE
COMPUTER MOTHERBOARD. IT USES "FIRST IN, LAST OUT" PROCESS. THE SIZE IS
LIMITED TO THE SIZE OF THE RAM CHIPS. HOWEVER, VIRTUAL MEMORY IS STORED
ON THE HARD DRIVE. VIRTUAL MEMORY IS USED WHEN THE RAM IS FILLED.
INFORMATIONS ARE LAID ACROSS THE HARD DRIVE IN FIXED SIZES. ITS SIZE IS
LIMITED BY THE SIZE OF THE HARD DRIVE. (see:
https://drive.google.com/open?id=1qsH816NqaA9KQUa_-hYHHc8AIwIi8kfw)
8. WHAT IS THE VON NEUMANN MODEL?
The Von Neumann Model is simply a model of a computer containing CPU, memory and
input/output devices. The block diagram shows in
https://drive.google.com/open?id=1QEsT4VNlXqPOnlhzwt8GCfVlSFWU2uCV.
 9. DISCUSS THE DIFFERENCES BETWEEN MEMORYAND STORAGE

CHARACTERISTICS MEMORY STORAGE

DEFINITION REFERS TO THE REFERS TO THE
COMPONENT IN THE COMPONENT TO THE
COMPUTER THAT ALLOWS COMPUTER THAT ALLOWS
TO ACCESS DATA THAT IS TO STORE AND ACCESS
STORED FOR A SHORT DATA IN A LONG TERM.
TERM.
WHEN SHUTTING CLEARS ALL THE REMAINS INTACT
DOWN THE COMPUTER ACTIVITIES
EXAMPLES EDITING A DOCUMENT, APPLICATIONS,
LOADING APPLICATIONS OPERATING SYSTEM AND
AND BROWSING THE FILES
INTERNET
SIZE LIMITED TO THE SIZE OF LIMITED BY THE SIZE OF
THE RAM CHIPS THE HARD DRIVE

Memory REFERS TO THE COMPONENT IN THE COMPUTER THAT ALLOWS TO ACCESS

DATA THAT IS STORED FOR A SHORT TERM. When shutting down the computer, it
CLEARS ALL THE ACTIVITIES. For example, EDITING A DOCUMENT, LOADING
APPLICATIONS AND BROWSING THE INTERNET. Its size is LIMITED TO THE SIZE OF
THE RAM CHIPS. On the other hand, storage REFERS TO THE COMPONENT TO THE
COMPUTER THAT ALLOWS TO STORE AND ACCESS DATA IN A LONG TERM. When
shutting down the computer, the information REMAINS INTACT. For example,
APPLICATIONS, OPERATING SYSTEM AND FILES. Its size is LIMITED BY THE SIZE OF
THE HARD DRIVE. (see:
https://drive.google.com/open?id=1EqjJOmJCxkxfSPQ__1j1oF4s996MAU7n)
10. WHAT IS CACHE?
Cache is a temporary memory wherein it is placed near the main memory wherein it is
designed to make the processing of the applications or any data that has been already
opened would speed up.