ASSIGNMENT 2

M12497296
Harshavardhan Medasani
1. Design a static CMOS circuit to generate f given a, b, c and d. Assume an external load at f
of 100fF. The desired maximum delay of the circuit is 10 ns assuming near-ideal step
inputs. Measure the delay from the time the inputs change to the time the output reaches
its final stable value. Size the circuit using Spice. Submit the circuit diagram annotated
with the transistor sizes. Write your last name, first name, M-number and the logic
expression of f next to the circuit diagram. Submit the Spice file and annotated simulation
results to show that the circuit works as desired.

f = (𝒂. 𝒃) + (𝒄. 𝒅)

pfet width = 2.4u pfet length = 0.6u

nfet width = 2.4u nfet length = 0.6u

HSPICE Code:
* ref

mp1 n2 a nd nd pfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mp2 n2 b nd nd pfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mp3 Out c n2 n2 pfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mp4 Out d n2 n2 pfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mn1 Out a n3 n3 nfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mn2 n3 b Gnd Gnd nfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mn3 Out c n4 n4 nfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

mn4 n4 d Gnd Gnd nfet w=2.4u l=0.6u

+ ad=4.8p pd=8.8u as=4.8p ps=8.8u

Cload Out Gnd 100fF

** hspice subcircuit dictionary
.include /home/medasahy/work/model_t36s.sp

Vdd nd Gnd DC 5v

Va A Gnd PULSE(5v 0 0n 0.01n 0.01n 8n 32.02n)

Vb B Gnd PULSE(5v 0 0n 0.01n 0.01n 8n 32.02n)
Vc C Gnd PULSE(5v 0 0n 0.01n 0.01n 8n 32.02n)
Vd D Gnd PULSE(5v 0 0n 0.01n 0.01n 8n 32.02n)
.options post
.tran 0.1n 40n
.plot V(Out)
.end

Simulation:
Output without capacitor
Results:

S. No. Property Value

1. Rise Time 153ps
2. Fall Time 60.6ps
3. Delay (Low to Low) 310ps
4. Delay (High to High) 720ps

Output with Capacitor

Results:

S. No. Property Value

1. Rise Time 1.34ns
2. Fall Time 536ps
3. Delay (Low to Low) 3.1ns
4. Delay (High to High) 4.88ns
MOS Diagram for the above-mentioned logic equation:

Note: Dimensions are in length x width

2. Design a CMOS layout for f using the sizing you did. Use the Magic layout editor with the
correct technology files. Extract and simulate the circuit using Spice (without attaching
any external load). Submit an annotated layout (in color if possible), extracted and
annotated Spice file, and annotated simulation wave forms identifying the worst-case
delay and worst-case rise and fall times.

f = (𝑎. 𝑏) + (𝑐. 𝑑)

NOTE: There are three different layouts corresponding to the same logic equation stated above
namely ckt1, ckt2, ckt3. This report compares the three different layouts with respect to delay, rise
and fall times.
ckt1 MAGIC Layout:
 ckt1 HSPICE Code without capacitor:
* HSPICE file created from ckt1.ext - technology: scmos

.option scale=1u

m1000 a_28_23 A Vdd Vdd pfet w=8 l=2

+ ad=272 pd=104 as=160 ps=80
m1001 Vdd B a_28_23 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 a_28_23 C Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=160 ps=80
m1003 Out D a_28_23 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 Out A a_20_n9 Gnd nfet w=8 l=2
+ ad=128 pd=88 as=48 ps=28
m1005 Out C a_44_n10 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=56 ps=30
m1006 a_20_n9 B Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=88 ps=78
m1007 a_44_n10 D Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 B Vdd 2.4fF
C1 Gnd GND 12.0fF
C2 Out GND 13.5fF
C3 D GND 18.1fF
C4 C GND 14.2fF
C5 a_28_23 GND 3.2fF
C6 A GND 17.3fF
C7 Vdd GND 8.3fF
C8 B GND 31.9fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp

*Cload Out Gnd 100fF

Vdd Vdd Gnd DC 5v
*for worst case calculation
Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
*for circuit verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

.options post
.tran 0.1n 130n
.plot V(Out)
.end
ckt1 Simulation:
a) Output:
 b) Propagation Delay:
Propagation Delay High to High
Propagation Delay Low to Low
 c) Worst case Scenario:
Worst case Rise Time
Worst case Fall Time

Results:

S. No. Property Value

1. Rise Time 5.39ns
2. Fall Time 1.86ns
3. Delay (Low to Low) 9.65ns
4. Delay (High to High) 7.57ns
ckt2 MAGIC Layout:

ckt2 HSPICE Code without Capacitor:

* HSPICE file created from ckt2.ext - technology: scmos

.option scale=1u

m1000 a_24_34 A Vdd Vdd pfet w=8 l=2

+ ad=144 pd=72 as=128 ps=72
m1001 Vdd B a_24_34 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 a_24_34 D Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=136 ps=74
m1003 Out C a_24_34 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 a_24_5 A Out Gnd nfet w=8 l=2
+ ad=64 pd=32 as=136 ps=90
m1005 Gnd B a_24_5 Gnd nfet w=8 l=2
+ ad=216 pd=82 as=0 ps=0
m1006 a_61_5 D Gnd Gnd nfet w=8 l=2
+ ad=64 pd=32 as=0 ps=0
m1007 Out C a_61_5 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 Out GND 15.3fF
C1 C GND 9.2fF
C2 a_24_34 GND 9.1fF
C3 D GND 9.2fF
C4 B GND 9.2fF
C5 A GND 9.2fF
C6 Vdd GND 4.9fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp

*Cload Out Gnd 100fF

Vdd Vdd Gnd DC 5v

*worst case calculation

Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)

*output verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

*Va A Gnd PWL(0 0 7n 0 8n 5V 15n 5v 16n 0v 39n 0v 40n 5v 47n 5v 48n 0v

55n 0v 56n 5v 63n 5v 64n 0v )
*Vb B Gnd PWL(0 0v 15n 0v 16n 5v 23n 5v 24n 0v 39n 0v 40n 5v 47n 5v
48n 0v 55n 0v 56n 0v 63n 0v 64n 5v 71n 5v 72n 0v )
*Vc C Gnd PWL(0 0v 23n 0v 24n 5v 31n 5v 32n 0 79n 0v 80n 5v 95n 5v 96n
0v )
*Vd D Gnd PWL(0 0v 31n 0v 32n 5v 39n 5v 40n 0v 79n 0v 80n 5v 87n 5v
88n 0v 95n 0v 96n 5v 103n 5v 104n 0v )
.options post
.tran 0.1n 140n
.plot V(Out)
.end
ckt2 Simulation:

a) Output:
 b) Propagation Delay:

High to High
Low to Low
 c) Worst Case Scenario:

Rise time
Fall Time

Results:

S. No. Property Value

1. Rise Time 5.24ns
2. Fall Time 1.59ns
3. Delay (Low to Low) 9.39ns
4. Delay (High to High) 7.44ns
ckt3 MAGIC Layout:

ckt3 HSPICE Code without capacitor:

* HSPICE file created from ckt3.ext - technology: scmos

.option scale=1u
m1000 n0 a Vdd Vdd pfet w=8 l=2
+ ad=224 pd=128 as=160 ps=80
m1001 Vdd b n0 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 n0 c Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=160 ps=80
m1003 Out d n0 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 Out a n1 Gnd nfet w=8 l=2
+ ad=80 pd=76 as=64 ps=60
m1005 Out c n2 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=64 ps=60
m1006 n1 b Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=80 ps=76
m1007 n2 d Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 b Vdd 2.4fF
C1 Gnd GND 12.0fF
C2 d GND 18.8fF
C3 Out GND 13.5fF
C4 c GND 14.0fF
C5 n0 GND 6.0fF
C6 a GND 17.3fF
C7 Vdd GND 9.0fF
C8 b GND 32.6fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp

*Cload Out Gnd 100fF

Vdd Vdd Gnd DC 5v

*worst case
Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)

*output verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

.options post
.tran 0.1n 140n
.plot V(Out)
.end
ckt3 Simulation:

a) Output
 b) Propagation Delay:

High to High
Low to Low
 c) Worst Case Scenario:

Rise Time
Fall Time

Results:

S. No. Property Value

1. Rise Time 5.18ns
2. Fall Time 1.72ns
3. Delay (Low to Low) 9.15ns
4. Delay (High to High) 8.15ns
3. Edit the extracted Spice file to attach a 100 fF capacitor at the output node. Simulate
using Spice. Submit the Spice file and annotated Spice simulation results showing the
worst-case delay and worst-case rise and fall times. How do these delays compare with
the predicted worst case delays from the Spice simulations before the layout was done?
Explain why the differences, if any, occurred.

f = (𝒂. 𝒃) + (𝒄. 𝒅)

pfet width = 2.4u pfet length = 0.6u

nfet width = 2.4u nfet length = 0.6u

NOTE: There are three different layouts corresponding to the same logic equation stated above
namely ckt1, ckt2, ckt3. This report compares the three different layouts with respect to delay, rise
and fall times.

ckt1 HSPICE Code with capacitor:

* HSPICE file created from ckt1.ext - technology: scmos

.option scale=1u

m1000 a_28_23 A Vdd Vdd pfet w=8 l=2

+ ad=272 pd=104 as=160 ps=80
m1001 Vdd B a_28_23 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 a_28_23 C Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=160 ps=80
m1003 Out D a_28_23 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 Out A a_20_n9 Gnd nfet w=8 l=2
+ ad=128 pd=88 as=48 ps=28
m1005 Out C a_44_n10 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=56 ps=30
m1006 a_20_n9 B Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=88 ps=78
m1007 a_44_n10 D Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 B Vdd 2.4fF
C1 Gnd GND 12.0fF
C2 Out GND 13.5fF
C3 D GND 18.1fF
C4 C GND 14.2fF
C5 a_28_23 GND 3.2fF
C6 A GND 17.3fF
C7 Vdd GND 8.3fF
C8 B GND 31.9fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp
Cload Out Gnd 100fF
Vdd Vdd Gnd DC 5v
*for worst case calculation
Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
*for circuit verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

.options post
.tran 0.1n 130n
.plot V(Out)
.end
ckt1 Simulation:
a) Propagation Delay:
Propagation Delay High to High
Propagation Delay Low to Low
 b) Worst case Scenario:
Worst case Rise Time
Worst case Fall Time

Results:

S. No. Property Layout Value Reference Value

1. Rise Time 7.23ns 1.34ns
2. Fall Time 2.39ns 536ps
3. Delay (Low to Low) 5.96ns 3.1ns
4. Delay (High to High) 10ns 4.88ns
ckt2 HSPICE Code with Capacitor:
* HSPICE file created from ckt2.ext - technology: scmos

.option scale=1u

m1000 a_24_34 A Vdd Vdd pfet w=8 l=2

+ ad=144 pd=72 as=128 ps=72
m1001 Vdd B a_24_34 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 a_24_34 D Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=136 ps=74
m1003 Out C a_24_34 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 a_24_5 A Out Gnd nfet w=8 l=2
+ ad=64 pd=32 as=136 ps=90
m1005 Gnd B a_24_5 Gnd nfet w=8 l=2
+ ad=216 pd=82 as=0 ps=0
m1006 a_61_5 D Gnd Gnd nfet w=8 l=2
+ ad=64 pd=32 as=0 ps=0
m1007 Out C a_61_5 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 Out GND 15.3fF
C1 C GND 9.2fF
C2 a_24_34 GND 9.1fF
C3 D GND 9.2fF
C4 B GND 9.2fF
C5 A GND 9.2fF
C6 Vdd GND 4.9fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp

Cload Out Gnd 100fF

Vdd Vdd Gnd DC 5v

*worst case calculation

Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
*output verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

.options post
.tran 0.1n 140n
.plot V(Out)
.end
ckt2 Simulation:

a) Propagation Delay:

High to High
Low to Low
 b) Worst Case Scenario:

Rise time
Fall Time

Results:

S. No. Property Layout Value Reference Value

1. Rise Time 6.87ns 1.34ns
2. Fall Time 2.13ns 536ps
3. Delay (Low to Low) 6.41ns 3.1ns
4. Delay (High to High) 9.53ns 4.88ns
ckt3 HSPICE Code with capacitor:
* HSPICE file created from ckt3.ext - technology: scmos

.option scale=1u
m1000 n0 a Vdd Vdd pfet w=8 l=2
+ ad=224 pd=128 as=160 ps=80
m1001 Vdd b n0 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1002 n0 c Out Vdd pfet w=8 l=2
+ ad=0 pd=0 as=160 ps=80
m1003 Out d n0 Vdd pfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
m1004 Out a n1 Gnd nfet w=8 l=2
+ ad=80 pd=76 as=64 ps=60
m1005 Out c n2 Gnd nfet w=8 l=2
+ ad=0 pd=0 as=64 ps=60
m1006 n1 b Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=80 ps=76
m1007 n2 d Gnd Gnd nfet w=8 l=2
+ ad=0 pd=0 as=0 ps=0
C0 b Vdd 2.4fF
C1 Gnd GND 12.0fF
C2 d GND 18.8fF
C3 Out GND 13.5fF
C4 c GND 14.0fF
C5 n0 GND 6.0fF
C6 a GND 17.3fF
C7 Vdd GND 9.0fF
C8 b GND 32.6fF

** hspice subcircuit dictionary

.include /home/medasahy/work/model_t36s.sp

Cload Out Gnd 100fF

Vdd Vdd Gnd DC 5v

*worst case
Vd D Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
VA A Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vb B Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)
Vc C Gnd PWL(0 5v 16n 5v 16.1n 0v 40n 0v 40.1n 5v 64n 5v)

*output verification
*Va A Gnd PULSE(5v 0 0n 0.1n 0.1n 8n 16.02n)
*Vb B Gnd PULSE(5v 0 0n 0.1n 0.1n 16n 32.02n)
*Vc C Gnd PULSE(5v 0 0n 0.1n 0.1n 32n 64.02n)
*Vd D Gnd PULSE(5v 0 0n 0.1n 0.1n 64n 128.02n)

.options post
.tran 0.1n 140n
.plot V(Out)
.end

ckt3 Simulation:

a) Propagation Delay:

High to High
Low to Low
 b) Worst Case Scenario:

Rise Time
Fall Time

Results:

S. No. Property Layout Value Reference Value

1. Rise Time 7.22ns 1.34ns
2. Fall Time 2.29ns 536ps
3. Delay (Low to Low) 6.23ns 3.1ns
4. Delay (High to High) 9.53ns 4.88ns
Observations and Inference:

• The delays and rise and fall times before and after the layout vary by a significant number.
• This difference can be because of the intrinsic capacitances (C0 to C8) generated in the layout
shown in the extracted HSPICE code.
• As the layout consists of different layers in contact which also involves metal wires, this creates
some capacitance to be built up in the circuit.
• The extracted HSPICE code also contains intrinsic capacitances between terminals of the same
transistor. This is not included in the initial (reference) HSPICE code created.
• Thus, it can be concluded that the difference in the delays and rise and fall times between the 2
codes before and after layout is due to the intrinsic capacitances in the layout.
4. Extract and simulate the circuit using IRSIM after attaching a 100 fF external capacitor at the
output node. Submit annotated simulation waveforms and IRSIM circuit file. Compare and
comment on the simulation results when using Spice vs. IRSIM.

f = (𝒂. 𝒃) + (𝒄. 𝒅)

pfet width = 2.4u pfet length = 0.6u

nfet width = 2.4u nfet length = 0.6u

IRSIM sim file:

| units: 100 tech: scmos format: SU
p A Vdd a_28_23# 2 8 26 43 g=S_Vdd! s=A_160,P_80 d=A_272,P_104
p B a_28_23# Vdd 2 8 44 43 g=S_Vdd! s=A_0,P_0 d=A_0,P_0
p C Out a_28_23# 2 8 26 23 g=S_Vdd! s=A_160,P_80 d=A_0,P_0
p D a_28_23# Out 2 8 44 23 g=S_Vdd! s=A_0,P_0 d=A_0,P_0
n A a_20_n9# Out 2 8 20 -3 g=S_Gnd! s=A_48,P_28 d=A_128,P_88
n C a_44_n10# Out 2 8 44 -3 g=S_Gnd! s=A_56,P_30 d=A_0,P_0
n B Gnd a_20_n9# 2 8 20 -11 g=S_Gnd! s=A_88,P_78 d=A_0,P_0
n D Gnd a_44_n10# 2 8 44 -12 g=S_Gnd! s=A_0,P_0 d=A_0,P_0
C B Vdd 2.4
C Gnd GND 12.0
R Gnd 407
R a_44_n10# 30
R a_20_n9# 36
C Out GND 13.5
R Out 818
C D GND 18.1
R D 978
C C GND 14.2
R C 787
C a_28_23# GND 3.2
R a_28_23# 465
C A GND 17.3
R A 942
C Vdd GND 8.3
R Vdd 470
C B GND 31.9
R B 1670
Cload Out Gnd 100fF
IRSIM command file:
stepsize 100

vector In1 A
vector In2 B
vector In3 C
vector In4 D
vector In5 Vdd

analyzer In1 Out

analyzer In2 Out
analyzer In3 Out
analyzer In4 Out
analyzer In5 Out

setvector In1 0
setvector In2 0
setvector In3 0
setvector In4 0
setvector In5 1
s

setvector In1 1
setvector In2 0
setvector In3 0
setvector In4 0
setvector In5 1
s

setvector In1 0
setvector In2 1
setvector In3 0
setvector In4 0
setvector In5 1
s

setvector In1 1
setvector In2 1
setvector In3 0
setvector In4 0
setvector In5 1
s

setvector In1 0
setvector In2 0
setvector In3 1
setvector In4 0
setvector In5 1
s
setvector In1 1
setvector In2 0
setvector In3 1
setvector In4 0
setvector In5 1
s
setvector In1 0
setvector In2 1
setvector In3 1
setvector In4 0
setvector In5 1
s

setvector In1 1
setvector In2 1
setvector In3 1
setvector In4 0
setvector In5 1
s

setvector In1 0
setvector In2 0
setvector In3 0
setvector In4 1
setvector In5 1
s

setvector In1 1
setvector In2 0
setvector In3 0
setvector In4 1
setvector In5 1
s
setvector In1 0
setvector In2 1
setvector In3 0
setvector In4 1
setvector In5 1
s

setvector In1 1
setvector In2 1
setvector In3 0
setvector In4 1
setvector In5 1
s

setvector In1 0
setvector In2 0
setvector In3 1
setvector In4 1
setvector In5 1
s
setvector In1 1
setvector In2 0
setvector In3 1
setvector In4 1
setvector In5 1
s
setvector In1 0
setvector In2 1
setvector In3 1
setvector In4 1
setvector In5 1
s
setvector In1 1
setvector In2 1
setvector In3 1
setvector In4 1
setvector In5 1
s
IRSIM Simulation:

Output:

Delay:

Observation:

• Delay: 1.13 units

5. Summarize what you learned from this homework.
• This homework helped improve the proficiency in MAGIC software to draw layouts for circuits.
• Through this homework it became clear that there are many factors affecting the final output of
the layout.
• Comparing the initial Spice file and the one extracted from the layout, it can be deduced that
the differences in characteristics of the output is due to the additional intrinsic capacitances in
the layout.
• Apart from that, after creating the same logic circuit in three different layouts, it was
understood that though the output (HSPICE) characteristics are similar, there are minor
differences due to the layout differences.
• Thus, for a logic circuit, the appropriate layout design is necessary to get the necessary output.