Unit - II

• Elements of VHDL
• Data objects - store values of a given type
• Literals - represent constant values
• Operators - operate on data objects.
• Every data object belongs to a specific type.
• Identifiers -a sequence of one or more characters
• The first character in an identifier must be a letter and
the last character may not be an underscore.
 Continued..
• Lower-case and upper-case letters are considered to be identical
when used in an identifier; as an example. Count, COUNT, and
CouNT, all refer to the same identifier.

• Also,-two underscore characters cannot appear consecutively.

• Comments in a description must be preceded by two consecutive

hyphens (-); the comment extends to the end of the line. Comments
can appear anywhere within a description .
 Data Objects
• holds a value of a specified type.
• created by means of an object declaration
• E.g variable COUNT: INTEGER;
• Here COUNT is data object

• Every data object belongs to one of the following three classes:

• Class indicates what can be done with the object.

1. Constant: can hold a single value of a given type. This value is

assigned to the object before simulation starts and the value cannot
be changed during the course of the simulation.

2. Variable: hold a single value of a given type. However in this case,

different values can be assigned to the object at different times using
a variable assignment statement.
 Continued..
3. Signal: has a past history of values, a current value, and a
set of future values. Future values can be assigned to a signal
object using a signal assignment statement.

• Signal objects can be regarded as wires in a circuit .

 Constant Declarations
• constant RISE_TIME: TIME := 10ns;
• constant BUS_WIDTH: INTEGER := 8:
• constant NO_OF_INPUTS: INTEGER;
• In the third example the value of the constant has not been specified
Such a constant is called a deferred constant and it can appear only
inside a package declaration. The complete constant declaration
with the associated value must appear in the corresponding
package body.
 Variable Declarations
• variable CTRL_STATUS: BIT_VECTOR(10 downto 0);
• variable SUM: INTEGER range 0 to 100 := 10;
• variable FOUND, DONE: BOOLEAN;

• The first declaration specifies a variable object CTRL_STATUS

as an array of 11 elements, with each array element of type BIT.

• In the second declaration, an explicit initial value has been

assigned to the variable SUM.
 Signal Declarations
• signal CLOCK: BIT;
• signal DATA_BUS: BIT_VECTOR(0 to 7);
• signal GATE_DELAY: TIME := 10 ns;

• The first signal declaration declares the signal object CLOCK of

type BIT and gives it an initial value of '0' ('0' being the leftmost
value of type BIT).

• The third signal declaration declares a signal object

GATE_DELAY of type TIME that has an initial value of 10 ns.
 Other Ways to Declare Objects

• Not all objects in a VHDL description are created using object

declarations. These other objects are declared as

1. ports of an entity - All ports are signal objects.

2. generics of an entity - These are constant objects.
3. formal parameters of functions and procedures –
Function parameters are constant objects or signal objects while
procedure parameters can belong to any object class.

• There are two other types of objects that are implicitly declared.
These are the indices of a for. . . loop statement and the generate
statement
 Continued..

• An example of such an implicit declaration for the loop index in

a for. . . loop statement is shown.
• for COUNT in 1 to 10 loop
• SUM := SUM + COUNT;
• end loop;

• In this for . . . loop statement, object COUNT has an implicit

declaration of type INTEGER with range 1 to 10, and therefore,
need not be explicitly declared.
• The object COUNT is created when the loop is first entered and
ceases to exist after the loop is exited.
 Data Types
• Every data object in VHDL can hold a value that belongs to a
set of values. This set of values is specified by using a type
declaration.

• A type is a name that has associated with it a set of values and

a set of operations.
• A signal (or variable) with a particular type can only be
assigned a value in the set of values that is defined for the type.
• Signals and/or values and/or expression must have matching
type at both side of the assignment ("<=").
• For example, INTEGER is a predefined type with the set of
values being integers in a specific range provided by the VHDL
system.
• The minimum range that must be provided is -(2^31 - 1) through
+(2^31 - 1).
 Standard types

• BIT : has two values represented as characters ‘0’ & ‘1’.

• has a set of logical & comparison operators.
• in practice very rarely used since has only two levels.

• Boolean: has two values true or false

• - during synthesis true value is represented by logic 1
• and false value by logic 0.
• Bit_vector: one dimensional array with elements of the bit data type.
• With bit & bit_vector one cannot define tristate, pull up, pull down
don’t care,uninitialised
• So std_logic came into existance.
•
• Std_ logic_ vector data types:
• Developed by IEEE to serve as an extension to bit & bit_vector
• Data types.
• Defined in the IEEE standard 1164.
• Consists of nine possible values.
• (‘U’ ,’X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’ ,’-’ )
• Also conversion functions are available for conversion between
• Bit & std_logic data types.
• to_bit (a)
• to_stdulogic(a)
• to_bitvector(a)
• to_stdlogicvector(a)
 Predefined data types
• All the possible types that can exist in the language can be
categorized into the following four major categories:

1. Scalar types: Values belonging to these types appear in a

sequential order.
• Integer-
• Real-
• Enumerated-
boolean
bit (these two are different!)
character
Physical- time
2. Composite types: These are composed of elements of a
single type (an array type) or elements of different types (a
record type).
 Continued..

3. Access types: These provide access to objects of a given

type (via pointers).
• Similar to pointers in other language
• Allows for dynamic allocation of storage
• Useful to implement queues, etc.

4. File types: These provides access to objects that contain a

sequence of values of a given type.
 Scalar Types

• The values belonging to this type are ordered, that is, relational
operators can be used on these values
• E.g – BIT
• There are four different kinds of scalar types. These types are
• 1. enumeration,
• 2. integer,
• 3. physical,
• 4. floating point.

• Enumeration Types
• Suitable for abstract modelling.
• Values of this type are user defined.
 Continued..

• One can represent only the values required for specific operation.
• Values can be identifiers or literals.

• Type MVL is ('U','0','1','Z);

• type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL, DIV);
• subtype ARITH_OP is MICRO_OP range ADD to DIV;
• Examples of objects defined for these types are
• signal CONTROL_A: MVL;
• signal CLOCK: MVL range '0' to '1'; -- Implicit subtype declaration.
• variable IC: MICRO_OP := STORE; -- STORE is the initial value for IC.
• variable ALU: ARITH_OP;
• MVL is an enumeration type that has the set of ordered values, 'U', '0', '1',
and 'Z'.
 Continued..

• Integer Types
• type INDEX is range 0 to 15;
• type WORD_LENGTH is range 31 downto 0;
• Some object declarations using these types are
• constant MUX_ADDRESS: INDEX := 5;

• signal DATA_BUS: DATA_WORD;

 Physical types

• contains values that represent measurement of some physical

quantity, like time, length, voltage, and current.
• Values of this type are expressed as integer multiples of a base
unit. An example of a physical type declaration is

• type CURRENT is range 0 to 1 E9

• units
• nA; -- (base unit) nano-ampere
• uA = 1000 nA; -- micro-ampere
• mA = 1000 µA; --milli-ampere
• Amp = 1000 mA; -- ampere
• end units;
 Floating Point Types

• Floating point literals differ from integer literals by presence of dot.

• Can also be expressed in an exponential form.

• type TTL_VOLTAGE is range -5.5 to -1.4;

• type REAL_DATA is range 0.0 to 31.9;
• An example of an object declaration is
• variable LENGTH: REAL_DATA range 0.0 to 15.9;
 Operators

• The predefined operators in the language are classified into the

following five categories:

• 1. Logical operators (and or nand nor xor xnor not)

• 2. Relational operators (= /= < <= > >=)

• 3. Shift operators (sll srl sla sra rol ror)

• 4. Adding operators (+ - &)

• 5. Multiplying operators (* / mod rem)

• 6. Miscellaneous operators (abs **)

 Continued..

• Concatenation
• In hardware terms, merging of buses to form a large bus.
• Allows an array to be built up out of smaller arrays & elements.
• Ex-
• Signal a ,b :std_logic_vector(15 downto 0);
• Signal z: std_logic_vector(31 downto 0);
• ….
• Z<= a&b;
• Here both sides of vector assignment symbol must be of equal
length.
 Concatenation

• Concatenation operator: &

• Resulting signal assignment:
• architecture EXAMPLE_1 of CONCATENATION is
signal BYTE : bit_vector (7 downto 0);
signal A_BUS, B_BUS : bit_vector (3 downto 0);
begin
BYTE <= A_BUS & B_BUS;
end EXAMPLE;
•
• architecture EXAMPLE_2 of CONCATENATION is
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;

• begin
Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT;
end EXAMPLE;

• The concatenation operator '&' is allowed on the right side

of the signal assignment operator '<=', only
 Arrays

• Collection of objects of same type

• Can be one dimensional, two dimensional ,one D by one D.

• Examples of array type declarations are

• type ADDRESS_WORD is array (0 to 63) of BIT;
• type DATA_WORD is array (7 downto 0) of MVL;
• type ROM is array (0 to 125) of DATA_WORD;
• type DECODE_MATRIX is array (POSITIVE range 15 downto 1,
• NATURAL range 3 downto 0) of MVL;
• --POSITIVE and NATURAL are predefined subtypes; these are:
• subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
• subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
• -- The HIGH attribute gives the highest value belonging to the type.
 Continued..

• Examples of object declarations using these types are

• variable ROM_ADDR: ROM;

• signal ADDRESS.BUS: ADDRESS_WORD;

• constant DECODER: DECODE_MATRIX; - A deferred constant.

• variable DECODE_VALUE: DECODE_MATRIX;

We have thus created an array of arrays.

 Constrained and unconstrained array

• No. of elements is explicitly specified in the type declaration – constrained

• Two predefined one dimensional unconstrained array types are
• STRING and BIT_VECTOR
• For an unconstrained array dimensions and indices types are specified but
bounds for dimensions are not specified.
• Type STD_ULOGIC_VECTOR is array (natural range<>) of
STD_ULOGIC;
• Type STD_LOGIC_VECTOR is array (natural range<>) of STD_LOGIC;
• Declarations using above types
• Signal raster_line : STD_LOGIC_VECTOR (0 to NBITS);
• Variable reg_file: STD_ULOGIC_VECTOR (UPPER_BND downto
LOWER_BND);
• Type that is unconstrained array of an unconstrained array is not allowed.
• Type memory is array (natuaral range<>) of STD_LOGIC_VECTOR
 Slice of array

• A value can be assigned to a bit or part of the array

• Ex
• Architecture
• Signal a_vect: std_logic_vector(4 downto 0);
• Signal b_vect: std_logic_vector(0 to 4);
• Begin
• a_vect(4)<=‘1’;
• a_vect(3 downto 0)<=“0110”;
• b_vect(0 to 3)<=“1001”;
• End;
• When a slice of array is assigned a value ,slice direction must be the
same as in the declaration.
 Aggregate

• Used to assign a value to an object of array .

• Ex
• a<= “10100000”;

• a<= (‘1’,’0’,’1’,’0’,’0’,’0’,’0’,’0’); - positional association

• a<= (7=>’1’, 6=>’0’, 5=>’1’, 4=>’0’, 3=>’0’, 2=>’0’, 1=>’0’, 0=>’0’);

The above is named association.

• a<= (7|5=>’1’, 6|4|3|2|1|0=>’0’);

• Or a <=(7|5 =>’1’, others =>’0’);
 Records

• It is a collection of elements which may be any constrained type

or subtype.
• Unconstrained arrays are not supported.
• Syntax
• Type<identifier> is record
• record definition
• End record;
• To access an element of record ,a dot notation is used.
 Continued..

• Ex –record declaration

• TYPE optype IS ( add, sub, mpy, div, jmp );

• TYPE instruction IS
• RECORD
• opcode : optype;
• src : INTEGER;
• dst : INTEGER;
• END RECORD;

• This example declares three fields: opcode of type optype, and src and
dst of type INTEGER.
• Each field can be referenced by using the name of the record, followed by a
period and the field name.
• PROCESS(X)
• VARIABLE inst : instruction;
• VARIABLE source, dest : INTEGER;
• VARIABLE operator : optype;
• BEGIN
• source := inst.src; --Ok line 1
• dest := inst.src; --Ok line 2
• source := inst.opcode; --error line 3
• operator := inst.opcode; --Ok line 4
• inst.src := dest; --Ok line 5
• inst.dst := dest; --Ok line 6
• inst := (add, dest, 2); --Ok line 7
• inst := (source); --error line 8
• END PROCESS;
 Comparison operators for signed nos
• Maximum of two signed values
• Library ieee;
• Use ieee.std_logic_1164.all;
• Use ieee.std_logic_arith.all;
• Entity max is
• Port (a,b: in signed( 7 downto 0);
• z: out signed (7 downto 0));
• End max;
• Architecture arch of max is
• Begin
• Z<= a when (a>b) else b;
• End arch;
• Packages STD_LOGIC_1164, NUMERIC_BIT, and NUMERIC_STD are
defined by IEEE standards and included in the IEEE Library.
• Although packages STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED,
and STD_ LOGIC_ARITH are usually included by tool vendors in their
IEEE libraries, they are not actually IEEE standards. However, because of
their widespread use, they are de facto standards.
 The NUMERIC_STD Package

• Provides numerical interpretation for 'std_logic' based

vectors
– signed: 2-complement (sign+absolute value)
– unsigned: binary representation of positive integers
• Overloaded mathematical operators
– allow mixture of vector and integer values (vector <= vector + 1)
• Overloaded relational operators
– avoid problems when dealing with different vector lengths
– comparison of vector with integer values
• NUMERIC_BIT package with 'bit' as basis data type
•
• To provide vector types for unsigned and signed arithmetic and to
ensure the widest possible portability between vendors' tools, the
IEEE created IEEE Std 1076.3. This standard defined two numeric
packages
• NUMERIC_ STD is based on vectors with elements that are type
std_Iogic
• The NUMERIC_STD package defines two arithmetic data types,
unsigned and signed, along with arithmetic, shift, type conversion,
and logical operators
• Functions in the package perform arithmetic operations
on unsigned and signed types, and return these types.
• Package NUMERIC_STD defines the types unsigned
and signed as unconstrained arrays:
• type unsigned is array (natural range <» of std logic;
• type signed is array (natural range <» of std_logic;
• While the elements of both the unsigned and signed
types are std_logic, they are two separate types, distinct
from each other and from std_logic_ vector.
• Functions are provided in package NUMERIC_STD to
provide conversions between types unsigned, signed,
and integer.
• All of these functions have the name to_type, where
type is the type being converted to.
• When converting type unsigned or type signed to
integer, the function has a single parameter, the vector
being converted.
• When converting an integer to unsigned or signed, the
function has two parameters. The first is the integer
being converted, and the second is a type natural that
specifies the number of bits in the result vector.
• If i is an integer and unsigned signal y has eight elements,the following
statement assigns the value of integer i to unsigned signal y:
• Y<= to_unsigned(i,8);

• To assign integer i to std_logic_ vector signal x, the previous two

techniques are combined:
• X<= std_logic_vector (to_unsigned (i, 8));
• STD_LOGIC_ARITH contains functions conv unsigned and conv _signed
that are used to resize (truncate or extend) values of the respective types.
• Four different types are used in package STD_LOGIC_ARITH: unsigned
,signed , std_logic_ vector, and integer. Type conversions between
std_logic_ vector and either unsigned or signed are implicit conversions
provided by the built-in conversions between similar array types.
Conversion functions are provided to accomplish other type conversions.
The functions are named conv _ type where type is the name of the type
being converted to.
• Conversion functions that convert to an integer have only one formal
parameter, the vector to be converted. Conversion functions that convert to
a vector have two formal parameters. The first parameter is the vector to be
converted and the second is the number of bits in the result vector. When
the vector converted from and the vector converted to are the same type,
the conversion function is acting as resize function.
• Std_logic_arith package cannot do bitwise logical operation
• Library ieee;
• Use ieee.std_logic_1164.all;
• Use ieee.std_logic_arith.all;
• Entity max is
• Port (a,b: in signed( 7 downto 0);
• z: out signed (7 downto 0));
• End max;
• Architecture arch of max is
• Begin
• Z<=unsigned (std_logic_vector(a) and std_logic-vector(b));
• End;