Arskom Tamvan

“ JAWABAN KISI2 ARSKOM “
Di susun oleh :
“Functional Units of a Computer”
1. The ______ format is usually used to store data.

a) BCD
b) Decimal
c) Hecadecimal
d) Octal
View Answer
Answer: a
Explanation: The data usually used by computers have to be stored and represented in a particular format for
ease of use.
2. The 8-bit encoding format used to store data in a computer is ______

a) ASCII
b) EBCDIC
c) ANCI
d) USCII
View Answer
Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way so as to be
provide secure processing of the data.
3. A source program is usually in _______

a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
View Answer
Answer: c
Explanation: The program written and before being compiled or assembled is called as a source program.
4. Which memory device is generally made of semi-conductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
View Answer
Answer: a
Explanation: Memory devices are usually made of semi conductors for faster manipulation of the contents.
5. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
View Answer
Answer: a
Explanation: These small and fast memory devices are compared to RAM because they optimize the
performance of the system and they only keep files which are required by the current process in them.
6. The ALU makes use of _______ to store the intermediate results.

a) Accumulators
b) Registers
c) Heap
d) Stack
View Answer
Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all the mathematical and logical
operations. In order to perform better it uses some internal memory spaces to store immediate results.
7. The control unit controls other units by generating ____

a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
View Answer
Answer: b
Explanation: This unit is used to control and coordinate between the various parts and components of the
CPU.
8. ______ are numbers and encoded characters, generally used as operands.

a) Input
b) Data
c) Information
d) Stored Values
View Answer
Answer: b
Explanation: Nothing.
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
View Answer
Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer has some data it
sends it to the processor.
10. ______ bus structure is usually used to connect I/O devices.

a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
View Answer
Answer: a
Explanation: BUS is a bunch of wires which carry address,control signals and data. It is used to connect
various components of the computer.
11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
View Answer
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS they’ve a
interface.
12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
View Answer
Answer: d
Explanation: The time required to access a part of the memory for data retrieval.
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
View Answer
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.
14. MFC stands for ___________
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
View Answer
Answer: b
Explanation: This is a system command enabled when a memory function is completed by a process.
15. The time delay between two successive initiation of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
View Answer
Answer: c
Explanation: The time taken to finish one task and to start another.
“Basic Operational Concept”
16. The decoded instruction is stored in ______

a) IR
b) PC
c) Registers
d) MDR
View Answer
Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched and stored in the
IR.
17. The instruction -> Add LOCA, R0 does _______

a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
View Answer
Answer: c
Explanation: Tidak ada penjelasan bosku
18. Which registers can interact with the secondary storage?

a) MAR
b) PC
c) IR
d) R0
View Answer
Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.
19. During the execution of a program which gets initialized first ?

a) MDR
b) IR
c) PC
d) MAR
View Answer
Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.
20. Which of the register/s of the processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both PC and MAR
View Answer
Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory.
21. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
View Answer
Answer: a
Explanation: Nothing
22. The internal Components of the processor are connected by _______

a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
View Answer
Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a direct connection to
the CPU.
23. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
View Answer
Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different results based on
the input.
24. The registers,ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
View Answer
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as data path.
25. _______ is used to store data in registers.

a) D flip flop
b) JK flip flop
c) RS flip flop
View Answer
Answer: a
Explanation: Nothing
“BUS Structure”.
26. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
View Answer
Answer: c
Explanation: By using single BUS structure we can minimize the amount hardware (wire) required and thereby
reducing the cost.
27. ______ are used to over come the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
View Answer
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the processor speed
and the data gets stored in the buffer.After that the data gets sent to or from the buffer to the devices at the
device speed
28. To extend the connectivity of the processor bus we use ________

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
View Answer
Answer: a
Explanation: PCI BUS is used to connect other peripheral devices which require a direct connection with the
processor.
29. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
View Answer
Answer: c
Explanation: tidak ada bosku
30. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
View Answer
Answer: b
Explanation: SCSI BUS is usually used to connect the video devices to the processor.
31. ANSI stands for __________
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
View Answer
Answer: a
32. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
View Answer
Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS only.
33. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
View Answer
Answer: b
34. The main advantage of multiple bus organisation over single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
View Answer
Answer: a
35. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
View Answer
Answer: c
“Addressing Modes”.
36. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
View Answer
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored in the location 45 is
added.
37. In case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
View Answer
Answer: c
Explanation: In this case the operands are implicitly loaded onto the ALU.
38. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
View Answer
Answer: b
39. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
View Answer
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory location and hence we
use pointers to get the data.
40. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
41. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct
View Answer
Answer: b
Explanation: In this the contents of the PC are directly incremented.
42. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
View Answer
Answer: d
Explanation: In case of, auto increment the increment is done afterwards and in auto decrement the decrement
is done first.
43. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
View Answer
Answer: a
44. The effective address of the following instruction is, MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])
View Answer
Answer: c
Explanation: The addressing mode used is base with offset and index.
45. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
View Answer
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
“Memory Locations and Addresses”
46. The smallest entity of memory is called as _______
a) Cell
b) Block
c) Instance
d) Unit
View Answer
Answer: a
Explanation: Each data is made up of a number units.
47. The collection of the above mentioned entities where data is stored is called as ______
a) Block
B) Set
c) Word
d) Byte
View Answer
Answer: c
Explanation: Each readable part of data is called as blocks.
48. An 24 bit address generates an address space of ______ locations.

a) 1024
b) 4096
c) 2 48
d) 16,777,216
View Answer
Answer: d
Explanation: The number of addressable locations in the system is called as address space.
49. If a system is 64 bit machine , then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
View Answer
Answer: b
Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.
50. The type of memory assignment used in Intel processors is _____

a) Little Endian
b) Big Endian
c) Medium Endian
View Answer
Answer: a
Explanation: The method of address allocation to data to be stored is called as memory assignment.
51. When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
View Answer
Answer: a
Explanation: tidak ada boscu
52. To get the physical address from the logical address generated by CPU we use ____
a) MAR
b) MMU
c) Overlays
d) TLB
View Answer
Answer: b
Explanation: Memory Management Unit, is used to add the offset to the logical address generated by the CPU
to get the physical address.
53. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
View Answer
Answer: c
Explanation: Segmentation is a process in which memory is divided into groups of variable length called
segments.
54. During transfer of data between the processor and memory we use ______
a) Cache
b) TLB
C) Buffers
d) Registers
View Answer
Answer: d
55. Physical memory is divided into sets of finite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
View Answer
Answer: a
“Memory Operations and Management”
56. Add #%01011101,R1 , when this instruction is executed then _________
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place , whereas this is similar to a MOV instruction
View Answer
Answer: a
Explanation: This performs operations in binary mode directly.
57. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use ___
symbol before the operand.
a) ~
b) !
c) $
d) *
View Answer
Answer: c
58. When generating physical addresses from logical address the offset is stored in _____
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
View Answer
Answer: b
Explanation: In the MMU the relocation register stores the offset address.
59. The technique used to store programs larger than the memory is ______
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
View Answer
Answer: a
Explanation: In this, only a part of the program getting executed is stored on the memory and later swapped in
for the other part.
60. The unit which acts as an intermediate agent between memory and backing store to reduce process time is
_____
a) TLB’s
b) Registers
c) Page tables
d) Cache
View Answer
Answer: d
Explanation: The cache’s help in data transfers by storing most recently used memory pages.
61. The Load instruction does the following operation/s,
a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
View Answer
Answer: b
Explanation: The load instruction is basically used to load the contents of a memory location onto a register.
62. Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
View Answer
Answer: d
63. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
View Answer
Answer: b
Explanation: The files which are required for the starting up of a system are stored on the ROM.
64. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
View Answer
Answer: a
Explanation: This mode of transfer involves the transfer of a large block of data from the memory.
65. Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
View Answer
Answer: c
Explanation: In this method only when the routine is required is loaded and hence saves memory.
“Accessing I/O Devices”
66. In memory-mapped I/O ____________
a) The I/O devices and the memory share the same address space
b) The I/O devices have a seperate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
View Answer
Answer: a
Explanation: Its the different modes of accessing the i/o devices.
67. The usual BUS structure used to connect the I/O devices is
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
View Answer
Answer: c
Explanation: BUS is a collection of address,control and data lines used to connect the various devices of the
computer.
68. In intel’s IA-32 architecture there is a seperate 16 bit address space for the I/O devices?
a) False
b) True
View Answer
Answer: b
Explanation: This type of accessing is called as I/O mapped devices.
69. The advantage of I/O mapped devices to memory mapped is

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
View Answer
Answer: c
Explanation: Since the I/O mapped devices have a seperate address space the address lines are limited by
amount of the space allocated.
70. The system is notified of a read or write operation by

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
View Answer
Answer: d
Explanation: It is necessary for the processor to send a signal intimating the request as either read or write.
71. To overcome the lag in the operating speeds of the I/O device and the processor we use
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
View Answer
Answer: b
Explanattion: The processor operating is much faster than that of the I/O devices , so by using the status flags
the processor need not wait till the I/O operation is done. It can continue with its work until the status flag is
set.
72. The method of accessing the I/O devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
View Answer
Answer: a
Explanation: In this method the processor constantly checks the status flags , and when it finds that the flag is
set it performs the appropriate operation.
73. The method of synchronising the processor with the I/O device in which the device sends a signal when it is
ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
View Answer
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power to the devices,
enabling them to intimate the processor when they’re ready for transfer.
74. The method which offers higher speeds of I/O transfers is

a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
View Answer
Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the memory with out the intervention
of the processor and the transfres take place in the form of blocks increasing the speed of operaion.
75. The process where in the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer: a
“Standard I/O Interfaces”

76. ______ is used as an intermediate to extend the processor BUS.
a) Bridge
b) Router
c) Connector
d) Gateway
View Answer
Answer: a
Explanation: The bridge circuit is basically used to extend the processor BUS to connect devices.
77. ________ is an extension of the processor BUS.

a) SCSI BUS
b) USB
c) PCI BUS
View Answer
Answer: c
Explanation: The PCI BUS is used as an extension of the processor BUS and devices connected to it, is like
connected to the Processor itself.
78. ISA stands for

a) International American Standard
b) Industry Standard Architecture
c) International Standard Architecture
View Answer
Answer: b
Explanation: The ISA is a architectural standard developed by IBM for its PC’s.
79. ANSI stands for

a) American National Standards Institute
b) Architectural National Standards Institute
c) Asian National Standards Institute
View Answer
Answer: a
Explanation: The ANSI is one of the standard architecture used by companies in designing the systems.
80. The video devices are connected to ______ BUS.

a) PCI
b) USB
c) HDMI
d) SCSI
View Answer
Answer: d
Explanation: The SCSI BUS is used to connect the video devices to processor by providing a parallel BUS.
81. SCSI stands for ___________

a) Signal Computer System Interface
b) Small Computer System Interface
c) Small Coding System Interface
d) Signal Coding System Interface
View Answer
Answer: b
Explanation: The SCSI BUS is used to connect disks and video controllers.
82. ISO stands for __________

a) International Standards Organisation
b) International Software Organisation
c) Industrial Standards organisation
d) Industrial Software Organisation
View Answer
Answer: a
Explanation: The ISO is yet another architectural standard, used to design systems.
83. The system developed by IBM with ISA architecture is ______

a) SPARC
b) SUN-SPARC
c) PC-AT
View Answer
Answer: c
84. IDE disk is connected to the PCI BUS using ______ interface.
a) ISA
b) ISO
c) ANSI
d) IEEE
View Answer
Answer: a
85. IDE stands for _________

a) Intergrated Device Electronics
b) International Device Encoding
c) Industrial Decoder Electronics
d) International Decoder Encoder
View Answer
Answer: a
Explanation: The IDE interface is used to connect the harddisk to the processor in most of the Pentium
processors.
“Parallel Port”
86. The _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger
View Answer
Answer: c
Explanation: The signal generated upon the pressing of a button is encoded by the encoder circuit into the
corresponding ASCII value.
87. To overcome multiple signals being generated upon a single press of the button, we make use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit
View Answer
Answer: b
Explanation: When the button is pressed,the contact surfaces bounce and hence it might lead to generation of
multiple signals.In order to overcome this we use Debouncing circuits.
88. The best mode of conncetion between devices which need to send or recieve large amounts of data over a
short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port
View Answer
Answer: c
Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence
increasing transfer rates.
89. The output of the encoder circuit is/are ______

a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
View Answer
Answer: b
Explanation: The encoder outputs the ASCII value along with the valid signal which indicates that a key was
pressed.
90. The disadvantage of using parallel mode of communication is ______
a) It is costly
b) Leads to erroneous data transfer
c) Security of data
d) All of the mentioned
View Answer
Answer: a
Explanation: The parallel mode of data transfer is costly as it involves data being sent over parallel lines.
91. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register
View Answer
Answer: d
92. The Status flag circuit is implemented using _____

a) RS flip flop
b) D flip flop
c) JK flip flop
d) Xor circuit
View Answer
Answer: b
Explanation: The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge
of the valid signal.
93. In the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data
b) Idle signal
c) Interrupt
d) Acknowledge signal
View Answer
Answer: b
Explanation: The idle signal is used to check if the device is idle and ready to receive data.
94. DDR stands for __________

a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
View Answer
Answer: a
Explanation: This register is used to control the flow of data from the DATAOUT register.
95. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
View Answer
Answer: a
“Serial Port”
96. The mode of transmission of data, where one bit is sent for each clock cycle is ______
a) Asynchronous
b) Parallel
c) Serial
d) Isochronous
View Answer
Answer: d
Explanation: In isochronous mode of transmission, each bit of the data is sent per each cycle.
97. The transformation between the Parallel and serial ports is done with the help of ______
a) Flip flops
b) Logic circuits
c) Shift registers
View Answer
Answer: c
Explanation: The Shift registers are used to output the data in a desired format based on the need.
98. The serial port is used to connect basically _____ and processor.
a) I/O devices
b) Speakers
c) Printer
d) Monitor
View Answer
Answer: a
Explanation: The serial port is used to connect keyboard and other devices which input or output one bit at a
time.
99. The double buffer is used for

a) Enabling receival of multiple bits of input
b) Combining the input and output operations
c) Extending the buffer capacity
View Answer
Answer: a
100. ______ to increase the flexibility of the serial ports.

a) The wires used for ports is changed
b) The ports are made to allow different clock signals for input and output
c) The drivers are modified
View Answer
Answer: b
Explanation: The ports are made more flexible by enabling the input or output of different clock signals for
different devices.
101. UART stands for ________
a) Universal Asynchronous Relay Transmission
b) Universal Accumulator Register Transfer
c) Universal Asynchronous Receiver Transmitter
View Answer
Answer: c
Explanation: The UART is a standard developed for designing serial ports.
102. The key feature of UART is

a) Its architectural design
b) Its simple implementation
c) Its general purpose usage
d) Its enhancement of connecting low speed devices
View Answer
Answer: d
103. The data transfer in UART is done in ______

a) Asynchronous start stop format
b) Synchrnous start stop format
c) Isochronous format
d) EBDIC format
View Answer
Answer: a
Explanation: This basically means that the data transfer is done in asynchronous mode.
104. The standard used in serial ports to facilitate communication is _____

a) RS-246
b) RS-LNK
c) RS-232-C
d) Both RS-246 and RS-LNK
View Answer
Answer: c
Explanation: This is a standard which acts as a protocol for message communication involving serial ports.
105. In serial port interface, the INTR line is connected to _____

a) Status register
b) Shift register
c) Chip select
View Answer
Answer: a
“Static Memories”
106. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time
View Answer
Answer: a
Explanation: The time between the issue of read signal and the completion of it is called memory access time.
107. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
View Answer
Answer: a
Explanation: The Time taken by the cpu to end one read operation and to start one more is cycle time.
108. MFC is used to _________

a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation
View Answer
Answer: c
Explanation: The MFC stands for memory Function Complete.
109. __________ is the bootleneck, when it comes computer performance.

a) Memory access time
b) Memory cycle time
c) Delay
d) Latency
View Answer
Answer: b
Explanation: The processor can execute instructions faster than they’re fetched, hence cycle time is the
bottleneck for performance.
110. The logical addresses generated by the cpu are mapped onto physical memory by ____
a) Relocation register
b) TLB
c) MMU
View Answer
Answer: c
Explanation: The MMU stands for memory management unit, which is used to map logical address onto
phsical address.
111. VLSI stands for ___________
a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
View Answer
Answer: a
112. The cells in a row are connected to a common line called ______
a) Work line
b) Word line
c) Length line
d) Principle diagonal
View Answer
Answer: b
Explanation: This means that the cell contents together form one word of instruction or data.
113. The cells in each column are connected to ______

a) Word line
b) Data line
c) Read line
d) Sense/ Write line
View Answer
Answer: d
Explanation: The cells in each column are connected to the sense/write circuit using two bit lines and which is
inturn connected to the data lines.
114. The word line is driven by the _____

a) Chip select
b) Address decoder
c) Data line
d) Control line
View Answer
Answer: b
115. A 16 X 8 organisation of memory cells, can store upto _____

a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
View Answer
Answer: d
Explanation: It can store upto 128 bits as each cell can hold one bit of data.
116. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised
into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
View Answer
Answer: d
Explanation: All the others require less than 10 address bits.
117. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache
View Answer
Answer: b
118. The number of external connections required in 16 X 8 memory organisation is _____

a) 14
b) 19
c) 15
d) 12
View Answer
Answer: a
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.
119. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption
View Answer
Answer: d
Explanation: This is because the cell consumes power only when it is being accessed.
120. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines
are there.
a) 10
b) 8
c) 9
d) 12
View Answer
Answer: c
Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8
organisation).
“Read-Only Memory”
121. If the transistor gate is closed, then the ROM stores a value of 1.
a) True
b) False
View Answer
Answer: b
Explanation:
122. PROM stands for __________

a) Programmable Read Only Memory
b) Pre-fed Read Only Memory
c) Pre-required Read Only Memory
d) Programmed Read Only Memory
View Answer
Answer: a
Explanation:
123. The PROM is more effective than ROM chips in regard to _______
a) Cost
b) Memory management
c) Speed of operation
d) Both Cost and Speed of operation
View Answer
Answer: d
Explanation:
124. The difference between the EPROM and ROM circuitory is _____
a) The usage of MOSFET’s over transistors
b) The usage of JFET’s over transistors
c) The usage of an extra transistor
View Answer
Answer: c
Explanation:
125. The ROM chips are mainly used to store _______

a) System files
b) Root directories
c) Boot files
d) Driver files
View Answer
Answer: c
Explanation:
126. The contents of the EPROM are earsed by ________
a) Overcharging the chip
b) Exposing the chip to UV rays
c) Exposing the chip to IR rays
d) Discharging the Chip
View Answer
Answer: b
Explanation:
127. The disadvantage of the EPROM chip is _______

a) The high cost factor
b) The low efficiency
c) The low speed of operation
d) The need to remove the chip physically to reprogram it
View Answer
Answer: d
Explanation:
128. EEPROM stands for Electrically Erasable Programmable Read Only Memory.
a) True
b) False
View Answer
Answer: a
Explanation:
129. The disadvantage of the EEPROM is/are ________

a) The requirement of different voltages to read,write and store information
b) The Latency inread operation
c) The inefficient memory mapping schemes used
View Answer
Answer: a
Explanation:
130. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
View Answer
Answer: c
Explanation:
131. The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to be
written.
a) True
b) False
View Answer
Answer: a
Explanation:
132. The flash memories find application in ______

a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
View Answer
Answer: d
Explanation:
133. The memory module obtained by placing a number of flash chips for higher memory storage called as
_______
a) FIMM
b) SIMM
c) Flash card
d) RIMM
View Answer
Answer: c
Explanation:
134. The flash memory modules designed to replace the functioning of an harddisk is ______
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
View Answer
Answer: b
Explanation:
135. The reason for the fast operating speeds of the flash drives is
a) The absence of any movable parts
b) The itegarated electronic hardware
c) The improved bandwidth connection
View Answer
Answer: a
Explanation:
“Heirarchy of Memory”.
136. The standard SRAM chips are costly as _________
a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
View Answer
Answer: b
Explanation: As they require a large number of transistors, their cost per bit increases.
137. The drawback of building a large memory with DRAM is ______________

a) The large cost factor
b) The inefficient memory organisation
c) The Slow speed of operation
View Answer
Answer: c
Explanation: The DRAM’s were used for large memory modules for a long time until a substitute was found.
138. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.
a) True
b) False
View Answer
Answer: a
Explanation: To improve the speed we use flash drives at the cost of memory space.
139. The fastest data access is provided using _______

a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
View Answer
Answer: d
Explanation: The fastest data access is provided using registers as these memory locations are situated inside
the processor.
140. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU
is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
View Answer
Answer: a
Explanation: These memory devices are generally used to map onto the data stored in the larger memories.
141. The larger memory placed between the primary cache and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
View Answer
Answer: b
Explanation: This is basically used to provide effective memory mapping.
142. The next level of memory hierarchy after the L2 cache is _______
a) Secondary storage
b) TLB
c) Main memory
d) Register
View Answer
Answer: d
143. The last on the hierarchy scale of memory devices is ______

a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
View Answer
Answer: b
Explanation: The secondary memory is the slowest memory device.
144. In the memory hierarchy, as the speed of operation increases the memory size also increases.
a) True
b) False
View Answer
Answer: b
Explanation: As the speed of operation increases the cost increases and the size decreases.
145. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory
in the hierarchy.
a) True
b) False
View Answer
Answer: b
Explanation: The flash drives will increase the speed of transfer but still it wont be faster than primary memory.
“Caches”
146. The reason for the implementation of the cache memory is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
View Answer
Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be inefficient.
147. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localisation
c) Memory size
View Answer
Answer: a
Explanation: This means that the cache depends on the location in the memory that is referenced often.
148. The temporal aspect of the locality of reference means

a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
View Answer
Answer: c
149. The spatial aspect of the locality of reference means

a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
View Answer
Answer: d
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely to be
executed in future.
150. The correspondence between the main memory blocks and those in the cache is given by _________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
View Answer
Answer: b
Explanation: The mapping function is used to map the contents of the memory to the cache.
151. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
View Answer
Answer: a
Explanation: As the cache gets full, older contents of the cache are swapped out with newer contents. This
decision is taken by the algorithm.
152. The write-through procedure is used

a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
View Answer
Answer: c
Explanation: When write operation is issued then the corresponding operation is performed.
153. The bit used to signify that the cache location is updated is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
View Answer
Answer: a
Explanation: When the cache location is updated in order to signal to the processor this bit is used.
154. The copy-back protocol is used

a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
View Answer
Answer: b
Explanation: This is another way of performing the write operation,wherein the cache is updated first and then
the memory.
155. The approach where the memory contents are transfered directly to the processor from the memory is called
______
a) Read-later
b) Read-through
c) Early-start
View Answer
Answer: c
“Cache Miss and Hit”
156. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
View Answer
Answer: a
Explanation: ABR stands for Address Buffer Register.
157. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
View Answer
Answer: a
Explanation: In modular approach to memory structuring only one module can be accessed at a time.
158. In memory interleaving, the lower order bits of the address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
View Answer
Answer: b
Explanation: To implement parallelism in data access we use interleaving.
159. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
View Answer
Answer: a
Explanation: The hit rate is a important factor in performance measurement.
160. The number failed attempts to access memory, stated in the form of fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
View Answer
Answer: b
Explanation: The miss rate is key factor in deciding the type of replacement algorithm.
161. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one,when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
View Answer
Answer: b
Explanation: Miss usually occurs when the memory block requiered is not present in the cache.
162. In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and
others remain same, in case of ______
a) Hit
b) Miss
c) Delay
View Answer
Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.
163. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
View Answer
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
164. The extra time needed to bring the data into memory in case of a miss is called as _____
a) Delay
b) Propagation time
c) Miss penalty
View Answer
Answer: c
165. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels
of hierarchy.
a) True
b) False
View Answer
Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss penalty.
“Hazards of Processor Architecture”
166. Any condition that causes a processor to stall is called as _____
a) Hazard
b) Page fault
c) System error
View Answer
Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.
167. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
View Answer
Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.
168. The contention for the usage of a hardware device is called as ______
a) Structural hazard
b) Stalk
c) Deadlock
View Answer
Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a deadlock state.
169. The situation where in the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.
170. The stalling of the processor due to the unavailability of the instructions is called as ____
a) Control hazard
b) structural hazard
c) Input hazard
View Answer
Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a cache miss.
171. The time lost due to branch instruction is often referred to as _____
a) Latency
b) Delay
c) Branch penalty
View Answer
Answer: c
Explanation: This time also retards the performance speed of the processor.
172. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
View Answer
Answer: a
Explanation: The periods of time when the unit is idle is called as Bubble.
173. _____ method is used in centralized systems to perform out of order execution.
a) Scorecard
b) Score boarding
c) Optimizing
d) Redundancy
View Answer
Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions are released
only when the scoreboard determines that there are no conflicts with previously issued and incomplete
instructions.
174. The algorithm followed in most of the systems to perform out of order execution is ______
a) Tomasulo algorithm
b) Score carding
c) Reader-writer algorithm
View Answer
Answer: a
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from
IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute
non-sequentially (out-of-order execution).
175. The problem where process concurrency becomes an issue is called as ______
a) Philosophers problem
b) Bakery problem
c) Bankers problem
d) Reader-writer problem
View Answer
Answer: d
“Address Translation – 1”
176. For converting virtual address into physical address, the programs are divided into _____
a) Pages
b) Frames
c) Segments
d) Blocks
View Answer
Answer: a
Explanation: On the physical memory side the memory is divided into pages.
177. The memory allocated to each page are contiguous.

a) True
b) False
View Answer
Answer: a
Explanation: Each page might be allocated memory deferentially but memory for one page will be continuous.
178. The pages size shouldn’t be too small, as this would lead to
a) Transfer errors
b) Increase in operation time
c) Increase in access time
d) Decrease in performance
View Answer
Answer: c
Explanation: The access time of the magnetic disk is much longer than the access time of the memory.
179. The cache bridges the speed gap between ______ and _____
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
View Answer
Answer: c
Explanation: The Cache is a hardware implementation to reduce the access time for processor operations.
180. The virtual memory bridges the size and speed gap between ______ and _____
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
View Answer
Answer: b
Explanation: The virtual memory basically works as an extension of the RAM.
181. The higher order bits of the virtual address generated by the processor forms the _______
a) Table number
b) Frame number
c) List number
d) Page number
View Answer
Answer: d
Explanation: The higher order bits indicate the page number which points to one particular entry in the page
table.
182. The page length shouldn’t be too long because

a) It reduces the program efficiency
b) It increases the access time
c) It leads to wastage of memory
View Answer
Answer: c
Explanation: If the size is more than the required size then the extra space gets wasted.
183. The lower order bits of the virtual address forms the _____
a) Page number
b) Frame number
c) Block number
d) Offset
View Answer
Answer: d
Explanation: This gives the offset within the page table.
184. The area in the main memory that can hold one page is called as ______
a) Page entry
b) Page frame
c) Frame
d) Block
View Answer
Answer: b
185. The starting address of the page table is stored in ______

a) TLB
b) R0
c) Page table base register
View Answer
Answer: c
Explanation: The register is used to hold the address which is used to access the table.
“Intel IA-32 Pentium Architecture-1”
186. The address space of the IA-32 is ____
a) 216
b) 232
c) 264
d) 28
View Answer
Answer: b
Explanation: The number of addressable locations in the memory is called as address space.
187. The addressing method used in IA-32 is ______

a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little and Big Endian
View Answer
Answer: a
Explanation: The method of addressing the data in the system.
188. The floating point numbers are stored in general purpose register in IA-32.
a) True
b) False
View Answer
Answer: b
Explanation: The floating registers are not stored in general purpose registers as they have a real part and a
decimal part.
189. The The Floating point registers of IA-32 can operate on operands up to _____
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
View Answer
Answer: d
Explanation: The size of the floating numbers that can be stored in the floating register.
190. The size of the floating registers can be extended upto _____
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
View Answer
Answer: c
191. The IA-32 architecture associates different parts of memory called ____ with different usages.
a) Frames
b) Pages
c) Tables
d) Segments
View Answer
Answer: d
Explanation: The memory is divided into parts called as segments.
192. The PC is incorporated with the help of general purpose registers.

a) True
b) False
View Answer
Answer: b
Explanation: Registers are not used to incorporate PC as in other architectures , but a separate space is allocated
to it.
193. IOPL stands for ________

a) Input/Output Privilege level
b) Input Output Process Link
c) Internal Output Process Link
d) Internal Offset Privilege Level
View Answer
Answer: a
Explanation: This indicates the security between the transfers between the I/O devices and memory.
194. In IA-32 architecture along with the general flags, the other conditional flags provided are _____
a) IOPL
b) IF
c) TF
View Answer
Answer: d
Explanation: These flags are basically used check the system for exceptions.
195. The register used to serve as PC is called as _______

a) Indirection register
b) Instruction pointer
c) R-32
View Answer
Answer: b
Explanation: The PC is used to store the next instruction that is going to be executed.
196. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction
prefix bit .
a) True
b) False
View Answer
Answer: a
Explanation: This switching enables a wide range of operations to be performed.
197. The Bit extension of the register is denoted with the help of ____ symbol.
a) $
b) `
c) E
d) ~
View Answer
Answer: c
Explanation: This is used to extend the size of the register.
198. The instruction, ADD R1, R2, R3 is decoded as _______

a) R1<-[R1]+[R2]+[R3].
b) R3<-[R1]+[R2].
c) R3<-[R1]+[R2]+[R3].
d) R1<-[R2]+[R3].
View Answer
Answer: d
199. The instruction JG loop , does

a) jumps to the memory location loop if the result of the most recent arithmetic op is even
b) jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
c) jumps to the memory location loop if the test condition is satisfied with the value of loop
d) none of the mentioned
View Answer
Answer: b
Explanation: This instruction is used to cause a branch based the outcome of the arithmetic operation.
200. The LEA mnemonic is used to __________

a) Load the effective address of an instruction
b) Load the values of operands onto a accumulator
c) declare the values as global constants
d) Store the outcome of the operation at a memory location
View Answer
Answer: a
Explanation: The effective address is the address of the memory location required for the execution of the
instruction.

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“ JAWABAN KISI2 ARSKOM “

1. The ______ format is usually used to store data.

2. The 8-bit encoding format used to store data in a computer is ______

3. A source program is usually in _______

6. The ALU makes use of _______ to store the intermediate results.

7. The control unit controls other units by generating ____

8. ______ are numbers and encoded characters, generally used as operands.

10. ______ bus structure is usually used to connect I/O devices.

16. The decoded instruction is stored in ______

17. The instruction -> Add LOCA, R0 does _______

18. Which registers can interact with the secondary storage?

19. During the execution of a program which gets initialized first ?

22. The internal Components of the processor are connected by _______

25. _______ is used to store data in registers.

28. To extend the connectivity of the processor bus we use ________

35. The ISA standard Buses are used to connect ___________

48. An 24 bit address generates an address space of ______ locations.

50. The type of memory assignment used in Intel processors is _____

69. The advantage of I/O mapped devices to memory mapped is

70. The system is notified of a read or write operation by

74. The method which offers higher speeds of I/O transfers is

“Standard I/O Interfaces”

77. ________ is an extension of the processor BUS.

78. ISA stands for

79. ANSI stands for

80. The video devices are connected to ______ BUS.

81. SCSI stands for ___________

82. ISO stands for __________

83. The system developed by IBM with ISA architecture is ______

85. IDE stands for _________

89. The output of the encoder circuit is/are ______

92. The Status flag circuit is implemented using _____

94. DDR stands for __________

99. The double buffer is used for

100. ______ to increase the flexibility of the serial ports.

102. The key feature of UART is

103. The data transfer in UART is done in ______

104. The standard used in serial ports to facilitate communication is _____

105. In serial port interface, the INTR line is connected to _____

108. MFC is used to _________

109. __________ is the bootleneck, when it comes computer performance.

113. The cells in each column are connected to ______

114. The word line is driven by the _____

115. A 16 X 8 organisation of memory cells, can store upto _____

118. The number of external connections required in 16 X 8 memory organisation is _____

122. PROM stands for __________

125. The ROM chips are mainly used to store _______

127. The disadvantage of the EPROM chip is _______

129. The disadvantage of the EEPROM is/are ________

132. The flash memories find application in ______

137. The drawback of building a large memory with DRAM is ______________

139. The fastest data access is provided using _______

143. The last on the hierarchy scale of memory devices is ______

148. The temporal aspect of the locality of reference means

149. The spatial aspect of the locality of reference means

152. The write-through procedure is used

154. The copy-back protocol is used

177. The memory allocated to each page are contiguous.

182. The page length shouldn’t be too long because

185. The starting address of the page table is stored in ______

187. The addressing method used in IA-32 is ______

192. The PC is incorporated with the help of general purpose registers.

193. IOPL stands for ________