Lab to investigate the Cache Technology

Objective
After completing the lab exercises the students should
Analyse Directly Mapped cache organization using different cache size and block size
Explain what cache hit and miss rates are
Understand the drawback of Directly Mapped cache type in comparison with set associative
map;ing
Investigate 2-way Set-Associative cache mapping
Investigate 4-way Set-Associative cache mapping
Explain the effect of cache size and mapping scheme on cache performance

Note: The exercised given below is simulated using Data Cache simulator, The data cahe
simulator can be accessed in the CPU-OS simulator by selecting the catche-pipeline tab.

Exercise 1 – To investigate the organization of Directly Mapped cache .

Write a new program in the CPU simulator and name it as call it Cache understanding1 and enter
the following code:
MOV #0, R02
STB R02, @R02
CMP #63, R02
JEQ 28
INR R02
JMP 6
HLT
Question: Can you think of another instruction in place of INR R02 ?
It can be ADD #01, R02. Then what change should be made in the JEQ 28 instruction? Why ? Explain.

The above code writes numbers 0 to 63 in memory locations 0 to 63. Run it and observe the
contents of the data in memory. To see the memory click on the SHOW PROGRAM DATA
MEMORY… button.

Click on the SHOW CACHE… button to display the data cache window. “ Stay on top “ check box is
checked to keep the cache always open. After flushing the cache by clicking on the FLUSH button ,
the cache is configured to the below setting.

Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = Write-Back

Now insert the following code below the instruction JMP 6 in the above code:
LDB 4, R03
LDB 5, R03
LDB 6, R03
LDB 7, R04
Execute the LDB instructions one by one by double clicking each one of them and then prepare the
table as given below after observing and reading the cache table. Make sure that you double click
only one instruction at a time. This can be ascertained by looking at the content of R03
Table:1
Address Data Hits Miss hits

Do note the following data displayed in the Cache Stats frame:

Table:2
miss % miss
hit % hit

Give explanation for your findings in the table.

Why is hit rate increasing as the instructions increase? Expain

Insert the instruction LDB 4, R03 after the last LDB instruction above and execute it by double-
clicking on it:
Besides making the Table:1 and Table:2 entry Prepare the following table:3 after executing the
instruction for the new entry.
Table:3
Address Data Block

Explain your observations.

Explain the reason for getting a different block?
We have run only a single instruction but the cache contains additional three information. Explain?

Exercise 2 – Comparison of different cache mapping, Directly Mapped cache, set associative and
fully associative
First flush the contents of the cache by clicking on the FLUSH button. Then enter the following
instructions after the last LDB instruction in the above program:
LDB 0, R00
LDB 4, R00
LDB 17, R00
LDB 20, R00

A. Next execute only the four instructions in the above program:

Execute the above instruction two times and make entry in the table:4
Table:4
Address Data Hits Miss hits

Table:5
miss % miss
hit % hit

Now select the option

Block Size = 4
Cache Type = Set Associative
Cache Size = 16
Set Blocks = 2-way
Write Policy = Write-Back

And then Repeat A

Table:5
Address Data Hits Miss hits

Table:6
miss % miss
hit % hit

Now looking at tables deduced explain the difference in the miss rate for the two cache
configuration and mapping scheme.
Exercise 3 - Investigating Set-Associatively Mapped cache organization

Configure the cache with the following settings:

Block Size = 4
Cache Type = Set Associative
Cache Size = 16
Set Blocks = 2-way
Write Policy = Write

B. Insert the following new LDB instructions and execute them one after another in the order
listed below
LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00

Write down your observations below

Table:6
Address Set Block
0000
0004
0008
0012

Next re-configure the cache so that the Set Blocks is set to 4-way.
Repeat step B

Clear the cache by clicking on the FLUSH button. Next execute only the following two LDB
instructions in the above program:
LDB 0, R00
LDB 16, R00

Address Data Hits

Explain all your findings that you observe in the table.

Exercise 4 – To investigate the effect of cache size and type on cache performance.
Enter the following program, compile it and load it in CPU memory:
program CacheTest
var a array(50) byte
i = 49
for n = 0 to 49
p = a(n) + a(i)
i=i-1
next
end

Select the correct cache parameters and fill in the tables below against each of the cache
sizes shown in the tables. Make sure the Write Policy is set to Write-Back.

Direct mapping (for cache sizes 16 to 256)

16 32 64 128 256

2-way set-associative mapping (for cache sizes 16 to 256)

16 32 64 128 256

4-way set-associative mapping (for cache sizes 16 to 256

16 32 64 128 256

8-way set-associative mapping (for cache sizes 32 to 128)

16 32 64 128

Briefly comment on the results (Tip: Switch from bar chart to line graph in the displayed charts and
compare the steepness of the slopes of the graphs or compare the individual values of the bars in
bar charts):