590 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. 7, NO. 5.
MAY 1988
A Universal Test Set for CMOS Circuits
Abstract-This paper addresses the problem of finding a universal
test set for CMOS circuits, which can be derived from the functional
description alone. It is shown that for a restricted class of CMOS cir-
cuits, the gate-level universal test set (UTS,) consisting of maximal false
vectors and minimal true vectors can sensitize every detectable stuck-
open fault in the circuit. A universal initialization set (UIS) is defined
which can also be derived from just the functional description, and
which contains initialization vectors for each of the test vectors. This
set consists of maximal true vectors and minimal false vectors. It is
shown that a test set based on UTS, and UIS can be guaranteed to
detect every detectable stuck-open fault in both redundant and irre-
dundant CMOS implementations of the function, even in the presence
of arbitrary delays and timing-skews. The size of the test set is also
investigated.
I. INTRODUCTION
D UE TO THE increasing popularity of CMOS tech-
nology for implementing Very Large Scale Inte-
grated (VLSI) circuits, the area of fault detection in
CMOS circuits is growing in importance. Various meth-
ods for generating test sets for CMOS circuits and obtain-
ing testable CMOS realizations have been presented by
researchers [ 11-[ 111. The test generation methods assume
that the CMOS circuit is known a priori. This often re-
sults in a near minimal test set, but the test generation
process becomes very complex and computationally de-
manding-more so for CMOS circuits because of the need
for two-pattern tests. Furthermore, it has been shown that
a two-pattern test, which consists of an initialization vec-
tor followed by a test vector, can be invalidated in the
presence of varying delays in the circuit [8]-[ 111. Obtain-
ing a test set, if one exists, which cannot be invalidated,
usually involves an increase in the test set size and the
complexity of the test generation process. Besides, the
test set is tailored to a very specific circuit implementation
and even the slightest change in the circuit may render the
test set useless.
In this paper we consider the general problem of deriv-
ing a test set from the functional description only. Our
fault model includes all detectable single stuck-open
faults. Akers [12] and Reddy [13] have already given so-
lutions to this problem with respect to gate-level circuits.
They showed that the universal test set, comprising of the
maximal false vectors and the minimal true vectors, tests
for all detectable stuck-at faults in a particular class of
Manuscript received June I O , 1987; revised October 13, 1987. This work
was supported in part by Siemens Corporation under Grant 170-405 1. The
review of this paper was arranged by Associate Editor E. J. McCluskey.
G . Gupta is with SILC Technologies, Waltham, MA 02254.
N . K . Jha is with the Department of Electrical Engineering, Princeton
University, Princeton NJ 08544.
IEEE Log Number 8719392.
0278-0070/88/0500-0590$01.OO
gate-level circuits. In such a circuit the inverters can be
present 'only at the primary inputs, the rest of the circuit
is assumed to be made up of AND and OR gates only. How-
ever, these results are also valid for other circuits which
can be reduced to the above class of circuits using De
Morgan's theorem. Consider a circuit in which all the
paths starting from the primary inputs and meeting at the
input of any gate have the same inversion parity (either
an odd number of inversions or an even number). A gate-
level (CMOS) circuit satisfying this property will be re-
ferred to as a restricted gate (CMOS) circuit. It is easy
to see that many restricted gate or CMOS circuit imple-
mentations exist for every function. Using arguments from
[13] one can show that the universal test set is valid for
any restricted gate circuit. Henceforth, the gate-level uni-
versal test set will be denoted as UTS,. The universal test
set derived later in this paper for any restricted CMOS
circuit implementation will be denoted as UTS,. We will
assume that the restricted CMOS circuits are formed by
interconnecting fully complementary CMOS gates.
We first show that for restricted CMOS circuits the
UTS,, as derived in [12] and [13], provides all the test
vectors required to test for each detectable single stuck-
open fault. We then consider the problem of finding ini-
tialization vectors for each of these test vectors. We show
that a universal initialization set (UIS) can be obtained
which guarantees the initialization of every initializable
stuck-open fault in the circuit even in the presence of re-
dundancies. We then show that the UTS,, comprising of
test vectors from the UTS, and the initialization vectors
from the UIS, is robust (i.e., it does not get invalidated
even in the presence of delays). In this paper when we
refer to robust test sets, we will assume that they are based
on two-pattern tests, although it is possible to base them
on n-pattern ( n > 2 ) tests.
The paper is organized as follows. In Section I1 we show
the usefulness of the UTS, when it is applied to any re-
stricted CMOS circuit implementation of the function. In
Section I11 we establish certain properties of the restricted
CMOS circuits. In Section IV we show how to derive the
UTS, using test vectors from the UTS, and initiaIization
vectors from the UIS. We prove that if there exists a ro-
bust test set for the circuit under test then UTS, is one such
test set. In Section V we evaluate the size of the test set.
We conclude in Section VI.
11. TEST VECTORS
In this section we show how the UTS, can be used to
provide test vectors for restricted CMOS circuit imple-
O 1988 IEEE
1-
GUPTA AND JHA: TEST SET FOR CMOS CIRCUITS
mentations, even in the presence of redundancies in the
circuit.
We will first briefly review the concept of the universal
test set as applied to the gate-level circuits.
Definition 1: A true (false) test vector is one for which
the circuit output in the fault-free case is logic 1 (0).
~ two vectors then 6* covers
Dejinition 2: If 61 and 1 3 are
6, if A 2 has 1’s in every bit-position in which has 1’s.
We denote this by h2 1 6,.
For example, 110 I 100, but 110 2 001.
+
Consider a functionf = ab bc. The dependent input
literals are a , b , b and c (the formal rules for finding the
set of dependent input literals are given in [ 121 and [ 131).
We form an expanded truth table as shown in Table I.
A row from this expanded truth table represents an ex-
panded vector.
Dejinition 3 [13]: A minimal true vector (minimal ex-
panded true vector) of a logic function is the input vector
(expanded input vector) that does not cover any other true
vector except itself. A maximal false vector (maximal ex-
panded false vector) is the input vector (expanded input
vector) that is not covered by any other false vector except
itself.
The minimal true vectors and maximal false vectors are
shown by asterisks in Table I. The set of minimal true
vectors and maximal false vectors is the universal test set
UTS,. It has been shown in [12] and [13] that the UTS,
can detect any detectable stuck-at fault in any restricted
gate circuit implementation of the function.
Henceforth, the word “expanded” may not always be
used when it is implied by the context.
A method to get the gate-level model for a CMOS cir-
cuit was presented in [2]. This can be used to arrive at the
following lemma.
Lemma 1: The gate-level model of a restricted CMOS
circuit is a restricted gate circuit.
Proof: The proof follows from the fact that the
equivalent gate-level sub-circuit of any CMOS gate in a
CMOS circuit is a feedback-free interconnection of AND/
OR gates with an inversion at each primary input [2]. If
no CMOS gate of the CMOS circuit has paths of different
inversion parities meeting at its input then, obviously, the
equivalent gate-level circuit cannot have such a gate
either. Hence, the gate-level model is a restricted gate
circuit. 0 output can be changed from odd to even by this method.
It follows from Lemma 1 and the previously mentioned
results from [I21 and [I31 that the UTS, provides test vec-
tors for every detectable stuck-at fault in the gate-level
model of any restricted CMOS circuit. Reddy et al. have
already shown [2] that any test set designed for detecting
single stuck-at faults in the gate-level model, also tests
for single stuck-open faults in the CMOS circuit, pro-
vided proper initialization vectors are used for every test
vector. Combining the above results, we can say that the
UTS, provides test vectors for all detectable single stuck-
open faults in any restricted CMOS circuit implementa-
tion of the given function.
I I-
59 I
TABLE 1
TRUTHTABLEFOR^ = uh
EXPANDED + hc
I
abbe f
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
111. PROPERTIES OF RESTRICTED CMOS CIRCUITS
In this section we will establish certain properties of
restricted CMOS circuits.
Definition 4: In a restricted CMOS circuit a CMOS gate
g is said to be an odd-numbered (even-numbered) gate if
an even (odd) number of CMOS gates are encountered
while traversing any path from the primary inputs to the
inputs of gate g .
In this definition the inverters present inside the circuit
are counted, but not the ones present at the primary in-
puts.
Consider the three gate-level implementations o f f =
+
ab bc in Fig. 1. The inversion parities of the paths to
the inputs of any gate in these implementations are the
same. Hence, these are restricted gate circuit implemen-
tations. Note that the inversions at the primary inputs are
ignored while determining the inversion parity. The
CMOS implementations of the above function which cor-
respond to these three gate-level circuits are, obviously,
restricted CMOS circuits.
Since every CMOS gate introduces an inversion, it
means that all paths incident at any CMOS gate in a re-
stricted CMOS circuit have either an even number or an
odd number of CMOS gates. In the discussion that fol-
lows, we shall assume that the number of CMOS gates in
each path from the primary inputs to the circuit output is
even. This does not result in any loss of generality, since
by applying De Morgan’s theorem we can always transfer
an inversion from the circuit output to the primary inputs.
The test set of the original circuit remains valid even for
the modified circuit obtained after the inversion transfer.
But the number of CMOS gates in each path to the circuit
The following lemmas follow from these observations.
Lemma 2: A true (false) test vector can only sensitize
stuck-open faults in the nMOS (PMOS) networks of odd-
numbered gates and the PMOS (nMOS) networks of even-
numbered gates on the sensitized path in a restricted
CMOS circuit.
Proof: A true (false) test vector activates the PMOS
(nMOS) network of the output CMOS gate since the out-
put is logic 1 (0). We have assumed that the output CMOS
gate is even-numbered. By retracing the path from the cir-
cuit output to the primary inputs and from the definition
of restricted CMOS circuits, it is clear that a true (false)
1
 592
I L
' fresultant test set, however, can be invalidated in the pres-
(C)
Fig. 1 . Restricted gate circuit implementations off
vector causes logic 1 (0) to appear at the outputs of the
even-numbered CMOS gates, and logic 0 (1) at the out-
puts of odd-numbered CMOS gates on the sensitized path.
Hence, the lemma follows.
Lemma 3: If 61 and 6, are two expanded vectors of a
functionf, and 6, I6,, then in the transition 62 -, 6, (6,
--f 6,) the output of an even-numbered gate in any re-
stricted CMOS circuit implementation can only change
from 0 to 1 ( 1 to 0), while the output of an odd-numbered
gate can only change from 1 to 0 ( 0 to 1 ).
Proof: We know that in a restricted CMOS circuit
1 the output of an even-numbered (odd-numbered) gate can
only be reached through an even (odd) number of inver-
sions on any path from the primary inputs. Hence, it fol-
lows that since input literals can only change from 0 to 1
in the transition 6, -+6,, the outputs of the even-num-
bered gates can also only change from 0 to 1, and the
outputs of the odd-numbered gates can only change from
1 to 0. Analogous results can be obtained for the transi-
tion + 6,. In this case, the output of each gate can only
vary in the complementary manner.
Since the circuit output is taken from an even-numbered
CMOS gate, from Lemma 3, the circuit is monotonic in
the expanded vectors. In other words, if 61 and 6* are two
expanded vectors of a functionfand 6, I t h e n f ( 6 , )
If ( 6 , ) , else if d1 I6, t h e n f ( 6 , ) If(6,).
IV. DERIVING UNIVERSAL TESTSETSFOR CMOS
CIRCUITS
In an irredundant restricted CMOS circuit, for every
single stuck-open fault sensitized by a vector 6, E UTS,,
there exsits another vector 6, E UTS,, which sensitizes the
stuck-open fault in the corresponding transistor (the tran-
sistor fed by the same input) in the complementary net-
work of that gate. The UTS,, therefore, provides all the
test and initialization vectors required for testing a re-
stricted CMOS circuit for single stuck-open faults. It is
sufficient to obtain two-pattern tests by preceding every
minimal true vector with every maximal false vector and,
vice versa, in order to derive a test set which detects all
IEEE 1'RANSACTIONS ON COMPUTER-AIDED DESIGN. VOL 7. NO. 5 . MAY 1988
single stuck-open faults in any irredundant restricted
CMOS circuit implementation of the given function. The
ence of arbitrary delays. Besides, the test set is not valid
for all redundant implementations.
In this section we look at the problem of deriving a test
set which can detect all detectable single stuck-open faults
in any restricted CMOS circuit implementation (redun-
dant or irredundant) of a given function. Furthermore, we
show that this test set does not get invalidated in the pres-
ence of delays.
A . Universal Initialization Set
In a redundant circuit, not every stuck-open fault can
be sensitized to the circuit output. We do have the guar-
= ab + &c. antee that the vectors in the UTS, will sensitize every sen-
sitizable fault to the circuit output. But there is no guar-
antee that vectors from UTS, can always initialize the
circuit, when it is possible to do so, to detect the sensi-
tized fault.
0 For example, consider the function f = ab + ac. A
redundant CMOS realization of this function is given in
Fig. 2. The UTS, for this function is given in Table 11.
Let a transistor in the PMOS network corresponding to a
transistor y in the nMOS network be referred to as y r .
Now a stuck-open fault in transistor 5' is sensitized by
p 2 , but neither a , nor c y 2 establishes a conduction path
through transistor 5. If we confine ourselves to the UTS,
for initialization vectors, this fault will be left undetected.
We will give a method for deriving a set of vectors, not
necessarily in the UTS,, which will guarantee the initial-
ization of the circuit for every detectable stuck-open fault.
Before doing so we define a few terms.
Definition 5: An expanded true vector K; is a maximal
expanded true vector if there is no other expanded true
vector K ; such that K , I K ; . Analogously, an expanded
false vector tiis a minimal expanded false vector if there
0 is no other expanded false vector 4, such that t j 1 4,.
The set of maximal expanded true vectors and minimal
expanded false vectors is said to be the universal initial-
ization set (UIS). We will denote the sub-set of true vec-
tors by ZI and the sub-set of false vectors by Io.
For example, for the function implemented in the cir-
cuit in Fig. 2 the UIS is given in Table 111.
The initialization of the circuit by the UIS is considered
in the following theorem.
Reorem 1: The set of maximal expanded true vectors
I , contains initialization vectors, if they exist, for every
false test vector in UTS,, while the set of minimal ex-
panded false vectors Io contains initialization vectors, if
they exist, for every true test vector in UTS, for any re-
stricted CMOS circuit implementation of the given func-
tion.
Proof: The proof is given for a true test vector only.
The proof for a false test vector follows in an analogous
fashion. Suppose Io does not have initialization vectors
for every true test vector, i.e., there exists a vector U;
 ~
GUPTA AND J H A : TEST SET FOR CMOS CIRCUITS
,Vdj
Fig. 2. A redundant restricted CMOS circuit implementation off
ac.
TABLE I1
1 0 1
1 0 0
0 1 1 02
which can serve as an initialization vector for some stuck-
open fault sensitized by a true test vector, but no vector
belonging to Io can do so. We know from Lemma 2 that
a true test vector tests for stuck-open faults in PMOS net-
works of even-numbered CMOS gates and nMOS net-
works of odd-numbered CMOS gates on the sensitized
path. To initialize the output of a CMOS gate for detect-
ing a fault in one of its networks, we need to establish a
conduction path through the complementary network, i.e.,
the nMOS networks of even-numbered gates and the
PMOS networks of odd-numbered gates on the sensitized
path. Since uiis not in Io there must be a vector tiE Io
such that t i 5 U ; . Thus, in the transition ui+ t ithe only
changes in the different bits can be from 1 to 0. From
Lemma 3 , the only resultant change can be from 1 to 0 at
the outputs of even-numbered gates and from 0 to 1 at the
outputs of odd-numbered gates. Thus the output of the
faulty CMOS gate initialized by uiwould also be initial-
ized by ti.This contradicts our initial assumption and,
hence, the theorem follows. 0 6;) cannot establish a spurious conduction path. Hence,
-_
-1- - --
593
TABLE 111
UIS FOR f = ab + ac
0 0 0
For the circuit in Fig. 2 the stuck-open fault in 5‘ can
be sensitized by 0,from the UTS, in Table I1 and initial-
ized by K , from the UIS in Table 111.
B. Universal Test Set
The universal test set UTS, is derived by obtaining two-
pattern tests by preceding every true (false) test vector
from the UTS, by every false (true) initialization vector
from the UIS. For the function f = ab + ac considered
earlier, the UTS, is given in Table IV.
C. Robustness of UTS,
We are now in a position to find out if our universal test
set remains valid in the presence of arbitrary delays.
Dejinition 6: Let 6, and 6, be two expanded vectors in
the expanded truth table of a function f. Then (6, 6,) +
is the vector obtained by a bitwise OR of the vectors 6,
= ab + and 6,.
For example, (011 +
101) is the vector 111.
Dejinition 7: Let 6, and 8, be two expanded vectors in
the expanded truth table of a function f. Then ( 6, . 6,) is
the vector obtained by a bitwise AND of the vectors and
62.
For example, (01 1 * 101) is the vector 001.
Lemmas 4 and 5 serve to establish a basis for ensuring
the robustness of a two-pattern test by comparing a par-
ticular two-pattern test with another two-pattern test which
is known to be robust.
Lemma 4: For a restricted CMOS circuit let ?i2 be an
expanded true test vector and 6, the corresponding ini-
tialization vector such that ( 6 , , 6,) is a robust two-pattern
test for detecting some stuck-open fault 4,. If (a;, 6;) is
another two-pattern test for detecting 6,such that (6; +
6;) I(6, + 6,), then (61, 6;) is also robust.
Pro08 From Lemma 2, to invalidate a two-pattern
test comprising of a true test vector, a spurious conduc-
tion path must get activated through the nMOS network
of an odd-numbered gate or the PMOS network of an even-
numbered gate on the sensitized path. This can happen if
there exists a vector &, (6, * 6,) Ia3 I( 6 , +
S,), that
establishes such a spurious conduction path. Since ( h l ,
6,) is a robust two-pattern test, clearly, there does not
exist such a vector 6,. In particular, the vector ( 6i +
6,)
does not establish such a spurious conduction path. Since
+
(6; 6;) I( 6 , +
6,), we know from Lemma 3 that the
+
only additional conduction paths that (6; 6;) can estab-
lish apart from the ones established by (6, +
6,) are
through the nMOS networks of even-numbered gates and
the PMOS networks of odd-numbered gates. Thus (6; +
1 1-
 p
594 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. 7, NO. 5. MAY 1988
TABLE IV
UTS<FOR f = ab + ac
f
01 01 00
0 0 0
again from Lemma 3 , there also does not exist any vector
+
6; 5 (6; 6;) that establishes a spurious conduction
path. (Si, A;), therefore, is a robust two-pattern test for
detecting 0 faults. From Lemma 2, 6, tests for stuck-open faults in
Lemma 5: For a restricted CMOS circuit let 6, be an
expanded false test vector and the corresponding ini-
tialization vector such that (A1, 6,) is a robust two-pattern
test for detecting a stuck-open fault d I . If (ai, 6;) is an-
other two-pattern test for detecting such that (6;* 6;)
-
2 (6, A 2 ) , then (6[,6;) is also robust.
Proot Analogous to the proof of Lemma 4. 0 UTS, and the UIS, there must exist an expanded true vec-
Lemma 6: If R is a restricted CMOS circuit which is
monotonic in the expanded vectors in the fault-free case,
then R remains monotonic even in the presence of a stuck-
open fault.
Proot Let g be the CMOS gate with the stuck-open
fault. We recall that the monotonic property for the re-
stricted CMOS circuits considered in Section I11 follows
directly from the fact that, if 61 and 6, are two expanded
vectors such that L then in the transition + 6,
the output of an even-numbered gate can only change from
1 to 0, while the output of an odd-numbered gate can only
change from 0 to 1. Analogously, in the transition li2 +
6, the output of an even-numbered gate can only change
from 0 to 1 , while the output of an odd-numbered gate
can only change from 1 to 0. We need to only show that
the above property holds even when the stuck-open fault
is present.
Let the faulty gate g be an even-numbered gate. Con-
sider the transition -+ 6*. All inputs to the gate g are
the outputs of odd-numbered gates. Besides, all gates in
the paths from the primary inputs to the inputs of gate g
are fault-free and, hence, from Lemma 3, the only tran-
sition at the inputs of the gate g can be 0 -+ 1. Clearly,
even in the presence of a stuck-open fault the only addi-
tional conduction paths established in g during the tran-
sition 6,-+ 6,are through the nMOS network. Hence, the
only transition at the output of g can be 1 0. Now con-
+ set UT&, comprising of test vectors from the UTS, and
sider the transition 6, ljl. The inputs to gate g can only
-+
change from 1 to 0 since all these inputs are the outputs
of odd-numbered gates. The only additional conduction
paths established as a result of this transition are through
the PMOS network of g. Hence, the only transition at the
output of g can be 0 .+ 1 . The above arguments prove
that a faulty even-numbered gate preserves the property
that ensures monotonicity. The case in which the faulty
gate is odd-numbered can be proved similarly. 0
We can now prove that UTS, is a robust test set.
Theorem 2: If there exists a robust test set for a re-
stricted CMOS circuit implementation of the given func-
tion, then UTS,, comprising of test vectors from the UTS,
and the initialization vectors from the UIS, is one such
robust test set.
Proof: Let V be a set of robust two-pattern tests de-
rived for all single stuck-open faults in the restricted
CMOS circuit under test. We shall prove that f?r every
robust two-pattern test in V , there exists a robpst two-
pattern test in UTS, which tests for the same stdck-open
I
faults.
\
Let 6, be an expanded true test vector and (S,&&a
robust two-pattern test in V for a set of single stuck-open
the nMOS networks of odd-numbered gates and the PMOS
networks of even-numbered gates on the sensitized path.
Since is the initialization vector for A,, it must establish
conduction paths through PMOS networks of odd-num-
bered gates and nMOS networks of the even-numbered
gates on the sensitized path. From the definitions of the
tor a E UTS, and an expanded false vector i E UIS, such
that a 5 and 5 It can be easily shown that a
sensitizes all stuck-open faults sensitized by 6,. In the
transition a -+ 6, the output of an odd-numbered gate can
only change from 1 to 0 and that of an even-numbered
gate from 0 to 1. Thus if a does not test for some stuck-
open fault, i.e., the circuit output is 1 even in the presence
of the fault, then, from Lemma 6, 6, also cannot test for
that fault. Further, since 4 Idl, in the transition 6, E +
the output of an odd-numbered gate can only change from
0 to 1 and that of an even-numbered gate from 1 to 0. As
a result, E initializes the circuit for each of the faults that
6, initializes the circuit for. Since a! I6, and t I61, ( a
+ +
4 ) I (6, 6,). From Lemma 4, (E, a ) is also a
robust two-pattern test for all the stuck-open faults de-
tected by (li1, 6,).
Now assume that ( A 1 , 6,) is a robust two-pattern test in
V in which 6, is an expanded false test vector. There must
exist an expanded false vector 6 E UTS, and an expanded
true vector K E UIS, such that 6 2 6, and K 2 6,.Then,
using Lemma 5 , we can prove in an analogous fashion
that ( K , 6 ) is a robust two-pattern test for all the stuck-
open faults detected by ( 6,). 0
V. SIZE OF THE TEST SET
In this section we compare the size of the universal test
initialization vectors from the UIS, with the size of the
minimal robust test set for some given implementation of
a function. In the discussion ahead we denote the set of
minimal (maximal) true vectors by T, ( I , ) and the set of
maximal (minimal) false vectors by To(I , ) . In accordance
with the definitions of UTS, and UIS, UTS, = TI U To
and UZS = ZI U Io.
GUPTA A N D JHA: TEST SET FOR CMOS CIRCUITS 595

- (Sol * min {IS21. IS31}

The proof is exactly similar to the proof of Case 2.

and To = SQU Ss. Theorem 3 gives the lower bound on Case 4: So f null, SI # null.
the size of th&.,UTS,. For this case we have to prove that 1 UTS, lmin is equal
Theorem 3: The minimal attainable size of the UTS,, to
denoted as I UTS, I, is equal to
2(lIol ( T I (+ (Ill- ITOl) - IS11
-min{lS41JS5Ij - IS01 -in{lS2/?IS3I}
*min{IS417 ISSI} - IS01 * m i n ( l S ? I ?IS313
-21SJ * ISII + 1.
-2ISol IS11 + P ,
Hence, we have to show that apart from the reduction
wherep = 1, if So and SI are non-empty, and 0 otherwise. in 1 UTS, I shown possible in the proofs of Cases 2 and
Proof: There are four cases to be considered. 3 , a further reduction of 2 I So I I SI 1 - 1 is possible.
Case 1: So = SI = null. By preceding every ar E S , ( 6, E So) with every P, E
Hence, we have to prove that So( CY E SI) we can obtain the'following two sequences
o I + IIII
l ~ T ~ c l m i n = 2 ( 1 ~IT11 ITol).
of two-pattern tests:

For this case there is no vector which can be used both

1)
. . . P /-% . P / % , P 1 a 2 ,
P,Ql,
9
7 * - 3 P P 2 , 3 P l a i ,

as a test vector of some two-pattern test and an initial- 2) a1019 aiP1, a1P2,
* * * * * aiP2, * c-wlP/,
. . . CYiPI.
9 7 9

ization vector of the next two-pattern test. Since there are

( I Io I I TI I +
9

1 I , I I To I ) initialization-test pairs, the The second sequence may be rearranged as

proof follows directly.
Case 2: So = null, SI # null.
Therefore, we have to prove that
(YIP29 -- * 9 CYlPI, QlP1, a 2 P 2 ,
*
9 %PI, a2P1,

* * aiP2, 3 crib/,u j P 1 .
l u T ~ c I m i n = 2 ( 1 ~* oIT11
I + 14 P o l )
*
This rearranged sequence can be merged with the first
sequence to arrive at the following sequence of vectors:
Pial * P / ~ I P ~
* *Q ~/ a 2
* P * * P l a i * P/aiPI.
First assume that I S4 I 5 1 S5 1 . Consider the follow-
ing sequence of vectors: This sequence of vectors can be looked on as either Se-
quence 1 with PI added at the end or as the rearranged
F l a l Y l , 41CY2YI9 * * * 9 t l W 1 , t 2 a l Y 2 , t2%Y2, * - 7 Sequence 2 with PI added at the beginning. Hence, it con-
tains all the two-pattern tests contained in Sequence 1 or
5 2 a i ~ 2 , 7 tmalYm, Erna2~rn, * 9 tmaiYm.
Sequence 2. Since the length of each of Sequence 1 and
This sequence uses a vector aqE SI as both a test vector 2 is 2 1 So I I SI 1, it follows that the length of the total test
and an initialization vector as many times as possible. set can be further reduced by ( 2 1 So I I SI 1 - 1). We
There are 1 SI 1 * I S4 I cases in which this can be done. cannot do any better since every vector in So or SI that
Also, the number of cases in which this is possible can be could be used as both a test vector and an initialization
no more. Hence, from the above arguments, vector has been used as such. 0
l U T S c l m i n = 2 ( l I 0 I . IT11 +(Ill * IT00
B. Comparisons of Test Set Size
I S4 I .
- I SI I *
The question naturally arises as to how the 1 UTS, Imi n
Similarly, if we assumed that 1 S4 1 > I Ss 1, then it can compares with the size of the minimal test set for any
be shown that particular CMOS implementation of the given function.

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596 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. 7, NO. S. MAY 1988
In other words, what is the price we pay in terms of the
increased test set size for obtaining a universal test set.
We have found that the increase is less, in general, for a
unate function than for a binate function.
Consider, for example, the implementation of the func-
tion f = ab + ac as shown in Fig. 2. The size of the
minimal test set for this circuit is 6 , while the size of the
minimal robust test set for this circuit is 7. I UTS, lmln for
this function is equal to 8. Even for the simple irredundant
NAND-NAND CMOS implementation of this function the
minimal robust test set has 7 vectors in it.
As the “binateness” of the circuit increases, however,
1 UTS, lmln increases rather sharply. But the size of the
corresponding minimal test set for any particular imple-
mentation of the function also registers a significant in-
crease, more so when the implementation is redundant and
we wish to ensure robustness.
Let us now look at some practical examples.
Example I : Consider the full adder. The sum S and the
carry output C in terms of the inputs a , b and c are as
follows:
S = ab? + Zib? + Zibc + abc
C = ab + ac + bc
Hence, while S is binate in every input, C is unate in
every input. By following the method presented here we
find that 1 UTS, lmln = 33 for S , and 1 UTS, l m l n = 12 for
C. Now assume an irredundant NAND-NAND CMOS im-
plementation for both S and C . One can check that the
size of the minimal robust test set for the circuit imple-
menting S is 24, and for the circuit implementing C is 9.
We see that in both the cases our universal test sets are
less than 40 percent larger. The increase in the size of the
test set is less for the unate function C than for the totally
binate function S .
Example 2: Consider another practical example of the
priority encoder [14]. This device has n input lines and
log, n output lines. When two input lines p l and p , , such
that i > j , request service at the same time, line p l has
priority over line p , . The encoder produces a binary out-
put code indicating which of the input lines requesting
service has the highest priority. Consider an eight-input,
three-output priority encoder. The logic equations for the
outputs zl, z 2 , and 24 are as follows:
z1 = PIP2P4P6 P3P4P6 + PSP6 + P7
2 2 = P2P4PS + P3P4P5 + P6 + P7
24 = P4 + P5 -k P6 + Pl.
The input line po is used with other input lines to find
out if any request is present or not. However, that appli-
cation of po is not shown here. I UTS, lmln for zl, z 2 , and
2 4 is 16, 14, and 9 respectively. The sizes of the corre-
sponding minimal robust test sets for the irredundant
NAND-NAND CMOS implementations of z I , z 2 , and z 4 are
11, 11 and 8 respectively. Hence, the worst-case increase
in the size of the test set is 45 percent.
Example 3: Consider a comparator of two two-bit
numbers X 2 = x I x 2and Y2 = y1y2 [14]. The comparator
has two outputs G 2 and S 2 , such that, G 2 = 1 iff X 2 >
Y2; S2 = 1 iff X 2 < Y2; and G 2 = S 2 = 0 iff X 2 = Y,.
The logic equations for G 2 and S 2 are as follows:
G2 = XIX2L2 + X2YIY2 + XlLl
s2 = X2YlY2 + XIX2Y2 + XlYl.
I UTS, lmln for both G 2 and S 2 is 16, while the size of
the minimal robust test set for the irredundant NAND-NAND
CMOS implementations of both G 2 and S 2 is 11. Thus in
this case also the size of the test set increases by 45 per-
cent.
It can be seen from the method presented in [8] that the
test generation process for generating a robust test set for
any CMOS circuit is extremely time-consuming. Here the
inherent robustness and ease of test generation of our uni-
versal test set gives it a substantial edge. Of course, an-
other advantage of having a universal test set is that a
change in the implementation does not render the test set
useless.
VI. CONCLUSION
In this paper we presented a method for generating uni-
versal test sets for CMOS circuits. We summarize this
method below.
Step I : Find the dependent input literals of the given
function by following procedures in [ 121 and [ 131. Obtain
the expanded truth table.
Step 2: Obtain the set of minimal (maximal) true vec-
tors TI ( ZI) and the set of maximal (minimal) false vectors
To ( l o ) .
Step 3: Obtain two-pattern tests by using every vector
from lo( ZI ) as an initialization vector for each vector from
Tl (To).
Step 4: Obtain a minimal universal test set by using as
many test vectors as initialization vectors as possible, fol-
lowing the method shown in the proof of Theorem 3.
It was shown that the UTS, sensitizes every sensitizable
stuck-open fault in any restricted CMOS circuit imple-
mentation of the function. The UIS, comprising of max-
imal true vectors and minimal false vectors, was defined,
and it was shown that it provides all the initialization vec-
tors needed to initialize the circuit even in the presence of
redundancies. Further, if a robust test set exists for the
given implementation then the universal test set UT&,
comprising of the test vectors from the UTS, and the ini-
tialization vectors from the UIS, is one such test set. The
method given here presents a choice between a smaller,
but computationally demanding circuit-dependent test set
and a larger, but easily obtained and robust universal test
set for CMOS circuits.
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*
Gopal Gupta (S’86) received the B.Tech. degree
in electrical engineering from Indiana Institute of
Technology, Madras, India, in 1985 and M.S. de-
gree in electrical engineering and computer Sci-
ence from University of Michigan, Ann Arbor, in
1987.
At present he is with SILC technologies, Wal-
tham, where he is currently engaged in the design
and development of logic synthesis automation
technology for high performance systems. His re-
search interests include digital system testing,
VLSI system design and design automation.
*
Niraj K. Jha (M’85), for a photograph and biography please see page 116
of the January 1988 issue of this TRANSACTIONS.
1