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SUBMITTED BY
CO-ORDINATOR
MJCET
MUFFAKHAM JAH
COLLEGE OF ENGINEERING AND TECHNOLOGY
ABSTRACT
The aim of this project was to create a four-bit arithmetic logic unit. This
ALU was to take two four bit numbers and perform the following
function. The ALU has 4 full adders and eight 2:1 multiplexers.
INTRODUCTION
This project was done in a structural manner. The implementation of the 4-bit ALU circuit
was done on Tanner Tools version 12.6 . We have laid out this report so that the information
portrayed will be easy to verify and comprehend. We have attempted to show all the
operations of ALU by giving all the possible inputs to the circuit .And the waveforms of both
This should allow the viewer to simply hold a sheet of paper over the waveform output and
DESCRIPTION
An arithmetic and logical operaions unit(ALU) must,obviously be able to add two binary
From the point of view of the logical operations it is essential to be able to And two binary
words (A.B). It is also desirable to Or (A+B) and perhaps also detect Equality, and of course
Substraction by adder is an easy operation provided that the binary numbers A and B are
presented in twos complement form. In this case, to find the difference A-B it is only
necessary to complement B (exchange for 0 and vice versafor all the bits of B), add 1 to the
number thus obtained , then add tis quantity to A using the standard assition process
discussed earlier.The output of the adder will then be required difference in twos
complement form.Note that the complement facility necessary for substraction also serve to
form the logical complement (which is indeed exchanging 0 and 1 and vice-versa).
would be nice if the adder could be made to perform logical operations as readily as it
performs substraction.
In order to examine this possibility, consider the standard adder equation set.
Sum S=H’kCk-1 + HkC’k-1
operation
Next,consider the carry output of each element, first if Ck-1 is held at logical 0.
Thus it may be seen that the suitable switching of the carry line between adder elements will
give the ALU logical functions.A possible arrangement of the adder elements for both the
* Design: azhar
* Cell: alu_4bit
* View: view0
* Exclude .model: no
* Exclude .end: no
* Wrap lines: no
.probe
.option probev
.option probei
.option probeq
MPMOS_1 Vout_inv Vin_inv Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
.ends
* Revision: 107
MN6 Out 3 Gnd 0 NMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p
PD=7.5u
MN1 G Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 4 Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 G Sel Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MP2 2 G Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP6 Out 3 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p
PD=7.5u
.ends
MPMOS_1 Vout A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Vout B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
.ends
MPMOS_1 N_2 A_nor Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MPMOS_2 Vout_nor B_nor N_2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
.ends
.subckt halfadder A_halfadder B_halfadder Carry_halfadder
Sum_halfadder Gnd Vdd
.ends
.ends
.ends
.op
.option prtdel=10ns
.end
FINDINGS
While creating this ALU we spent most of my time on the switch unit. We tried to implement
the switch unit but we faced problems,and then we replaced switch unit with 2:1 mux.
All of the other units were straightforward and no hurdles were faced in the rest of the
project.
CONCLUSIONS
All the possible inputs and corresponding outputs cases have been testes and no errors
We now feel that we have a very good understanding implementation of usage of Tanner