Understanding of digital logic: setup and hold, pipelines, latency and throughput, etc.

- FPGA architecture questions: how different circuits are synthesized, process of timing
closure, differences between FPGA and ASICs, clock and reset schemes
For example, a signal derived in clock domain A is used in a sequential process in clock
domain B. What can potentially happen if you use the signal directly in clock domain B?
What is the proper way to handle the signal before using it in clock domain B?

1. What is speed grade and how do you select FPGA as per requirements
1. Speed Grade is what that determines how max a clock can run in FPGA.
Companies use different values, while -1, -2 indicates the scale. Higher the
grade, higher the cost of FPGA
2. What is the maximum possible speed achievable for a given device say Virtex6
device (some speed grade)
1. The Fmax is determined by Flop-to-Flop timing using shortest route
(CLB) with least clock skew. To put it simple, usually this is calculated
based on logic levels between a source to destination path
3. What is logic level
1. Number of logics levels in your combo circuit. Google for more info
4. How do you code to reduce power in FPGA design
1. Avoid reset for FPGA
2. Clock Gate
3. Use synchronous design
4. Avoid overconstraining
5. Reduce Device temperature (cooling solution)
6. Use clk_en and control enable for all Memory
7. Use LUT for smaller memory. BRAM takes more power
5. What is clock gating and how do you do it in FPGA
1. Xilinx and Altera provides primitive components for this. Check them
6. How do you manage multiple clocks and how do you route them
1. CDC tools can help this like Spyglass, etc. But asynchronous transfers
must be handles carefully in design and later they can be assigned false
path for the tool to go easy on compilation
7. How do you do IO planning and can you explain few types of IO types
8. how do add debug probes for chipscope and what are the benefits inserting it and
inferring it?
1. Inferring it along with your RTL gives you freedom of debugging
whenever required. Adding it as a probe requires you to sort the netlist file
 and break up your head in finding the net names.
2. Sometimes some logic needs to be always put on JTAG for status/debug.
9. How do you program multiple FPGA images in flash and load?
1. Check google on this
10. How do you control reset logic
1. For FPGA, global reset is sufficient. Use async reset for internal logic and
sync that reset in main clk (if they are in same clock, else use accordingly)
2. Always assert the reset asynchronously and de-assert synchronously with
clock
11. How do you do STA
12. What are the timing constraints that you do for a typical design having
synchronous and asynchronous logic.
1. For async, false path or TIG constraints. We do not do any constraint for
async path if it is taken care in RTL
13. How does the RTL logic convert to logic gate, say a comparator or counter, please
describe
14. Can you write a code in RTL for a debounce logic or 9-bit counter?
15. Some questions about RTL coding for FPGA primitive components, what are the
primitive components and what have you used.
1. BUFGMUX, ibuff, obuff, etc