Basic Architecture of 32-bit RISC

Processor

Talal Khaliq

MSEE (DSSP)-7

Reg No: 118396

Supervisor: Dr. Awais M. Kamboh

 32-Bit Processor Architecture
Introduction:

The main purpose of this project is to develop simple RISC (Reduced Instructon Set Computer) based
GPP (General Purpose Processor). In this academic project, a simple 32-bit RISC processor will be
designed and tested using set compilers and tools defned.

The processor core conforming to the IEEE-1754 (SPARC V8) architecture. It will be designed for
embedded applicatons, combining high performance with low complexity and low power consumpton.
It will consist of following subsystems:

 Integer Unit (based on 7-Stage Pipeline Harvard Architecture)

 Cache (Data and Instructon)
 Floatng Point Unit & Co-processor
 Hardware Multplier and Divider
 Memory Management Unit
 Debug Support Unit
 Interrupt Controller

Its block diagram is shown below:

Integer Unit:

It will implement the full SPARC V8 standard, including hardware multply and divide instructons. The
implementaton will be focused on high performance and low complexity. The number of register
windows will be confgurable within the limit of the SPARC standard (2 - 32), with a default setng of 8.
The pipeline will consist of 7 stages with a separate instructon and data cache interface (Harvard
architecture). Its 7-stage pipeline is shown below:
These can be summarized as:

1. FE (Instructon Fetch): If the instructon cache is enabled, the instructon is fetched from the
instructon cache. Otherwise, the fetch is forwarded to the memory controller. The instructon is
valid at the end of this stage and is latched inside the IU (Integer Unit).
2. DE (Decode): The instructon is decoded and the CALL and Branch target addresses are
generated.
3. RA (Register access): Operands are read from the register fle or from internal data bypasses.
4. EX (Execute): ALU (Arithmetc Logic Unit), logical, and shif operatons are performed. For
memory operatons (e.g. LD) and for JMPL/RETT, the address is generated.
5. ME (Memory): Data cache is accessed. Store data read out in the executon stage is writen to
the data cache at this tme.
6. XC (Excepton) Traps and interrupts are resolved. For cache reads, the data is aligned as
appropriate.
7. WR (Write): The result of any ALU, logical, shif, or cache operatons are writen back to the
register fle.
Cache Sub-system:

Processor will implement a Harvard architecture with separate instructon and data buses connected to
two independent cache controllers. Both caches will be confgured with 1 - 4 sets, 1 - 256 kbyte/set, 16
or 32 bytes per line. Sub-blocking will be implemented with one valid bit per 32-bit word. The instructon
cache will use streaming during line-refll to minimize refll latency. The data cache will use write-
through policy and implement a double-word write-bufer. The data cache will also perform bus-
snooping on the AMBA based AHB (Advanced High performance BUS) bus.

Memory Management Unit:

A SPARC V8 Reference Memory Management Unit (SRMMU) will be optonally enabled. The SRMMU will
implement the full SPARC V8 MMU specifcaton, and provides mapping between multple 32-bit virtual
address spaces and 36-bit physical memory. A three-level hardware tablewalk will be implemented, and
the MMU would be confgured to up to 64 fully associatve Translaton Look-Aside Bufer (TLB) entries.

On-Chip Debug Support:

IU pipeline will include functonality to allow non-intrusive debugging on target hardware. To aid
sofware debugging, up to four watchpoint registers will be enabled. Each register will cause a
breakpoint trap on an arbitrary instructon or data address range. When the (optonal) debug support
unit is atached, the watchpoints can be used to enter debug mode. Through a debug support interface,
full access to all processor registers and caches will be provided. The debug interfaces will also allow
single stepping, instructon tracing and hardware breakpoint/watchpoint control. An internal trace
bufer will monitor and store executed instructons, which will later be read out over the debug
interface.
Interrupt Controller:

The processor will support the SPARC V8 interrupt model with a total of 15 asynchronous interrupts. The
interrupt interface will provide functonality to both generate and acknowledge interrupts. In case of
multple processor system, AMBA system will provide an interrupt scheme where interrupt lines are
routed together with the remaining AHB/APB bus signals. Interrupts from AHB and APB units will be
routed through the bus, combined together, and propagated back to all units. The mult-processor
interrupt controller core (IRQMP) will atached to AMBA bus as an APB slave, and monitors the
combined interrupt signals. The IRQMP core prioritzes, masks and propagates interrupts to one or more
processors.

Memory Controller:

The memory controller will handle a memory bus hostng PROM, memory mapped I/O devices,
asynchronous statc ram (SRAM) and synchronous dynamic ram (SDRAM). The controller will act as a
slave on the AHB bus. The functon of the memory controller will be programmed through memory
confguraton registers 1, 2 & 3 (MCR1, MCR2 & MCR3) through the APB (Advanced Peripheral Bus) bus.
The memory bus will support four types of devices: PROM, SRAM, SDRAM and local I/O. The memory
bus would also be confgured in 8- or 16-bit mode for applicatons with low memory and performance
demands. The controller decodes three address spaces (PROM, I/O and RAM) whose mapping is
determined through VHDL-generics (parameters). Following diagram shows diferent connectons with:

Bus Architecture:

Bus architecture is based on Advanced Microcontroller Bus Architecture (AMBA). The AMBA
specifcaton can be regarded as an on-chip communicatons standard for designing high performance
embedded microcontrollers. The typical AMBA bus system is shown in the fgure below, here there are
two bus systems, one requiring high performance for the high speed components, like, the on-chip
memory and DMA are connected to the high performance bus, whereas the other that do not need such
high bandwidth are connected through a bridge to the low power bus.
AMBA AHB & APB Introduction:

The AMBA AHB is the high-performance system backbone bus. It is for the high performance, high clock
frequency system modules. It supports the efcient connecton of processors, on-chip memories and
of-chip external memory interfaces with low-power peripheral macro-cell functons. AHB is also
specifed to ensure ease of use in an efcient design fow by using synthesis and automated test
techniques.

AMBA APB is optmized for minimal power consumpton and reduced interface complexity to support
peripheral functons. The APB is for the low power peripherals. APB can be used in conjuncton with
either version of the system bus.

Processor Design (with Bus, MMU and Peripherals):

This processor will be based on Leon-3 architecture is centered around the AMBA Advanced High-Speed
bus (AHB), to which the processor and other high-bandwidth devices will be connected. External
memory will accessed through a combined PROM/IO/SRAM/SDRAM memory controller. The on-chip
peripheral devices will include Ethernet, Dual CAN-2.0 interface, Serial and JTAG debug interfaces, two
UARTs, Interrupt Controller, Timers and an I/O port. The design will be highly confgurable as desired by
use. Leon3 SoC is shown below:
This Leon-3 processor will be used to understand proper functonality of sub-systems and controller
defned above. It will be simulated through Bare-C Cross Compiler (BCC) and Boot Prom Builder
(mkprom2) with default and custom customizaton as defned above. We will add new peripherals by
using AHB/APB bus architecture to enhance processor capabilites and also, try to customize compiler to
re-simulate new peripherals properly.