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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
FIR Filter Realization via Deferred End-Around
Carry Modular Addition
Armin Belghadr and Ghassem Jaberipur
Abstract— Hardware realization of FIR filters that are based
on residue number systems leads to increased speed and reduced
power, where besides the popular Mersenne numbers, several
moduli of the form 2n ± δ(δ ≥ 3) are commonly used. However,
additional weighted 2 i (i > 1) end-around carries (EACs) slow
down and complicate the required modular adders in comparison
to modulo-(2n − 1) adders. For example, for δ = 3, the modular
sum is obtained via A + B ∓ 3cout , where A and B are modulo-
(2n ± 3) operands and cout is the carryout of binary addition
A + B. In this paper, a new multioperand modular adder is
proposed, where the key improvement is that all the required
EAC additions (e.g., +3cout ) are postponed until after the last
filter tap, whereby tens of addition operations take place without
the EAC secondary addition; hence considerable savings of
time, area consumption, and power dissipation. The proposed
deferred EAC addition scheme has been applied to three previous
relevant works. The corresponding synthesis results showed
over 11%–32%, 27%–29%, and 21%–37%, reductions in delay,
area, and power measures, respectively. This is achieved despite
area and power overhead of the few appended stages into the
pipelined architecture of the filter, which are nevertheless shown
to become less significant as the number of filter taps grows.
Index Terms— FIR filter, digital signal processing, residue
number system, modular adder.
I. I NTRODUCTION
F INITE-FIELD and infinite-field impulse response
(FIR & IIR) filtering are quite common in digital signal
processing (DSP). The former, in both transposed and direct
forms, is also widely used in wireless communication, and
many other applications [1]. This is chiefly due to the linear
phase and inherently stable properties of FIR filters. The key
to such stability, contrary to the IIR, is the lack of feedback,
so that any bounded input results in a bounded output [2].
Hardware realization of a k-tap FIR filter is based on
(1), where x(t) is the temporal input signal and coefficients
Manuscript received November 7, 2017; revised January 3, 2018; accepted
January 21, 2018. This work was supported in part by IPM under
Grant CS1396-2-03 and in part by Shahid Beheshti University. This paper was
recommended by Associate Editor M. Mozaffari Kermani. (Corresponding
author: Ghassem Jaberipur.)
A. Belghadr is with the Department of Computer Science and Engi-
neering, Shahid Beheshti University, Tehran 1983963113, Iran (e-mail:
a_belghadr@sbu.ac.ir).
G. Jaberipur is with the Department of Computer Science and Engineering,
Shahid Beheshti University, Tehran 1983963113, Iran, and also with the
School of Computer Science, Institute for Research in Fundamental Sciences,
Tehran 1953833511, Iran (e-mail: jaberipur@sbu.ac.ir).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2018.2798595
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
ai (0 ≤ i ≤ k − 1) are provided either as constants or dynamic
variables. Each tap includes a multiplication and an addition
operation whose circuits can be considered as a pipeline stage.

k−1
y (t) = ai x (t − i ) (1)
i=0
Introduction of residue number system (RNS) as a vehi-
cle for implementation of the aforementioned addition and
multiplication operations has been shown [3]–[14] to gain
advantages in terms of speed, area consumption and power
dissipation over the conventional binary FIR filter realizations.
An RNS is recognized by a set of often mutually prime
moduli as its bases, so that a wide word multiplier or adder
is broken down into narrower RNS computation channels that
operate in parallel; hence better performance and commonly
lower power dissipation that is believed to be due to broken
carry chains. However the overhead of residue generation
and the final RNS-to-binary conversions must be considered
in evaluations. On the other hand, performance of an RNS
operation is dictated by the slowest computing channel that
generally corresponds to the smallest modulo. Therefore, it is
desirable to set up a moduli set containing small modulus
that lead to balanced speed of the corresponding channels.
However, in order to accommodate the required dynamic
range, one needs to increase the number of modulus, besides
the commonly used moduli 2n − 1, 2n , and 2n + 1, and the
less balanced 2n± p − 1. This calls, as a viable solution, for
inclusion of moduli of the form 2n ± δ(δ ≥ 3).
Several FIR filter realizations have been reported that
in particular reiterate the benefits of RNS implementation.
For example, three of the most recent relevant contributions
(i.e., [9], [12], and [14]) and an older one [13] are notable that
are briefly described below.
• In [9] a constant-coefficient (i.e., the ai constants in (1))
RNS-FIR filter architecture is proposed. The filter benefits
from an improved version of a multiplication algorithm
based on level-constrained common subexpression elimi-
nation [15]. It is shown that careful use of RNS leads
to delay and energy efficiency. In terms of figures of
merit, this work shows 22% performance improvement,
up to 14% reduction in power consumption and also
12% area reduction, in comparison with 2’s complement
implementations of FIR filter.
• In [12] the required multipliers for the utilized moduli
set {2n − 1, 2n , 2n+1 − 1} are implemented via preloaded
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
TABLE I
S ELECTED M ODULI S ETS FOR AN FIR A REA -D ELAY
T RADEOFF S CENARIO [17]
look-up tables (LUT), where improved figures of merit
are evident for the proposed RNS-FIR filters with respect
to previous relevant works. Since the moduli set is fixed,
the operation speed directly depends on the value of n.
That is should there be a need for larger dynamic ranges,
slower filters are achieved.
• The work of [14], shows that the RNS-FIR structures in
comparison to the binary counterparts, are more tolerant
to delay variations, in the context of process variation
prone Nano-scale VLSI implementations. The RNS ben-
efit is highlighted by reporting around 60% reduction
in normalized delay variation against the normal 2’s
complement realizations.
• The RNS-FIR filter of [13] focuses on moduli sets with
only prime moduli, which enables the use of isomorphic
modular multipliers. As such, the authors show power
efficiency of the RNS realization, wherein up to 50%
power reduction has been achieved at the same clock rate
as in the traditional normal binary implementations.
Moduli selection is of utmost importance in general DSP
applications due to its significant impact on design parame-
ters. So that a simple methodology does not guarantee a
suitable moduli set. For example, in order to speed up the
operations via higher parallelism, it is possible to employ
large number of small moduli to fulfill a required dynamic
range. This in turn undesirably escalates the complexity of
the required reverse conversion circuitry. To better explore the
vast design space induced by several possible moduli sets,
Re et al. [16] have proposed a tool for automatic generation of
the hardware description of RNS-FIR filters. This design tool
is capable of choosing an appropriate moduli set according
to a number of important criteria as listed in [2], as well
as the required dynamic range, and the target technology
library specifications. For instance, the contents of Table I
(borrowed from [17]), which are generated by the aforemen-
tioned tool, illustrate the moduli sets selected for different
dynamic ranges, within an experiment aiming at the best area-
delay tradeoff. Also similar studies over proper moduli-set
selection for efficient FIR filter implementations have been
reported in [4] and [18].
While the aforementioned moduli selection study of [16]
focuses on specific prime modulus, there are other FIR filter
designs that are based on small parametric moduli sets such as
τ = {2n , 2n − 1, 2n + 1} [4], [9]–[11], [19], [20]. For example,
the widest dynamic range in Table I can be accommodated by
an instance of τ with n = 16, for which very efficient modular
adders [21], [22] and multipliers [23], [24] are available.
Nevertheless, to cover such large dynamic ranges with even
smaller n (i.e., bit-width), 2-level RNS architectures have been
proposed [11], where higher level of parallelism, and fast
small-sized modular arithmetic units are achieved, at the cost
of doubling the efforts for forward and reverse conversions.
In order to expand the dynamic range, while keeping the
width of RNS channels reasonably low, moduli of the form
2n ± δ, for δ > 1, can be useful in the general parametric
designs. Nevertheless, such moduli can be found in the relevant
designs with fixed moduli, such as the proposed 48-bit case of
Table I. For example, 11 = 8 + 3, 19 = 16 + 3, 23 = 32 − 9,
29 = 32 − 3. Such endeavor requires hardware realizations of
the corresponding modular adders and multipliers. However,
while we have not encountered any dedicated realization for
the case of 2n + δ (δ > 1), the fastest modulo-(2n − δ) adder,
tailored for δ = 2q + 1 (e.g., modulo-11, −23, −29) [25],
is slower than modular adders for the popular moduli set τ .
Although this modulo-(2n − δ) adder can be considered as
latency-compatible with the τ -adders, the results in [25] show
considerable additional area and power measures. On the
other hand, in case of arbitrary δ-values, no single-adder
realization has been reported for modulo-(2n − δ) or modulo-
(2n + δ) addition, whereas commonly one n-bit half carry-
save adder (HCSA), two parallel adders followed by an n-bit
multiplexer (MUX) are required [26]. The need for an extra
adder and a bulky multiplexer array stems from the necessity
to incorporate the impact of δ-folded end-around carry (EAC)
signal into the final addition result (see Section II).
In this paper, we propose a new multi-operand modular
adder design via postponing the EAC handling per the required
single addition operations, while keeping track of the EACs
via an incrementor that is off the critical delay path (CDP).
This leads to elimination of the aforementioned MUX array.
Consequently, saving the delay and area of one n-bit MUX
array within the CDP is expected in addition to reduction of
the consumed area via replacing one adder with an incrementor
and the corresponding power savings. Moreover, the usual
additional complexities for the case of modulo-(2n + δ) adders
are avoided via implementing them as modulo-(2n+1 − δ  )
adders, where δ  = 2n − δ. As a common application of multi-
operand modular addition, we study the impact of the proposed
deferred EAC addition method in consecutive modulo-(2n ±δ)
additions that occur in RNS realization of FIR filters with
constant coefficients.
In Section II RNS-FIR filter architecture and a commonly
used general modular adder structure are introduced. Proposed
FIR filter architecture with the new addition approach is
presented in Section III. Section IV provides analytical and
synthesis based evaluations and comparison results, followed
by our concluding remarks in Section V.
II. RNS-FIR F ILTER A RCHITECTURE
Recalling (1), as the main equation for implementation of an
FIR filter, its RNS realization is provided by the architecture of
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BELGHADR AND JABERIPUR: FIR FILTER REALIZATION VIA DEFERRED EAC MODULAR ADDITION
Fig. 1. General view of an RNS-FIR filter.
Fig. 2. Modulo-m j k-tap FIR filter in transposed form.
Fig. 1, where the l gray boxes represent the parallel modulo-
m j (1 ≤ j ≤ l) channels that realize (2).
 k−1 
   
   
y j (t) =  |ai |m j |x (t − i )|m j   (2)
 mj
i=0 mj
The residual factors x j = |x (t − i )|m j are prepared via
the left forward conversion blocks in Fig. 1. However, |ai |m j
constants can be obtained via offline residue generators.
In addition, an RNS to binary conversion unit (the rightmost
block) composes the temporal outputs y j = |y (t)|m j into y(t)
signals of (1).
Fig. 2 reveals the inside of each gray box (see Fig. 1),
as the bulk of RNS-FIR filter computations, where there are
k consecutive filter taps, each of which contains a modular
multiplier, a modular adder (except for the leading tap), and
a pipeline register. It is well known that the pipelining clock
should be set equal to the delay of one tap [2]. To reduce
such clock period, researchers have taken advantage of the fast
LUT-based multipliers [12], [13]. To keep the size of required
LUTs reasonably low, the corresponding modulo should be
adequately small. Therefore, as was discussed in Section I,
one way of accommodating the required dynamic range is to
employ as many moduli of the form 2n ± δ, as necessary.
The conventional realization of |A + B|2n −δ [26] imple-
ments (3), a realization of which is given in Fig. 3, as a
compact version of the one in [26]. The provided fast parallel
architecture consists of an array of half-adders/pseudo-half-
adders that is marked as HCSA, where other blocks (two
adders and the multiplexor) are self-explanatory. However,
since the figures of merit of this architecture is not compatible
with those of the moduli set τ , and given the corresponding
considerations on different realizations of modulo-(2n − δ)
adders in Section I, we propose a new multi-operand architec-
ture for such modular adders that works for arbitrary δ values
3
Fig. 3. Detailed implementation of the modular adder (Equation 3).
with better impact in realization of RNS-FIR filters.

|A + B + δ|2n i f A + B + δ ≥ 2n
|A + B|2n −δ = (3)
A+B i f A + B + δ < 2n
The case of modulo-(2n + δ) adders can be handled via (4),
to be similarly realized by Fig. 3, where δ  = 2n − δ. For
example, modulo-19 adders can be realized as modulo-(32-13)
instead of modulo-(16+3).
|A + B|2n +δ = |A + B|2n+1 −δ  (4)
A. Previous Works of Interest
In order to show the impact of our proposed method
(as will be described in Section III) on the previously reported
architectures for RNS-FIR filter realization, we briefly describe
two selected works [12], [13] here. These works will be
accordingly modified in the next section and their figures of
merit will be compared with those of ours in Section IV.
The RNS-FIR filter of [13] is considered as an effective
RNS realization that, as is reiterated in [27], leads to low power
realization of DSP applications. The main innovation of this
work is to take advantage of the isomorphism technique [28] in
implementation of the required multipliers, which reduces the
complexity of modular multiplication into a modular addition
and three LUT retrievals. Regarding the employed moduli set,
however, all the moduli should be prime numbers.
Reddy and Sahoo [12] have proposed two approaches for
constant coefficient RNS-FIR realization, for the moduli set
{2n − 1, 2n , 2n+1 − 1}, which are called “RNS1” and “RNS2.”
Both architectures take advantage of LUTs for binary-to-RNS
conversion and radix-16 partial product generation to imple-
ment the required multipliers. The main difference between the
two architectures is that in each tap of RNS1 (see Fig. 6) the
radix-16 partial products are added to those of the previous tap,
via non-modular adders with carry-in (i.e., the single bit EAC
from the previous tap) while in RNS2 (see Fig. 8), the partial
products are reduced to one via CSAs and modular adders and
added to that of the previous tap similar to RNS1.
III. P ROPOSED D EFERRED EAC FIR
F ILTER A RCHITECTURE
Prominent impact of modular addition in the performance
of RNS-FIR filters is evident through (2). The heavily required
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 4. Proposed New1 modulo-m j k-tap FIR filter using deferred end-around carry modular addition.

Fig. 5. FIR filter tap comparison, a) Proposed architecture used in Fig. 4, b) Conventional architecture used in Fig. 2 and [13].

modulo-m j addition, where m j = 2n ± δ j can be described (see Fig. 3), as is shown by the gray crossed circle in the
via (5) and (6) (with δ representing an arbitrary δ j ). These (k + 2)th tap of Fig. 4. To appreciate the simplicity of the new
equations are the elaborated editions of (3) and (4), where architecture (see Fig. 5a), referred to hereafter as “New1”, and
W = A + B + δ = wn wn−1 . . . w0 (wn+1 wn . . . w0 , in case ease of comparison, we provide Fig. 5b. This figure contains
2n + δ) represents the interim sum. the structure of each tap of Fig. 2 based on the adder of Fig. 3
  (i.e., a general modular adder [26]). To evaluate the figures of
|W |2n i f wn = 1
|A + B|2n −δ = = wn−1 . . . w0 − δwn merit of [13] that was briefly described at the end of Section II,
W − δ i f wn = 0
as one of the reference works, we consider the latter modular
(5) adder as had been utilized in [13] due to lack of adequate

|A + B|2n +δ = |A + B|2n+1 −δ  = wn . . . w0 − δ wn+1 (6) information therein.
Functionality of the proposed realization of RNS-FIR filter,
Direct realization of (5) (and likewise for (6)) requires the
regardless of its multipliers’ detailed architecture, can be also
costly −δwn operation per each tap. However, these subtrac-
demonstrated with a simple numerical example, as follows,
tions (on wn = 0 instances) can be avoided by accumulating
for k = 5. This is with the understanding that the number
the number of required subtractions in a register until after
of taps is commonly in order of tens for high frequency
the last tap, when the accumulated value times δ is subtracted
selectivity in real applications [2]. Therefore, the overhead of
(i.e., only one subtraction). More details of this endeavor is
our two extra stages becomes negligible.
depicted by Fig. 4 and Fig. 5a (bearing the details of one
Example 1 (5-Tap Case): Equation (7) describes an instance
tap of Fig. 4.) that is supported by the following additional
of (2), for k = 5.
explanations. To count the required number of −δ operations,    
we use an incrementor per tap (i.e., the +1 boxes after each tap  |a | × |x (5)|  
 0 mj mj 
in Fig. 4). The incrementor within tap j receives the current   mj  
 
count and its clock is triggered if wn = 0 in tap j − 1  + |a1 |m j × |x (4)|m j  
  m j 
(see also Fig. 5a). Let p denote the value of the total count 
 + |a | × |x (3)|  
(i.e. the output of the last incrementor in the (k + 1)th tap). |y (5)|m j =  2 mj mj  (7)
  m j 
The correction term − pδ is obtained via an LUT that is   
 + |a3 |m j × |x (2)|m j  
preloaded with k integers |− pδ|2n −δ , where 0 ≤ p < k.   m j 

This is indicated by a multiplication box in the (k + 1)th tap  + |a | × |x (1)|  
 4 mj mj 
in Fig. 4, which is followed by a modulo-(2n − δ) adder m j mj
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BELGHADR AND JABERIPUR: FIR FILTER REALIZATION VIA DEFERRED EAC MODULAR ADDITION 5

Fig. 6. Proposed New2 modulo-(28 − 1) k-tap FIR filter, based on RNS1 of [12] and using deferred end-around carry modular addition.

Fig. 7. FIR filter tap comparison, a) Proposed architecture used in Fig. 6, b) Architecture used in RNS1 of [12].

TABLE II
N UMERICAL E XAMPLE TO D EMONSTRATE F UNCTIONALITY
OF THE P ROPOSED M ODULAR FIR F ILTER A RCHITECTURE
and that of Fig. 2 (Tap 5). Note that decimal values are used
instead of the actual binary, for ease of tracing. 
To better demonstrate the impact of the proposed deferred
EAC modular addition on RNS-FIR filter realization, without
loss of generality, we embark upon applying our technique on
two other quite recently reported architectures [12] RNS1 and
RNS2 that were briefly described at the end of Section II.
Consequently, Figs. 6 and 8 depict the corresponding two
new designs New2 and New3, respectively, where details of
each tap is illustrated by Figs. 7a (i.e., our technique applied
on RNS1), 7b (RNS1 of [12]), 9a (ours on RNS2), and
9b (RNS2), respectively.

IV. E VALUATION AND C OMPARISON

Table II contains the steps of computation of |y (5)|m j
(for m j = 23, and arbitrary values for ai and x (5 − i )) based
on the proposed architecture of Fig. 4 (delivered in Stage 7),
In order to show the potential benefits of the proposed
addition technique, our comparison baseline contains three
of the best previous RNS-FIR realizations; namely two
from [12] and one from [13]. The main influential components
for comparing the figures of merit of the proposed and
the reference works are the corresponding tap architectures
(see Figs. 5, 7, and 9), and less importantly the extra stages
in Figs. 4, 6, and 8.
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 8. Proposed New3 modulo-(28 − 1) k-tap FIR filter, based on RNS2 of [12] and using deferred end-around carry modular addition.

Fig. 9. FIR filter tap comparison, a) Proposed architecture used in Fig. 8, b) Architecture used in RNS2 of [12].

For evaluation and comparison purposes, the required hard-
ware descriptions (i.e., all the required memory units, registers,
buffers, adders and multipliers), for the circuits under test,
regarding the three comparison sets, are implemented and sim-
ulated to verify their correct functioning. The corresponding
HDL codes are mapped to the CMOS standard cell library of
the 90nm technology node of the TSMC, using the Synopsys
Design Compiler. Note that there are other components (such
as binary-to-RNS and reverse converters) that are exactly the
same in all designs and thus are not taken into account in
our evaluations. Regarding the evaluation of power dissipation,
it is worth mentioning that the power measures are extracted
based on simulation of synthesis results with back-annotation
of toggling activity, where uniformly distributed sample input
values are applied.
Two general scenarios are deliberated in our evaluation
experiments. One is comparing the results of single tap
realizations (see Subsection A, below). The other mainly aims
to consider impact of the extra stages, and thus compares the
corresponding implementations in one similar channel and in
the span of all taps (including the extra stages) whose number
varies from 16 to 1024 (see Subsection B). The exact measures
resulted from our experiments are compiled in Tables III-VII.
However, for ease of comparison and better reading, we pro-
vide eight plots (see Figs. 10-17) based on the contents of these
tables. Note that since the architectures RNS1 and RNS2 of
the reference work [12] cannot be realized for other moduli
besides 2n −1, we do the same for New2 and New3. However,
for comparison with [13], note that neither their design nor
ours is dependent on the value of δ. Therefore, for synthesis
purposes, we have considered the widest possible registers that
may be required depending on δ, n, and k. In other words,
hardware realization for the modulo-(2n ± δ) filter tap/channel
consumes the same amount of hardware and follows the same
structure for any value of δ, as far as it provides sufficient
space for its registers. This is possible due to the realization of
the multipliers using LUTs and also use of general structure for
modular adders. However, in actual implementations, where
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BELGHADR AND JABERIPUR: FIR FILTER REALIZATION VIA DEFERRED EAC MODULAR ADDITION 7

TABLE III
A REA (mm2 ) AND AT (A REA -T IME P RODUCT ) C OMPARISON FOR S INGLE TAP

TABLE IV
P OWER (uW) AND E NERGY (PDP) C OMPARISON FOR S INGLE TAP

the moduli set is clearly known (i.e., all δ j s are determined),
register sizes can be precisely set with no additional memory
allocation. Moreover, there are two restrictions in [13]; namely
the moduli of the form 2n ± δ should be prime and with n ≤ 6
to allow for reasonable LUT sizes. Although our contribution
does not enforce such limitations, for fair comparison, our
New1 design observes the same restrictions as in [13].
A. Tap Comparison
Structural difference of the proposed tap architecture with
those of the reference works can be captured by examining
Figs. 5, 7 and 9, where critical delay paths (highlighted
red) contain the same multiplier architecture within each
comparison set.
We should reiterate that, in our experiments, all adders
of [12] and [13] have been realized via parallel prefix
architecture (see also Section III), while all other basic
building blocks are implemented as were proposed in the
original papers.
Comparison Set 1: Regarding the comparison of [13] and
New1 designs, the Adder1 and one n-bit multiplexer of the
former design are to be compared against the incrementor
(and the associated register) of the latter. Therefore, obvi-
ous delay improvement (due to lack of multiplexer), and
area/power reduction (due to lack of the Adder1 and mul-
tiplexer) are expected for the proposed work. This expecta-
tion is confirmed by the synthesis results that are reflected
in Tables III and IV.
Comparison Sets 2 and 3: In the comparisons between
architectures in [12] and the corresponding proposed cir-
cuits, components of the critical delay paths are the mod-
ular and non-modular adder blocks of the reference work
and the simple non-modular adders and incrementors of the
proposed architectures. In the proposed realizations, lower
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 10. Area comparison of FIR filter tap (New designs vs. references). Fig. 12. Power comparison of FIR filter tap (New designs vs. references).

Fig. 11. AT comparison of FIR filter tap (New designs vs. references). Fig. 13. Energy comparison of FIR filter tap (New designs vs. references).

TABLE V
area and power consumptions are expected, due to lack of C OMPARISON OF F IGURES OF M ERIT FOR S INGLE TAP OF FIR F ILTER
carry-in supplements in the utilized parallel prefix adder, (I MPROVEMENT F IGURES IN THE 2’s C OMPLEMENT C OLUMN
and replacement of large modular adder blocks with non- R EGARD THE P ERCENTAGE OF N EW 2 M EASURES OVER
THE 2’s C OMPLEMENT E XPERIENCE )
modular simple adders. The curves in Figs. 10-13 compare
the area, area-time product (AT), power, and energy (power-
delay product or PDP) measures, respectively, for the three
comparison sets (i.e., [13] vs. New1, RNS1 of [12] vs.
New2, and RNS2 of [12] vs. New3) and only for n = 8.
These are drawn based on the data of Tables III and IV,
which are extracted from reiterated experiments for differ-
ent time constraints applied into synthesis process. Note
that the curves related to the proposed designs cover a
range of higher working frequencies (see left-most part of
the curves) not shared with those of the reference works,
where the synthesis tool was not able to produce as fast
circuits.
The least delay values acquired by the synthesis tool,
show 13.2%, 16.8%, and 48.9% speed up against the refer-
ence works [13], RNS1 [12], and RNS2 [12], respectively.
Greater impacts are evident through the curves of Fig. 10 for
area reduction (27.3%, 27.8%, and 29.2%) and Fig. 12 for frequency achieved by both designs in each comparison set,
power saving (21.2%, 28.7%, and 37.2%). Note that the latter not those of the highest frequency experienced by each design.
reported area and power improvements regard the highest To better capture the exact figures of merit, the values are
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BELGHADR AND JABERIPUR: FIR FILTER REALIZATION VIA DEFERRED EAC MODULAR ADDITION
Fig. 14. Area improvement for modulo-(28 −δ) channel of the realized filters
for the three comparison sets.
Fig. 15. AT improvement for modulo-(28 − δ) channel of the realized filters
for the three comparison sets.
summarized in Table V. Acknowledgement of RNS advantages
in FIR filter realization by previous studies was addressed in
Section I. Nevertheless, we provide design parameters for a
plain 2’s complement FIR tap implementation with the same
technology that are obtained based on behavioral description
for the synthesis tool. The results are compared against the
fastest RNS alternative (i.e., New2) in Table V. Superiority of
the latter is clearly evident.
Although we have run our experiments only for n = 8
and n = 16, it is easy to analytically conclude that the same
superiority of the new designs in all the three comparison sets
could be experienced for larger values of n. The reason is that
the impact of n is equally sensed in the depth (i.e., the number
of node levels) of the parallel prefix adders utilized in both
designs of each comparison set. That is doubling n adds one
parallel prefix level with the effect of additional delay of two
simple 2-input gates, and extra area consumption and power
dissipation due to almost doubled size of circuits.
B. Overhead of Extra Stages
The synthesis results show that delay of the two extra
terminating stages in Fig. 4 (i.e., 0.48 ns, and 0.36 ns) are less
9
Fig. 16. Power improvement for modulo-(28 − δ) channel of the realized
filters for the three comparison sets.
Fig. 17. PDP improvement for modulo-(28 −δ) channel of the realized filters
for the three comparison sets.
than that of a single tap and thus do not violate the pipeline
clocking that is based on one filter tap delay. Similarly, extra
circuitry at the final stages of the reference architectures
RNS1 and RNS2 of [12] exist that must be evaluated in
this part. The improved area and power measures that were
reported in Tables III and IV, regard one tap comparison.
However, in order to consider the overhead of the added final
stages of the proposed and reference architectures, modulo-
(2n ± δ) filter channels (2n − 1 for the comparison with
reference works RNS1 and RNS2) with varying number of
taps (including the final taps), are realized and compared for
the proposed and reference designs.
Tables VI and VII provide for area/AT and power/energy
measures, respectively, which are obtained for the highest
working frequency that is experienced by both designs in
each comparison set for operands of width n = 8, 16 and
seven different number of taps from 16 to 1024. For ease
of comparison, we use the tables’ contents for n = 8 and
different number of taps to draw the plots in Figs. 14-17 that
demonstrate the improvement percentage (regarding the pro-
posed design vs. the referenced work in each comparison set)
in area, AT, power, and energy, respectively. Convergence of
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE VI
A REA AND AT (A REA -T IME P RODUCT ) VALUES FOR M ODULO -(2n − δ) FIR F ILTER C HANNEL D ESIGNS

TABLE VII
P OWER AND E NERGY (P OWER -D ELAY P RODUCT ) VALUES FOR M ODULO -(2n − δ) FIR F ILTER C HANNEL D ESIGNS

the percentage curves to constant values towards the high
number of taps indicate that overhead of the extra stages
become negligible as the number of taps grows, as is the
case for high frequency selectivity applications. Also note
that the improvement curves related to the comparison set of
RNS1 [12] and New2 show less variation against different
number of taps. This is due to the extra circuitry employed at
the final stage of the RNS1 filter architecture.
V. C ONCLUSION
It is well known that introduction of residue number sys-
tem into hardware realization of FIR filters is advantageous.
On the other hand, different studies over the problem of
RNS moduli selection concluded that the popular moduli set
τ = {2n , 2n + 1, 2n − 1} may not be adequate in order to cover
the required dynamic range in such applications. Therefore,
the use of repeated moduli of the form 2n ± 1, with larger n,
and additional moduli of the form 2n ± δ has been experienced
in RNS realization of FIR filters. Regarding the required
modulo-(2n ± δ) adders, however, the existing realizations for
arbitrary δ-values by far are not adequately compatible with τ -
adders, particularly in timing balance. This can result in longer
tap delay, a problem for which we were motivated to look for
a solution.
We reviewed the previous RNS-FIR filter realizations and
focused on their multi-operand modular adder architectures,
which we found it not very efficient. Therefore, we proposed
a new technique for realization of such adders that is based on
postponing the end-around carry (EAC) addition. We studied
the impact of this method in consecutive modulo-(2n ± δ)
additions that occur in FIR filter RNS realization. A few
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BELGHADR AND JABERIPUR: FIR FILTER REALIZATION VIA DEFERRED EAC MODULAR ADDITION
extra stages were added to the sequence of taps for EAC
correction, with no penalty on the pipeline clocking time. Our
synthesis results showed over 11-32%, 27-29%, and 21-37%,
reductions in delay, area, and power measures, respectively.
These improvements were achieved despite the area and power
cost of the added stages into the pipelined architecture of
the filter which was shown to become less significant as the
number of filter taps grows.
As for the future relevant work, we plan to study the impact
of the deferred EAC technique on RNS multipliers, especially
in RNS-FIR filter applications.
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Armin Belghadr received the B.S. degree in com-
puter hardware engineering and the M.S. degree in
computer architecture from Shahid Beheshti Univer-
sity, Tehran, Iran, in 2011 and 2013, respectively.
He is currently pursuing the Ph.D. degree in
computer architecture with the Department of Com-
puter Science and Engineering, Shahid Beheshti
University. He focuses on teaching and research
in the mainstreams of computer-aided design, com-
puter arithmetic, and 3-D field programmable gate
arrays. His research interests include computer
arithmetic and particularly residue and redundant number systems.
Ghassem Jaberipur received the B.S. degree in
electrical engineering from the Sharif University
of Technology in 1974, the M.S. degree in engi-
neering from UCLA in 1976, the M.S. degree in
computer science from the University of Wisconsin,
Madison, in 1979, and the Ph.D. degree in computer
engineering from the Sharif University of Technol-
ogy in 2004. He is currently a Professor of com-
puter engineering with the Department of Computer
Science and Engineering, Shahid Beheshti Univer-
sity, Tehran, Iran. He is also with the School of
Computer Science, Institute for Research in Fundamental Sciences, Tehran.
His main research interest is in computer arithmetic. He is recognized as one
of the 50 distinguished graduates for years 1966–2016 in the Sharif University
of Technology.