Applications of Silicon-Germanium Heterostructure Devices

Applications of Silicon–Germanium
Heterostructure Devices
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Series in Optics and Optoelectronics
Applications of Silicon–Germanium
Heterostructure Devices
C K Maiti and G A Armstrong
Indian Institute of Technology,

Kharagpur 721302, India
and
The Queen’s University of Belfast,
Belfast, Northern Ireland, UK
Institute of Physics Publishing

Bristol and Philadelphia
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c IOP Publishing Ltd 2001
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A catalogue record for this book is available from the British Library.
ISBN 0 7503 0723 4
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Consultant Editor: S C Jain

Commissioning Editor: Tom Spicer
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In memory of
Dr Suva Maiti
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CONTENTS
PREFACE xiii
1 INTRODUCTION 1
1.1 Evolution of bipolar technology 5
1.2 Heterojunction bipolar transistors 9
1.3 Development of SiGe/SiGeC HBT technology 13
1.4 Heterostructure field-effect transistors 16
1.5 Vertical heterostructure FETs 18
1.6 Optoelectronic devices 20
1.7 Applications of SiGe HBTs 21
1.8 Summary 25
Bibliography 25
2 FILM GROWTH AND MATERIAL PARAMETERS 32
2.1 Strained layer epitaxy 33
2.2 Deposition techniques 42
2.2.1 Wafer cleaning 43
2.2.2 Molecular beam epitaxy 44
2.2.3 UHVCVD 46
2.2.4 LRPCVD and RTCVD 47
2.2.5 Very low pressure CVD 48
2.2.6 Remote plasma CVD 48
2.2.7 Atmospheric pressure CVD 48
2.2.8 Solid phase epitaxy 49
2.2.9 SiGeC film growth 49
2.2.10 Strained-Si film growth 50
2.3 Thermal stability of alloy layers 51
2.4 Bandgap and band discontinuity 52
2.4.1 Si/SiGe 54
2.4.2 Si/SiGeC 56
2.4.3 Strained-Si 58
2.5 Mobility 59
2.5.1 Si/SiGe 59
2.5.2 Si/SiGeC 59
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viii Contents
2.5.3 Strained-Si 63
2.6 Summary 64
Bibliography 65
3 PRINCIPLE OF SIGE HBTS 73
3.1 Energy band 75
3.2 Terminal currents in a SiGe HBT 77
3.3 Transit time 83
3.4 Early voltage 85
3.5 Heterojunction barrier effects 90
3.5.1 Effect of undoped spacer layers 92
3.6 High level injection 94
3.7 High-frequency figures-of-merit 96
3.7.1 Unity gain cut-off frequency, fT 96
3.7.2 Maximum oscillation frequency, fmax 98
3.8 Breakdown voltage, BVceo 99
3.9 Summary 100
Bibliography 100
4 DESIGN OF SIGE HBTS 104
4.1 Device modelling 106
4.2 Numerical methods 108
4.3 Material parameters for simulation 110
4.3.1 SiGe: hole mobility 112
4.3.2 SiGe: electron mobility 113
4.3.3 SiGe: bandgap 115
4.3.4 Recombination and carrier lifetime 117
4.4 History of simulation of SiGe HBTs 118
4.5 Experimental SiGe HBTs 119
4.6 Device design issues 121
4.6.1 Base design 122
4.6.2 Emitter design 126
4.6.3 Collector design 129
4.7 Small-signal ac analysis 134
4.7.1 Small-signal equivalent circuit 134
4.7.2 Evaluation of transit time 139
4.7.3 ECL gate delay 141
4.8 Summary 145
Bibliography 145
5 SIMULATION OF SIGE HBTS 152
5.1 Epitaxial-base SiGe HBT (1995) 155
5.2 Double polysilicon self-aligned SiGe HBT (1998) 159
5.3 Energy balance simulation 162
5.4 SiGe HBTs on SOI substrates 166
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Contents ix
5.5 Low-temperature simulation 172

5.5.1 Low-temperature SiGe HBTs 173
5.5.2 Low-temperature simulation using ATLAS 175
5.6 I2 L circuits using SiGe HBTs 180
5.7 Noise performance 182
5.8 Radiation effects on SiGe HBTs 186
5.8.1 Low dose-rate effects 189
5.8.2 Simulation of radiation hardness 190
5.9 Summary 192
Bibliography 192
6 STRAINED-SI HETEROSTRUCTURE FETS 196
6.1 Mobility in strained-Si 198
6.1.1 Theoretical mobility 198
6.1.2 Experimental mobility 200
6.2 Band structure of strained-Si 203
6.3 Device applications 204
6.3.1 Strained-Si n-MOSFETs 206
6.3.2 Strained-Si p-MOSFETs 209
6.4 Simulation of strained-Si HFETs 213
6.5 MODFETs 217
6.6 Heterojunction Si/SiGe CMOS 226
6.7 Summary 231
Bibliography 232
7 SIGE HETEROSTRUCTURE FETS 238
7.1 HFETs: structures and operation 241
7.1.1 Experimental HFETs 242
7.2 Design of SiGe p-HFETs 245
7.2.1 SiGe: MOS capacitor simulation 245
7.2.2 Si-cap/oxide thickness variation 246
7.2.3 Germanium mole fraction 247
7.2.4 Choice of gate material 249
7.2.5 Current–voltage characteristics 250
7.2.6 δ-doped p-HFETs 252
7.3 SiGe p-HFETs on SOI 254
7.4 SiGeC p-HFETs 257
7.5 Devices using poly-SiGe 259
7.5.1 Poly-SiGe gate MOSFETs 260
7.5.2 Poly-SiGe thin-film transistors 261
7.6 Vertical FETs 263
7.6.1 Vertical SiGe HFETs 263
7.7 Noise in p-HFETs 265
7.8 Summary 267
Bibliography 268
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x Contents
8 METALLIZATION AND HETEROSTRUCTURE

SCHOTTKY DIODES 272
8.1 Deposition of metal films 274
8.2 Fabrication of Schottky diodes 276
8.3 Silicidation of group IV alloy films 276
8.4 Silicidation with titanium 278
8.4.1 Rutherford backscattering characterization 279
8.4.2 Auger electron spectroscopy characterization 282
8.4.3 Sheet resistivity 284
8.5 Silicidation using Pt and Pd 285
8.6 Heterostructure Schottky diodes 287
8.7 Schottky diodes on strained-Si1−x Gex 291
8.7.1 Barrier height and ideality factor 293
8.7.2 Interface state density distribution 300
8.8 Schottky diodes on strained-Si 303
8.9 Summary 305
Bibliography 307
9 SIGE OPTOELECTRONIC DEVICES 310
9.1 Optoelectronic devices in silicon 315
9.1.1 p–n junction photodiode 316
9.1.2 Schottky barrier photodiode 317
9.1.3 p–i–n photodetectors 318
9.1.4 Metal–semiconductor–metal photodetectors 318
9.2 Optical properties of SiGe and SiGeC films 321
9.3 Optical devices using SiGe alloys 325
9.4 Optical devices with SiGeC and GeC alloys 334
9.5 Simulation of optoelectronic devices 336
9.5.1 PtSi/SiGe Schottky photodetectors 338
9.5.2 SiGe p–i–n photodetectors 341
9.5.3 MSM photodetectors 345
9.5.4 SiGe/Si waveguide photodetectors 350
9.6 Summary 352
Bibliography 353
10 RF APPLICATIONS OF SIGE HBTS 359
10.1 SiGe: perspective for wireless communication 363
10.2 Technology comparison 367
10.3 MOS versus bipolar 369
10.4 SiGe BiCMOS technology 375
10.5 RF circuits 378
10.5.1 Low-noise amplifiers 378
10.5.2 Power amplifiers 381
10.5.3 VCOs and frequency synthesizers 384
10.6 Passive components 386
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Contents xi
10.7 Commercially available products 388

10.7.1 TEMIC Semiconductors 388
10.7.2 IBM 390
10.8 Summary 392
Bibliography 392
INDEX 397
PREFACE
Since the first report of SiGe heterostructure bipolar transistors (HBTs) in

1987, there has been tremendous progress in SiGe research. The successful
demonstrations of SiGe HBT technology, in both high-performance digital
and analogue circuit applications, are the results of over 15 years of steady
research progress from initial material preparations in 1984, through device
demonstrations from 1987–1992 to large scale circuit fabrication in 1994
and commercial products in 1998.
With the development of the ultrahigh vacuum chemical vapour
deposition (UHVCVD) system, which produces highly uniform SiGe
heterostructures more rapidly than other methods, such as molecular beam
epitaxy (MBE) or low-pressure CVD, only minor modifications to the
process flow are required to incorporate the manufacture of SiGe HBTs
into a conventional bipolar or complementary metal–oxide-semiconductor
(BiCMOS) line. Indeed, SiGe HBTs integrated with CMOS (BiCMOS)
circuits have been shown to be substantially cheaper than III–V technology.
Qualified full-scale production devices (with cut-off frequencies in the
50–60 GHz range) and circuits using 200 mm wafers in a standard 0.5 µm
CMOS line are now available.
SiGe HBTs are superior to Si bipolar junction transistors (BJTs) and
comparable to the best GaAs transistors, in that they are ideally suited for
low-voltage, low-power wireless communication applications. Promising
research results, combined with recent commercialization announcements,
have generated considerable optimism. Silicon has been pushed to the
1–2 GHz frequency domain. However, many new RF applications, such as
handheld and personal communication systems (PCS), direct broadcast
TV, local multipoint distribution systems and wireless LANs, require
circuit operation at frequencies up to 30 GHz.
High-speed digital communications (up to 40 Gbps) such as
synchronous optical network (SONET) applications also require high-
speed devices—typically with a maximum oscillation frequency, fmax in
excess of 100 GHz. It is now believed that, in many of these markets,
SiGe will provide direct competition for GaAs on the grounds of cost
and design flexibility. Indeed, it is possible that SiGe technology may
xiii
xiv Preface
eventually be applicable in the frequency range above 30 GHz, where GaAs

is currently well established, in projects requiring wireless technology for
traffic management and control, such as global positioning systems (GPS),
sensor collision avoidance systems, road speed monitors and side airbag
triggers.
The application of strained-SiGe to heterostructure field-effect
transistors (FETs) is not as well developed as that of HBTs. In MOS
technology, scaling the gate length is impeded by lithographic techniques
and scaling device width is limited by the relatively low hole mobility
of a silicon p-channel metal–oxide-semiconductor field-effect transistor
(p-MOSFET). When used in a heterojunction FET, strained-SiGe enhances
the mobility of holes but not of electrons. Thus, the current drive of
the p-MOSFET is improved, but not that of the n-MOSFET. However,
strained-Si grown on a relaxed-SiGe buffer layer improves the electron
mobility and current drive of an n-MOSFET. Other important research
topics include synthesis of SiGeC, a carbon-containing alloy of SiGe and Si,
and quantum-confined structures, which may ultimately offer an alternative
to lithographic techniques or serve as single-electron devices.
Integrated optoelectronics is another promising research field for SiGe
devices, although development is hindered by the lack of a SiGe light
emitter. Detectors and waveguides have been demonstrated, and integrated
SiGe and Si devices are possible. Work is underway on a graded buffer
layer—a virtual substrate—of SiGe that would permit III–V/SiGe/Si
integration. Possible photonic devices are under development including:
low-loss optical waveguides, photodetectors for 1.3–1.6 µm, light emitters,
long-wave infrared detectors, optical switches and photonic integrated
circuits.
In this textbook, we discuss the relevance of SiGe technology to all
the above application areas. The main focus of the book is on device
applications, backed up by an extensive survey of the literature. Chapter 1
reviews the key developments in SiGe technology from the earliest research
to the present day, leading to a brief summary of the current status of SiGe
products in the marketplace. Chapter 2 describes key technology issues for
the growth of stable strained-SiGe layers using different types of reactors.
The effect of the Ge composition on strain and the consequent effect
on bandgap and mobility is described. Chapter 3 gives the background
theory of the HBT. Chapter 4 describes issues relating to optimal design of
SiGe HBTs and considers how device simulation can be used to determine
key indicators of device performance. Chapter 5 extends the concepts of
chapter 4 to give a number of examples of the use of device simulation to
study a wide range of device structures involving application of SiGe.
Chapter 6 describes how growth of a strained silicon (strained-Si)
layer on a relaxed-SiGe buffer layer has led to higher values of electron
mobility with the resultant enhancement in the high-frequency performance
Preface xv
of heterojunction field-effect transistors (HFETs). Strategies for the

enhancement of hole mobility using either MOSFET or modulation-doped
field-effect transistor (MODFET) structures are given. The impact of both
strained-Si MODFETs and MOSFETs as a basis for future deep submicron
CMOS is considered. In chapter 7, an alternative approach to the formation
of a p-HFET is described, involving growth of a strained-SiGe epitaxial
layer on a silicon substrate. Once again, the overall objective is a higher
mobility, in this case hole mobility, to improve both the transconductance
and bandwidth associated with the p-channel MOSFET.
Chapter 8 discusses design, characterization and application of
Schottky diodes, while chapter 9 considers the design and application
of optoelectronic devices. Finally, chapter 10 assesses how SiGe
technology competes with other alternative technologies in the wireless
telecommunications marketplace. It also focuses on how SiGe technology
has rapidly matured, allowing its integration into a mixed signal BiCMOS
process.
In summary, this book fills a gap in the literature in a rapidly evolving
field, as it blends together wide ranging descriptions of SiGe technology,
device physics and circuit applications. Where possible, the theoretical
material is backed up by computer simulation. An extensive bibliography
is provided for each chapter, which helps the reader identify the key stages
in the development of SiGe from early research through to its integration
in high-performance BiCMOS.
We wish to extend special thanks to Professor S C Jain, Consultant
Editor, Institute of Physics Publishing, for his keen interest and valuable
comments. We are grateful to Tom Spicer, Commissioning Editor, for his
personal support for this project. It was due to the skill and efforts of
his colleagues, Simon Laurenson, Production Editor, and Sarah Plenty,
Production Controller, that the project could be completed in a relatively
short time. They deserve our sincere thanks. The help of the Production
Department in removing the deficiencies in several figures is gratefully
acknowledged.
Finally, we must thank sincerely our families for their support and
help during the preparation of this book.
C K Maiti
G A Armstrong
26 October 2000
Chapter 1
INTRODUCTION
Silicon is by far the most widely used semiconductor material and is likely
to remain so for the foreseeable future, although from the perspective of an
integrated circuit (IC) designer silicon is hardly a perfect semiconductor.
Compared with other semiconductors, it is relatively poor in terms of
how fast the charge carriers can move through the crystal lattice, which
limits the speed at which silicon devices can operate. ‘Why is silicon still
dominant?’ The answer to this question is economics. Silicon is abundant
in nature, non-toxic, strong and an excellent conductor of heat. It can be
grown to a very high purity and very large diameter (with 12 inch now
being contemplated) wafers, and it readily forms a stable insulating film
(SiO2 or Si3 N4 ) of high quality. Properties of this kind make silicon a
natural choice for IC manufacturing and, in fact, over the past 40 years or
so, the performance of silicon ICs and the density of devices per unit area
have soared, while the cost per function has plunged (see figure 1.1). ICs
are more difficult and more expensive to fabricate from III–V compound
semiconductors such as GaAs/AlGaAs or InP. High-quality oxides are
scarce in the III–V semiconductors, impeding device integration. High-
purity, large diameter crystals are difficult to grow and yield is poor because
of more defect density.
For decades, miniaturization has been the key to faster performance
of ICs. As the size of a transistor, whether field effect or bipolar,
influences its speed of operation, designers have focused on creating
ever smaller transistors. The strategy for enhancing the function of an
electronic device by reducing its critical dimensions is commonly referred
to as scaling. Although scaling has led to improvement in the speed
and flexibility of silicon-based electronics, the trend cannot continue
indefinitely. Researchers are actively pursuing alternative approaches to
boost the speed of electronic devices by introducing ‘bandgap engineering’.
In silicon technology, two materials may be used in bandgap-engineered
transistors: silicon carbide (SiC) and silicon–germanium (SiGe). Silicon
1
2 Introduction
Figure 1.1. Moore’s law: the gate length and cost of production lines as a
function of time. Source: National Technology Roadmap for Semiconductors,
Semiconductor Industry Association, San Jose, USA, 1997. (After Paul D J 1999
Adv. Mater. 11 191–204.)
carbide is a suitable emitter material, since it has a wider bandgap of

2.2 eV, while SiGe is a suitable base material with a lower bandgap which
is dependent on the Ge content.
The evolution of SiGe technology has been very rapid. It has gone
from laboratory research in less than eight years to a commercial reality.
As an example, a 12-bit digital-to-analogue converter (DAC) has been
developed jointly by IBM and Analog Devices that processes data at
1.0 Gbit s−1 , which matches the speed of the best such circuits built using
GaAs technology and it operates on a fraction of the power they require.
At present, aggressively designed SiGe transistors have cut-off frequencies
in excess of 130 GHz.
In recent years, SiGe transistors, and other devices based on SiGe
alloys, have been evident in an increasing number of products. SiGe
heterojunction bipolar transistor (HBT) technology has the advantage of
relatively simple integration with conventional complementary metal–oxide
semiconductor (CMOS) silicon circuits to form a SiGe BiCMOS technology,
in which the Si bipolar devices and SiGe HBTs can be integrated for critical
high-speed analogue or digital functions. Silicon CMOS can serve for very
high density memory or compact on-chip signal processing functions, which
cannot be realized in other technologies.
The two most important devices used in silicon technology are
the bipolar and field-effect transistors, each having their strengths and
Introduction 3
Figure 1.2. Capacity of backbone network. (After Nakamura M 1998 IEEE

ISSCC Tech. Dig. pp 16–21.)
weaknesses. Bipolar transistors with their high transconductance have

predominantly been used in analogue applications, such as small-signal
amplification, and in high-speed digital circuits, such as emitter coupled
logic (ECL). For digital circuit applications, CMOS technology dominates
because of its low power dissipation and high density of integration.
The variety of bipolar transistors can, in general, be grouped into
those optimized to satisfy the requirements of two major industries:
communications and computers.
As all activities of modern society have become information oriented,
the need for high-speed and large capacity telecommunications systems
is rapidly increasing. The rapid growth in data transmission has also
created an urgent demand for increasing transmission capacity in backbone
networks. Today, 10 Gb s−1 systems are in commercial use. Figure 1.2
shows the predicted trend for optical fibre transmission capacity. Two
methods exist for achieving a higher transmission capacity:
(i) time division multiplexing (TDM), and
(ii) wavelength division multiplexing (WDM).
Figure 1.3 shows the relationship between the bit rate and the required
cut-off frequency (fT ) of devices from differing technologies. A 10 Gb s−1
system with fT in the range 25–50 GHz can be satisfied using Si bipolar
technology, while a 40 Gb s−1 system, with corresponding fT in the range
100–200 GHz, will require SiGe, GaAs or InP HBTs.
In communication applications, the increased importance of
transmitting, receiving and interpreting data transmissions at high speeds
has generated a need for high-frequency precision analogue circuitry. With
4 Introduction
Figure 1.3. Electron devices for backbone network. (After Nakamura M 1998
IEEE ISSCC Tech. Dig. pp 16–21).
internet host counts doubling every five to seven months, there is a

pressing need for high-speed interconnect circuits [1]. In these circuits,
the high operating frequency, high transconductance, close matching of the
device parameters and bandgap voltage referencing capabilities of bipolar
transistors make them invaluable to the design of analogue circuits.
In the computer industry, the high-frequency performance and high
current drive capabilities of bipolar transistors enable the realization of
digital circuits with very low gate delay and high fan-out compatibility. The
switching delay of a bipolar circuit is made up of three major components.
The importance of these two characteristics can be best illustrated by
a graph of the ECL gate delay time versus the collector current of the
bipolar transistors, as shown in figure 1.4. In the low collector current
range, the gate delay is a function of the load resistance, RL , and the input
capacitance of the gate, Cin , which is determined by the capacitance of
the bipolar transistors as seen from the gate input. In the high collector
current range, the gate delay decreases, approaching a minimum set by
the total forward transit time of the transistor, τF . At higher currents,
the product of the combination of extrinsic and intrinsic base resistance
and the diffusion capacitance begins to dominate the propagation delay.
As is evident from figure 1.4, the realization of low gate delays requires
the use of increased collector currents. Thus, if the operating current per
gate is a limiting factor, the design should be focused on the reduction of
parasitic capacitances. The delay contributed by each part of the transistor
is different, depending on the type of circuit used.
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Evolution of bipolar technology 5
Figure 1.4. Variation of delay components of a bipolar circuit versus collector

current. At low currents, the gate delay is determined by the charging of the
junction capacitances. At high currents, the minority carrier storage associated
with high-level injection prevails.
However, power consumption and dissipation restrictions in digital

bipolar circuits limit the collector current of the densely packed transistors.
For high-speed digital applications, the challenges for designers of bipolar
junction transistors (BJTs) include an increased level of integration, lower
operating currents, reduction in base resistance and lower minimum gate
delays.
1.1. EVOLUTION OF BIPOLAR TECHNOLOGY
The design and study of a new semiconductor device structure hold promise
at both the device level, where the transistor’s electrical behaviour may lead
to novel effects, and the circuit level, where the device characteristics may
be exploited to enhance functional performance. Since the revolutionary
invention of the point-contact transistor at Bell Laboratories in 1947,
numerous new transistor structures have been proposed and demonstrated.
Of the many transistors demonstrated in the last fifty years, however, the
IC market is dominated by just two devices: the BJT with a market share
of about 20%, and the metal–oxide semiconductor field-effect transistor
(MOSFET) with 75%. BJTs and MOSFETs are the dominant high-
performance devices in silicon technology. In this section, we shall present
an overview of the high-performance transistors in silicon.
6 Introduction
Figure 1.5. (a)–(g) The evolutionary continuum between bipolar and field-effect
transistors. A conventional FET is shrunk in lateral dimension (a), then
converting to a stacking configuration (b). Rotating the structure by 90◦ produces
(c). Reducing the vertical dimensions from (c) to (e) yields a permeable base
transistor. Replacing the grid with a sheet of metal produces a metal-base
transistor (f ). Finally, replacing the metal base with a p-doped layer results in
the conventional bipolar transistor (g). (After Stoneham E B 1982 Microwaves
55–60.)
Evolution of bipolar technology 7
The FET represents a class of devices (including MOSFETs, metal–

semiconductor field-effect transistors (MESFETs) and junction field-effect
transistors (JFETs)) which operate on a principle substantially different
from that of the class of devices represented by the BJT. FETs represent
lateral geometries and spatial charge control (via depletion regions), while
BJTs represent vertical geometries and charge control. An ideal three-
terminal device may be considered to move the charge within a finite time,
when stimulated by some input voltage or current. Stoneham [2] has shown
that most new devices lie somewhere between the extreme cases of BJTs
and FETs. By manipulating the geometries and translating lateral and
vertical properties, the evolution of one device into the other is possible as
shown in figure 1.5.
Although MOSFETs have constantly challenged the BJTs for
performance superiority, bipolar devices have consistently kept their
advantage by evolving new and/or improved process and design. The
historical advantage of the bipolar device is the fact that its vertical
dimensions are easier to control than the lateral MOS structure. Current
gain in a homojunction npn bipolar transistor is mainly determined by the
ratio of the density of electrons injected from the emitter into the base and
the density of holes reinjected from the base into the emitter, and results in
a finite dc current gain. Many attempts have been made to design improved
emitter structures to minimize the disadvantages of the homojunction Si
BJT with a heavily-doped emitter. Among these, polysilicon technology
is by far the most advanced but problems with contact resistance still
exist. Techniques to reduce contact resistance lead to reduced emitter
efficiency [3, 4].
In a circuit environment, however, parasitics tend to dominate. The
base–collector extrinsic junction and the base resistance prevent input
signals from reaching the appropriate internal junctions until sufficient
charge has filled the depletion regions (in the case of the base–collector
capacitance), while the base resistance reduces the voltage seen by the
internal emitter–base junction, lowering the effective transconductance.
The steady improvement in performance of the BJT is the result of
technology maturing sufficiently to build these scaled optimal structures.
The evolution of new process technologies, such as silicon-on-insulator
(SOI), trench isolation and epitaxial regrowth, provide techniques to
drastically reduce the junction capacitances. These techniques have pushed
the evolution of the transistor to its technical limits. As lateral geometries
continue to shrink, devices require vertical design modifications in order to
maintain higher performance.
Several alternative structures have been proposed in the literature
to extend the performance of silicon bipolar devices. The metal-base
transistor at one time held the most promise of all hot electron devices [5].
The injection of electrons from the emitter occurs as in a BJT, but electrons
8 Introduction
entering the base from the emitter see a large band discontinuity. This
accelerates them to a large momentum in the vertical direction. The
base being very narrow, electrons remain hot throughout the base region,
resulting in a reduction in the base transit time. In addition, the use of a
metal for the base reduces the base resistance. In principle, the metal-base
transistor should have a significant performance advantage over the BJT.
Unfortunately, no metal-base transistor has yet achieved even unity current
gain.
Nishizawa [6] proposed a high-speed switching device known as the
bipolar static induction transistor (BSIT) which may be thought of as
a bipolar transistor with the intrinsic base region missing. Control of
collector current in this device is only possible because the extrinsic p+
base regions are physically close together and current is controlled by
forward biasing the base–emitter junction. A high transconductance is
obtained compared to FETs of comparable dimensions and also leads
to faster switching times. Indeed, several types of circuits have been
successfully fabricated with the BSIT device [6, 7]. However, due to its
extreme sensitivity to process variations, the BSIT could hardly be useful
for high levels of circuit integration.
Another interesting structure, a tunnel transistor, which is identical
to that of a p-channel MOSFET with a very thin (20 Å) gate oxide layer
has also been proposed [8]. The thin oxide layer allows substantial electron
tunnelling currents in the vertical direction. The gate can thus act as
an emitter, the substrate as a collector and the source/drain regions as
extrinsic base regions. The intrinsic base is replaced with a mobile hole
layer or ‘inversion channel’ whose charge density modulates the electric
field strength across the oxide, and thus controls the electron tunnelling
currents in the vertical direction. This hole charge density is controlled by
the extrinsic base potential. Using this concept, Simmons and Taylor [8]
have theoretically and experimentally studied tunnel transistors built in
the Alx Ga1−x As/GaAs material system. GaAs was used as the emitter
and the collector semiconductors and AlAs was used as a wide bandgap
semiconductor replacing the insulator. However, limited current density
and transconductance resulted in a much slower device.
Despite much research on alternative technologies, silicon integrated
circuits dominate mainstream electronics. Impressive improvements in
high-speed Si bipolar technology have been made in the last few years.
Self-aligned bipolar transistors having polySi base electrodes have been
effective in reducing base resistance through their small resistance in the
base electrode and short length between the emitter and the base.
Si homojunction transistors with a maximum oscillation frequency,
fmax above 80 GHz have been obtained using low base resistance self-
aligned metal/IDP (SMI) technology. The base resistance is reduced to a
half compared to conventional polySi technology and a 12.2 ps gate delay
Heterojunction bipolar transistors 9
Figure 1.6. Si and SiGe device performance over the past several years. In terms
of device speed, SiGe has maintained about 50% advantage over Si devices.
time in an ECL ring oscillator at a voltage swing of 250 mV has been

achieved [9]. In 1999, Bopp et al [10] reported a near production, standard
implanted base silicon bipolar technology for mixed-signal applications.
Applicability for mobile communications up to at least 6 GHz, and for
high-speed data links in the range 10–40 Gbits s−1 , was demonstrated.
Transistors exhibited an fmax of 65 GHz, a minimum noise figure of 1.3 dB
at 6 GHz and a 12 ps ECL gate delay.
Summarized in figure 1.6 are some of the reported results obtained
with high-performance Si homojunction transistors. Although the data
for Si are only plotted up to 1997, the trend line shows that SiGe offers
approximately 50% advantage in overall device performance. By way of
comparison, back in 1991, AlGaAs/GaAs MODFETs achieved an fT of
over 250 GHz [11] and exceeded the 400 GHz barrier for fmax . In an
effort to improve single chip functionality, it is not surprising that, despite
increased process complexity, BiCMOS processes have been developed to
combine the advantages of CMOS and bipolar devices [12].
1.2. HETEROJUNCTION BIPOLAR TRANSISTORS
The idea of varying the bandgap in a bipolar transistor structure to increase

the emitter injection efficiency is almost as old as the bipolar junction
transistor itself. Shockley described the idea in his application for a
patent on the junction bipolar transistor [13]. The inherent performance
advantages of HBTs over conventional bipolar junction transistors have
been recognized and Kroemer [14] first explained the underlying principle
10 Introduction
of the heterojunctions. The heterojunction offers a larger set of device

configurations and has become the basis for the so-called field of bandgap
engineering [15].
The principle of operation of an HBT is identical to that of the BJT,
except that the bandgap of the emitter region exceeds that of the base
region by ∆Eg , typically of the order of 0.1–0.2 eV. The resultant e∆Eg /kT
exponential increase in current gain permits scaling of the base region to
smaller thicknesses and higher doping levels. Conceptually, the simplest
way to incorporate a heterojunction into a silicon bipolar transistor process
is to replace the polySi emitter of a standard bipolar process with a
wide bandgap material having a high-quality interface to the silicon base,
thereby combining the minimized parasitic capacitances and resistances
of the device structure with the increased emitter injection efficiency of
the wide bandgap emitter HBT. Several wide bandgap materials have
been investigated, such as GaP [16–18], semi-insulating polycrystalline
silicon (SIPOS) [19–21], oxygen-doped silicon epitaxial films [22], epitaxial
β-SiC [23], polycrystalline β-SiC [24], amorphous silicon (α-Si) and
microcrystalline (µc-Si) silicon [25–27]. Major problems encountered were
antiphase domains and cross doping (GaP), high bulk or contact resistance
(α-Si and poly-β-SiC), and high processing temperature (single crystalline
β-SiC). Moreover, it seems difficult to realize ideal, or at least reproducible,
base currents with these materials [26, 28]. β-SiC can now be grown at
750 ◦ C, greatly improving its prospects for integration into Si HBTs with
narrow and heavily-doped bases.
A key point concerning wide bandgap emitter silicon HBTs is that the
shape of the conduction band barrier in the base is identical to that of an Si
homojunction transistor. It is therefore impossible to obtain improvements
in transit time and output resistance associated with a bandgap grading
between the emitter and collector sides of the base leading to a built-in
drift field for the minority carriers in the base. Some of these structures
may prove useful for special applications. However, in general, these have
not been accepted by the semiconductor industry due to the difficulties in
process optimization and reproducibility.
Although the performance advantages of HBTs over BJTs were well
understood, no fabrication technologies were available to produce high-
quality heterojunctions until the 1970s. The emergence of two new growth
techniques, namely molecular beam epitaxy (MBE) [29] and metal–organic
chemical vapour deposition (MOCVD) [30], sparked a thrust in the research
of high-speed HBTs. Most research has been on the AlGaAs/GaAs
system and related compound semiconductors. The high performance
demonstrated by HBTs is a result of not only the inherent advantages
of heterojunctions, but also the use of semiconductor materials with higher
mobilities and saturated drift velocities. For instance, implementation of an
Alx Ga1−x As/GaAs HBT has yielded the lowest demonstrated gate delay of
Heterojunction bipolar transistors 11
1.9 ps, and an AlInAs/InGaAs HBT has given a unity current gain cut-off
frequency exceeding 200 GHz.
Despite the advances in HBT fabrication techniques, mostly using
group III–V and II–VI materials, silicon devices continue to dominate
due to the low cost and ease of manufacturability. Silicon readily forms
a high-quality oxide which can be used to mask implants, diffusion
and metallization. The isolation technique, chemical vapour deposition,
diffusion, ion implantation, contact technology and etching methods
are highly developed in Si technology. GaAs and the other III–V
semiconductors lack this important property.
It is well known that GaAs or InP technologies exhibit superior fT
and fmax , compared to a SiGe device, for a specified geometry. An
excellent comparison of the technologies has been presented by Konig and
Gruhle [31]. Plots from [31] of both fT and fmax as a function of base
width are shown in figures 1.7 and 1.8. A further performance comparison
of a III–V material HBT with a SiGe HBT has been presented by Larson
[32]. Clearly, if maximum bandwidth or speed is the only criterion, then
Figure 1.7. Comparison of cut-off frequency, fT , as a function of base width

for SiGe HBTs and devices from III–V technologies. (After Konig U and
Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High Speed
Semiconductor Devices and Circuits pp 14–23.)
12 Introduction
Figure 1.8. Comparison of maximum frequency of oscillation as a function of

base width for SiGe HBTs and devices from III–V technologies. (After Konig U
and Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High
Speed Semiconductor Devices and Circuits pp 14–23.)
III–V technology is a superior option. In overall radio frequency (RF)

system performance, including antenna interfacing, low noise and low power
amplifier performance and relatively high levels of integration, SiGe HBT
technology offers significant advantages, as summarized in table 1.1.
Table 1.1. Technology comparison in the frequency range of 1–10 GHz. (After
Temic Semiconductors, Germany.)
Si BJT SiGe HBT GaAs FET

Low-frequency noise + + −
Low RF noise O + +
Low voltage + + O
High gain − + +
High power − + +
High efficiency − + +
Analogue capability O + +
Integration level + + O
Power supply + + −
Development of SiGe/SiGeC HBT technology 13
1.3. DEVELOPMENT OF SIGE/SIGEC HBT TECHNOLOGY
As silicon BJTs reach their fundamental limits on speed because of the

physical properties of the semiconductor material, advanced high-speed
devices require heterojunction technology, as has been demonstrated in
the previous section. Although Ge had made its mark as the point-contact
electrode on the first transistor, Si eventually became the semiconductor
of choice for its material properties. In 1957, Kroemer patented the first
heterojunction Si bipolar transistor and eighteen years later, Erich Kasper
at Daimler–Benz (now Daimler–Chrysler) made the first SiGe strained
layer [33]. With the advent of heteroepitaxy, the concept of strained
layers has been extended to include other elemental semiconductors. These
developments set the stage for IBM’s development of SiGe HBTs in 1987
using MBE. The use of the ultrahigh vacuum chemical vapour deposition
(UHVCVD) tool for HBT and BiCMOS devices followed.
SiGe HBTs are particularly exciting because of their ability to take
immediate advantage of highly developed silicon processing techniques.
Impressive improvements in high-speed SiGe bipolar technology have been
made through the growth of device quality strained-Si1−x Gex layers. This
strain, which occurs because of a ∼4% difference in the lattice constants
of Si and Ge, is used to vary the bandgap energy, band discontinuities
and other properties of the material. For any given Ge content, there
is a critical thickness of SiGe, above which dislocations cause severe
performance degradation, as discussed more fully in chapter 2. The thin
base layer of Si1−x Gex , sandwiched between the Si collector and emitter,
must be thin enough to prevent the formation of these dislocations. Of
additional significance is the enhanced mobility in a strained layer which
offers the possibility of improved performance in SiGe-based FET devices,
as discussed in chapters 6 and 7, although much of this work is still in the
research stage. Higher mobility in digital circuits permits a smaller voltage
swing to switch between states, leading to both faster switching times and
reduced power consumption.
Although the introduction of Ge in the base increases process
integration complexity, it offers an additional degree of freedom which
relaxes a series of trade-offs affecting device design. Several key advantages
over conventional bipolar transistors include:
• reduction in base transit time—resulting in higher frequency

performance;
• increase in collector current density and hence current gain;
• lower intrinsic base resistance; and
• increase in Early voltage.
The design of a SiGe HBT, for a particular technology generation, is

optimized by appropriate scaling of the emitter, base and collector regions
14 Introduction
and their associated doping profiles. A SiGe HBT offers additional design
flexibility in that the bandgap of the base may be tailored by grading
the Ge concentration. Reducing the width of the base region reduces the
base transit time with associated improvement in cut-off frequency, but
inevitably increases overall base resistance with possible reduction in fmax .
For effective design, it is thus essential to use an appropriate simulation
tool. Many of the significant issues have been published in a number of
reports dealing with aspects of both numerical and analytical modelling of
SiGe HBTs [34–41]. In chapters 4 and 5 of this book, we discuss the design
considerations for SiGe HBTs in terms of the following:
• optimization of base, emitter and collector doping profiles;
• effect of Ge profile on the transit times;
• prediction of cut-off frequencies, fT and fmax ; and
• design issues at low temperature.
Since the first report of SiGe HBTs in 1987, there have been numerous
demonstrations (see figure 1.6) of its impressive potential. For example,
an early theoretical study [42] predicted a unity gain cut-off frequency in
excess of 300 GHz. Since then there have been a number of significant
milestones in the measured performance of SiGe HBTs, including fT in
excess of 130 GHz [43], fmax values of 160 GHz [44], ECL and current
model logic (CML) gate delay of less than 10 ps [45–47]. Recently, an
Si/Si0.65 Ge0.35 abrupt SiGe HBT with an fT of 213 GHz and fmax of
115 GHz at 77 K has been reported [48]. Summarized in table 1.2 are some
of the reported results obtained with high-performance SiGe HBTs, which
relate to state-of-the-art performance in commercially available devices.
The addition of substitutional carbon to silicon–germanium thin films
Table 1.2. Some of the commercially available (as of 1998) device results from
various SiGe research groups.
Group IBM IBM
parameter (1996) (BiCMOS) NEC HP Daimler–Benz
fT /fmax 48/60 48/60 60/50 40/– 59/90
(GHz) 113/65
Rbi /Rb 7–9 k 7–9 k – 40k 380–780
(Ohms/square)
Wb 700–1000 700–1000 – 500–600 150
(Å) w/spacers
Ge Profile 0–15% 0–15% 15% 16% 30%
various various graded graded uniform
shapes shapes
Development of SiGe/SiGeC HBT technology 15
leads to a new class of semiconducting materials (SiGeC) [49, 50]. This

new material can remove some of the constraints (such as the critical layer
thickness) on strained-Si1−x Gex and may help to open up new fields of
device applications for heteroepitaxial Si-based systems. The incorporation
of carbon [51] can be used:
• to enhance the SiGe layer properties;
• to obtain layers with new properties; and
• to control dopant diffusion.
A summary of possible applications of C-containing Si and SiGe films
are shown in table 1.3.
The incorporation of a low concentration of carbon (<1020 cm−3 ) in
the SiGe region of SiGe HBTs can suppress boron out-diffusion caused by
subsequent processing steps [52]. This allows one to use higher boron doses
within the SiGe base layer and/or narrower undoped SiGe spacers, leading
to a significantly improved transistor performance. For example, SiGeC
HBTs have demonstrated excellent fT and fmax values [53] comparable to
the performance of state-of-the-art SiGe HBTs, as shown in figure 1.9.
The presence of carbon also relaxes technological process design
constraints by reducing the sensitivity of dopant profiles to subsequent
processing steps. When compared with SiGe technologies, the addition
of carbon offers a significantly greater flexibility in process design
and a greater latitude in processing margins [54–56]. Basic growth
techniques, the mechanical and electrical properties of Si1−x−y Gex Cy layers
Figure 1.9. Cut-off and maximum oscillation frequencies versus collector current
for SiGeC HBTs. (After Osten H J et al 1999 IEEE BCTM Proc. pp 109–16.)
16 Introduction
Table 1.3. Possible applications of C-containing Si and SiGe films. (After

Osten H J et al 1998 Thin Solid Films 321 11–14.)
Material advantages Possible device applications

Increase performance and
process margins for HBTs
Suppress transient enhanced
diffusion of boron
Reduce undoped SiGe spacers HBT
Increase thickness, stability,
Ge content of Si1−x Gex p-Channel FET, npn HBT
Use strained-Si1−y Cy on Si
instead of Si on relaxed buffer n-Channel FET, pnp HBT
Design new buffer concepts
with Si1−x−y Gex Cy
Use the reduction of
dislocation propagation Virtual substrates for hetero-FETs
Strain symmetrization on Si Superlattices on Si(001) for optical
applications
grown pseudomorphically onto Si(001) and their applications have been

comprehensively reviewed by Osten [57].
1.4. HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS
The Semiconductor Industry Association (SIA) roadmap for CMOS

technology predicts that the minimum feature size will approach 10 nm
by 2024. For the most aggressively scaled DRAM, the scale of integration
will reach 64 Gbits in 2010. The slowing of the scaling rate noted in
the roadmap indicates several key technological hurdles that must be
surmounted in order to attain the milestones of the roadmap. These
challenges encompass almost all aspects of device science, processing
and integration architectures including interconnections and patterning
technology.
The field-effect transistor (FET) is customarily a lateral structure,
while the bipolar transistor discussed in the previous section is, in general,
vertical. The first insulated gate field-effect transistor (IGFET) was
demonstrated in 1960, a metal–oxide semiconductor FET (MOSFET)
which uses silicon as the semiconductor and silicon dioxide as the insulator.
A primary reason for the success of this device is the passivating effect that
the silicon dioxide has on the underlying silicon interface. For this reason,
Heterostructure field-effect transistors 17
the most successful IGFETs are still silicon-based MOSFETs. MOSFETs

using an n-channel (i.e., with electrons rather than holes as the charge
carriers between n-type source and drain), are smaller than those of p-MOS
due to the higher electron drift velocity.
Because of the technical difficulty in passivating other semiconductor
materials, other successful FET structures which avoid the need for
passivation have also been proposed. In the metal–semiconductor FET
(MESFET), the insulating layer is replaced with a Schottky contact. The
need for passivation of column III–V semiconductors, such as GaAs, is
circumvented at the expense of substantially larger gate leakage currents.
The high-performance MESFETs are generally n-channel due to the higher
electron drift velocity. In scaling down the classical planar MOS device
towards deep submicron dimensions, the most important technological
limit encountered is the definition of the channel length by lithographic
techniques. From a physical point of view, the short channel effect,
which translates into drain-induced barrier lowering (DIBL) and as such
into threshold voltage roll-off and off-state leakage current, is the most
important limitation.
Heterojunction FETs (HFETs) can be pictured as a hybrid between
the MOSFET and MESFET and are the high performing junction FETs.
Instead of a very wide bandgap oxide, a moderately wide bandgap
semiconductor is used as the insulator. Often this layer is doped with
impurities, but the resulting charge carriers are localized in the narrower
bandgap and therefore lower potential, second semiconductor. Due to the
separation of doping and charge carriers, the resulting FETs are frequently
referred to as modulation-doped field-effect transistors (MODFETs). An
alternative name, high electron mobility transistors (HEMTs) is derived
from the much higher mobilities that result from modulation doping,
since the physically segregated impurities are less effective in scattering
the charge carriers. However, for high-performance short-channel devices
fabricated to date, the mobility plays only a small role, and it is the
saturated drift velocity which determines the channel transit time of an
FET.
In the area of SiGe electronics, the bulk of the effort has concentrated
on HBTs. However, the inherent capabilities of an Si/SiGe heterostructure
can also be applied to create SiGe-based modulation-doped FETs, as
well as being inserted into MOS structures to create heterostructure
complementary metal–oxide semiconductor (HCMOS) transistors, in which
the Schottky gate, used in a MODFET, has been replaced with a MOS-
gate [58].
Typically, n-MODFETs use Si quantum wells (QW), while
p-MODFETs use a SiGe or a Ge QW, with both structures requiring
the growth of a thick SiGe buffer layer. Ismail [59] has reported on
0.4 µm gate length n-MODFETs with a measured peak transconductance
18 Introduction
of 420 mS mm−1 , which is about a factor of two higher than Si

n-MOSFETs. This MODFET exhibited an fT and fmax of 33 and
40 GHz, respectively. Introduction of the graded SiGe buffers dramatically
increases two-dimensional electron gas (2DEG) mobility values as high as
180 000 cm2 V−1 s−1 at low temperature for n-MODFETs. However, what
is more important for device applications is room temperature mobility,
which is found to range from 1000 to 3000 cm2 V−1 s−1 —a factor of four
to six times greater than for Si-only MOSFETs. A 0.7 µm gate length
SiGe p-MODFET has shown peak transconductance of 200 mS mm−1 ,
while similar transconductance values for Si-only p-MOSFETs can only be
achieved with gate lengths reduced to 0.2 µm or below. The p-MODFETs
exhibited an fT and fmax of 10 and 18 GHz, respectively, along with
room temperature mobilities of 1400–1800 cm2 V−1 s−1 —a factor of six
to nine times those above standard p-MOSFETs with comparable doping.
Simulation studies on the performance of complementary MODFET
structures predict, for a 0.1 µm gate length device, peak transconductance
of 820 mS mm−1 for an n-MODFET, and 610 mS mm−1 for a p-MODFET,
comparable to the performance achievable with III–V-based materials.
The application of strained-SiGe layers to FETs is not as well
developed as HBT applications. A fundamental limitation has been that
strained-SiGe enhances the mobility of holes but not electrons. Thus,
the current drive of p-FET devices is improved, but not that of n-FETs.
However, strained-Si grown on a relaxed-SiGe layer improves electron
mobility and n-FET device performance. Techniques for forming high-
quality relaxed-SiGe on Si substrates have demonstrated performance
improvements for both n- and p-HFETs [60–62].
Hartmann et al [63] have proposed that SiGeC alloys may offer
an increased leverage in CMOS technology, just as SiGe has increased
the performance of bipolar technology. It has been shown that both
electron and hole confinement appear possible without the need of relaxed
buffer layers, making the SiGeC alloy a potential for CMOS technology.
Recently, Quinones et al [64] have presented the evaluation of the strain-
stabilizing capabilities of C in the SiGe material system by fabricating
SiGeC heterojunction p-MOSFETs over a range of Ge concentrations.
Several excellent reviews on the possibilities and potential of the SiGe-
channel MOSFETs for a submicron CMOS technology have also appeared
[65–67].
1.5. VERTICAL HETEROSTRUCTURE FETS
Vertical MOS structures are being explored for increasing the integration
density and for incorporation of quantum effects into MOS devices.
Vertical MOS heterostructures are expected to solve the scaling issues
of lithography, doping confinement and DIBL. Vertical devices will have
Vertical heterostructure FETs 19
small contact areas and will facilitate interconnects and minimize the via
contacts leading to a minimization of the area per function. Present
projections, based on the operation of a 20 nm channel length vertical
device at room temperature, result in an on-current of 20 000 µA µm−1 ,
an off-state current less than 1 pA µm−2 , a peak transconductance of more
than 3500 mS mm−1 , a VT of less than 0.3 V at VDD of 1 V and an intrinsic
carrier transit time of less than 1 ps.
In establishing its potential advantages and assessing its performance
with respect to conventional transistors, a technology which provides
denser and faster structures, and uses the standard processing technology
and production equipment, research has been initiated. In fact, the
SiGe technology has been implemented in the Si process lines by several
manufacturers and is expected to facilitate a low-cost transfer of the new
vertical SiGe heterostructure MOS into production. In addition, a CMOS
possibility also exists if the heterojunction is made by a SiGe/Si(p-MOS)
or SiGe/Ge(n-MOS) combination. All these materials are compatible with
Si technology and allow for an easy integration into production.
A vertical heterostructure MOS (VHMOS) has the following
advantages.
• The device is not a lateral but a vertical one; source/channel and
drain regions are grown epitaxially. As such the device channel
length is defined by the channel layer epitaxial growth and thus fully
decoupled from lithographic limitations. Therefore, much shorter
channel lengths (down to 20 nm) become feasible.
• At the source side of the device, a heterojunction is used which keeps
the barrier for conduction in the off-state constant and not affected
by the drain voltage. In order to have conduction in the on-state,
the source side closest to the channel region is intrinsic. This allows
for Fermi-level modulation by the action of the overlapping gate and
thus conduction. The DIBL effect no longer exists [68].
The experimental evidence of the enhancement of out-of-plane hole
mobility in SiGe using a vertical p-MOSFET structure, fabricated by
high-dose Ge implantation followed by solid phase recrystallization, has
been reported [69]. The structure combines the merits of a very short
channel device without a critical lithography process and a higher hole
mobility in the channel region. Superior performance with respect to
a homojunction structure has been demonstrated, especially for deep
submicron dimensions. Although the p-MOS devices have been reported
so far, similar work is being performed on n-MOS devices with strained-
Si/SiGe in the source/channel and drain regions. However, in this case, a
virtual substrate consisting of a relaxed-SiGe layer is needed [68, 70].
Up to this point, we have described the major application areas where
SiGe technology has become established. However, there are a number of
20 Introduction
other application areas in which SiGe devices may have a role to play.
Bipolar inversion channel field-effect transistors (BICFETs) have been
studied extensively theoretically [71] as well as experimentally in SiGe
materials [72–74]. Taft and Plummer [71] implemented the concept in
the SiGe material system in order to take advantage of the established
Si technology and showed that the SiGe BICFET could potentially fulfil
both the ends: high performance (due to its intrinsic speed advantage) and
manufacturability (due to the lower costs of silicon processing). Kasper
and Reitemann [75] have explored the idea of a common device structure
for different functions by combining a SiGe HBT and a charge injection
transistor (CHINT) on Si–SiGe–Si–SiGe [76]. It is a hot electron device;
VDS accelerates the carriers, which cross the SiGe–Si barrier to be collected
at the real space transfer output as stated.
1.6. OPTOELECTRONIC DEVICES
The optoelectronics realm has traditionally been reserved to III–V

and II–VI compound semiconductors, due to the availability of direct
transitions and heterostructures. However, the introduction of SiGe allows
heterostructures to be fabricated in traditional Si-only technologies, which
expands the potential of Si optoelectronics. A conceptual integrated silicon
chip of the future including CMOS, HBT/bipolar, SiGe quantum devices,
SiGe detectors, SiGe waveguides and light emitter all on a chip is shown
in figure 1.10. Integrated optoelectronics is another promising research
Figure 1.10. The integrated silicon chip of the future: CMOS, HBT/bipolar,
SiGe quantum devices, SiGe detectors, SiGe waveguides and light emitter all on
a chip. (After Paul D J 1998 Thin Solid Films 321 172–80.)
Applications of SiGe HBTs 21
field for SiGe devices, although development is hindered by the lack of a

SiGe light emitter. Detectors and waveguides have been demonstrated, and
integrated SiGe and Si devices are possible.
Si-based heterostructures, such as Si/SiGe, offer the possibility of
improving the standard Si device performances, particularly in high-
frequency and low-noise applications, with the additional advantage of
still being compatible with mainstream Si technology. Furthermore, SiGe
microstructures can also enable the integration of optical devices (LEDs
and photodiodes) with silicon-based integrated circuits.
Research has been initiated on a graded buffer layer of SiGe—a virtual
substrate—that would permit III–V/SiGe/Si integration and open the door
for integrated optoelectronics [77]. The growth of device quality GaAs
epitaxial layers on Si substrates is a long-range goal of electronic materials
research. The epitaxial growth of GaAs on Si substrates through the use of
a Ge/graded-Si1−x Gex /Si buffer layer would allow monolithic integration
of GaAs-based optoelectronics with Si microelectronics [78].
1.7. APPLICATIONS OF SIGE HBTS
The revolution in wireless communications has been brought about by

a combination of advances in digital integrated circuit technology, RF
components, digital communications and networking techniques [79]. RF
communication systems can be broadly categorized in two market sectors,
namely, ‘low-end’ such as pagers, cordless phones etc, and ‘high-end’
such as personal communication service (PCS), GSM, IS-136 etc. SiGe
HBTs are suitable for applications in the high-end applications where
the best performance is essential, while CMOS technology will dominate
the low-end applications. Several excellent reviews of research in wireless
communications systems presently in use may be found in [32, 80, 81].
Figure 1.11 shows the present wireless system trends. The vertical
axis is a measure of mobility, and the horizontal axis is the information
rate. Analogue cellular systems are called first generation systems, and
the present digital cellular and digital cordless systems are called second
generation systems. The third generation systems, however, only represent
a midpoint in the planned development of mobile communication systems.
Fourth generation systems will provide high bit rates of more than 2 Mbps
under high mobility conditions.
The sell-off of rights to the spectrum by the US Federal
Communications Commission is creating a large market opportunity for
SiGe in the USA, while the same trend is occurring elsewhere in the world.
Components for PCS devices operating between 1.8–2.2 GHz are a fast
growing market segment, along with pagers, beepers and wireless local
area networks. The implementation of a complete RF integrated circuit on
a single silicon chip is a complicated task, as wireless circuits have a very
22 Introduction
Figure 1.11. Wireless system trends. (After Muraguchi M 1999 Solid-State

Electron. 43 1591–8.)
Figure 1.12. Selected high-frequency applications and allocated frequency

bands between 1 and 100 GHz. The three market segments labelled
communication, traffic and navigation will drastically expand in the next few
years, mainly in the range up to about 10 GHz. (After Schaffler F 1998 Thin
Solid Films 321 1–10.)
Applications of SiGe HBTs 23
broad range of requirements including noise figure, linearity, gain, phase

noise and power dissipation. The advantages and disadvantages of each
of the competing technologies Si CMOS, BJTs, Si/SiGe HBTs and GaAs
MESFETs, HEMTs and HBTs have been examined by Larson in the light
of these requirements [79].
Wireless communication systems require very high efficiency power
amplifiers to extend battery life, simplify thermal design, and reduce the
cost of handheld phones. In order to serve this new high volume market,
faster and more powerful integrated circuit chips are required. For many
of these applications, as shown in figure 1.12, all-silicon transistors have
been pushed to the 1–2 GHz frequency domain. However, many new
Table 1.4. Summary of several circuits reported in the literature using SiGe
HBT technology.
Reference Circuit type Results

[10] Transceiver complete chip
[82] Limiting amplifier 60 dB Gain
55 dB dynamic range 10 Gb s−1
[83] Optical receiver 40 Gb s−1 analogue IC
[84] Mixer Conversion loss 6.5 dB,
LO power 10 dBm
1/f noise corner frequency 3 kHz, 1 mA
[85] Radio transceiver 900/1900 MHz, 2.7 V
[86] 6.25 GHz LNA NF 2.2 dB, gain 20.4 dB
Dissipation 9.4 mW, 2.5 V supply
[87] 1.88 GHz power amplifier Power gain 16 dB, PAE 53%
[88] ECL inverter chain 16 ps/stage, 660 µA @ 3.3 V
[88] 2.4 GHz downconverter LNA: gain 10.5 dB
(LNA + mixer) NF 0.95 dB
Mixer: +4 dBm
input intercept 5 mA @ 1 V (total)
[88] Broadband amp Gain 8 dB
Bandwidth 17 GHz
16.8 mA @ 2.5 V
[89] 12 GHz VCO 19 dBm, 5% tuning range,
−80 dBc Hz−1 phase noise
[89] 12 GHz active mixer >0 dB gain @ +3 dBm LO,
100 KHz IF BW, 30 dB isolation
[89] 12 GHz power amp >6 dB gain, 19 dBm output
[90] 1/128 frequency divider 6.4–23 GHz, 1.5 W
[91] RZ comparator 5 GHz, 1.5 V, 89 mW
[92] Gilbert mixer Bandwidth 12 GHz GBW >22 GHz
[93] 12-bit DAC 1.2 Gsps, 750 mW
24 Introduction
RF applications require circuit operation at frequencies up to 30 GHz,

a regime well out of the realm of devices based solely on Si. A number
of circuit designs have been fabricated in SiGe technology in order to
demonstrate its capability in the RF marketplace. Among the circuits
that have been reported are: voltage controlled oscillators (VCOs), low-
noise amplifiers (LNAs), power amplifiers (PAs), mixers and digital delay
lines. Several reported circuit results are presented in table 1.4, and a more
comprehensive survey is included in chapter 10.
An exciting example of a communications application is the 10 Gbps
data transmission system designed by Alcatel using advanced IBM SiGe
technology [94]. In this system, SiGe technology has made a significant
contribution toward the implementation of a cost effective transmission on
a standard optical fibre, offering operators the advantage of upgrading their
existing networks to terabit speed, without the time and cost of laying new
cables.
Table 1.5. List of devices available in the SiGe BiCMOS technology. The main
characteristics are provided for each device which are available to the designers
to make a full custom design. (After Brenner et al 1999 IBM MicroNews 5 1–4.)
Device Parameter
1 npn SiGe HBT fT = 47 GHz
fmax = 65 GHz
2 npn Higher breakdown SiGe HBT
fT = 27 GHz, fmax = 55 GHz
3 n-FET ID,sat = 485µA/µm
Leff min=0.39 µm
4 p-FET ID,sat = 213µA/µm
Leff min=0.39 µm
5 Gated lateral pnp β = 107, VA = 67 V
6 Spiral inductor L = 10 nH, Q = 6 at 1 GHz
7 Varactor 1.4 fF µm−2
8 Schottky barrier diode Vf = 0.31 V @ 100 µA for 5 × 5 µm
9 Substrate contact 330 Ωs (p+ subs.) for 2 × 10 µm
10 Polysilicon resistor (RP) 220 Ω/square
11 Polysilicon resistor (XN) 340 Ω/square
12 Reach-through implant resistor (RN) 23.5 Ω/square
13 n+ -subcollector resistor (RS) 8 Ω/square
14 Ion implanted resistor (RI) 1750 Ω/square
15 Metal–insulator–metal capacitor 0.7 fF µm−2
16 Decoupling capacitor 1.5 fF µm−2
17 p–i–n diode 6 Ω for a 2 × 10 µm
18 ESD protective device 2000 V HBM
Summary 25
An excellent review of the application-driven origins of SiGe

technology, how it has evolved and how the limitations of conventional
silicon bipolar scaling have enhanced its adoption in the semiconductor
industry, has been written by Meyerson [95]. This review demonstrates
that SiGe HBTs are superior to Si BJTs and comparable to the best
GaAs transistors and ideally suited for low-voltage and low-power wireless
communication applications. In some aspects, such as low noise and low
power consumption, SiGe HBTs have advantages over III–V HBTs, and
approach the performance of some HEMTs, at least below 10 GHz.
So far, Si BJT performance has been the main barrier for silicon
to penetrate wireless RF front-ends. While SiGe HBTs have removed
the barrier, RF isolation and system cost issues still remain. Since
silicon substrates are conductive, it is not practical to build high-quality
passive elements on-chip. However, much of the cost in current RF
systems using discrete components comes from the passive elements. In
addition to the SiGe HBT, recent progress in passive component design
on silicon substrates, listed in table 1.5, now gives the RF designers a rich
environment to realize applications for the wireless marketplace.
1.8. SUMMARY
This introductory chapter has described the evolution of SiGe technology

from early materials research to its current established position in
the marketplace. The evolution of bipolar technology has led to the
development and application of a SiGe transistor through utilization of
strained layers. SiGe HBT technology has the potential to revolutionize
high-frequency transceiver design in a way comparable to the revolution
in digital integrated circuit technology brought about by CMOS. Its
unique combination of outstanding high-frequency performance, low
manufacturing cost and high yield will provide abundant opportunities for
new architectures and new systems in the near future. Subsequent chapters
in this book describe the basis of SiGe technology in much more detail.
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30 Introduction
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[83] Masuda T, Ohhata K, Oda K, Tanabe M, Shimamoto H, Onai T and
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[89] Larson L, Case M, Rosenbaum S, Rensch D, Macdonald P, Matloubian M,
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[90] Case M, Knorr S, Larson L, Rensch D, Harame D, Meyerson B and
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[91] Gao W, Snelgrove W M, Varelas T, Kovacic S J and Harame D L 1995 A
5 GHz SiGe HBT return-to-zero comparator IEEE BCTM Proc. pp 166–9
[92] Glenn J, Case M, Harame D and Meyerson B 1995 12 GHz Gilbert mixers
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[93] Harame D L, Schonenberg K, Gilbert M, Nguyen-Ngoc D, Malinowski J,
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[94] Brenner T, Wedding B and Coene B 1999 Alcatel’s revolutionary 10 Gbps
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[95] Meyerson B S 2000 Silicon:germanium-based mixed-signal technology for
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44 391–407
Chapter 2
FILM GROWTH AND MATERIAL

PARAMETERS
Silicon-based heterostructures have come a long way from the use of

strain as a parameter for bandgap engineering, to the present state of
devices/circuits with enhanced performance compared to those obtained
in bulk-Si and competing III–V compound semiconductors. Apart from
the inherent performance enhancement, undoubtedly the main attraction
of high mobility Si/SiGe, SiGe/strained-Si and Si/SiGeC heterostructures
is their basic compatibility with standard Si processing. For any material,
issues important to the device designer include bandgap difference, band
alignments and mobility. The first two properties determine the class of
devices that can be fabricated. For example, quantum confinement of
electrons cannot occur without a conduction band discontinuity.
It is the purpose of this chapter to consider the recent developments in
growth techniques and the performance levels achieved to date in group IV
alloy systems, to address the problems related with film development and
process integration and to discuss alternative routes that could circumvent
the use of strain adjusting epilayers, which are presently the bottleneck
for an introduction of these promising materials (such as strained-Si and
SiGeC) into a production environment. We shall discuss various growth
and doping techniques and strain-induced material properties of different
group IV alloy layers. The electronic properties of Si/SiGe, Si/SiGeC and
strained-Si films will be presented.
Semiconductor heterostructure devices rely on the differences in the
electronic bandstructure of the two semiconductors used to fabricate a
device. In the beginning of heterostructure devices, the emphasis was on
finding a pair of semiconductors with different bandgaps but with nearly
the same lattice constants. This was necessary so that a good epilayer
of one semiconductor could be grown on the other. In lattice matched
heterostructures, one can obtain an interface of high quality without
32
Strained layer epitaxy 33
defects, so that as a free carrier approaches a heterostructure boundary,

it would be influenced only by the potential gradients and is not trapped
or artificially scattered at the heterostructure boundary.
Heterostructures based on column III–V and II–VI compound
semiconductors, such as AlAs and GaAs, can be easily fabricated
since there are direct structural and chemical matches among these
semiconductors. On the other hand, for silicon-based heterostructures this
is not the case as silicon has no natural semiconductor partner with respect
to the configuration of its atomic lattice and chemistry, although silicon
and germanium are completely miscible over the entire compositional
range and give rise to alloys with a diamond crystal structure. At room
temperature, the lattice constants for silicon and germanium are 5.43 Å and
5.65 Å, respectively, leading to a 4.2% lattice mismatch. Clearly, the large
mismatch between silicon and germanium precludes depositing epitaxial
germanium directly on silicon. The miscibility of silicon and germanium,
however, allows deposition of epitaxial Si1−x Gex , without adhering to
stoichiometric ratios, on silicon. As a result, the lattice mismatch between
silicon and Si1−x Gex is lessened. Because a significant lattice mismatch
still exists, Si1−x Gex on silicon can range from a fully strained to a fully
relaxed state. Normal heterostructures of Si and Ge thus grow with high
dislocation densities that were believed to be incompatible with most device
applications. In the early 1980s, however, the situation changed when it
was demonstrated that by utilizing strained layer epitaxy, defects could
be eliminated in thin silicon-based heterostructures. In strained alloys
of Si and Ge, Si1−x Gex , it was found that heterostructure effects were
much stronger than expected, making them very attractive for device
applications.
2.1. STRAINED LAYER EPITAXY
Before we discuss the deposition and properties of strained layers, we

briefly discuss the properties of the relevant bulk materials as given in
table 2.1. Ge has been known to be produced with extremely poor impurity
concentrations and large mobilities with both p- and n-type conductivity.
Both the n- and p-type high-quality Ge samples exhibit mobilities of about
2 000 000 cm2 V−1 s−1 at about 4 K. On the other hand, high-purity Si
exhibits electron mobilities slightly in excess of 500 000 cm2 V−1 s−1 at
4 K.
As the atomic spacing of germanium is 4.2% larger than that of silicon,
when the first few atomic layers of Ge are deposited, it is energetically
desirable that they maintain full bonding with the silicon by compressing
together. In the fully strained case, the larger Si1−x Gex horizontal lattice
compresses to match the silicon substrate and the Si1−x Gex vertical lattice
constant expands to accommodate the horizontal compression as shown
34 Film growth and material parameters
Table 2.1. Room-temperature materials data of selected group IV elements.

Element C Si Ge α–Sn
Lattice Diamond Diamond Diamond Diamond
Lattice constant, ao (Å) 3.5668 5.431 5.657 6.489
Density, g cm−3 3.515 2.329 5.323 7.285
TCE, α (10−6 K−1 ) 1.0 2.56 5.9 4.7
Bandgap, Eg (eV) 5.48 1.11 0.664 –
Dielectric constant, 5.7 11.9 16.2 24
Electron mobility,
1800 1450 3900 1400
µe (cm2 V−1 s−1 )
Hole mobility,
1600 450 1900 1200
µh (cm2 V−1 s−1 )
Effective mass m∗
Electron, m∗e (⊥) – 0.19 0.08 0.024
Electron, m∗e () – 0.92 0.64 0.2–0.45
Light-hole, m∗h (l) 0.7 0.15 0.043 –
Heavy-hole, m∗h (h) 2.18 0.54 0.28–0.38 –
Figure 2.1. A schematic diagram of strained-Si1−x Gex crystal lattices

illustrating two types of strain. In both cases, the epitaxial film is constrained
by the substrate along two axes, as indicated by the arrows.
in figure 2.1. The higher energy state of strained-Si1−x Gex is sustained

because the activation energy for the dislocation formation has not been
reached. Since the Si substrate lattice is both much thicker and stiffer, it
remains essentially undistorted. The growth of Si1−x Gex on silicon begins
as a strained layer, but when the thickness or germanium concentration
of the layer exceeds a critical value, the layer relaxes. Since the lattice
www.ebook3000.com
Figure 2.2. Lattice constant for an Si1−x Gex alloy as a function of x. Vegard’s
law is a linear interpolation between aSi and aGe .
constants of Si1−x Gex alloys are larger than that of Si, pseudomorphic
Si1−x Gex layers grown on silicon have biaxial in-plane compression of the
alloy and an extension normal to the interface. If layers are grown on a
germanium substrate the reverse is the case. In both cases the layers suffer
a tetragonal distortion.
In fully relaxed Si1−x Gex on silicon, the lattice constant returns
to the bulk value. The lattice constants of bulk-Si1−x Gex alloys have
been measured and the results obey Vegard’s law to a very good
approximation. Assuming Vegard’s law applies, the bulk-Si1−x Gex lattice
constant (aSi1−x Gex ) is a function of the silicon and germanium lattice
constants (aSi and aGe ) and the mole fraction of germanium, x in
equation (2.1). The lattice constant of Si1−x Gex alloys varies linearly, as
shown in figure 2.2 obeying Vegard’s rule:
a(Si1−x Gex ) = aSi + x(aGe − aSi ). (2.1)
Due to the relatively large lattice mismatch between SiGe and silicon,
commensurate (defect-free) SiGe alloy films cannot be grown on silicon
substrates without introducing large amounts of strain.
As the thickness of the SiGe layer increases, so does the integrated
strain energy and at some point this configuration will reach a thickness,
which is known as the ‘critical layer thickness’, beyond which the total
energy becomes larger and results in ‘misfit dislocations’ or periodic arrays
of incompletely bonded atom rows. Misfit or threading dislocations appear
at the interface in both the relaxed and partially relaxed cases. Threading
dislocations affect the heterojunction by acting as a pathway for enhanced
dopant diffusion. This leads to increased junction leakage current. Misfit

dislocations located inside a heterojunction depletion region result in
an increased space-charge layer recombination and generation current.
For most device applications, dislocations are deleterious and should be
avoided.
Since the dangling bond can become a trap or leakage site, such
dislocations must be avoided within the active volume of a heterostructure
device. This implies that active device areas must not lie at the interface
of the Si1−x Gex and Si layers. This is possible in certain devices but,
unfortunately, there are also segments of dislocations that thread from the
heterostructure interface up to the surface of the crystal. A number of
strategies have been suggested to minimize the impact of such threading
dislocations [1].
The first possibility is extending the dislocation plane either to the edge
of the wafer or at least to the boundary of a device die where threading
dislocations would be irrelevant. Alternating thin layers can also be grown
so that dislocations do not form and instead the atomic spacings of one or
both materials shift to accommodate one another. This occurs naturally
in very thin layers (e.g., 10–100 atoms thick) and can persist in much
thicker layers (100–1000 layers) if a low-temperature growth technique is
used, where dislocations do not have enough energy to form and grow.
In some recent applications, however, the use of thick relaxed-Si1−x Gex
layers as a starting substrate for strained silicon (strained-Si) deposition
has been made. Relaxed-Si1−x Gex layers can be grown thick enough to
cause threading dislocations to loop around. As a result, the surface is
nearly defect-free. Alternating layers of silicon and Si1−x Gex may also be
used to filter out threading dislocations.
Contrary to the simplistic view given above, the transition from the
strained to the relaxed case is not abrupt and is not clearly defined. Varying
degrees of strain relaxation can exist [2]. Figure 2.3 shows three regimes
(stable, metastable and relaxed) in the plot of Si1−x Gex layer thickness on
silicon versus germanium mole fraction. The germanium concentration is
directly related to the lattice mismatch according to Vegard’s law. The
term ‘critical thickness’ was initially defined to denote the transition from
a strained to a relaxed-Si1−x Gex layer. Van der Merwe [3, 4] calculated
the critical thickness as a function of increased lattice mismatch, by
minimizing the sum of the interfacial and strain energy. However, most
of the published literature accepted the mechanical equilibrium theory of
Matthews and Blakeslee [5, 6] as defining the transition from the stable to
metastable regimes. Mechanical equilibrium theory assumes the existence
of a threading dislocation. The energy required to glide a threading
dislocation into a misfit dislocation is balanced with the strain energy from
the lattice mismatch to define the critical thickness as a function of lattice
mismatch. When the strain energy exceeds the misfit dislocation forms to
Figure 2.3. Critical layer thickness versus Ge content showing stable, metastable
and relaxed ranges of Si1−x Gex layers on Si. (After Schuppen A et al 1995
J. Mater. Sci., Mater. Electron. 6 298–305.)
relieve the strain energy. A simplified Matthews–Blakeslee critical thickness

calculation (hc ) where angular dependences have been ignored [7], is given
by equation (2.2)
1 b hc
hc ln +1 (2.2)
f 4π(1 + ν) b
where ν is Poisson’s ratio (0.3), b is the slip distance (0.4 nm), f is the
mismatch between the film and substrate and for Si1−x Gex on silicon, f is
0.042x. For a detailed derivation of the critical thickness, the reader may
refer to an excellent review by Jain and Hayes [8].
Although the Matthews–Blakeslee equilibrium theory is widely cited,
strained-Si1−x Gex layers have been deposited much thicker than the theory
predicts. Bean et al [9] deposited strained layers by molecular beam epitaxy
at 550 ◦ C with the thickness an order of magnitude or more above the
Matthews–Blakeslee curve, as shown by the solid curve in figure 2.3. The
dashed curve demarcates the metastable and dislocation regimes. Above
the dashed curve, strained-Si1−x Gex layers were impossible to deposit.
Between the solid mechanical equilibrium curve and the dashed curve,
the layers are labelled metastable. Layers in the metastable regime are
strained, even though the layers are above the Matthews–Blakeslee critical
thickness. However, metastable layers relax with subsequent annealing.
People and Bean sought to reconcile these differences by including
the kinetics of relaxation in their calculation [10]. Their critical thickness
prediction fits their data, but their theory has not been widely accepted
by other researchers. Many other researchers have also contributed with
critical thickness theories based on energy, mechanical equilibrium and
kinetics of dislocations [11–13]. The critical thickness theories based
on dislocation formation are disputed by some researchers because other
factors, such as wafer preparation and particulate contamination, may play
a much larger role in determining misfit dislocations [14]. Furthermore,
methods for determining whether a layer is strained or relaxed may not
have enough sensitivity to detect the onset of dislocation formation [15].
As a result, dislocation techniques with poor resolution overestimate the
critical thickness. Determination of the critical thickness curve depends on
the deposition methods and characterization methods used. Nonetheless,
most researchers concur that the Matthews–Blakeslee equilibrium curve
distinguishes the point where strained-Si1−x Gex layers cannot sustain
extended thermal processing.
When a thin film with a larger lattice constant (e.g., Si1−x Gex )
is grown on a smaller lattice constant substrate (e.g., silicon), the film
maintains an in-plane lattice constant of the substrate and is under
a biaxially compressive strain. Since layer sequences with well-defined
electrical and optical properties require coherence of the in-plane lattice
constant, biaxial strain is always present in such heterostructures. This
asymmetry of the strain with respect to the (001) growth direction leads
to a splitting of the sixfold degenerate conduction band and also of the
heavy-hole/light-hole valence band degeneracy. The band ordering in this
heterosystem is therefore strongly strain dependent, and a type I band
alignment is obtained where the entire band offset occurs in the valence
band (figure 2.4(a)) while the band offset in the conduction band is very
small. This type of structure is favourable for hole confinement and has
been exploited in several novel heterostructure devices, namely buried
channel p-MOSFETs, p-MODFETs and HBTs (see for example, a review
by Konig and Daembkes [16]).
Similarly, a smaller lattice constant silicon epilayer (strained-Si) will
be under biaxial tension when grown on a larger lattice constant relaxed-
Si1−x Gex substrate. In this case, type II band offset occurs (figure 2.4(b))
and the structure has several advantages over the more common type I
band alignment. A large band offset is obtained in both the conduction
and valence bands, relative to the relaxed-Si1−x Gex layer [7]. This allows
both electron and hole confinements in the strained-Si layer, making it
useful for both n- and p-type devices for strained-Si/SiGe-based CMOS
technology. The ability to achieve both n-MOS and p-MOS devices
Figure 2.4. Band alignments for (a) Si0.8 Ge0.2 on (001)Si, (b) strained-Si
on (100)Si0.8 Ge0.2 and (c) Si0.6 Ge0.4 /Si heterostructure on (001)Si0.8 Ge0.2
substrates.
using strained-Si provides a promising alternative for next generation

high-performance SiGe CMOS technology (see for example, reviews by
Maiti et al [17] and Schaffler [18] and references therein). Since strained-
Si provides both larger conduction and valence band offsets and does not
suffer from alloy scattering, a significant improvement in carrier mobility
can be achieved. However, strained-Si is more difficult to grow compared
to strained-Si1−x Gex , as the growth of thick relaxed-Si1−x Gex is difficult
without forming a large concentration of defects due to dislocation, and a
total thickness of several microns leads to non-planarity, high defect density
and surface roughness.
To fully exploit strain as an additional parameter for bandgap

engineering, it is necessary to have substrates available that provide the
desired in-plane lattice constant for the subsequent pseudomorphic layers.
For this purpose, strain-relaxed SiGe buffer layers on an Si substrate are
used. In an effort to extend the Si1−x Gex strained layer technology and to
search for new materials, experimental work on Si1−x Cx and Si1−x−y Gex Cy
alloys was started in the early 1990s and recently on Ge1−y Cy alloys.
A different concept for strain adjustment has been suggested by adding
carbon into the Si/SiGe material system [19, 20] indicating that the
addition of carbon is a promising way for new relaxed buffer concepts with
low threading dislocation densities. As the lattice parameter of carbon
(3.546 Å) is much smaller than that of Si and Ge, C may be used as a
substitutional impurity in the SiGe to decrease the lattice mismatch of
the SiGe system. In the case of a ternary alloy such as Si1−x−y Gex Cy ,
assuming Vegard’s law and for a fully relaxed film, the lattice parameter
can be written as
aSiGeC = aSi + x (aGe − aSi ) + y(aC − aSi ) (2.3)
where ai is the lattice parameter of the ith component. The third term
being negative, it is possible to adjust composition of the alloy to cancel
the second and third term leading to an alloy with exactly the Si lattice
parameter (i.e., zero net strain). According to equation (2.3), for about
12% Ge in Si and 1% C in silicon, the mismatch is equal and opposite and
a strain symmetrized structure with average zero strain may be obtained.
Addition of substitutional carbon to the Si1−x Gex material system
can provide an additional design parameter in band structure engineering
on Si substrates. Since large bandgap variations from 5.5 eV (diamond)
to 0.66 eV (Ge) exist, the Si1−x−y Gex Cy system may result in an
increase in the bandgap to values greater than those of SiGe and Si,
in addition to other interesting properties such as the highest known
thermal conductivity (diamond), high hole mobility (Ge) and matured
processing technology (Si). The incorporation of C, however, presents
difficult challenges due to the large lattice mismatch between C and Si, low
solubility of carbon in Si and silicon carbide precipitation. Attempts have
been made to form strained layers on Si or Ge substrates containing Sn as a
constituent. Synthesis of dislocation-free Siy (Snx C1−x )1−y [21] and growth
of quaternary Si1−x−y−z Gex Cy Snz alloy have also been announced [22].
For the last few years, experimental studies on strained-SiGe materials
have resulted in a significant progress in the understanding of strain
relaxation kinetics and optimization of graded buffer layers with respect
to relaxation and surface morphology [23–27]. These parameters are
of crucial importance as they are interdependent and are affected by
growth temperature, grading rate and composition. It appears that the
competition between dislocation nucleation and propagation determines
Figure 2.5. Cross-sectional transmission electron micrograph and secondary ion

mass spectrometry profile of a graded SiGe buffer layer on an Si substrate. (After
Schaffler F 1998 Thin Solid Films 321 1–10.)
the final threading dislocation density in the film. The compositional

grading is believed to promote propagation while suppressing nucleation
of dislocations and leading to reduced amounts of surface strain, thus
allowing higher growth temperature [28,29]. Figure 2.5 shows the secondary
ion mass spectrometry (SIMS) profile together with a cross-sectional
transmission electron micrograph (TEM) micrograph of a graded SiGe
buffer layer grown at 750 ◦ C by MBE. It is interesting to note that,
close to the substrate interface, the misfit dislocation segments appear
quite irregular with respect to spacing and length, whereas long-stretched
misfits can be observed in the upper part of B1. B2 remains free of misfit
dislocations, as expected, because once B1 is fully relaxed, B2 becomes
strain-free. In fact, the use of a compositionally graded, relaxed, Si1−x Gex

buffer layer has been advocated as ‘virtual substrate’ and allows the strain
in the film to be tailored at will. (For a detailed discussion on strain
adjustment in SiGe buffer layers see, for example, excellent reviews by
Schaffler [18, 30].)
In the following sections, we discuss the technology of growth of
SiGe, SiGeC and strained-Si films. Only a brief review is given for well-
established results, and readers are referred to the original publications
for more detail. We shall examine the deposition of heteroepitaxial films
using various reactors in greater depth. As the reactor configurations differ
substantially, the advantages and disadvantages of each system are also
compared. For a detailed discussion, the reader may refer to a review by
Maiti et al [31].
2.2. DEPOSITION TECHNIQUES
Many methods exist for depositing low-temperature silicon and Si1−x Gex
on silicon. These can be broadly categorized into physical deposition and
chemical vapour deposition (CVD) methods. To cope with the difficulties of
growing SiGe alloys, molecular beam epitaxy was used at first to produce
thin, device quality films. MBE is a physical vapour deposition method
and is mostly used for the deposition of III–V compound semiconductors
because of the excellent control of layers. Pioneering studies in the mid-
1980s at AT&T Bell Laboratories, IBM Thomas J Watson Research Center
and Daimler–Benz Research Laboratories, Germany, British Telecom, UK,
Hitachi and NEC, Japan, among others, used molecular beam epitaxy
to show that SiGe alloys could be bandgap-engineered controllably and
successfully used to realize a host of novel electronic and photonic devices.
MBE allows the fabrication of moderately defect-free heterojunctions.
However, MBE not being a production tool, they are only used for
demonstration devices.
On the CVD side, Gibbons et al [32] at Stanford were one of the
first groups to demonstrate high-quality Si1−x Gex on silicon. Towards
commercialization of SiGe technology, the development of UHVCVD by
Meyerson et al [33] at IBM has been a key step forward which appeared
at nearly the same time in the mid-1980s as limited reaction processing
CVD (LRPCVD). The UHVCVD reactor combines a standard diffusion
furnace with an ultrahigh vacuum and has made the most significant
impact in the fabrication of Si/Si1−x Gex HBTs. An excellent review of
this technique, and of the devices fabricated using this method of growth,
has been published [34]. Other CVD techniques have also been used to
grow device quality SiGe layers [35]. Results of Si1−x Gex film depositions
at atmospheric pressure CVD by ASM, the only commercial entry in the
late 1980s, have been published. These atmospheric CVD results may
Deposition techniques 43
be the most promising for widespread application of Si1−x Gex on silicon

heterostructures in a production environment.
In the following, we briefly discuss several reactors, the wafer cleaning
method, reactor kinetics such as Ge incorporation control, dopant control
and selective deposition, and compare the performances of various reactors.
Focus is placed on systems that have successfully demonstrated devices and
the discussion of the reactors proceeds in order of increasing base pressure.
2.2.1. Wafer cleaning

Perhaps the most important issue in silicon-based heteroepitaxy is wafer
preparation and in situ cleaning prior to epitaxial growth. Poor surface
cleaning results in defects at the epitaxial interface that are independent
of the lattice mismatch between Si and Si1−x Gex . Conventional silicon
homoepitaxial reactors use an in situ high-temperature hydrogen or
hydrogen chloride (HCl) ambient to ensure that the surface is free of
oxide prior to epitaxial growth. Several approaches to the cleaning
problem have been made in the low-temperature deposition of Si1−x Gex
on silicon: retaining the high-temperature step and using an ultrahigh
vacuum to desorb oxide; using a lamp-heated system to rapidly change
from the cleaning temperature to the deposition temperature; using
ion bombardment to physically remove the oxide; or using the unique
properties of silicon wafers after dipping in liquid hydrofluoric (HF) acid for
an H2 -terminated surface. Carbon and oxygen contamination is a common
problem in epitaxy. Having a very low base pressure reduces the oxygen
and carbon contamination and prevents the formation of a native oxide.
Using a load-lock during the wafer load and unload is an additional method
of keeping the deposition chamber free of oxygen and carbon from the
atmosphere.
In silicon homoepitaxy, emphasis is placed on obtaining a high growth
rate for high throughput and reducing the autodoping from deposition. In
low-temperature silicon and Si1−x Gex epitaxy, autodoping is not a problem
and desired layer thicknesses are of the order of 100 nm or less. Precise
control of the germanium and dopant concentration profiles becomes more
important than high growth rates. Certain device applications need
bandgap grading, so Ge incorporation control down to 1–2% is desirable.
High and moderate levels of dopants of both types are needed to form
different device structures. Quick transitions from high to low and low
to high dopant and Ge concentrations are also desired for the formation
of lightly-doped spacers for modulation-doped structures. Control of in
situ doping profiles down to 50 nm and formation of dopant profiles
with peaks below the surface are extremely important for precise vertical
dopant profiles and lower junction capacitance. As ion implantation
cannot produce these types of profiles, in situ doping is a necessity.
For CVD techniques, gas chemistry and gas purity are very important
issues. Silane (SiH4 ) is more reactive than dichlorosilane (SiH2 Cl2 ),
so a lower deposition temperature is possible. Even lower deposition
temperatures can be achieved by using disilane (Si2 H6 ).
2.2.2. Molecular beam epitaxy
Molecular beam epitaxy is the growth technique most widely used to grow
pseudomorphic Si1−x Gex layers on Si. This is a growth technique where
the thermally evaporated molecules of the desired species impinge on an
atomically clean heated substrate to form a crystalline solid. The growth
technique is intrinsically clean due to UHV growth environment (base
pressure ∼10−11 Torr). Cryopumps provide an oil-free evacuation system.
MBE is specially suited for the growth of heterostructures requiring precise
control of alloy composition, layer thickness and doping. The main
characteristics of the MBE growth technique are as follows:
• very low growth pressure (∼10−9 Torr) allowing atomic layer by layer
growth on a atomically clean surface;
• low growth temperature (350–600 ◦ C) which minimizes solid state
diffusion and autodoping;
• slow growth rate (0.1–5 Å s−1 ) which permits atomically thin-layer
growth and better uniformity;
• multilayer growth capability that allows growth of quantum well and
superlattice structures;
• in situ surface analysis capability such as high-energy electron
diffraction (RHEED), Auger electron spectroscopy (AES) and x-ray
photoelectron spectroscopy (XPS).
Most MBE systems retain some type of high-temperature cleaning

or anneal cycle. The resistively heated substrate can be lowered to the
deposition temperature without worry of surface recontamination because
of the very low partial pressures of oxygen and carbon in the process
chamber. Argon sputter cleaning has been used to etch 10 nm from the
surface of the wafer. The etch is followed by a 850 ◦ C anneal before lowering
down to the deposition temperature, between 500–750 ◦ C. But sputter
cleaning leads to degradation in the minority carrier lifetime by heavy
metal contamination sputtered from the chamber onto the surface of the
wafer [36]. Because of the UHV conditions, medium temperature (<850 ◦ C)
bakeouts are sufficient to cause native oxide and other contaminants to
desorb from the surface of the wafer [37]. The success of using HF dips
as a cleaning method in UHVCVD has also spread to MBE, allowing
silicon homoepitaxy at a temperature down to 370 ◦ C without any high-
temperature anneals [38].
Molten pools of extremely pure elemental sources such as silicon

and germanium at the base of the MBE apparatus provide a source of
atoms, with beams of these atoms directed at the substrate to produce
the desired film. The atoms strike the silicon substrate and accumulate
in a crystalline manner (epitaxial growth). The deposition kinetics are
simple in MBE, since a chemical reaction does not take place. The
heated substrate provides the surface mobility necessary to epitaxially
align the impinging molecules. Deposition rate is controlled by the flux
of the evaporated molecules and the substrate temperature. Deposition
rates of up to 600 nm min−1 for silicon are possible. However, typical
Si1−x Gex deposition rates are in the 30 nm min−1 range for greater profile
control [39].
Also, extremely abrupt compositional profile control is possible by the
use of mechanical shutters. To minimize the strain that results from lattice
mismatch, generally SiGe alloys layers containing less than 30% Ge are
grown. Bean et al [39] found that the maximum germanium incorporation
before the occurrence of non-planar growth depends on the deposition
temperature, as shown in figure 2.6. At 750 ◦ C, the maximum germanium
mole fraction is 10%, whereas at 550 ◦ C 100% germanium is possible [9,39].
Figure 2.6. Temperature dependence for planar Si1−x Gex growth as a function
of Ge concentration. It is noted that for the Ge fraction more than 0.5, the
growth temperature must be lower than 550◦ C.
A limited range of dopant incorporation by coevaporation is possible

in MBE, specifically for n-type dopants, because of low sticking coefficients
of Sb and As and surface segregation. Low-energy implantation during
deposition may solve these problems, but increases the complexity and
the cost of MBE. Wafer uniformity is another limitation. Rotating the
substrate partially circumvents the problem, but large wafers (>125 mm)
may present an insurmountable problem from a uniformity stand point.
The inability to in situ dope n-type dopants and to deposit selective layers
has been surmounted by using gas source MBE (GSMBE) [37, 40–42].
In GSMBE, Si2 H6 , germane (GeH4 ), diborane (B2 H6 ) and phosphine
(PH3 ) are introduced into the deposition chamber instead of evaporating
elemental sources. The deposition is controlled by the chemical reaction
of the gaseous radicals at the surface of a heated wafer. GSMBE may be
described as a hybrid MBE/CVD system, but the deposition pressure is an
order of magnitude or more below other CVD systems. At these deposition
pressures, gas phase equilibrium may not be achieved, so standard CVD
kinetics may not apply.
2.2.3. UHVCVD
Chemical vapour deposition systems utilize precursor gases that
incorporate the desired atoms to the substrate surface. This technique,
which has been well known for decades, is in many ways simpler than MBE.
CVD is the most advantageous process because it is a high throughput
process and also it has in situ doping capabilities. An ultrahigh vacuum
chemical vapour deposition reactor consists of a diffusion furnace under
ultrahigh vacuum, as shown in figure 2.7. Since the base pressure is
comparable to MBE at 10−9 Torr, the advantages of low contamination
Figure 2.7. A schematic cross section of a UHVCVD reactor.

and prevention of native oxide after loading are similar to MBE. UHVCVD
does not use an in situ cleaning step, but relies on the passivation of the
surface immediately after an HF dip [43]. A load-lock is also used to
prevent exposing the deposition chamber to the atmosphere. The gases
SiH4 , GeH4 , B2 H6 and PH3 provide the sources for CVD of p-type and
n-type silicon and Si1−x Gex . The deposition pressure is about 1–2 mTorr,
with deposition rates around 1–2 nm min−1 . The control of the wafer
temperature in a diffusion furnace is extremely good. As a result, a surface
rate-limited reaction results in a very uniform layer.
2.2.4. LRPCVD and RTCVD
Limited reaction processing CVD for silicon homoepitaxy and Si1−x Gex
heteroepitaxy was first developed at Stanford University. The unique
feature of this system is that the surface reaction is temperature driven,
and the temperature of the substrate acts as a switch either to initiate
a reaction, terminate a reaction or to change the reaction rate. This
technique employs rapid isothermal processing, and the temperature of
the substrate (hence the reaction rate) can be rapidly varied (as fast as
350 ◦ C s−1 ). In this system, the base pressure is about 1 mTorr and
the gas flows are established at low temperature. Typical gases used
include SiH2 Cl2 , GeH4 , B2 H6 , AsH3 and PH3 as source gases. The
lamps are turned on to raise the substrate temperature and initiate
the deposition, hence the terminology limited reaction processing. As
a result of the rapid temperature transitions, the high-temperature in
situ cleaning step occurs with hydrogen or hydrogen chloride in a short
time, thus reducing the total thermal budget compared to commercial
epitaxial deposition systems. Many other research groups have used
similar configurations and have adopted the name rapid thermal chemical
vapour deposition (RTCVD) instead of LRPCVD because they use gas
switching rather than lamp heating to control the reaction. However, rapid
doping and compositional transitions are possible by using the lamps as
a thermal switch to control the reaction. In situ doping and selective
silicon and Si1−x Gex heteroepitaxy have been demonstrated. Si1−x Gex
layers need to be deposited at a lower temperature to avoid relaxation
and three-dimensional growth problems. The deposition temperature used
for Si1−x Gex is about 625 ◦ C and is increased to 850 ◦ C for silicon cap
layer deposition, if required. One of the major problems with reducing the
temperature, however, is increased oxygen incorporation in the Si1−x Gex
layers. The oxygen incorporation problem may be reduced with the use of
a load-lock and point-of-use filtration of SiH2 Cl2 .
2.2.5. Very low pressure CVD

The very low pressure CVD (VLPCVD) deposition tool follows the more
conventional CVD method with some differences and was first developed at
MIT. The deposition chamber is a quartz tube evacuated by a turbopump
to a base pressure of 10−8 Torr when cold. The susceptor and wafer are
heated by a bank of quartz halogen infrared lamps up to a temperature of
800 ◦ C. The base pressure increases to about 10−7 Torr when the chamber
is heated to 800 ◦ C. Process gases during deposition include silane (SiH4 ),
germane (GeH4 ), diborane (B2 H6 ), arsine (AsH3 ) and phosphine (PH3 ) as
the semiconductor and dopant gas sources. Unlike MBE or UHVCVD, the
base pressure in VLPCVD is not low enough to prevent the formation
of oxide in the reaction chamber. Therefore, in situ plasma cleaning
techniques are needed to prepare the surface for epitaxial deposition. The
VLPCVD reactor resembles the UHVCVD deposition kinetics because of
the mTorr deposition pressure and SiH4 gas chemistry. Deposition of in
situ doped n- and p-type layers of up to 1020 cm−3 dopant concentrations
and the deposition of selective epitaxial layers using VLPCVD have been
demonstrated [44–46].
2.2.6. Remote plasma CVD

Remote plasma enhanced CVD (RPCVD) has also been used for the Si
and Si1−x Gex epitaxy [47]. It is a low-temperature process and has been
successfully employed for silicon homoepitaxy and Si1−x Gex heteroepitaxy
in the temperature range of 150–450 ◦ C. The epitaxial process employs
an ex situ wet chemical clean, an in situ remote hydrogen plasma clean,
followed by a remote argon plasma dissociation of silane and germane to
generate the precursors for epitaxial growth. Boron doping concentration
as high as 1021 cm−3 has been achieved in the low-temperature epitaxial
films by introducing B2 H6 /He during growth. The growth rate of epitaxial
Si can be varied from 0.4–50 Å min−1 by controlling the RF power. The
wide range of controllable growth rates makes RPCVD an excellent tool for
applications ranging from superlattice structures to more conventional Si
epitaxy. Defect densities below the detection limits of TEM (∼105 cm−2 or
less) have been reported. The RPCVD process also exploits the hydrogen
passivation effect at a temperature below 500 ◦ C to minimize the adsorption
of C and O during growth. Low oxygen content ∼ 3 × 1018 cm−3 has
been achieved by RPCVD. Silicon and Si/Si1−x Gex films with boron
concentrations ranging from 1017 to 1019 have been achieved.
2.2.7. Atmospheric pressure CVD

Atmospheric pressure reactors hold the greatest promise for widespread
commercial use of Si1−x Gex heteroepitaxy of silicon. CVD of epitaxial SiGe
films from SiH4 –GeH4 –HCl–H2 gas mixtures in an atmospheric pressure

CVD process has been reported [48]. IBM [49,50] and ASM [51–53] deposit
silicon and Si1−x Gex at atmospheric pressure using SiH2 Cl2 and GeH4 .
Layer depositions are carried out in a horizontally arranged, induction-
heated and air-cooled conventional epitaxy reactor. RCA precleaned silicon
wafers were treated in situ in hydrogen at 1070 ◦ C for 10 min and then HCl
gas-etched for a further 10 min. Gas purifiers and load locks are essential in
both cases to reduce the oxygen and carbon incorporation. The IBM system
uses a silicon carbide susceptor, whereas the ASM system uses a quartz
support plate. The deposition kinetics appear similar to the LRPCVD
or RTCVD systems since SiH2 Cl2 and GeH4 are used. The IBM system
deposited smooth Si1−x Gex layers with up to 44% germanium at 550 ◦ C;
they speculate that the chlorine-based gas chemistry suppresses islanding
at high germanium concentrations. Unfortunately, no in situ doping data
or Si1−x Gex device results have been reported using atmospheric CVD.
2.2.8. Solid phase epitaxy

From the viewpoint of the compatibility with conventional silicon
processing, it may be difficult and extremely costly to merge MBE
techniques within a standard bipolar/BiCMOS process. An alternative
approach to forming the SiGe layer, is to implant high-dose Ge ions on the
silicon substrate using solid phase epitaxy (SPE) [54–56]. This produces
an amorphous SiGe layer on the silicon substrate and subsequent thermal
annealing is required to induce crystallization. Residual implantation
defects due to high-dose germanium implantation may be removed by
sequential RTA. This method is fully compatible with the conventional
silicon IC manufacturing process and is relatively simple. SPE growth of
a SiGe alloy using Ge ion implantation and prolonged furnace anneal has
been reported [57–60]. Carbon has a very low bulk solubility in Si and Ge.
It is known that the incorporation of elements into Si at concentrations
far in excess of their bulk solubility limit is possible by SPE. Thus, SPE
provides another possible synthesis route for forming metastable Si1−y Gey
or Si1−x−y Gex Cy layers.
2.2.9. SiGeC film growth

SiGe grown on Si(001) is compressively strained due to the larger lattice
constant of germanium compared to silicon. This causes limitations such
as a critical thickness for planar pseudomorphic growth. Adding a small
amount of carbon into the SiGe material system allows strain adjustment
due to the small lattice constant of carbon. Exactly strain compensated
SiGeC structures have been shown to exhibit a smaller bandgap than
silicon with a considerable valence band offset [61–64]. Si1−y Cy and
Si1−x−y Gex Cy alloys in which C is incorporated substitutionally offer

considerably greater flexibility compared to that available in Si/Si1−x Gex
heterostructures. In particular, the growth of Si1−x−y Gex Cy alloys with
a Ge:C ratio of about 8:1 offers the possibility of fabricating group IV
heterostructure devices lattice matched to Si.
Due to the smaller lattice constant of carbon, synthesis of carbon-
containing alloys with high electronic quality is challenging in part because
of the low equilibrium solubility of carbon on the Si lattice. A number
of research groups have investigated the maximum amount of carbon that
can be incorporated in Si1−x−y Gex Cy by MBE and CVD [62, 65, 66] and
also studies have been carried out to determine the fraction of the total
carbon concentration that is substitutional on the lattice. An MBE system,
equipped with an electron beam evaporator for silicon, a pyrolytic graphite
filament for carbon and effusion cells for germanium and boron, has been
used for the growth of Si1−x−y Gex Cy samples with Ge contents up to 6%
and carbon concentrations up to 0.55% at 450 ◦ C on a thick Si buffer layer.
High-quality Si/Si1−x−y Gex Cy heterojunctions have been grown [67] by
RTCVD using dichlorosilane (Si2 H2 Cl2 ), germane (GeH4 ) and methylsilane
(SiCH6 ) as the precursors of Si, Ge and C, respectively.
Using a cold-wall, ultrahigh vacuum, stainless steel chamber with
single-wafer-processing capability, epitaxial SiGeC films have been grown
at 550 ◦ C with 1–20 sccm of Si2 H6 , 0.1–2 sccm of GeH4 and 0.8–
1.6 sccm of CH3 SiH3 . Carbon incorporations of 2.6 atomic wt.% in Si and
1.4 atomic wt.% in SiGe were obtained [68]. Photoluminescence studies
of Si1−x−y Gex Cy and electrical measurements on the Si1−x−y Gex Cy -based
bipolar transistors [69] indicate that the incorporation of substitutional C
increases the bandgap of Si1−x−y Gex Cy pseudomorphically grown on an
Si(100) substrate, with the bandgap increasing by 21–25 meV when 1% C
is added.
2.2.10. Strained-Si film growth

High-quality completely lattice-relaxed SiGe buffer layers have been grown
on Si(001) using MBE in the temperature range of 750 and 900 ◦ C and
compositional grading of the order of 10% µm−1 or less with final Ge
concentrations of about 30%. Xie et al [1] have grown compositionally
graded relaxed-Si1−x Gex buffer layers on Si with various composition
gradients and temperatures. The authors reported a threading dislocation
density in fully relaxed-SiGe buffer layers grown using both MBE and
RTCVD in the range of 105 –106 cm−2 [70]. GSMBE [71, 72] has also been
successfully employed for the growth of high-quality completely lattice-
relaxed step-graded SiGe buffer layers on Si(001) in the temperature
range of 750 and 800 ◦ C. A more abrupt compositional transience of the
SiGe/Si interface is expected in GSMBE-grown QWs, owing to reduced Ge
Thermal stability of alloy layers 51
segregation at the heterointerface [73], than in those grown by solid source

MBE where Ge segregation has been recognized as an important issue [74].
Another advantage of GSMBE is that uniform thickness and composition
can be obtained without sample rotation. However, GSMBE is associated
with autodoping of doping gas impurities, which would affect the device
characteristics.
2.3. THERMAL STABILITY OF ALLOY LAYERS
Since most of the low-temperature grown strained layers are metastable

in nature, at a high processing temperature these coherently strained
layers can relax by forming misfit dislocations. Even for sub-critically
strained (i.e., thermodynamically stable) epilayers, interdiffusion can be
important at a high temperature. Since standard silicon processing steps,
such as implantation annealing and thermal oxidation, typically exceed the
strained layer deposition temperature, thermal stability of strained layers
is of utmost importance. The Matthews–Blakeslee curve imposes severe
limitations on stable strained-Si1−x Gex layer thickness and germanium
concentration. Understanding the relaxation processes of metastable layers
is imperative if thicknesses and germanium concentrations greater than the
equilibrium curve are needed. Relaxation processes from thermal cycling
can be categorized into three mechanisms: temperature dependence of
the threading dislocation glide force [75]; dislocation multiplication [76];
and germanium diffusion [77]. In an advanced very large scale integration
(VLSI) process, there are two high-temperature steps: (i) thermal oxidation
to grow gate oxide and (ii) post implant anneal after ion implantation.
For gate oxidation, a temperature between 850–950 ◦ C is typically used,
whereas for rapid thermal implant anneal a temperature as high as 1050 ◦ C
is used depending on the dopant and dose. These high-temperature
process steps impose serious limitations on the thermal budget that can
be used to fabricate a device based on these metastable films. The
characterization methods used vary due to the detection limits of each
technique. Detection methods include plan-view TEM, in situ plan-view
TEM, Raman spectroscopy, double crystal diffractometry (DCD) and
defect etching.
X-ray diffraction analysis is not very sensitive to study dislocation
defect densities device grade materials. Capacitance–voltage (C–V )
measurements can be employed to study the carrier confinement in the QW.
The SiO2 /Si/SiGe/Si MOS low-frequency capacitance shows a plateau
region in inversion. This property of the low-frequency capacitance can
be used to qualitatively study the degradation of the material properties
due to high-temperature process steps. The plateau in the C–V curve is
sensitive to the band offset in the valence band at the Si/SiGe interface [78].
This band offset in the valence band is reduced if the quality of the
heterointerface is degraded either due to the creation of misfit dislocation

defects or due to interdiffusion.
A few general trends may be established from the published literature
on thermal stability of the strained layers:
• layers below the Matthews–Blakeslee equilibrium curve appear stable;

• relaxation of uncapped layers ranges from 600–700 ◦ C;
• unstrained silicon cap layers improve the thermal stability by
extending the point of relaxation to 800 ◦ C. A silicon cap suppresses
dislocation nucleation and propagation; and
• interfacial contaminants play a major role in the number of as-
deposited dislocations.
2.4. BANDGAP AND BAND DISCONTINUITY
Theoretical calculations based on the electronic structure of heterointer-

faces, involving a variety of SiGe layers on Si and Ge substrates, have
been employed to predict the band offset [7, 79]. Computations are gen-
erally based on local density functional theory, [80], phenomenological
deformation potential theory [81] and self-consistent ab initio pseudo-
potential [82]. Experimental determination of the valence band offset be-
tween strained-Si1−x Gex and Si (type I band alignment) has been reported
by several workers using different techniques such as x-ray photoelectron
spectroscopy (XPS) [83], admittance spectroscopy [84], deep-level transient
spectroscopy (DLTS) [85], capacitance–voltage and temperature-dependent
current–voltage (I–V ) characteristics [86–88].
In the case of a p-type Si/Si1−x Gex MOS capacitor, as the gate bias is
swept negative, holes will accumulate first in the buried Si1−x Gex potential
well formed by the valence band offset ∆Ev , rather than at the silicon/oxide
interface. Carrier accumulation in the buried well produces a bias region
over which there is little change in the capacitance as a function of gate
bias. As the gate bias continues to be swept to negative voltage, holes
will eventually begin accumulating at the silicon/oxide interface. The
capacitance then rises towards the maximum value of Cox , as is usual
for an Si MOS capacitor. Band offsets can be extracted by fitting the
shape of simulated MOS capacitance–voltage curves in the plateau region
to measurements at different temperatures, typically ranging from 100–
300 K [87].
To extract band offsets from C–V measurements of p-MOSFETs,
threshold voltages at heterointerface (VTH ) and SiGe/SiO2 interface (VTS )
√
are measured both from the ID –VG characteristics and a plot of ID / gm
versus VG curve of a MOS device [89]. The relationship between threshold
Bandgap and band discontinuity 53
voltages and valence band offset (∆Ev ) is given by [90]

tSi tox
VTH = VFB + φTH − qNB xdm + (2.4)
Si ox
and
qNB xdm
VTS = VFB + φTS − 1 + H(φH ) (2.5)
Cox
where
∆Ev
φTH = 2φF + (2.6)
q

φTH − φH
H(φH ) = ho exp (2.7)
kT /q
where
2
ho = 2Si NB kT / (qNB xdm ) (2.8)
where VFB is the flatband voltage, φTH is the potential at threshold at the
top Si/Si1−x Gex interface, φTS is the potential at Si/Si1−x Gex interface,
φF is the Fermi potential, q is electronic charge, NB is the effective doping
concentration in the bulk of the semiconductor, xdm is the maximum
depletion layer width in strong inversion, tSi is the Si cap layer thickness,
tox is oxide thickness, ox is the oxide permittivity, k is the Boltzmann
constant, T is temperature and ∆VT = VTH − VTS .
By subtracting equation (2.5) from equation (2.4) and rearranging, a
system of two nonlinear equations (2.9) and (2.10) with ∆Ev and φH as
unknown is obtained:
2
kT tSi Cox (∆VT − ∆Ev ) −1
∆Ev = φH −2φF + ln 1 + Cox + −1 (ho )
q Si qNB xdm
(2.9)
and φH is given by
2
kT Si (φH − 2φF ) −1
φH = φTH − ln − 1 (ho ) . (2.10)
q qNB xdm tSi
For an Si/SiGe heterostructure, an experimental valence band offset

(∆Ev ) is obtained by iterating equations (2.9) and (2.10) using the
values of doping concentration and threshold voltages obtained from
the experimental high-frequency apparent doping versus gate voltage
characteristics [89], as shown in figure 2.8.
Figure 2.8. Apparent doping versus distance from the Si/SiO2 interface. Data
obtained from the high-frequency C–V measurements.
2.4.1. Si/SiGe
The electronic properties of SiGe materials depend on the substrate

material on which they are grown, the germanium mole fraction in the film,
and the quality of the film and interface. Although SiGe can be grown on
silicon, germanium or even SiGe substrates, the fabrication of SiGe HBTs
requires SiGe growth on silicon substrates. When a thin film with a larger
lattice constant (e.g., Si1−x Gex ) is grown on a smaller lattice constant
substrate (e.g., silicon), the film maintains the in-plane lattice constant
of the substrate and is under a biaxially compressive strain. Figure 2.4,
described earlier, shows the band offset between a strained-Si0.8 Ge0.2 film
grown on silicon and strained-Si on a relaxed-SiGe layer.
A discussion of strain-induced splittings within the framework of
deformation potential theory has been given by van de Walle and
Martin for strained-SiGe [79]. Depending on the composition, the
bandgap of Si1−x Gex alloy varies from 1.1–0.7 eV, corresponding to the
wavelength range of about 1–1.5 µm. This is a very useful range for
discrete optoelectronic devices and for integrated optoelectronics on silicon.
Figure 2.9 shows the bandgap difference compared to bulk-Si of unstrained
Si1−x Gex [91] and the calculated values of strained-Si1−x Gex [92] at room
temperature. The strained-Si1−x Gex curve splits into two lines because
of uncertainty in some of the parameters used in the calculations. The
Figure 2.9. Germanium mole fraction and strain-dependent bandgap of

Si1−x Gex . The bandgap reduction for compressive (strained-SiGe), tensile
(strained-Si) and relaxed cases are shown. (After People R 1986 IEEE J.
Quantum Electron. 22 1696–710.)
calculated strained value lies in between the two dotted curves. The
calculations for the bandgap of strained-Si1−x Gex were confirmed by
Lang [93] using photocurrent spectroscopy. The bandgap depends on the
germanium fraction in both cases, but strained-Si1−x Gex experiences a
faster drop in bandgap than the unstrained case due to splitting of the
valence band degeneracies. Figure 2.9 indicates that strained-Si1−x Gex
layers need less germanium to achieve the desired bandgap difference.
The bandgap alignment for strained-Si0.8 Ge0.2 on silicon appears in
figure 2.9 based on pseudopotential and deformation potential calculations
by van de Walle [82] and People [81]. Since the conduction band
discontinuity is much smaller than the valence band discontinuity,
researchers often ignore the conduction band discontinuity. Quantum
confinement of electrons at the Si–strained-Si1−x Gex heterointerface is
difficult because of the small conduction band discontinuity. However, the
state of the initial substrate plays a major role in determining the band
offsets, as shown in figure 2.9. In fact, calculations show virtually any
bandgap alignment is possible [14].
2.4.2. Si/SiGeC
Present knowledge about the band structure of tensilely strained-SiGeC
ternary alloys on Si001 is limited. Assuming an average band structure
for Si1−x−y Gex Cy alloys, Soref [94] has suggested an empirical interpolation
between Si, Ge and diamond (C) for the bandgap which increases in the
fundamental gap of Si1−x−y Gex Cy layers with increasing y. This result
has been contradicted by Demkov and Sankey [95] who have shown that
the fundamental gap is reduced when a small percentage of carbon is
added to the silicon lattice. This reduction in bangap is in agreement
with the photoluminescence measurement data. To describe adequately
the observed energy shifts for pseudomorphic carbon-containing layers,
strain-induced effects and effects due to alloying should be considered
[96]. An estimation for the band offsets and the fundamental bandgap
for Si1−x−y Gex Cy alloys (containing up to 3% carbon and 30% Ge
concentration) tensile or compressive strained has been reported by Osten
[97]. This estimation considers both the band alignment at the interface of
two different materials, as well as strain effects.
Figure 2.10 summarizes the results for the highest valence band
for different tensile and compressive strained-Si1−x−y Gex Cy layers on
Si001. The plot shows ∆Ev as a function of the effective Ge or C
Figure 2.10. Valence band offsets for compressively strained Si1−x Gex and
Si1−x−y Gex Cy (x = 10%, 20% and 30%, y varies between 0% and 3%) and tensile
strained Si1−y Cy and Si1−x−y Gex Cy (y = 1%, 2% and 3%, x varies between 0%
and 30%) plotted as a function of the effective lattice mismatch—expressed in
‘effective’ Ge or C concentrations, respectively. (After Osten H J 1998 J. Appl.
Phys. 84 2716–21.)
concentration for the compressive or tensile strained layers, respectively.

The effective concentration corresponds to the concentration needed for
identically strained binary layers. The valence band offset between
compressive strained layers and Si is generally much larger than that
at the tensile strained layer/Si interface. Photoluminescence studies
of Si1−x−y Gex Cy sandwiched between Si layers [62, 63] and electrical
measurements on the Si1−x−y Gex Cy -based bipolar transistors [69] indicate
that the incorporation of substitutional C increases the bandgap of
Si1−x−y Gex Cy pseudomorphically grown on an Si(100) substrate, with the
bandgap increasing by 21–25 meV when 1% C is added.
Analysis of n- and p-type MOS capacitors indicates that most of the
band offset is in the valence band for Si/Si1−x−y Gex Cy heterojunctions
with carbon contents less than or equal to 0.8 at.%, i.e., no capacitance
plateau region is observed for n-type Si/Si1−x−y Gex Cy /Si capacitors.
Figure 2.11 summarizes the extracted valence band offsets as a function
of the mismatch to Si for Si/Si1−x−y Gex Cy capacitors with Ge contents
of 20 and 30% and carbon contents up to roughly 1 at.%. From the
data it is seen that the extracted valence band offset decreases as carbon
is added to Si1−x−y Gex Cy . This is consistent with the widening of the
Si1−x−y Gex Cy bandgap with the increasing carbon content that has been
Figure 2.11. Summary of valence band offsets extracted from MOS

capacitance–voltage characteristics for p-type Si/Si1−x−y Gex Cy capacitors. The
offset is extracted by fitting C–V simulations to the measured data. (After
Hoyt J L et al 1998 Thin Solid Films 321 41–6.)
observed by photoluminescence measurements [63, 98]. It is also observed

from figure 2.11 that, for a given mismatch to Si, the valence band offsets
appear to be slightly higher for Si/Si1−x−y Gex Cy than for Si/Si1−x Gex
heterojunctions.
XPS has been used to measure the conduction and valence band
offsets in thick, relaxed Ge-rich Si1−x−y Gex Cy alloys grown by solid
source molecular beam epitaxy on (100) Si substrates [99]. It was shown
that addition of C increased the valence band maximum of SiGeC by
+48 meV %C−1 . The bandgap energies were obtained from optical
absorption, and were combined with the valence band offsets to yield
the conduction band offsets. For SiGeC/Si heterojunctions, the offsets
were typically 0.6 eV for the valence band and 0.38 eV for the conduction
band, with a staggered type II alignment. These offsets provide significant
electron and hole confinement for device applications.
Admittance spectroscopy has been used to measure valence band
offsets in Si/Si1−x Gex and Si/Si1−x−y Gex Cy heterostructures grown by
MBE. The Si/Si1−x Gex and Si/Si1−x−y Gex Cy samples consisted of 250 Å
Si1−x Gex or Si0.796 Ge0.20 C0.004 alternating with 350 Å Si for ten periods,
and both layers were doped p-type with dopant concentrations of 7.4 ×
1016 cm−3 and 1 × 1017 cm−3 , respectively. These heterostructures
were grown on a 2000 Å Si buffer on Si substrates and capped with
2000 Å Si. Measurements of conductance and capacitance as functions of
temperature at various frequencies were used to determine the activation
energy for thermal excitation over the Si barriers in the p-type multiple
quantum well (MQW) structures; band offsets were then obtained from
the measured activation energies. For Si/Si0.75 Ge0.25 and Si/Si0.80 Ge0.20
heterostructures coherently strained to Si, valence band offsets of 198 ± 12
and 160 ± 20 meV, respectively, were obtained. For a Si0.796 Ge0.20 C0.004
heterostructure, the valence band offset was 118 ± 10 meV. This value
is slightly lower than the valence band offset of approximately 135 meV
expected in a Si/Si0.833 Ge0.167 heterojunction, for which the lattice
mismatch is the same as in the Si/Si0.796 Ge0.20 C0.004 heterojunction.
2.4.3. Strained-Si
The heterojunction band offsets (∆Ec , ∆Ev ) in a strained-Si/SiGe

heterostructure have been determined from the measurement of threshold
voltages of surface channel strained-Si p-MOSFET structures [89, 100].
The extracted experimental valence band offset ∆Ev was found to be
160 meV. Using the valence band offset value, the conduction band offset
was obtained from the following equation
∆Ec = Eg (Si1−x Gex ) + ∆Ev (Si1−x Gex /Si) − Eg (strained-Si) (2.11)

Mobility 59
where Eg (strained-Si) is given by [7, 101]
Eg = 1.11 − 0.4x (2.12)
where x is the Ge concentration in the top part of a completely relaxed

SiGe buffer cap. The conduction band offset ∆Ec was found to be 126 meV
for a Ge concentration of 0.2 at the top of the relaxed-SiGe layer.
2.5. MOBILITY
Strain not only modifies the bandgap energy and band alignments but also
lowers the effective mass at the band edges and higher mobilities may be
expected [102]. In the following, we discuss some experimental work used
to determine mobility in strained layers. A more comprehensive discussion
of the electron and hole mobility on strain level and the band structure will
be given in chapter 4.
2.5.1. Si/SiGe
Calculations have been made for strained and unstrained Si1−x Gex that
have shown an increased electron mobility perpendicular to the growth
interface and increased hole mobility parallel to the growth interface for
strained layers with increasing Ge content. If an Si1−x Gex strained epilayer
is grown on (100) Si, the splitting of the conduction band minimum due
to strain reduces the effective mass and improves the electron mobility in
a direction perpendicular to the interface by about 50% [103, 104]. These
results, however, have been contradicted by other simulations showing that
the mobility peaked and then decreased with increasing Ge concentration
[105, 106]. If the epilayer is grown on a thick relaxed-Si1−x Gex buffer
layer with a higher Ge concentration than in the epilayer, the mobility
perpendicular to the layer is reduced while the mobility parallel to the
interface increases [107]. As the doping concentration in the semiconductor
increases, the strict periodicity of the lattice is disturbed by the existence
of the impurity atoms, and various heavy doping effects occur. Besides the
dependence of carrier mobilities on the doping concentration and electric
field, in alloy semiconductors, mobilities also depend on the composition.
It is well known that heavy doping of a semiconductor can reduce the
bandgap. In SiGe alloys and strained layers, the combined effect of strain
and heavy doping on the bandgap and bandgap narrowing have been
reported [8, 108].
2.5.2. Si/SiGeC
Given the potential of Si/Si1−x−y Gex Cy , it is imperative to know its carrier
transport properties and compare them with those in the Si/Si1−x Gex
system. Two-dimensional modulation-doped hole gases can in principle

be fabricated since the band offset at the Si/Si1−x−y Gex Cy interface
is predominately in the valence band [109, 110]. To date, however,
there are very few reports on the transport properties of holes in the
Si/Si1−x−y Gex Cy interface and reports of transport properties are limited
to the temperature range of 77–300 K. In the following, we discuss the
transport properties of a two-dimensional hole gas in an Si/Si1−x−y Gex Cy
modulation-doped structure.
Using modulation-doped p-type Si1−x−y Gex Cy QWs, transport
properties of boron-doped tensile strained, perfectly strain compensated
and compressively strained-Si1−x−y Gex Cy alloy layers on Si(001)
substrates have been studied by Duschl et al [111]. The layer sequence
of the p-type modulation-doped Si0.85−y Ge0.5 Cy QWs is 200 nm undoped
silicon, 20 nm Si0.85−y Ge0.5 Cy , 10 nm Si spacer, a 30 nm thick 2×1018 cm−3
boron-doped Si layer and a 30 nm Si cap. The mobility and charge
carrier density were determined in a temperature range 40–300 K using
the standard van der Pauw technique at a magnetic field of 0.3 T.
At room temperature, acoustic and optical phonon scattering is
dominant. However, with the freeze-out of phonons at cryogenic
temperatures, ionized impurity scattering becomes dominant in moderately
doped semiconductors. In Si1−x−y Gex Cy layers, alloy scattering
contributes as a further mechanism. The carrier mobility also depends
on the amount of ionized impurities, the germanium and carbon contents.
In the following, we discuss the effect of the addition of carbon and
germanium on the hole mobility of strained and exact strain compensated
Si1−x−y Gex Cy layers.
Figure 2.12 shows the room temperature mobility and hole density
data. Besides a silicon reference layer (solid square), the first (open squares)
starts with the compressively strained Si0.94 Ge0.06 . By adding carbon,
while leaving the germanium content constant, the strain is subsequently
reduced until exact strain compensation is reached (C = 0.55%). Then
the amount of Ge is reduced leading to tensile strained Si0.995−x Gex C0.0055
and finally to Si0.995 C0.0053 . The second sequence (open circles) starts with
Si0.96 Ge0.04 and ends at Si0.996 C0.0037 .
Considering the Hall mobility (figure 2.12(a)) it is quite evident that
additional germanium and carbon reduces the mobility as compared to
pure silicon. A general trend is that the room temperature mobility on the
compressive strain side is nearly independent of the carbon content. On
the other hand, the hole density (figure 2.12(b)) decreases from compressive
to tensile strain.
Figure 2.13 shows the temperature dependence of the Hall mobility.
The reduced mobility of the Si1−x−y Gex Cy alloys compared to pure
silicon at room temperature agrees well with the results published in the
literature [18, 112, 113]. The reasons for the drop in mobility are the
Mobility 61
Figure 2.12. Room temperature mobility (a) and hole density (b) of pure Si
(solid square) and two sample sequences. The first sequence (open squares)
starts with Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content
constant, the strain is subsequently reduced until strain relaxation is reached
Si0.935 Ge0.06 C0.055 then the amount of germanium is reduced leading finally
to Si0.995 C0.0053 . The second sequence starts with Si0.96 Ge0.04 and ends with
Si0.996 C0.004 . (After Duschl R et al 1998 Thin Solid Films 336 336–9.)
alloy scattering and the enhancement of optical phonon scattering with

increasing germanium incorporation due to the smaller optical phonon
energy of germanium compared to silicon. But the theoretically predicted
and experimentally observed small decrease of the effective mass due to
the germanium incorporation, which should lead to a higher mobility,
cannot compensate these effects. However, at a low temperature, the
Si1−x−y Gex Cy layers show a higher mobility than the silicon due to the
lower carrier concentration which leads to a lower effective mass and minor
role of the optical phonon scattering at a low temperature. It is seen that
Figure 2.13. Temperature dependence of the hole mobility for the compressively
strained Si0.94 Ge0.06 , exact strain compensated Si0.935 Ge0.06 C0.055 and tensile
strained Si0.995 C0.053 layers. (After Duschl R et al 1998 Thin Solid Films 336
336–9.)
the room temperature mobility decreases with C and Ge alloy concentration

compared to pure Si from 180 to 120 cm2 V−1 s−1 , which is due to the
increasing alloy scattering and enhanced scattering at optical phonons. At
temperatures below 100 K, a higher mobility is measured for the samples
containing C, due to the lower carrier concentration and because ionized
impurity scattering becomes dominant.
Figure 2.14 shows the mobility and carrier density of a two-dimensional
hole gas in the Si1−x−y Gex Cy channel from room temperature to 10 K.
The initial decreasing and eventual saturation of hole density indicate the
freeze-out of parallel conduction paths and the gradual transfer of holes to
the Si1−x−y Gex Cy channels as temperature is decreased. In contrast, the
hole mobility increases with decreasing temperature. This is evidence of
the formation of two-dimensional hole gas in the Si1−x−y Gex Cy channels.
The hole mobility at a low temperature decreases as C is incorporated. For
example, at 10 K the mobility with no C is 1800 cm2 V−1 s−1 compared
to 1500 and 800 cm2 V−1 s−1 with C levels of 0.3% and 0.6%, respectively.
It is not clear if the decrease in hole mobility is due to enhanced alloy
scattering with the addition of C, or other factors, such as increased
interface roughness or C-related defects. The carrier density saturates at
∼1012 cm−2 at a low temperature, suggesting a complete hole transfer,
as intended, from the Si dopant layer to Si1−x−y Gex Cy channels. The
variation in the carrier density may be due to imperfect doping control
during growth and is not thought to result from a change in the valence
band.
Mobility 63
Figure 2.14. Hole density and mobility as a function of temperature for

Si/Si1−x−y Gex Cy modulation-doped heterostructures. (After Chang C L et al
1998 Thin Solid Films 321 51–4.)
2.5.3. Strained-Si
Low-temperature Hall mobility measurements are commonly used to
determine the overall quality of a heterostructure and are used to
optimize the growth parameters. At low temperature, where the thermal
effects and scattering by phonons are dramatically reduced, the electron
mobility becomes very sensitive to residual scattering mechanisms due to
background charge impurities, roughness and dislocation. Experimental
electron mobility data from strained-Si/SiGe modulation-doped structures
may be divided into two categories: (i) data from devices with the uniform
composition buffer and (ii) devices with the compositionally graded buffer.
A detailed discussion on the mobility of electrons and holes in strained-Si
may be found in [17].
At room temperature, strained-Si electron mobility values are between
2000 and 2800 cm2 V−1 s−1 for n-channels [118,119], which exceed those in
bulk-Si MOSFETs by a factor of four to six. High hole mobilities in excess
of 9300 cm2 V−1 s−1 at 4 K in p-type modulation-doped Si/Si0.87 Ge0.13 /Si
heterostructures have been reported by Whall et al [120]. For p-MOSFETs,
room temperature values between 1400 and 1800 cm2 V−1 s−1 have been
reported [121], a factor of six to nine above those of conventional Si p-
MOSFETs. The dependence of low-field electron and hole mobility on
strain level is shown in table 2.2. A more comprehensive discussion of the
dependence of low-field electron and hole mobility on strain level and the
band structure will be given in chapter 6.
Table 2.2. Experimental low-field electron and hole mobility: dependence on

strain level.
Ge concentration Strain in Si Temperature Mobility

in the buffer (%) (%) (K) enhancement factor Ref.
Electron
10 0.4 300 1.45 [114]
20 0.8 1.67
29 1.3 1.75
29 1.3 77 1.35
Hole
29 1.33 300 1.2 [115]
18 0.8 300 1.4 [116]
18 0.8 77 2.0
25 1.0 300 1.5 [117]
2.6. SUMMARY
In this chapter we have given the background for growing different strained
layers using various types of reactors. Basic Si1−x Gex properties and
deposition systems have been briefly covered. A variety of methods exist
to deposit high-quality alloy layers. In addition to depositing layers with
germanium concentrations of at least 15%, control of the germanium profile
to within 1% is desirable for bandgap grading. The use of Si/Si1−x Gex
heteroepitaxial structures for heterojunction devices is hindered by the
lattice mismatch between the two materials. However, strained-Si1−x Gex
layers can be deposited on silicon at or above the Matthews–Blakeslee
critical thickness curve without interfacial dislocations. Typical bandgap
engineering applications may require up to 150 meV bandgap difference.
Therefore, the deposition technique must be able to deposit Si1−x Gex
layers with germanium concentrations of at least 20%. Layers deposited
above the Matthews–Blakeslee curve must contend with thermal relaxation
during thermal processing. Unfortunately, the Matthews–Blakeslee critical
thickness at 20% germanium is only about 20 nm, and is a limitation
for applications requiring higher Ge mole fractions. Partially strain-
compensated or fully strain-compensated SiGeC films may extend the
application areas.
Differences in the reactor design, base pressure, gas chemistry and
deposition temperature do not appear to limit the ability to deposit device
quality group IV alloy layers. MBE is commonly used as a research
tool due to its low wafer throughput. UHVCVD appears to have the
www.ebook3000.com
Bibliography 65
most advantages in terms of material quality and throughput. Research

using LRP/RTCVD reactors have demonstrated device quality material.
Extension of the LRP/RTCVD reactor concept to commercial atmospheric
CVD reactors holds promise, but additional work in characterizing
atmospheric reactors is needed. Furthermore, the throughput of these
single wafer atmospheric CVD reactors needs to be examined.
The experimental determination of valence band and conduction band
offsets (∆Ev , ∆Ec ) in a heterostructure, from the measured threshold
voltages (VTH and VTS ) of a p-MOSFET have been discussed. A review of
experimental work to determine the variation of mobility in SiGe, SiGeC
and strained-Si layers on strain, doping and temperature has also been
described.
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Chapter 3
PRINCIPLE OF SIGE HBTS
In chapter 2, the technologies involved in SiGe layer growth and the

electronic properties of strained-Si1−x Gex layers have been described with
special emphasis on those properties which are related to their use as a
narrow bandgap material in the base of a heterojunction bipolar transistor
(HBT). In this chapter, we examine the underlying physics of the npn SiGe
HBT, with particular emphasis on the fundamental differences between the
operations of the SiGe HBT and the Si BJT.
The concept of a bipolar transistor in which the emitter has a greater
bandwidth than the base dates back to the time of Shockley’s original
patent on the junction bipolar transistor [1]. A detailed theoretical analysis
of the potential performance advantages of this type of device, commonly
known as a heterojunction bipolar transistor, was presented by Kroemer in
1957 [2]. However, it was not until 1987 that a functional HBT employing
a base layer was demonstrated. The introduction of Ge into the base of
an npn Si BJT reduces the bandgap of the SiGe alloy in the p-doped
base, relative to Si in the n-doped emitter and collector regions. This
bandgap discontinuity creates the heterojunctions needed for the enhanced
performance of a SiGe HBT.
Before discussing heterojunction action in a bipolar transistor we start
by recapping well-established Si BJT fundamentals [3]. If the effect of
carrier recombination is initially ignored, the electron and hole injection
currents in a forward biased pn junction can be expressed as

qADnb qVbe
In = np0 exp −1 (3.1)
Lnb kT

qADpe qVbe
Ip = pn0 exp −1 (3.2)
Lpe kT
where Vbe is the applied bias, A is the area of the junction, Dnb and Dpe are
the minority carrier diffusion constants, Lnb and Lpe are minority carrier
73
74 Principle of SiGe HBTs
diffusion lengths, and np0 and pn0 are the equilibrium minority carrier
concentrations in the neutral base and emitter, respectively.
In conventional homojunction transistors, the doping concentration in
the emitter is considerably higher than in the base, in order to obtain a
high injection efficiency. For a typical gain of 100, the emitter must be
doped 100 times more heavily than the base. As the doping concentration
increases to more than 1018 cm−3 , bandgap narrowing due to heavy doping
becomes significant [4].
The following substitutions can be made in equations (3.1) and (3.2)
n2io
np0 = (3.3)
Nb
n2ie
pn0 = (3.4)
Ne
∆Ebgn
n2ie = n2io exp (3.5)
kT
where nio is the intrinsic carrier concentration and ∆Ebgn represents the
bandgap reduction in the emitter due to heavy doping.
When bandgap narrowing is included, the current gain β becomes

Ne Lpe Dnb −∆Ebgn
βSi = exp . (3.6)
Nb Lnb Dpe kT
In an HBT with a narrow bandgap base, the bandgap of the emitter

is larger than the base and therefore the injection efficiency can be made
very high, even if the base is doped more heavily than the emitter [2, 5].
In a SiGe HBT, a narrow bandgap SiGe base is used and the bandgap
difference between the emitter and base is ∆Eg (x) = Eg,Si − Eg,SiGe (x).
Due to its smaller bandgap, the intrinsic carrier concentration in the SiGe
base increases.
The difference between the HBT and BJT is that the concentration of
the injected electrons is much higher (several orders of magnitude) into the
base due to lower conduction band barrier. The current gain for a SiGe
HBT becomes
∆Eg (x)
βSiGe = βSi exp . (3.7)
kT
This means that the collector current will be much higher than in
a similarly doped BJT, by a factor of exp(∆Eg (x)/kT ), while the base
current is not affected. In a SiGe HBT, the bandgap difference ∆Eg (x)
can be made much larger than kT . For example, a Ge fraction x = 0.2
in the base yields a bandgap difference of more than 170 meV. Therefore,
the current gain of the HBT can be made large, irrespective of the doping
ratio in the emitter and the base. However, the real advantage of the HBT
Energy band 75
is not to achieve a very high current gain, but to trade it against a high
base doping, necessary to reduce the base resistance.
High values of maximum oscillation frequency and low values of gate
delay τd (for digital switching applications) can be obtained in HBTs [6,7].
Base resistance is an important parameter in determining fmax . In a well-
designed HBT, a value of 50 for β is usually sufficient, so emitter injection
efficiency can be traded for increased doping in the base. Increased base
doping gives rise to reduced base resistance which is also desirable in helping
to avoid punch-through as the base–collector voltage is increased.
High base doping may contribute to the onset of tunnelling current at
the emitter–base junction. This can be avoided by deliberately reducing
the doping concentration in the emitter. Indeed, in the HBT, it is in
principle feasible to consider the possibility of interchanging collector and
emitter, providing additional advantage in some digital circuits. Many of
the specific issues involved in transistor design are more fully covered in
chapter 4. For the remainder of this chapter, we focus in more detail on
device physics, showing how the incorporation of germanium significantly
changes the physics of the base region and the emitter–base and base–
collector junctions.
3.1. ENERGY BAND
The first step in understanding how a heterostructure device will operate

is to consider the energy band diagram. For homostructures, the electron
affinity and bandgap are position independent, and there is no need to
worry about the reference level. But for heterostructures, a reference level is
essential, normally taken to be the field-free vacuum level. To draw energy
band diagrams for devices with a position-dependent alloy composition, it
is essential to know how the bandgap varies with position and also the band
line up at compositional junctions.
Figure 3.1 shows the band diagram of an npn bipolar transistor. In
forward active mode, the emitter–base junction is forward biased by the
input voltage Vbe , and the base–collector junction is reverse biased by the
output voltage Vbc . The collector current Ic consists of electrons which are
injected from the n-emitter into the thin p-base, move through the base by
drift and diffusion, and are collected in the n-collector layer (a drift field
in the base can be caused by either a doping or a bandgap gradient). The
number of electrons injected into the emitter side of the base is determined
by the height of the potential barrier, ∆Vn , in the conduction band between
the emitter and the base, which can be controlled by the input voltage Vbe .
The dominant component of the base current Ib consists of holes which are
injected from the p-base into the n-emitter (no holes are injected into the
n-collector in forward active mode because the base–collector junction is
reverse biased). The number of holes injected into the emitter is determined
Figure 3.1. Simulated band diagram of an npn bipolar transistor. (After

Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si
heterojunction bipolar transistors PhD Dissertation Princeton University.)
Figure 3.2. Simulated band diagram of a narrow bandgap base npn

heterojunction bipolar transistor. (After Prinz E J 1992 Base transport and
vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors
PhD Dissertation Princeton University.)
Terminal currents in a SiGe HBT 77
by the potential barrier ∆Vp in the valence band between base and emitter,
which is also controlled by the input voltage Vbe .
The key idea of an HBT is to lower the potential barrier seen by
the carriers responsible for the output current (electrons in npn devices)
compared with the one seen by the carriers constituting the input current
(holes in npn devices), thereby increasing the ratio of output to input
current, the common emitter current gain of the HBT [5]. This is done
by fabricating the emitter and the base using materials having different
bandgaps. Depending on the layer in which the bandgap is changed
compared to a homojunction device, two HBT configurations can be
distinguished:
(i) in a narrow bandgap base HBT, the bandgap in the base is lowered
thereby increasing the collector current, whereas
(ii) in a wide bandgap emitter HBT, the bandgap in the emitter is
increased compared to the base, resulting in a lower base current.
In both cases, the common emitter current gain is increased by a
factor proportional to exp(∆Eg /kT ) if spike and notch effects at the
heterojunctions are neglected. Note that in an HBT, where the emitter
bandgap is larger than that in the base, the current gain β should
increase when the temperature is lowered, making it possible to operate
the transistors more effectively at cryogenic temperature.
3.2. TERMINAL CURRENTS IN A SIGE HBT
In this section we consider a comparison of a SiGe HBT with the equivalent

Si BJT. For the purpose of comparison, it is assumed that both the silicon
bipolar and the SiGe HBT are identical, other than the fact that germanium
is present in the SiGe HBT. Figure 3.3 shows how the base bandgap changes
are brought about by the incorporation of Ge into the base.
In thermal equilibrium, the Fermi level, EF , is constant across the
junction. Therefore, for an abrupt Si/SiGe interface, the difference in
bandgap between the emitter and base causes discontinuities to exist at
the conduction and valence bands, shown in figure 3.3 as ∆Ec and ∆Ev ,
respectively. Also, the total discontinuity, ∆Ec + ∆Ev , is equal to the base
bandgap difference between the silicon emitter and SiGe base, ∆Egc−b . In
SiGe, the valence band discontinuity, ∆Ev , tends to be considerably larger
than the conduction band discontinuity, ∆Ec .
Figure 3.4 shows the band diagram in forward active mode, where
in this more general case, the germanium concentration is graded linearly
across the base, increasing from emitter towards the collector. With the
presence of germanium, the electron injection barrier from emitter to base,
ψn , is reduced and there will be greater electron injection from emitter to
base. This means an increase in the collector current. However, the hole
Figure 3.3. Effect of strained-SiGe layer on the bandgap of emitter–base

junction for an abrupt Si/SiGe interface. (After Tang Y T 2000 Advanced
characteristics and modelling of SiGe HBTs PhD Thesis University of
Southampton.)
injection barrier from base to emitter, ψp , remains the same as in a silicon

bipolar transistor. Therefore, the hole current from base to emitter, which
is the main contributor to base current, remains the same. Hence, silicon
bipolar transistors and SiGe HBTs tend to have approximately the same
base current.
The following derivations [8], used to show enhancements resulting

from Ge incorporation in the base, closely follow derivations contained
in [9]. We consider the most general case of germanium grading and show
how constant grading may be treated as a particular case for which the
theoretical treatment is still valid. The collector current of a graded SiGe
HBT can be obtained by altering the collector current equation of a silicon
bipolar transistor. Assuming uniform base doping for the device, the silicon
bipolar collector current density, Jc,Si , for uniformly-doped base can be
Figure 3.4. Bandgap energy diagram across a graded SiGe HBT in forward
active mode of operation. Of and Wf are the electrical boundaries of the neutral
base region on the emitter and collector sides of the base, respectively. (After
Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis
University of Southampton.)
written using the Moll–Ross relation [10]

−1
Wf
Nb (x)dx
Jc,Si = q (exp (qVbe /kT ) − 1) (3.8)
Of Dnb (x)n2ie (x)
qDnb n2io
app
= exp ∆Egb /kT [exp (qVbe /kT ) − 1] (3.9)
Wb Nb
where q is the charge on an electron, Vbe is the forward biased emitter–
base voltage, k is the Boltzmann constant, T is temperature, Of and Wf
are the base electrical junction positions at the emitter and collector side
of the neutral base, in forward active mode, Wb is the neutral base width,
Nb (x) is the positional-dependent base doping concentration, Dnb (x) and
nie (x) are the positional-dependent base electron diffusion coefficient and
effective intrinsic carrier concentration, respectively, nio is the intrinsic
carrier concentration in the absence of heavy doping effects, Nb is the

app
base doping, and ∆Egb is the base apparent bandgap narrowing due to
the heavy doping effect.
In equation (3.8), nie (x) accounts for the effective intrinsic carrier
concentration across the base and is a function of the bandgap. For a graded
SiGe HBT, bandgap changes across the base, as depicted in figure 3.4, can
be accounted for [9]
app

2 2
∆Egb ∆Eg,SiGe (grade)(x/Wb ) ∆Eg,SiGe (Of )
nie (x) = γnio exp + +
kT kT kT
(3.10)
where [11]
(Nc Nv )SiGe
γ= ≈ 0.4 (3.11)
(Nc Nv )Si
and neutral base width, Wb = Wf −Of . The term Eg,SiGe (grade) represents
the bandgap difference across the neutral base. The term ∆Eg,SiGe (Of )
represents the bandgap difference at the emitter side of the neutral base,
Nc and Nv are the density of states in the conduction and valence bands,
respectively.
Putting equations (3.8) and (3.10) together and integrating, the
most general form for the SiGe HBT collector current density, Jc,SiGe ,
incorporating both bandgap offset and grading, can be written as [9]
app

qDnb n2io ∆Egb qVbe
Jc,SiGe = ζ̄ γ̄ exp + −1
Wb Nb kT kT
(3.12)
∆Eg,SiGe (grade) exp ∆Eg,SiGe (Of )/kT
×
kT 1 − exp − ∆Eg,SiGe (grade)/kT
where
(Dnb )SiGe
ζ= >1 (3.13)
(Dnb )Si
where the symbol ‘–’ refers to a position averaged quantity. The ratio of
(Dnb )SiGe to (Dnb )Si accounts for the strain enhancement of the minority
carrier electron mobility with increasing germanium content [12].
Taking the ratio of Jc,SiGe to Jc,Si , the collector current enhancement
due to bandgap engineering can be estimated by,
Jc,SiGe ∆Eg,SiGe (grade) exp (∆Eg,SiGe (Of )/kT )
≈ ζ̄ γ̄ (3.14)
Jc,Si kT 1 − exp (−∆Eg,SiGe (grade)/kT )
where we can draw important conclusions by considering the magnitudes

of the terms in the above equation in giving rise to collector current
enhancement, i.e.,
• ζ̄ > 1 defines the effect of the difference in diffusivity/mobility

between
SiGe and Si;
∆Eg,SiGe (Of )
• exp kT > 1 defines the effect of basic heterojunction action
due to bandgap shrinkage in the base; and
∆Eg,SiGe (grade)/kT
• > 1 defines the effect of bandgap grading
1−exp −∆Eg,SiGe (grade)/kT
across the base.
It should be pointed out that equation (3.12) applies in the general
case. In the limiting case, where there is no grading, the latter term tends
to unity as ∆Eg,SiGe (grade) tends to zero, and the overall expression for
collector current is still valid in a much simplified form.
Even though γ̄ < 1 [11], exp(∆Eg,SiGe (Of )/kT ) increases the SiGe
HBTs collector current exponentially for a finite germanium content. For
a SiGe HBT having a germanium concentration varying from 4% at the
emitter–base junction to 12% with a trapezoidal shape across the base (see
figure 3.5), a collector current enhancement by a factor of 4.5 has been
reported [9].
The base current in a bipolar transistor, consists of several
components. In the emitter, holes can recombine with electrons at the
Figure 3.5. Uniform (flat), triangle, and trapezoid Ge profiles in the base of
a SiGe HBT. (After Harame D L et al 1995 IEEE Trans. Electron Devices 42
455–68.)
emitter surface, in the neutral emitter, or in the wide bandgap part of the
emitter–base space-charge region. In the narrow bandgap base, electrons
can recombine with holes in the narrow bandgap part of the emitter–
base space-charge region, or in the neutral base. An additional source
of collector and base current consists of electron–hole pairs created by
avalanche multiplication or thermal generation in the base–collector space-
charge region. The various base current components can be distinguished
by their dependence on emitter–base voltage, base–collector voltage, and
temperature. If both base and emitter material have a high minority
carrier lifetime, which is usually the case in SiGe HBTs, the base current is
dominated by emitter surface recombination current or the current in the
neutral emitter.
Since the boundary conditions for the injected minority carriers into
the emitter remain the same as in the homojunction, the reverse injected
hole current can be written as
qDpe n2ie,Si qVbe /kT
Jp = e −1 . (3.15)
Nde We
Equation (3.15) assumes a short, uniformly-doped emitter. For emitters

with a short minority carrier lifetime, We is replaced by the diffusion
length Lpe = Dpe τp where Dpe and τp are the respective minority carrier
diffusivity and lifetime in the emitter region, giving
qDpe n2ie qVbe /kT

Jp = e (3.16)
Nde Lpe
where Nde and Lpe are the emitter doping density and hole diffusion length,
respectively. Equation (3.16) implies that Jp has an ideality factor of unity.
The potential barrier for hole injection into the emitter is the same
for both the homojunction and the narrow bandgap heterojunction device,
which implies that this component of the base current should be identical
in the two devices, if they have similar emitters. This has indeed been
observed in experimental SiGe HBTs and is evident from figure 3.6.
Auger recombination deals with the heavy doping effects. This band-
to-band recombination mechanism occurs at dopant concentrations beyond
1019 cm−3 [13]. One of the main objectives in SiGe HBT design is to lower
the base resistance by increasing the base doping concentration. The lower
base resistance improves high-frequency performance. In the highly-doped
emitter of a BJT, the net effect of Auger recombination is a lower effective
lifetime in the emitter, leading to a shortened diffusion length and increased
base current. In a device simulator this effect is easily included as an extra
term in the current continuity equations.
Figure 3.6 shows the collector and base currents of a flat-base SiGe
HBT (x = 0.2) compared to the corresponding Si homojunction device.
Transit time 83
Figure 3.6. Room temperature Gummel plots of a flat-base SiGe HBT and
silicon control device with similar base sheet resistances, and emitter areas,
showing the increased collector current due to the narrow bandgap base. (After
In the Gummel plot, the collector current of an ideal bipolar transistor

should be proportional to eqVbe /kT , corresponding to an inverse slope of
approximately 60 mV per decade of collector current at room temperature.
The ∼50× increase in the collector current (and the current gain) of the
HBT compared to the homojunction transistor is due to the narrower
bandgap in the base, since both the devices have the same integrated base
dopant concentration. Since the base current of silicon and SiGe HBTs
are virtually identical, the current gain enhancement due to germanium
incorporation is similar to the collector current enhancement. Therefore,
the superior current gain potential of a SiGe HBT can be traded off for an
increased fmax and reduced base resistance, leading to higher power gain,
faster switching speed and a lower noise figure.
3.3. TRANSIT TIME
Bandgap grading across the base creates a drift electric field that accelerates
the electron minority carriers through the base. The graded electric field
reduces the amount of base stored charge per unit collector current. This
reduces the energy and time required to move charge in and out of the base
during transients. As a result, the base transit time, τb , decreases.
In any bipolar transistor, the base transit time for constant base doping
can be written as [10]
Wf 2
Wf
Qb nie (z) Nb (y)dy
τb = = dz (3.17)
Ic Of Nb (z) z Dnb (y)n2ie (y)
where Qb is the total base stored charge and Ic is the collector current.
Putting equation (3.10) into (3.17) and integrating, τb,Si [13,14] and τb,SiGe
[9] become:
Wb2
τb,Si = (3.18)
2Dnb
Wb2 kT
τb,SiGe = (3.19)
ζ̄Dnb ∆Eg,SiGe (grade)

kT −∆Eg,SiGe (grade)
× 1− 1 − exp .
∆Eg,SiGe (grade) kT
Taking the ratio of τb,SiGe /τb,Si gives:
τb,SiGe 2 kT
= (3.20)
τb,Si ζ̄ ∆Eg,SiGe (grade)

kT −∆Eg,SiGe (grade)
× 1− 1 − exp .
∆Eg,SiGe (grade) kT
For a finite germanium grading of more than 1% at room temperature,

τb,SiGe /τb,Si will be less than 1 and therefore the SiGe HBT base transit
time will be shorter than the silicon bipolar. The cut-off frequency, fT of a
bipolar device, as explained in section 3.7, is a function of base transit time,
implying that bandgap grading will also increase the usable frequency of
operation of the device.
An additional benefit of incorporating Ge into the base is a reduction
in emitter transit time τe , compared to a silicon BJT. Since τe is inversely
proportional to the collector current, for a given base doping profile, the
enhancement in τe , is obtained from the inverse of (3.14) as
τe,SiGe Jc,Si 1 − e−∆Eg,SiGe (grade)/kT

≈ = . (3.21)
τe,Si Jc,SiGe ∆E (grade) ∆Eg,SiGe (0)/kT
ζ̄ γ̄ g,SiGe
kT e
The emitter transit time can potentially be a limiting factor in HBTs which
include a low-doped emitter region to avoid tunnelling current from base
to emitter. Such structures are discussed in chapter 4. The effect of base
and emitter transit times on ac performance is more fully discussed in
section 3.7.
Early voltage 85
3.4. EARLY VOLTAGE
For analogue circuit applications, a high value of the product of current

gain and Early voltage (βVA ) is desirable. There are several physical effects
which cause the collector current to increase with collector–emitter voltage
for a constant base current. The most important of these is the increase of
the collector current caused by a decrease of the width of the neutral base
with base–collector reverse bias [15].
Output conductance is a measure of collector current variation with
base–collector reverse bias. In figure 3.8, the base–collector depletion
region widens and reduces the neutral base width as the reverse biased
base–collector voltage increases, while keeping a fixed emitter–base voltage.
Reduction of the neutral base width leads to an increase in the gradient
of the injected electron distribution in the p-type base. Since the electron
diffusion current across the base is directly proportional to this gradient,
the collector current will increase. A low output conductance is desirable
to achieve invariant output current in low-frequency analogue applications.
The Early voltage, VA , an indicator of the extent of base width
modulation, can be obtained by extrapolation of the output characteristics.
With reference to figure 3.7, the Early voltage (ignoring recombination in
the base) is given by

∂Vce ∂Vce ∂Wb
VA ≈ Jc = Jc . (3.22)
∂Jc ∂Wb ∂Jc
The rate of change of the neutral base width Wb with respect to the
Figure 3.7. Definition of the Early voltage VA . The linear parts of the output
characteristics of a bipolar transistor are extrapolated to zero collector current.
Figure 3.8. Minority carrier distribution in an npn transistor for increasing

base–collector reverse bias voltage in forward active mode. np (x) is the electron
concentration in the p-type base. (After Tang Y T 2000 Advanced characteristics
and modelling of SiGe HBTs PhD Thesis University of Southampton.)
base–collector voltage, for constant emitter–base voltage, is given by

∂Wb Cjc
=− (3.23)
∂Vbc qNb (Wb )
and the change of the collector current density with respect to the base
width is
∂Jc Nb (Wb )/ n2ie (Wb )Dnb (Wb )
= −Jc Wb . (3.24)
∂Wb Nb (x)/ (n2 (x)Dnb (x)) dx
0 ie
For a constant base profile, combining equations (3.23) and (3.24) one gets

qn2 (Wb )Dnb (Wb ) Wb
VA = ie Nb (x)/ n2ie (x)Dnb (x) dx (3.25)
Cjc 0
where n2ie (Wb ) denotes the intrinsic carrier density at the end of the neutral
base on the collector side. Combining equation (3.25) with the standard
equation for bipolar current gain
−1
Wb 2
q
β= p(x)/ nie (x)Dn (x) dx (3.26)
Jb0 0
Early voltage 87
and assuming p(x) = Nb (x) yields an important figure-of-merit for bipolar

transistors, βVA , given by
q2 2
βVA = nie (Wb )Dn (Wb ) . (3.27)
Jb0 Cjc
The following three points are significant:

• βVA is a strong function of Ge concentration at the end of the neutral
base (base–collector junction);
• βVA is larger in SiGe than in silicon due to the larger n2io (Wb ) value
in SiGe; and
• to maximize βVA , the base–collector junction capacitance should be
as low as possible.
Harame et al [9] showed that Early voltage enhancement of a graded
SiGe HBT can be expressed as

VA,SiGe ∆Eg,SiGe (grade) 1 − exp (−∆Eg,SiGe (grade)/kT )
≈ exp .
VA,Si kT ∆Eg,SiGe (grade)/kT
(3.28)
Combining equations (3.28) and (3.14), the enhancement in βVA at

constant emitter–base voltage can be shown as
βVA,SiGe
≈ γζe∆Eg,SiGe (Of )/kT e∆Eg,SiGe (grade)/kT (3.29)
βVA,Si
which is significantly greater than unity for a profile with finite Ge content.
For finite germanium grading, ∆Eg,SiGe (grade), of more than 1% across the
base, τb,SiGe /τb,Si , ratio will be larger than 1. Therefore, grading Ge across
the neutral base improves not only base transit time, but also Early voltage.
Furthermore, since current gain is essentially enhanced by the difference in
bandgap at the emitter–base junction and Early voltage by Ge grading
across the base, respectively, the composite product βVA is significantly
enhanced by up to two orders of magnitude.
Figure 3.9 shows the SiGe/Si ratio for the three parameters of
interest—current gain, Early voltage, and the product of current gain times
Early voltage [9]. This figure needs to be interpreted with some care, as
the integrated Ge dose across the base has been kept constant in order to
provide a meaningful comparison. In this figure, when ∆Eg,Ge (grade) = 0,
a pure Ge box profile of 8.4% Ge is implied, while ∆Eg,Ge (grade) =
125 meV, (the x-axis limit in figure 3.5), implies a purely triangular profile
from 0–18.6% Ge. Any other grading between these limits indicates the
corresponding trapezoidal Ge profile. The triangular profile has the largest
Early voltage and gain–Early voltage product. The Ge box profile has an
Figure 3.9. Early voltage and current gain Early voltage products. (After
Harame et al 1995 IEEE Trans. Electron Devices 42 455–68.)
exponentially increased current gain, by the factor exp(∆Eg,SiGe (Of )/kT ),

but the same Early voltage. The βVA product is strongly influenced by
base–collector capacitance Cbc , but there is always a trade-off between the
separate terms. If β is increased, by reducing the base doping, VA will
decrease, so it is therefore not desirable to have excessively high current
gain.
In a SiGe HBT with a box Ge profile, the improvement in βVA is
limited by critical thickness considerations. For example, for a base width
of about 500 Å, the Matthews–Blakeslee theory predicts a maximum Ge
concentration of about 7% corresponding to a bandgap difference of 55 meV
compared to Si. This bandgap difference translates into ∼5× improvement
in the βVA product. In a graded base SiGe HBT, insertion of a very
thin Si1−x Gex region between base and collector will reduce base–collector
capacitance and increase Early voltage, while leaving the current gain
virtually unchanged [16]. The thickness of this Si1−x Gex layer has to be
sufficient to include the base edge of the base–collector depletion region
even at maximum reverse bias Vbc . Since the equilibrium critical thickness
decreases with increasing Ge concentration in a strained-Si1−x Gex layer,
the improvement possible in the βVA product of a graded-base HBT is
greater compared to that of β alone in a box profile HBT.
A simple structure to investigate the β versus VA trade-off in graded
base HBTs is a stepped base transistor, where the base consists of two
separate p-doped layers with constant bandgap in each layer. Figure 3.10
shows the calculated band diagrams and measured collector current
Early voltage 89
Figure 3.10. Calculated band diagrams and measured collector current

characteristics showing the effect of the position of the biggest bandgap region
in the base on the output resistance of SiGe HBTs. The devices had an
emitter area of 62 × 62 µm. (After Prinz E J 1992 Base transport and vertical
profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD
Dissertation Princeton University.)
characteristics for two stepped-base devices. Both devices had similar

current gains because of the similar width and height of the highest barrier
for electrons in the base. The output resistance of device in which the
narrow gap layer was located at the base–collector junction, however, was
vastly increased compared to device which had its narrow gap layer at
the emitter–base junction. Prinz and Sturm [16] have experimentally
demonstrated βVA products of 168 000 using a two step 14–28% germanium
base. State-of-the-art silicon bipolar processes have a βVA product of
6000. The effects of base dopant out-diffusion leading to a base–collector
heterojunction barrier on the Early voltage have also been reported [17].
A more complete discussion on the effects of parasitic barriers is given in
the following section.
3.5. HETEROJUNCTION BARRIER EFFECTS
The computed conduction band offset in the silicon to strained-Si1−x Gex

heterojunction is small (typically 20 meV) [18]. If a significant conduction
band offset exists, a reduction in the gain may result. In a heterostructure,
compositional grading across the heterojunction may be used to eliminate
the conduction band spike. In the case of an Si/SiGe/Si system, the
conduction band spike is not a severe problem if the emitter dopant
concentration is larger than the base doping concentration, as the band
bending appears on the side with lower doping. In an npn transistor any
small conduction band spike may be disregarded. However, it is not true for
the pnp transistor, as the spike will be large in this case because valence
band offsets are much larger than the conduction band offsets. At high
current densities or high forward bias, the transport of carriers is strongly
influenced by the potential barrier that develops due to alloy grading
potential of the heterojunction. A retrograde Ge profile near the collector
junction also creates a barrier to the flow of the minority carriers [19].
Another type of parasitic barrier arises due to the boron out-diffusion
from the base. Extension of base dopant beyond the Si1−x Gex region
occurs during thermal cycling, or improper control of the as-deposited
profile [20, 21]. Even small amounts of boron out-diffusion from a heavily-
doped Si1−x Gex base into the Si emitter and collector cause parasitic
barriers in the conduction band which can drastically reduce the collector
current enhancement.
Shafi et al [22] fabricated a SiGe HBT with a very narrow base width
of 214 Å, doped with a boron concentration of 5 × 1019 cm−3 and a Ge
concentration of 15%. The width of emitter was 0.3 µm doped with a
uniform As concentration 1018 cm−3 , while the doping in the collector was
3 × 1016 cm−3 . The collector current enhancement factor was 13, while
the base current was also found to increase sixfold. The authors attributed
this increase in base current to a either very low lifetime near the collector
region in the base, or a parasitic barrier at the base–collector junction.
Shafi et al [23] have also reported the collector current degradation due
to out-diffusion of boron and creation of parasitic barriers. The minority
carrier concentration in the base increases due to the barriers and this will
increase the recombination and base current, irrespective of the value of
the lifetime of the minority carriers.
Out-diffusion of boron into the collector results in the formation of
a parasitic conduction band barrier, as illustrated in figure 3.11, where
an exponential out-diffusion tail region of varying diffusion length, LD ,
Heterojunction barrier effects 91
Figure 3.11. Simulation of band diagram and electron concentration for a SiGe
HBT with the doping profile of (a). Note the exponential dopant out-diffusion
tail (diffusion length LD ) into the Si collector region. The band diagram (b) shows
the parasitic conduction band barrier at the Si1−x Gex /Si interface. (c) and (d)
show conduction and valence bands, respectively, at the base–collector junction
for various diffusion lengths LD . (e) The parasitic conduction band barrier
causes a deviation from the triangular electron profile in the base leading to
increased minority carrier charge storage in the base even as Ic decreases. (After
Figure 3.12. Simulation of normalized collector current enhancement versus

inverse temperature for various values of LD . (After Prinz E J 1992 Base
transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction
bipolar transistors PhD Dissertation Princeton University.)
extending into the Si collector region, has been superimposed upon an

Si0.8 Ge0.2 base with a constant doping of 1019 cm−3 . Even a small
amount of boron out-diffusion (LD ∼ 30 Å) causes a large parasitic barrier
for electrons at the base–collector junction (barrier height ∼85 meV), as
shown in figure 3.11(c). This barrier leads to increased minority carrier
storage in the base significantly impeding electron diffusion through the
base, increasing neutral base recombination and degrading the collector
current, as shown in figure 3.11(e). The parasitic barriers thereby reduce
the potential enhancement in current gain once the diffusion length exceeds
11 Å, as shown in figure 3.12.
With increased minority carrier charge storage in the base, as shown
in figure 3.11(e), the parasitic barriers increase the base transit time, τb ,
because of the increase in electron charge and the decrease in collector
current Ic , as the ideal triangular electron profile for electron concentration
in the base is replaced by a trapezoidal profile. This effect, demonstrated
by simulation, was experimentally observed by Pruijmboom et al [24] in
high-frequency measurements of SiGe HBTs.
3.5.1. Effect of undoped spacer layers
The deleterious effect of base dopant out-diffusion from the Si1−x Gex
base into silicon emitter and collector can be limited by inserting thin
undoped Si1−x Gex layers on both sides of the base [20, 21]. These
Heterojunction barrier effects 93
Figure 3.13. Doping profile of HBT structure with undoped SiGe spacer
layers. (After Prinz E J 1992 Base transport and vertical profile engineering in
Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton
University.)
Figure 3.14. Simulated boron doping profile (SUPREM III) for various anneals.
If the Si1−x Gex layer thickness is increased by adding 150 Å thick intrinsic
Si1−x Gex spacer layers on both sides of the base, the diffused boron profile is
still contained inside the Si1−x Gex layer for a temperature below 800 ◦ C. (After
spacers have to be wide enough to contain the tail regions of the boron
out-diffusion. Inevitably, this change increases the overall width of the
strained-Si1−x Gex layer, making the structure more likely to relax by
forming misfit dislocations at the interface.
To demonstrate the effect of thermal cycle on SiGe HBT performance,
consider the device structure shown in figure 3.13 with a base doping of
5×1019 cm−3 , a base width of 300 Å and box Ge profile (x = 0.18), leading
to a base sheet resistance of ∼800 Ω/square. The 1017 cm−3 collector
doping represents a trade-off between breakdown voltage BVceo and the
onset of high level injection in the collector (Kirk effect) [25, 26]. If the
base is doped above 2 × 1018 cm−3 a lightly-doped n-Si spacer has to be
inserted between base and emitter to prevent tunnelling leakage in the
emitter–base junction [27].
Figure 3.14 shows calculated doping profiles for a 10 min anneal at
various temperatures and figure 3.15 the corresponding band diagrams for a
structure (a) without and (b) with 150 Å thick spacers. Note the absence of
parasitic barriers in the device with spacers up to an annealing temperature
of 850 ◦ C. However, increase in the thermal budget of the process leads to a
strong degradation of the collector current. The intrinsic spacers, therefore,
substantially improve the tolerance of the device structure for the thermal
budget of the process. These simulations show that in the design of a SiGe
HBT process, intrinsic Si1−x Gex spacer layers on both sides of the base,
should be considered according to the thermal budget of the process. The
critical thickness limitation of the strained-Si1−x Gex layer, however, limits
the total permissible thickness of the base including the spacer layers.
3.6. HIGH LEVEL INJECTION
In a bipolar transistor, two different type of high level injection (HLI)

can occur. The first occurs in the base region from the large number of
electrons injected at high emitter–base voltage. The effect was analysed
for Si BJTs by Webster [28]. Since the reverse injected base current retains
an eqVbe /kT dependence, the current gain falls off inversely proportional to
Ic [3]. In general, this effect does not appear in HBTs if the base dopant
concentration is high.
The other HLI effect occuring in the collector region is the Kirk
effect [25] which arises as the base–collector depletion width spreads into
the collector at high current levels due to electron velocity saturation. The
effect of velocity saturation at large collector current densities depends
on the relative base and collector doping concentrations. Forward bias of
the internal base–collector junction increases the base current due to hole
injection into the collector and results in a rapid drop in dc current gain.
In a SiGe HBT, the valence band offset prevents the injection of holes into
the collector and subsequently the collector current saturates at densities
High level injection 95
Figure 3.15. Simulated band diagrams for a structure (a) without and (b)
with 150 Å thick spacers for a 10 min anneal at different temperatures. (After
less than the classical Kirk effect. In addition, excess charge is stored in
the base, which results in decreased current gain and fT .
Cottrell and Yu [29] and Yu et al [30] attempted to model the valence
band barrier effects at high collector current densities for a SiGe HBT.
The authors noted that the valence band barrier effect appears at high
current densities for npn and at all current densities for pnp devices. Other
researchers [31, 32] examined the effect of two-dimensional lateral carrier
diffusion on the gain. In this case, the electrons accumulating in the
base–collector space-charge layer (SCL) diffuse laterally before collection,

resulting in an increased effective collector area. Recently, a comprehensive
investigation of the impact of the Ge profile shape as well as the scaling of
base and collector doping on high injection heterojunction barrier effects
has been described [33] over a wide temperature range. The onset of the
Kirk effect in a SiGe HBT was shown to expose the Si/SiGe heterojunction
which blocks the flow of holes into the collector under the Kirk effect
and hence induces an electron barrier in the conduction band. The
combined effect reduces collector current, increases base current and rapidly
degrades fT . Various strategies to simultaneously reduce the impact of the
conduction band barrier, and increase fmax and BVceo were discussed.
Experimental evidence of the valence band barrier in a pnp SiGe HBT
has been confirmed [19, 34, 35]. The knee current (at which Ic × β is
maximum) which increases with applied base–collector bias, is found to
be much stronger than can be explained by the Kirk effect. Similarly, the
graph of unity gain cut-off frequency fT versus collector current density
also shows a strong dependence on the base–collector bias. From the
experiments, the knee current density was found to be much less than
the current density calculated by accounting solely for velocity saturation.
3.7. HIGH-FREQUENCY FIGURES-OF-MERIT
For high-frequency ac operation, bipolar transistors are often assessed

according to two figures-of-merit. The first is known as the unity gain
cut-off or transition frequency, fT . The second is known as the maximum
oscillation frequency. While both figures-of-merit may not necessarily be
suitable for all applications of SiGe HBTs, both are still widely quoted,
particularly in device research publications.
3.7.1. Unity gain cut-off frequency, fT

fT is defined as the frequency at which the common emitter short circuit
ac current gain is unity [13]. It is related physically to the bipolar device,
as the total delay for the minority carrier across the device from emitter
to collector, τec [3]. The total delay consists of the minority carrier stored
charge delay and the junction capacitance charging delay, and is often
related to fT through the equation:
1
fT = (3.30)
2πτec
where the total transit time τec comprises of a number of components:
τec = τe + τeb + τb + τbc + τje + τc . (3.31)

High-frequency figures-of-merit 97
The major components, due to minority carrier stored charge, are τe for the
neutral emitter and τb for the neutral base region (as previously discussed
in section 3.3). The term τeb represents minority carrier transit time in the
emitter–base depletion region, and is often small enough to be included in
the emitter transit time term. The transit time τb , the delay due to the
excess minority carrier storage in the base, is generally the most significant
term in equation (3.31) and the relevant expressions for a SiGe HBT and
the effect of Ge grading have been given in equations (3.19)–(3.20).
The delay term τbc is known as the collector depletion layer transit
time. It can be approximated as [13, 36]
Wjc
τbc = (3.32)
2vscl
where Wjc is the base–collector depletion layer width, vscl is the carrier
scattering limited velocity which is approximately equal to 1×107 cm s−1 at
room temperature for silicon [37]. For high-speed devices, as the base width
is consistently scaled down, τb reduces, and τe and τbc become progressively
more significant.
The delay term τje is the total charging time associated with emitter–
base and base–collector depletion layers and is given by [3]
kT
τje = (Cje + Cjc ) (3.33)
qIc
where Cje and Cjc are the emitter–base and the base–collector depletion
capacitances. As the collector current increases, it is often assumed that
this transit time component becomes negligible. However, for low power
devices, the effect of low Ic on τje becomes more significant, emphasizing
very clearly the importance of minimizing the junction capacitances Cje
and Cjc .
The delay term τc is the collector charging time [3]
τc = Rc Cjc . (3.34)
In a well-designed transistor, Rc is usually quite small and therefore τc

is usually not very significant. By combining all equations, fT can be
conveniently formulated as
−1
1 kT Wb2 Wjc
fT = (Cje + Cjc ) + + τe + τeb + + Rc Cjc .
2π qIc αDnb 2vscl
(3.35)
Figure 3.16 shows the typical variation of fT with collector current. From
equation (3.33), it is clear that τje is dominant at low collector current, and
therefore fT tends to increase with increase in Ic . However, the influence
of τje reduces drastically as the collector current continues to increase. At
Figure 3.16. Variation of fT with collector current in a SiGe HBT.
peak fT , τe , τb and τbc are usually the dominant terms for an optimal
transistor design [13]. Therefore, to improve the peak value of fT , all three
terms need to be minimized. Eventually high injection occurs and the base
transit time increases at high collector current, causing the reduction in fT
as shown in figure 3.16.
3.7.2. Maximum oscillation frequency, fmax
The unity gain cut-off frequency provides a good indication of the intrinsic
delay associated with a bipolar transistor. However, it is not a realistic
parameter for a circuit environment, as it assumes that the output is
short circuited. In addition, it is independent of base resistance and hence
does not take the base resistance base–collector depletion capacitance time
constant into account. These are important parameters for determining
the transient behaviour of bipolar circuits. Therefore, another more
practical and widely accepted figure-of-merit, fmax , is commonly used,
which characterizes the power transfer in and out of the bipolar device.
fmax is defined as the frequency at which the unilateral power gain becomes
unity. Here the output is essentially isolated from the input by an
appropriate external matching circuit comprising reactive and resistive
components. The load that it drives is also assumed to be conjugately
matched to the transistor output impedance. It can be shown [38] that:

fT
fmax = (3.36)
8πCjc Rb
Breakdown voltage, BVceo 99
where Rb is the base resistance. Equation (3.36) shows that it is not

sufficient to obtain a high value of fT , by decreasing base width, but that
base resistance and base–collector capacitance must also be minimized.
However, as base width decreases rapidly to achieve high fT , Rb will
increase unless the doping is increased. To counter that effect, the base
needs to be more highly doped, which means that emitter doping has to
be lowered to prevent emitter–base junction tunnelling for very high base
doping levels. The increased current gain capability of a SiGe base enables
lowering of emitter doping without jeopardizing sufficient current gain.
An alternative figure-of-merit, the ECL gate delay (see section 4.7.3)
has been used to characterize the effects of transistor parameters at high
frequency [39]. Unlike the frequencies fT and fmax , there is no standard
expression for the switching time or the propagation delay. The gate delay
depends not only on the intrinsic characteristics of the transistor but also
the circuit configuration and the values of load resistance and capacitance.
In all cases, base resistance and base–collector capacitance appear in the
expressions. Even though fmax does not accurately represent the device
performance at high frequencies, the qualitative effect of reducing base
resistance and base–collector capacitance is apparent. A further discussion
on the computational aspects of determining the various components of fT
from device simulations will be presented in chapter 5.
3.8. BREAKDOWN VOLTAGE, BVCEO
Although several breakdown voltages are defined for a bipolar transistor,

the most important is the collector–emitter breakdown voltage, BVceo ,
as it determines the maximum supply voltage that can be applied. The
collector–emitter breakdown is limited by two different reverse bias junction
breakdown mechanisms: Zener and avalanche. Zener breakdown occurs
when both sides of a junction have high dopant concentrations. Avalanche
breakdown occurs when a large electric field appears across the depletion
region causing an impact ionization and generation of electron–hole pairs.
BVceo , limited by avalanche breakdown, occurs when the product of the
avalanche multiplication factor and dc current gain approaches unity. For
design purposes it is often approximated by [40]
BVcbo
BVceo √ (3.37)
m
β
where BVcbo is the base–collector breakdown voltage with emitter open-
circuited and m ranges from 2–3 for silicon [41].
In general, the optimization of breakdown voltages for a homojunction
transistor and an HBT does not differ. However, extension of the Ge profile
into the collector region to avoid the parasitic heterojunction barriers may
lead to increased impact ionization. But simulations of carrier energy
seem to indicate that impact ionization is more likely to occur deeper into
the collector than originally thought [42]. Therefore, a narrow bandgap
Si1−x Gex -base may not affect the breakdown voltage. A trade-off exists
between the breakdown voltage and the collector velocity saturation effects.
Increases in breakdown voltage for both emitter–base and base–collector
junctions have been obtained by placing lightly-doped spacers on both sides
of the heavily-doped base without incurring collector velocity saturation
effects [43–45].
3.9. SUMMARY
The objective of this chapter has been to describe the basic physics of
SiGe HBTs. Use was made of energy band diagrams in deriving the
expression for collector current in the most general case of a graded base
SiGe HBT. It was evident that significant enhancement in current gain,
base transit time and Early voltage is possible with the incorporation of
germanium in the base region. The way in which the resultant reduction
of emitter and base transit times leads to a corresponding enhancement
in high-frequency performance measures such as fT and fmax was clearly
indicated. The onset of a parasitic conduction band barrier at the base–
collector junction through out-diffusion of boron from the base was shown
to be undesirable, since it increases minority carrier storage in the base,
and reduces both collector current and fT . Consequently, the advantage in
use of thin undoped SiGe spacer layers between base and emitter and base
and collector was discussed.
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Chapter 4
DESIGN OF SIGE HBTS
As semiconductor technology continues to evolve, numerical modelling of

the electrical behaviour of advanced devices has become vital. Numerical
device modelling based on the self-consistent solution of the fundamental
semiconductor equations dates back to the famous work of Gummel in
1964 [1]. In Gummel’s one-dimensional (1D) discretization, the Poisson
equation and the current continuity equations are decoupled and solved
sequentially until convergence. Gummel’s approach was later extended by
de Mari [2] and applied to transient simulations of a 1D p–n junction. A
very important breakthrough in the discretization of the current transport
equations was reported by Scharfetter and Gummel in 1969 [3]. The
Scharfetter–Gummel (SG) discretization scheme has since been used by
all important device simulation programs.
During the 1970s and 1980s, several 1D and 2D programs were
developed, and made freely available to the research community. Examples
include SEDAN [4] for 1D simulations, MINIMOS [5] for 2D MOS
transistor simulations, BAMBI [6] for arbitrary semiconductor structures
and PISCES [7], a 2D finite-element simulator, which rapidly became an
industry standard and formed the basis of future commercial products such
as Silvaco–ATLAS [8], Avant–Medici [9] and PISCES–2ET [10].
In 1977, Sutherland and Hauser [11] were the first to use numerical
techniques to analyse heterojunction devices. They showed that the basic
formulation for homojunction devices could easily be generalized to include
the effects of a position-dependent band structure. The formulation was
further developed [12] to include field-dependent mobility to fit the steady-
state velocity field characteristics, and later expanded to treat degenerate
semiconductors via Fermi–Dirac statistics [13–15].
HQUPETS [16] was an early 2D simulation tool developed for SiGe
HBTs, and has been extensively used for device design [17]. Several
advanced 1D simulators, specific to SiGe HBTs, such as a simulator
for cryogenic research and silicon–germanium bipolar device optimization
104
Design of SiGe HBTs 105
(SCORPIO) [18] and PROSA [19], have been reported.

Although the drift–diffusion (DD) model is the most widely used
and understood tool for semiconductor device simulation, it unfortunately
fails to predict non-stationary transport effects. As a derivative of
the Boltzmann transport equation (BTE), it also fails to reflect the
quantum mechanical nature of carrier transport. The continuous push
toward smaller devices has led to a need to address these shortcomings,
and to the development of more sophisticated physical models, such as
the hydrodynamic and energy transport models [20, 21], the spherical
harmonics expansion method [22] and the Monte Carlo technique [23–27].
Unfortunately, since the Monte Carlo method involves keeping statistics on
a large number carriers undergoing random collisions, it is very expensive
in terms of computer time. The simulation of a complete transistor requires
tracking a prohibitive number of carriers in order to attain statistical
significance. This typically limits the Monte Carlo technique to use an
aid in studying only part of the transistor, for instance the emitter–base
junction.
In the hydrodynamic or energy transport model, the first three
moments of the BTE are taken, yielding the particle, momentum and
energy conservation equations [20]. To solve these equations, it is generally
necessary to make many assumptions (for instance invocation of the
relaxation time approximation). As the drift–diffusion model is pushed
to its limits, more people are trying the hydrodynamic method of solution.
A complete hierarchy of approaches and analyses has been reviewed by
Ravaioli [28]. However, the increased rigour of such models comes at the
expense of increased CPU time, so for the simulations reported in this
book we confine our discussion almost exclusively to the drift–diffusion
model. Regardless of the modelling methodology used, the ultimate
responsibility will always rest on the user of the simulator to intelligently
interpret the results and know when the assumptions inherent to the
method are being violated. Otherwise, as was pointed out by Tang
and Laux [29], ‘. . . computationally sophisticated 2D or even 3D device
simulations are rendered merely expensive, and perhaps misleading, curve-
fitting programs’.
The aim of this chapter is to give some insight into the formulation
of a physical device model for a SiGe HBT and to show how it can
be applied for HBT transistor design. The model equations account for
the position-dependent variation of energy bandgap, the dependence of
mobility on different scattering mechanisms, carrier velocity saturation,
doping-dependent carrier lifetime and heavy doping effects. The resulting
HBT model corresponds closely to that implemented in the Silvaco–ATLAS
device simulator [8], which has been used in a number of the examples
considered. A number of studies are presented where model prediction is
compared to measured data.
106 Design of SiGe HBTs
4.1. DEVICE MODELLING
Physically based device simulation predicts the electrical characteristics

associated with a specified physical structure and bias conditions. This
is achieved by mapping the structure onto a two-dimensional or three-
dimensional grid consisting of a number of grid points called nodes. By
applying a set of partial differential equations, derived from Maxwell’s
equations to this grid, the transport of carriers can be simulated. By
specification of appropriate boundary conditions, dc, ac and transient
modes of operation can be modelled. Physical simulation has two
important characteristics. It is much quicker and cheaper than performing
experiments. In addition it provides information that is difficult or
impossible to measure. The main drawback is that all the relevant physics
must be incorporated into the simulator. The user must specify the problem
to be solved by defining:
• the physical structure;
• the physical models; and
• the bias conditions for which electrical characteristics are required.
A basic requirement for a successful physical simulation of a
semiconductor device is a mathematical model describing its operation.
The model is characterized by a set of fundamental equations which link
the electrostatic potential and the carrier densities within some predefined
simulation domain. These equations are derived from Maxwell’s laws and
consist of Poisson’s equation and the continuity equations for electrons and
holes. Poisson’s equation relates variations in electrostatic potential to the
space-charge density and is given by,

∇ · (∇ψ) = −q p − n + ND+ − NA− − ρs (4.1)
where ψ is the electrostatic potential, is the local dielectric permittivity,

q is the charge of an electron, p and n are the hole and electron
concentrations, ND and NA are the ionized donor and acceptor impurity
concentrations and ρs is the surface charge density.
The continuity equations, which describe the way that electron and
hole carrier densities evolve as a result of transport processes, generation
and recombination processes, are given by,
∂n 1
= ∇ · J5n + (G − R) (4.2)
∂t q
∂p 1
= − ∇ · J5p + (G − R) (4.3)
∂t q
where Jn and Jp are the electron and hole current densities, and G and R
are the generation and the recombination rates, respectively. The above
Device modelling 107
equations provide the general framework for device simulation. However,

further secondary equations are necessary to specify particular physical
models for current density, generation recombination rates. The current
density equations are usually obtained by applying approximations and
simplification to the BTEs. These assumptions can result in a number of
possible transport models such as the drift–diffusion model [30], the energy
balance and the hydrodynamic models [20]. The choice of transport model
can impact on the choice of generation and recombination model. By far
the simplest and most commonly used model in device simulation is the
drift–diffusion model. Until recently this model was adequate for nearly
all semiconductor devices but it tends to become less accurate for small
feature sizes [28].
In the drift–diffusion model, the current densities are expressed in
terms of quasi-Fermi levels Φn and Φp as
J5n = −qµn n∇φn (4.4)

J5p = −qµp p∇φp (4.5)
where µn and µp are the electron and hole mobilities. Using Boltzmann
approximations, the quasi-Fermi levels may be related to the carrier
concentrations and the potential as given by

q (Ψ − φn )
n = nie exp (4.6)
kTL

−q (Ψ − φp )
p = nie exp (4.7)
kTL
where nie is the effective intrinsic carrier concentration and TL is the lattice
temperature. These two equations may then be rewritten as
kTL n
Φn = ψ − ln (4.8)
q nie
kTL p
Φp = ψ + ln . (4.9)
q nie
By substituting these equations into the current density expressions,
one obtains
J5n = qDn ∇n − qnµn ∇Ψ − µn nkTL ∇ (ln(nie )) (4.10)
J5p = −qDp ∇p − qpµp ∇Ψ + µp pkTL ∇ (ln(nie )) (4.11)
where the last term accounts for the gradient in the effective intrinsic carrier
concentration, taking into account bandgap narrowing effects. Effective
electric fields are given by

5 kTL
En = −∇ ψ + ln nie (4.12)
q

kTL
E5p = −∇ ψ − ln nie . (4.13)
q
From the above and using Einstein relationships, the familiar drift–diffusion
expressions are as follows:
J5n = qµn E5n + qDn ∇n (4.14)
J5p = qµp E5p − qDp ∇p. (4.15)

In the case of Boltzmann statistics, Dn and Dp are given by
kTL
Dn = µn (4.16)
q
kTL
Dp = µp . (4.17)
q
In the case of the energy balance (EB) model, a higher-order solution to
the generalized BTE is necessary to include an additional coupling of the
current density to the carrier temperature (energy). Then the current
density and energy flux densities are expressed as
J5n = qDn ∇n − µn n∇Ψ + qnDnT ∇Tn (4.18)

kδn 5
S5n = −Kn ∇Tn − Jn Tn (4.19)
q
J5p = qDp ∇p − µp p∇Ψ + qpDpT ∇Tp (4.20)

kδp 5
S5p = −Kp ∇Tp − Jp Tp (4.21)
q
where Kn,p and δn,p are respective transport coefficients for electrons and
holes that depend on the corresponding carrier temperatures Tn and Tp .
Sn and Sp are the flux of energy (or heat) from the carrier to the lattice.
Full details of the formulation are given in [31].
4.2. NUMERICAL METHODS
Several different numerical methods can be used to solve the semiconductor

equations. In general, there are three approaches: decoupled (Gummel
method), fully coupled (Newton method) or a combination method. The
decoupled method will solve for each unknown in turn keeping other
variables constant, repeating the process until a stable unchanging solution
is achieved. Fully coupled techniques, such as the Newton method, solve the
total system of unknowns together. The combined method will only solve
some of the equations fully coupled. The Newton method is the preferred
Numerical methods 109
method as it offers quadratic convergence, provided a suitable initial guess

can be estimated. Because of this constraint, it is always advisable to use
small incremental changes to the applied voltage.
In performing a simulation, the device starts with zero bias on all
electrodes. Solutions are obtained by stepping the bias on electrodes from
this initial equilibrium condition, using small steps in voltage. Once a
solution is obtained, the current flowing through each electrode is calculated
by numerical integration. Internal quantities, such as carrier distributions
and electric field throughout the device, can then be computed or presented
graphically.
There are several ways to predict the small-signal and large-signal
high-frequency properties of semiconductor devices. A review of these
different techniques has been given by Laux et al [32]. Frequency domain
perturbation analysis is used to calculate the small-signal characteristics,
while Fourier analysis is required for a large-signal response. In
ATLAS, frequency domain perturbation of a dc solution can be used
to calculate small-signal characteristics at any frequency. Variables are
represented as the sum of a known dc component and an unknown
sinusoidal ac component. The semiconductor equations are expanded with
differentiation in time becoming equivalent to multiplication by jω. The
dc solution is subtracted, and what remains is a complex linear system
whose unknowns are the ac components. Solving this linear system gives
the small-signal y-parameters. If the Newton method is used for the dc
solution, then the Jacobian matrix associated with the dc operating point
can be used directly in the small-signal analysis without recomputation. If
the semiconductor device is treated as a two port network, with defined
input and output ports, then knowledge of the y-parameters permits all
other small-signal parameters to be calculated. The advantage of this
approach is that the determination of y-parameters is based solely on
the physical structure, and hence does not rely on any predefined lumped
element equivalent circuit model.
These y-parameters can then be used to find different power gains [33].
Among the various power gains described so far in the literature several,
such as maximum available gain (MAG), maximum stable gain (MSG)
and maximum available unilateral gain (MAUG), have found widespread
use. Additionally, a figure-of-merit that has been used extensively for
microwave characterization is Mason’s invariant U (or Mason’s gain).
These quantities are calculated from the measured small-signal scattering
parameters because of the ease of measurement at high frequencies.
All the above mentioned gains can be conveniently expressed in
y-parameters as follows:

y21
M SG = (4.22)
y12

y21
MAG = k − k2 − 1 (4.23)
y12
where
2Re(y11 )Re(y22 ) − Re(y12 y21 )
k= (4.24)
|y12 y21 |
|y21 − y12 |2
U= (4.25)
4[Re(y11 )Re(y22 ) − Re(y12 )Re(y21 )]
|y21 |2
MAU G = . (4.26)
4Re(y11 )Re(y22 )
Maximum available gain is obtained when both input and output are
simultaneously conjugately matched. MAG exists only when the device
is unconditionally stable when k > 1. As can be seen from equations (4.25)
and (4.26), U equals MAUG only if the device is unilateral, i.e., y12 = 0.
MAG and MSG are equal to each other once the device is unconditionally
stable. The frequency at which MAG becomes unity is often defined as
fmax . However, a full discussion on the interpretation of fmax is given
in [34]. Since common-emitter microwave transistors may have power gain
with no impedance transformation, they can have useful gain when inserted
into a 50 Ω system. This gain is identical to |s21 |2 .
ATLAS has an option to easily convert y-parameters obtained from
ac analysis, to s-, z- or h-parameters. The unity gain cut-off frequency
is extracted from extrapolation of the high-frequency asymptote of a plot
of the magnitude of h21 in dB versus log (frequency). Most BJT devices
at a sufficiently low frequency can be represented as single pole devices.
This assumption is equivalent to a high-frequency asymptote with a slope
of −20 dB per decade. However, both Cbe and Cbc capacitances are bias
dependent, and so is the cut-off frequency. From the MAG (in dB) versus
log (frequency) plot, fmax is extracted at the point where MAG becomes
0 dB.
4.3. MATERIAL PARAMETERS FOR SIMULATION
Electrons and holes in a device are accelerated by electric fields but lose
momentum as a result of various scattering processes. These scattering
mechanisms include lattice vibrations, impurity ions, other carriers,
interfaces and material imperfection. To simplify these mechanisms for
modelling purposes, mobility is usually defined as a function of lattice
temperature, local electric field and doping concentration. In a device
simulator, a mobility model is further subdivided into
• low-field behaviour,
Material parameters for simulation 111
• high-field behaviour,
• bulk semiconductor regions, and
• inversion layers.
In the low-field region, mobility is principally dependent on phonon

and impurity scattering, both of which tend to decrease the low-field
mobility. High-field behaviour shows that carrier mobility decreases with
electric field. The mean drift velocity no longer increases linearly with
increasing electric field, but rises more slowly. Eventually the velocity
saturates at a constant velocity commonly denoted by the symbol vsat
which is principally a function of lattice temperature. Modelling mobility
in bulk material involves characterizing µn0 and µp0 as a function of doping
and lattice temperature and describing the transition between low-field and
high-field regions. Modelling carrier mobility in inversion layers presents
additional complications due to surface scattering and quantum mechanical
effects. These effects are important for accurate simulation of MOS devices.
The transverse electric field is often used to characterize mobility variation
within inversion layers.
In ATLAS, a wide (and somewhat baffling) range of different silicon
mobility models is available. Full details are given in the ATLAS manual
[8]. The low-field mobility can be characterized in five different ways: user
defined; a lookup table as a function of doping; an analytic function of
doping and temperature [35]; a carrier scattering model relating mobility
to carrier concentration and temperature; or a unified model dependent on
impurity, lattice and carrier–carrier scattering and temperature [36,37]. For
bipolar device simulation, the latter model is recommended as it applies a
unified description of minority and majority carrier mobilities. The model
shows excellent agreement with available experimental data.
As carriers are accelerated in an electric field, their velocity will begin
to saturate at a high electric field. This effect has to be accounted for by
a reduction of effective mobility, since the drift velocity is the product of
mobility and electric field in the direction of current flow. The following
expression [38] is used to implement a field-dependent mobility for both
holes and electrons, that provides a smooth transition between low-field
and high-field behaviour,
β β1
µo E
µ(E) = µo 1 1+ (4.27)
vsat
where µo is the low-field mobility, E is the electric field parallel to the

direction of current flow, β is a constant, and vsat is the saturation velocity.
The coefficient β is one for holes and two for electrons. The saturation
velocity vsat is calculated by default from the temperature-dependent
model,
2.4 × 107
vsat (T ) = (4.28)
1 + 0.8 exp (T /600)
but specific values for holes and electrons can be specified, if required.
The incorporation of germanium significantly changes the properties
of the base region and the emitter–base and base–collector junctions in a
SiGe HBT. While silicon has been well characterized over the past 40 years,
still not nearly as much is known about strained-SiGe. Many simplifying
assumptions are made in the SiGe material parameters. The addition of
Ge reduces the bandgap of Si, leading to the narrow bandgap SiGe base of
the HBT, as discussed in chapter 3. The lattice constant of the strained-
Si1−x Gex alloy differs considerably from that of Si. The incorporation
of Ge also modifies the energy band structure, and density of states in
the conduction and valence bands. In addition, carrier mobilities and
diffusivities change owing to changes in the effective masses and alloy
scattering. Finally, the dielectric constant, built-in potentials and depletion
widths in the p–n heterojunctions depend on the Ge concentration. As all
the device simulations reported in this book have been carried out using
the Silvaco–ATLAS simulator [8], we consider in the following section, the
material parameters used in the simulations.
4.3.1. SiGe: hole mobility

There have been few reports on the measurements of mobility in strained-
Si1−x Gex alloys. Mansevit et al [39] reported enhanced electron mobilities
at room temperature, but the Ge mole fraction of the samples was not
accurately known. Monte Carlo simulations of electron mobility heavily-
doped SiGe at room temperature indicate that µn will be almost 50% higher
than for silicon due to the smaller effective mass in SiGe [40]. Enhanced
low-temperature mobilities have been also observed for both holes and
electrons [41]. In addition to phonon, impurity and alloy scattering
mechanisms, strain is expected to play a major role in determining carrier
mobility. Due to strain effects, mobilities in SiGe are different for carriers
travelling parallel and perpendicular to the direction of growth.
In ATLAS version 5.0, there is no specific SiGe mobility model
incorporated, but a separate user specified model can be created by
writing specific functions in the C programming language, which are then
interpreted when running the simulation. For this purpose, a hole mobility
model may be based on a model developed by Mau [42] originating from
an empirical fit to experimental data. The electron mobility model may be
based on theoretical computations by Manku and Nathan [43].
The composition, temperature and doping dependent hole mobility is
given by:
(i) for majority carriers

−0.45 −2.2 −0.45
T 480.0 (T /300) − 49.0 (T /300)
µp = 49.0 + (4.29)
300 1.0 + (T /300)
−2.4
(Ntot /1.7 × 1017 )
0.74
(ii) for minority carriers

−0.45
T 480.0(T /300)−2.2 − 122.3(T /300)−0.45
µp = 122.3 + 0.7 ρ
300 (1.0 + (T /300)−2.4 ) (Ntot /1.4 × 1017 )
−1
1.0
× 1.0 + 2 (4.30)
0.5 + (7.2 × 1020 /Ntot )
where

(µmax (x) − µmin (x))
ρ= µmin (x) +
1 + (Ntot /2.35 × 1017 )0.88
−1
µmax (0) − µmin (0)
× µmin (0) + (4.31)
1 + (Ntot /2.35 × 1017 )0.88
where
µmin (x) = 68.7 exp 51.2x3 − 34.2x2 + 8.7x (4.32)
and
µmax (x) = 461.9 exp 32.5x3 − 22.2x2 + 6.4x . (4.33)
4.3.2. SiGe: electron mobility

The alloy scattering limited electron mobility components for coherently
strained Si1−x Gex , along directions perpendicular and parallel to the
growth direction are given by [43]
5.5 × 1018 T
µalloy
⊥ = (4.34)
22.0Nc x(1 − x)m2t
5.5 × 1018 T
µalloy
= (4.35)
4.0Nc x(1 − x)m2l
where Nc is the effective density of states for silicon.
It may be noted that the alloy mobility decreases with increasing Ge
content. At low doping levels, alloy scattering and phonon scattering
predominate, both of which have an E 1/2 dependence. At high doping
levels, impurity scattering becomes important, and it too has the same
energy dependence. Since the conduction band of SiGe for x < 0.3 is
similar to that of silicon, and all the predominant scattering rates have an
E 1/2 dependence, the individual parallel and perpendicular components

may be defined.
The parallel component of electron mobility in SiGe can thus be
obtained by using Mathiessen’s rule
1 1 1
= Si + alloy (4.36)
µSiGe
µ µ
and the corresponding perpendicular component becomes

1 1 1
= + alloy (4.37)
µSiGe
⊥
Si
µ⊥ µ⊥
where the mobility of silicon for parallel and perpendicular to the growth
plane is expressed as [43]
3.0µSi
µSi
⊥ = (4.38)
(mt /ml + 2.0)
3.0µSi
µSi
= (4.39)
2.0(ml /mt ) + 1.0
where ml and mt are longitudinal and transverse density of state masses
in silicon.
At very high concentrations, the Caughey–Thomas relationship [38]
no longer suffices to describe the carrier mobility. The effect of ultrahigh
concentrations on mobility have been analysed by Klaassen [36], and the
modified expression for majority and minority mobility for electron in sili-
con is given by:
(i) for majority carriers

−0.45
Si T 1430.0(T /300)−2.3 − 74.5(T /300)−0.45
µ = 74.5 + Z
300 (1.0 + (T /300)−2.6 (Ntot /8.6 × 1016 )0.77
(4.40)
(ii) for minority carriers
−0.45
Si T 1430.0(T /300)−2.3 ) − 200.0(T /300)−0.45
µ = 200.0 +
300 (1.0 + (T /300)−2.6 )(Ntot /5.3 × 1016 )0.68 )
(4.41)
where
1.0
Z = 1.0 + (4.42)
0.21 + (4.0 × 1020 /Ntot )2
where Ntot is the total doping and the ‘clustering’ function Z(N ) is fitted
analytically.
To evaluate the mobility of strained-SiGe, alloy scattering as well as

energy shifts in the conduction band have to be included. The shifts
are taken into account through the electron concentration, since the
total mobility is given by a weighted average of the unstrained electron
concentration of the ith conduction band, with the corresponding strained
electron concentration.
The components of the total electron mobility of strained-SiGe, for the
growth plane µxx , and plane parallel to the growth direction µzz , can be
represented as [43]

µSiGe
⊥ + µSiGe
exp(−∆Ex /kT ) + µSiGe
⊥ exp(−∆Ez /kT )
µxx = (4.43)
2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT )
2.0µSiGe
⊥ exp(−∆Ex /kT ) + µSiGe
exp(−∆Ez /kT )
µzz = (4.44)
2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT )
where ∆Ex = −0.21x and ∆Ez = 0.42x are the splitting energies due to
the shift in the [001], [010] and [100] bands.
Despite the apparent complexities of the latter model, a more
straightforward model has been proposed in the 1D SCORPIO simulator
[18], which describes the mobility enhancement of both carriers in SiGe as
a linear function
µSiGe (x) = (1 + K.x)µSi (4.45)
where K is a fitting constant taken to be 10. Although there are conflicting
reports concerning the degree of SiGe mobility enhancement which occurs
in a HBT, Richey et al [18] conclude that their much simpler model gives
excellent agreement with measured data.
4.3.3. SiGe: bandgap

The most significant material parameter to be specified in the simulation
of SiGe HBTs is the bandgap narrowing induced by incorporation of a
Ge fraction x. A number of different models have been put forward.
Polynomial fits by Bludau et al [44] describe the temperature dependence
of the energy bandgap of pure silicon at or below room temperature. The
high-temperature model from Sze [45] is slightly modified to match the
room temperature value and is given by
Eg (T ) = 1.170 + 1.059 × 10−5 T − 6.05 × 10−7 T 2 0 ≤ T ≤ 170 K (4.46)
Eg (T ) = 1.1785 − 9.025 × 10−5 T − 3.05 × 10−7 T 2 170 ≤ T ≤ 300 K

(4.47)
4.73 × 10−4 T 2
Eg (T ) = 1.170 − T ≥ 300 K. (4.48)
T + 624.93
An empirical a fit to the data provided by People [46] for the bandgap

of strained-Si1−x Gex alloys on Si(100) substrates is given by
Eg (x) = 1.124 − 1.22x + 0.88x2 x ≤ 0.6. (4.49)
A linear fit is used for 0.6 < x < 1.0, which assumes that the bandgap of
strained pure Ge on (100) Si is 0.6 eV. Note that the bandgap of strained-
SiGe is considerably smaller than that of bulk-SiGe.
In ATLAS, to give increased accuracy, the SiGe bandgap is modelled
by a complex piecewise linear function of x, as defined in full in the ATLAS
manual. For values of x likely to be encountered in a SiGe HBT (x < 0.245),
the following equation applies
Eg (x) = 1.08 + x(0.945 − 1.08)/0.245. (4.50)
In ATLAS, an alternative temperature dependence of the bandgap Eg (T )

for SiGe is given as

αT 2 3002 T2
Eg (T ) = Eg (0) − = Eg (300) + α − (4.51)
T +β 300 + β T +β
where the composition dependences of α and β are given by:
α = (4.73(1 − x) + 4.77x)10−4
β = 636.0(1 − x) + 235.0x.
The electron affinity of SiGe is assumed to be independent of the

composition x and equal to 4.07 eV, identical to that of Si.
In a BJT model, the intrinsic carrier concentration nio , which depends
on the effective density of states in the conduction and valence bands and
the bandgap, plays an important role. The effective conduction and valence
band density of states in silicon are given by the well-known expressions:
3/2 3/2
2πm∗n kT 2πm∗p kT
Nc = 2 Nv = 2 (4.52)
h2 h2
where h is Planck’s constant, and m∗n and m∗p are the effective masses of
the electron and hole density of states.
The effective density of states decreases with increasing Ge content,
because the amount of degeneracy in both the valence and conduction
band decreases [43, 47]. In ATLAS, an empirical function used to give the
composition dependence of densities of states for SiGe is given by:
Nc = 2.8 × 1019 + x(1.04 × 1019 − 2.8 × 1019 ) (4.53)
Nv = 1.04 × 1019 + x(6.0 × 1018 − 1.04 × 1019 ). (4.54)

By using equations (4.53) and (4.54), one can calculate the intrinsic carrier
concentration as a function of the Ge content

2 Eg (x, T )
nio (x) = Nc Nv exp − . (4.55)
kT
In addition to the Ge-induced bandgap narrowing, the high doping in the

base induces additional bandgap narrowing, similar to that observed in
silicon. Although several bandgap narrowing and mobility models have
been proposed for silicon [48–50], little information is available in the
literature for Si1−x Gex [51]. The default model in ATLAS version 5.0
assumes that the bandgap narrowing due to heavy doping is the same
as that in silicon. This approach has the advantage that any differences
in the simulation of Si BJT and SiGe HBTs can then be unambiguously
attributed to heterojunction action (due to Ge incorporation), rather than
differences in model parameters. This assumption of equal values of doping-
induced bandgap narrowing in silicon and Si1−x Gex is reasonably good for
base doping concentrations up to approximately 1 × 1019 cm−3 [51], but
for higher concentrations there is some evidence [52] to suggest that the
bandgap narrowing in Si1−x Gex is lower than that in silicon.
Bandgap narrowing effects due to heavy doping are modelled by
replacing the intrinsic carrier concentration nio with an effective carrier
concentration nie (x, y) where
  1/2 
 N (x, y) 2 
qa 1 N (x, y)
nie (x, y) = nio exp  ln + ln + a3 
2kT  a2 a2 
(4.56)
where a1 = 0.00692, a2 = 1.3 × 1017 cm−3 and a3 = 0.5 are model

parameters. In ATLAS, the dielectric constant of SiGe as a function of
composition is given by
= 11.9 + 4.1x. (4.57)
4.3.4. Recombination and carrier lifetime

The dominant recombination processes in bulk-Si are Shockley–Read–Hall
(SRH) and Auger recombination. Radiative recombination is negligible
since silicon is an indirect bandgap semiconductor, and recombination
involving excitons and shallow-level traps is only important at low
temperature. The total recombination rate due to Auger and SRH
recombination can be written as:

1
R = An n + Ap p + np − n2ie . (4.58)
τn (p + p1 ) + τp (n + n1 )
In equation (4.58), An and Ap are the electron and hole Auger

recombination coefficients and nie is the effective intrinsic carrier
concentration including bandgap narrowing effects. τn and τp are the
minority carrier SRH lifetimes and n1 and p1 are constants which depend
on the energy of the deep-level traps. Commonly used (default) values for
the radiative and Auger recombination coefficients are An = 5.0×10−32 and
Ap = 9.9 × 10−32 for silicon [53]. Since strained-SiGe is similar to silicon
in band structure, exactly the same recombination model is assumed for
SiGe.
The minority carrier lifetimes in silicon are doping-dependent. For
doping concentrations up to 1019 cm−3 , an empirical fit to experimental
data gives
τ (0)
τ (N ) = (4.59)
1 + N/N0
for both electrons and holes. τ (0) is the minority carrier lifetime in lightly-
doped silicon and N0 is the reference doping. A good fit to experimental
data is achieved by setting N0 = 7.1 × 1017 cm−3 for both n- and p-
type silicon, τ (0) = 3.95 × 10−4 s for holes and τ (0) = 1.70 × 10−5 s for
electrons [54]. However, τ (0) is very much process dependent. Studies
on the determination of minority carrier lifetime in SiGe have shown that
the lifetimes are believed to be somewhat shorter than silicon minority
carrier lifetimes (in the nanosecond range), due to the large number of
misfit dislocations.
4.4. HISTORY OF SIMULATION OF SIGE HBTS

Numerous papers have appeared in the literature on both the numerical
and analytical modelling of the SiGe HBTs [40, 55–61]. Much of the early
work on simulation of SiGe HBTs was carried out over a decade ago and
significant improvements in performance have since been achieved.
Smith and Welbourn [40] reported that for a SiGe transistor with a
0.15 µm thick strained layer base (with 15% Ge, ∆Ev = 170 meV and 50%
enhancement of electron mobility due to strain) an fT of 20 GHz should
be realizable before the onset of base widening. The value of fmax was
estimated to be 40 GHz. This represented a threefold increase of speed
over the homojunction devices at that time. Pejcinovic et al [56] simulated
numerically the small-signal performance of a SiGe HBT. The heavy doping
effect in SiGe was assumed to be the same as in Si, and effects of strain and
alloy scattering on the mobility were included in the model. The doping
concentrations in the emitter, base and collector were 7×1019 , 2×1019 and
4.5 × 1017 cm−3 , respectively. The authors found that for the Ge fraction
x = 0.2, the turn-on voltage of the HBT was smaller by 0.12 V as compared
to an otherwise identical Si homojunction transistor. The frequency fT was
twice as large as in the Si transistor and fmax was even larger.
Experimental SiGe HBTs 119
In early 1989, Won and Morkoc [60] examined theoretically the high-
speed capability of the SiGe HBTs. They included alloy scattering and
strain effects on the mobility in the model. Several doping concentrations
were considered. The collector and base doping concentrations were
optimized by making a compromise between speed and breakdown voltage.
If the parameters are optimized to obtain an fT of 75 GHz, the estimated
fmax value is 35 GHz at a current density of 1×105 A cm−2 and Vbc = 5 V.
The theoretical work done during this period showed that the HBTs had
great promise, once technological problems encountered in their fabrication
were resolved.
Hueting et al [61] have optimized a SiGe HBT design for high-
frequency performance and claimed that a box type Ge profile with the
leading edge approximately in the middle of the base is optimal. The
doping concentrations in the emitter, base and collector were 2 × 1021 ,
2.2 × 1018 and 1 × 1017 cm−3 , respectively, while the Ge concentration in
the base was 11.5%. An fT value of 45 GHz for a base thickness of 600 Å
was obtained. Hueting et al studied the effect of grading the Ge profile
in the base and concluded that (in their opinion) the grading of Ge in the
base is of minor importance. Several other simulation techniques such as
Monte Carlo [62–64], energy transport [19, 65] have also been employed for
the simulation studies of SiGe HBTs.
4.5. EXPERIMENTAL SIGE HBTS
Since the introduction of SiGe into conventional Si technology, various

research groups have demonstrated high-performance SiGe base HBTs with
differing approaches to forming the Ge profile in the base. While the IBM
group uses graded Ge profiles, the Daimler–Benz group focuses on SiGe
HBTs with a uniform Ge box profile. The epitaxial growth of active device
regions in Si-based technology is a significant departure from past device
fabrication, where epitaxy had been used solely for the controlled substrate
formation. Epitaxial base technology has many advantages over an ion-
implanted technology.
A box-like profile provides independent control over base width and
doping concentration. Thus, a base width as small as 30 nm, with a
very high doping concentration, can be obtained. Even for these small
thicknesses, the base resistance is acceptable and punch-through is avoided.
This allows reduction of charge storage in the emitter and independent
control of base resistance and base transit time. By tailoring the base
profile, low values of emitter–base and base–collector capacitance, Cbe and
Cbc , can be obtained. The design can also be tailored for optimum ECL
performance in a digital circuit by obtaining high fT at low base resistance.
Epitaxial base technology provides the opportunity to independently
control each of the delays defined in equation (3.31). Transit time is
reduced by both vertical scaling and Ge grading in the base. Self-aligned

epitaxial base technology also allows reduction of extrinsic capacitances
and resistance to reduce the gate delays [66, 67]. Harame et al [68] have
developed a high-performance SiGe BiCMOS HBT process. During the
emitter formation, considerable out-diffusion of boron takes place as the
diffusion coefficient of boron is considerably larger than that of arsenic.
The problem of boron out-diffusion can be avoided, and narrow bases can
be formed, if arsenic is replaced by phosphorus for doping the emitter [69].
The diffusivity of phosphorus is much larger than that of arsenic and is
close to that of boron. In the devices designed and fabricated by Crabbe
et al [69], phosphorus-doped emitters were used. The epitaxial SiGe bases
were grown by UHVCVD [70] at 550 ◦ C. The Ge profile was graded from
0% at the emitter–base junction to 15% at the base–collector junction.
The collector doping was 4 × 1017 cm−3 to avoid base widening at high
current densities. Lightly-doped spacers were placed in the emitter–base
and base–collector junctions to maintain reasonable values of BVebo and
BVceo . The narrow base width reduced the intrinsic transit time from
2.1 ps to 1.9 ps [71]. The cut-off frequency was 73 GHz at a collector
current density of 2 mA µm−2 . The peak fmax was only 26 GHz, due
to high extrinsic base resistance caused by insufficient activation of boron
because of low emitter anneal temperature.
Gruhle et al [72] fabricated a high-performance MBE-grown SiGe
transistor. Ge concentrations of 21–28% and boron concentrations of up
to 2 × 1020 cm−3 were used to obtain simultaneously high current gains
and low base resistance. The SiGe HBT with the highest fmax (in 1995)
was reported by Schuppen et al [73]. This transistor used a relatively thick
(60 nm) base and heavy doping to minimize the intrinsic base resistance.
The base transit time was reduced by a strong electric field with 0–15%
Ge grading. The SiGe base was grown selectively by using a self-aligned
CVD technology. The performance achieved was an fmax of 160 GHz and
a gate delay of 19 ps in an ECL circuit. In the same year, Meister et al [74]
reported a SiGe HBT with a 74 GHz fmax , resulting in a record CML gate
delay (at that time) of 11 ps.
Recently, a 0.2 µm self-aligned selective epitaxial growth (SEG) SiGe
HBT, with shallow-trench and dual deep-trench isolations and Ti–salicide
electrodes, has been developed. The process, except for the SEG, is almost
completely compatible with well-established silicon BiCMOS technology.
The SiGe HBTs exhibited a peak fmax of 107 GHz and a record minimum
ECL gate delay of 6.7 ps [75]. An Si/Si0.65 Ge0.35 abrupt HBT with transit
frequencies fT of 133 and 213 GHz at 300 and 77 K, respectively, has
been announced recently [76]. The corresponding maximum oscillation
frequencies are 81 and 115 GHz. A detailed analysis of the intrinsic delay
times has shown that the base transit time plays the dominant role.
Device design issues 121
4.6. DEVICE DESIGN ISSUES
In the following sections, important parameters of SiGe HBTs (fT , fmax

and VA ) will be considered in detail and attempts are made to illustrate
how simulation has been used to optimize the device design for circuit
applications. Base, emitter and collector profile design issues at room
temperature will be discussed. All the simulations have been performed
using the Silvaco–ATLAS device simulator as described in sections 4.1 and
4.2, using default material parameters.
Figure 4.1. Doping profile and Ge profile (flat or box) of a SiGe HBT.
4.6.1. Base design
We consider a uniform (flat or box) Ge profile (x = 0.12) in the base.

The device structure and the doping concentration used for simulation is
shown in figure 4.1. A simulated band diagram comparing SiGe and Si
transistors is shown in figure 4.2. As can be seen in figure 4.3, the uniform
Ge box profile produces the sevenfold increase in β for 12% Ge at 300 K,
since the enhancement depends exponentially on the bandgap reduction
at the emitter–base junction. In the conventional Si BJT, β is inversely
Figure 4.2. Schematic band diagrams of a homojunction (Si BJT) and a

heterojunction (SiGe HBT) bipolar transistor.
Figure 4.3. Comparison of dc current gain of an Si BJT and a flat base SiGe
HBT.
proportional to the integrated base charge. Since base doping cannot be

increased indefinitely while maintaining adequate β, the flat Ge profile is
particularly useful in realizing a transistor with either a very high β, or a
moderate β with lower intrinsic base resistance.
However, any significant enhancement in peak fT of a SiGe HBT over
an Si BJT, depends principally on the utilization of Ge grading across the
base. The simulated peak cut-off frequency of 42 GHz for a uniform Ge
profile is shown in figure 4.4.
Now we consider a graded Ge profile (defined for reference purposes
as triangular) having 0% Ge at the emitter–base junction and 12% Ge
Figure 4.4. Simulated cut-off frequency of an Si BJT and a flat base SiGe HBT.
at the collector–base junction, as shown in figure 4.5. The Ge grading

(0–12%), is effective for reducing τb , and thus increasing fT . In this
type of Ge profile design, there is no Ge-induced bandgap reduction at
the emitter–base junction, and the β is reduced compared to the flat Ge
profile. However, as the β enhancement depends approximately linearly on
the Ge grading when there is no bandgap reduction at the emitter–base
junction, an enhancement in β of approximately 5 has been simulated. In
high-speed analogue applications, which require a high βVA product, the
triangular Ge profile would appear to offer a superior design [77]. Because
β is still enhanced for the triangular Ge profile, it is still possible to trade β
Figure 4.5. Doping profile and Ge profile (triangular) of a SiGe HBT.
for lower base resistance. Using this approach, both fT and base resistance
can be tailored to significantly increase fmax . It is seen from figure 4.6 that
for a graded Ge profile in the base, fT has increased from 42 GHz (Ge box
profile) to 63 GHz, but the gain has dropped from 360 to 200, as shown in
figure 4.7.
A trapezoidal profile would appear to be a logical compromise between
the two previous Ge profiles. This type of profile was used successfully
to realize the first 1.0 Gb s−1 12-bit digital-to-analogue converter [77].
Figures 4.8 and 4.9 show a simulation of a trapezoidal profile where the Ge
mole fraction at the emitter–base edge is 5% and it has been graded to reach
a maximum Ge concentration of 15% at the base–collector junction. It is
seen that the trapezoidal grading results in a good compromise between
peak current gain of 200, and fT of 50 GHz.
Figure 4.6. Comparison of peak cut-off frequency of a graded base versus a flat
base SiGe HBT.
4.6.2. Emitter design
An ideal emitter should provide low emitter saturation current density,

low emitter resistance, low charge storage, low emitter–base depletion
capacitance, and good passivation at the perimeter of the emitter. The
polysilicon emitter contact used in conventional Si technology meets most
of these requirements. The polysilicon–silicon interface also provides a
barrier-to-hole injection into the emitter. An alternative approach to the
polysilicon emitter contact is to use single-crystal emitter. Such a structure
Figure 4.7. Comparison of dc current gain of a graded base and a flat base SiGe
HBT.
is ideal to decouple the base from the emitter, thereby allowing arbitrarily
high base dopant concentrations. Furthermore, it allows a reduction in
emitter–base capacitance, leading to higher fT at lower collector current
density, as long as the delay associated with minority carrier charge storage
in the quasi-neutral emitter can be minimized by maintaining sufficient
current gain. A high–low emitter profile, consisting of a heavily-doped
polysilicon contact on top of a thin epitaxial emitter cap addresses both
requirements [78]. The emitter cap thickness should be small to minimize
charge storage and is typically 200–300 Å. The highly-doped polysilicon
contact ensures low total emitter resistance.
Figure 4.8. Comparison of dc current gains of flat, graded (triangle and

trapezoid) base SiGe HBTs.
Three different thicknesses of low-doped emitter, namely 100, 200 and

300 Å, have been used for simulation as shown in figure 4.10. The peak
value of Ge fraction x is 0.08. As expected, fT decreases marginally from
30 GHz as the emitter cap thickness is increased from 100 to 300 Å. The
location of the Ge profile with respect to the metallurgical emitter–base
junction plays a key role in the dc and ac characteristics of the HBT. For
an HBT with a linearly graded Ge profile and with a poly emitter contact,
locating the emitter–base metallurgical junction right at the bottom of
the Ge ramp is a good compromise to ensure moderate current gain while
Figure 4.9. Comparison of cut-off frequency of flat base, graded trapezoidal

base SiGe HBTs.
taking full advantage of the Ge grading to minimize the base transit time.
The slope of the Ge profile at the edge of the emitter–base space-charge
region on the base side can affect the ideality of the collector current [79].
4.6.3. Collector design

The design of the collector is dictated by conflicting requirements to
simultaneously achieve high breakdown voltage BVceo , low base–collector
capacitance, low base–collector signal delay τbc , and a high value of
Figure 4.10. Emitter with different low-doped spacer layers. Ge and Boron
profiles in the base are also shown.
the knee current density at which fT decreases. The collector doping

profile determines two critical performance parameters of the transistor:
the base–collector delay time τbc , which is a significant component of
the total intrinsic delay τec , and the intrinsic base–collector capacitance
which governs circuit performance. A conventional approach to suppress
base widening is simply to utilize a thin highly-doped epitaxial collector
layer. Consequently, base widening is suppressed at the expense of BVceo
degradation. One of the methods to increase BVceo , while suppressing base
widening, is to introduce a retrograde collector profile [80].
In determining HBT performance, it should be recalled that the
collector–emitter breakdown voltage BVceo is directly related to the
Figure 4.11. Different collector doping profile and Ge profile (triangular) of a

SiGe HBT.
cut-off frequency, according to the theoretical ‘Johnson limit’, and falls

monotonically for increasing values of fT [81]. A 50 GHz transistor
corresponds to a breakdown voltage of 3.3 V. In general, therefore, some
degree of optimization is always required to yield the appropriate higher
fT for a lower BVceo .
Increasing the peak collector doping density (Ncoll ) above 1 ×
1017 cm−3 improves the frequency performance in two ways:
(i) a reduction in transit time τbc giving increase in fT ; and

(ii) a delay onset of Kirk effect permitting operation at higher collector
current density since the Kirk (knee) current density (Jk ) is
proportional to the collector doping.
In simulations, as a compromise, we have assumed a minimum collector

concentration of 5 × 1016 cm−3 at the base–collector junction, and have
ramped the doping as shown in figure 4.11. Profiles 1, 2, and 3 correspond
to peak values of 1.5 × 1017 cm−3 , 2 × 1017 cm−3 and 4 × 1017 cm−3 at
a depth of 0.4 µm. The effects of the different collector profiles on fT are
shown in figure 4.12.
As expected, profile 3 (highest doping) produces the highest fT of
49 GHz. Early work on achieving high fT with SiGe HBTs utilized collector
concentrations in the range 2 to 6 × 1017 cm−3 [82, 83]. These higher
collector dopings led to unacceptably high values of Cbc for most circuit
Figure 4.12. Effect of collector doping (ramping) on cut-off frequency.

applications, as they increase the input capacitance of the device via the
Miller effect. Optimizing the collector profile consists therefore in trading
an increased transit time τec , arising from an increase in τbc with reduced
collector doping, for a reduction in the base–collector capacitance. This
point is considered again in chapter 5 where two variants of a process are
considered: one to achieve very short ECL gate delay by using a relatively
low collector doping and the other using a much higher collector doping to
achieve fT of more than 100 GHz. Figure 4.13 shows the effect of collector
doping on the simulated output characteristics. It is evident that the profile
with the highest fT yields the lowest BVceo .
Figure 4.13. Effect of collector doping on BVceo .

4.7. SMALL-SIGNAL AC ANALYSIS
A useful outcome of physical device simulation is the opportunity to use

the results to extract parameters which can be used in a compact model
for circuit simulation. The particular virtue of device simulation in this
context is the ability to visualize how changes to a particular process or
structure affect the overall circuit performance. The whole field of compact
modelling for bipolar transistors is extensive, with the Gummel–Poon
model, and recently the vertical bipolar inter-company (VBIC) model,
widely used [84, 85]. A detailed consideration of these models is beyond
the scope of this book. However, by way of illustration, we present an
example showing how device simulation can yield component values for a
rudimentary small-signal lumped element model. In addition, a method of
determining the different components of the transit time by integration of
the carrier distribution is also discussed.
4.7.1. Small-signal equivalent circuit

By treating the bipolar transistor as a two port network, it has been
explained in section 4.2 that a device simulator such as ATLAS has
the capability to determine all small-signal parameters. It is therefore
possible to use these parameters to extract the components of the hybrid-
π small-signal equivalent circuit as shown in figure 4.14. This equivalent
circuit represents a somewhat idealized representation of the transistor and
neglects distributed effects of minority carrier storage in the quasi-neutral
emitter and base regions [86]. It assumes that all parasitic components
associated with resistance, inductance and capacitance of probes, pads and
Figure 4.14. Simplified hybrid-π model of a SiGe HBT.

Small-signal ac analysis 135
interconnects have been successfully de-embedded. In this model, Cbe is the

emitter–base capacitance (representing the sum of diffusion and depletion
capacitance), rbe is the dynamic emitter resistance, Cbc is the base–
collector capacitance, rbb is the base resistance, rcc the collector resistance
and ree the emitter resistance. The small-signal transconductance is
expressed as [87]
gm = gmo exp (−jωτd ) (4.60)
where gmo is the low-frequency intrinsic transconductance and τd is the
transit time phase delay of transconductance.
To determine series resistance, it is most convenient to use small-signal
z-parameters, where it can be shown [87]
Zπ
Z11 = rbb + ree + (4.61)
1 + gm Zπ
Zπ
Z12 = ree + (4.62)
1 + gm Zπ

Zπ gm
Z21 = ree + 1− (4.63)
1 + gm Zπ jωCbc
1 1 Zπ
Z22 = rcc + ree + + (4.64)
jωCbc 1 + gm Zπ 1 + gm Zπ
where
rbe
Zπ = . (4.65)
1 + jωrbe Cbe
If small-signal ac simulations are carried out at relatively high frequency
(typically in the range 0.02–0.1 fT ), then since gmo ≥ 1/|Zπ |
1
ree = Re (Z12 ) − (4.66)
gmo
rbb = Re (Z11 − Z12 ) (4.67)

Cbe
rcc = Re (Z22 − Z21 ) − . (4.68)
gmo Cbc
The method of extraction of rbb and ree appears to work well, but
extraction of rcc is problematic, because rcc is expressed as the small
difference between the real parts of Z22 and Z21 , and a further term
representing the high-frequency ac output resistance. This latter term,
involving a ratio of capacitance, tends to be much larger than the unknown
value of rcc , so it proves very difficult to obtain a consistent value of
rcc which is independent of the frequency at which it is evaluated. In
addition, the accuracy of the second term is dependent on the accuracy
of the evaluation of the other three parameters Cbe , Cbc and gmo . None
of these parameters are known with absolute certainty and have to be

extracted using either y- or h-parameters using
Im(y12 )
Cbc = − (4.69)
ω
Im(y11 ) (rbb + rbe )2

Cbe = 2 − Cbc (4.70)
ω rbe
and rbe can be reliably obtained from
1 − Re(y11 )(rbb + ree )

rbe = (4.71)
Re(y11 )
at a frequency low enough that the reactance of Cbe does not affect Re(y11 ).
Figure 4.15 shows how the value of base resistance, extracted using
equation (4.67), varies with frequency, as collector current is increased.
The well-established mechanism of reduction in base resistance at higher
collector current due to current crowding is evident in this figure. The
choice of frequency is important in so far as one would like to evaluate
the base resistance at a frequency where the extracted value is relatively
insensitive to the choice of frequency. Based on the pattern of variation
seen in figure 4.15, it would appear that extraction of rbb at a frequency
of around 1 GHz, significantly below fT would appear to be a reasonable
choice.
Figure 4.15. Variation of rbb = Re(Z11 − Z12 ) with frequency.

Figure 4.16. Extraction of input resistance using (a) h-parameters and

(b) z-parameters.
Figure 4.17. Extraction of output resistance using (a) h-parameters and

(b) z-parameters.
Figure 4.16 shows that the equations (4.67) and (4.68) for rbb and
rcc based on z-parameters are relatively independent of frequency in the
range 1–8 GHz and it is clear that while rbb can be relatively accurately
determined from z-parameters (rather than h-parameters), the small value
of rcc , believed to be of the order of 20 ohms from sheet resistance
calculations, is masked by the much higher value of more than 200 ohms of
the additional term involving the ratio of capacitance. This point is further
illustrated in figure 4.17, which shows that the total output resistance can
be estimated by two methods: one using z-parameters, the other using
h-parameters. As indicated on the figure, both expressions nominally give
the same value. Neither equation however, is exact. Both involve a degree
of approximation, and the expected value of rcc is of the same order as the
likely error in using either of the two expressions. This example highlights
the difficulty which can occur in determining collector series resistance from
small-signal parameters.
To evaluate gm , it transpires that the most appropriate method is to
use h-parameters, rather than y-parameters. It has been shown that for
the small-signal equivalent circuit shown [34]
Re(h21 )
gm = . (4.72)
Re(h11 )
Figure 4.18 shows that the above equation involving the ratio of
Figure 4.18. Extraction of gm using (a) y-parameters and (b) h-parameters.

h-parameters is more reliable in estimating the transconductance, gm . Use

of Re(y21 )/ω always underestimates gm , because it takes no account of the
effect of the voltage divider ratio due to rbb and rbe . This correction of
course requires accurate values of rbb and rbe so the computation using
h-parameters is always liable to be more reliable.
4.7.2. Evaluation of transit time

While small-signal analysis is useful in extracting fT from |h21 |, it does
not permit insight into the magnitude of the individual components that
comprise the total transit time τec . To find the individual components of τec
from device simulation, it is necessary to integrate the carrier concentration
within defined regions of the transistor, according to the analysis given
in [88]. When the semiconductor equations are solved numerically, the
carrier concentration is known at every node in the structure. Hence, it is
relatively straightforward to integrate the carrier concentration numerically
to give the individual components of transit time. The total transit time
is given by
xbc L
xeb
q
τec = ∆n(x)dx + ∆n(x)dx + ∆n(x)dx . (4.73)
∆Jc 0 xeb xbc
Here we define the individual components by the incremental

relationships:
• emitter–base depletion charging time
xeb
q
τeb = (∆n(x) − ∆p(x)) dx (4.74)
∆Jc 0
• base–collector depletion charging time
L
q
τbc = (∆n(x) − ∆p(x)) dx (4.75)
∆Jc xbc
• emitter transit time

xeb
q
τe = ∆p(x)dx (4.76)
∆Jc 0
• base transit time xbc

q
τb = ∆n(x)dx (4.77)
∆Jc xeb
• collector transit time

L
q
τc = ∆p(x)dx. (4.78)
∆Jc xbc
In the formulation given, the integration is implicitly defined as one-

dimensional through the active transistor region, where x = 0 defines the
emitter contact, and x = L the collector contact. In this analysis, for
simplicity, the parameters xeb and xbc define the respective positions of
emitter–base and base–collector metallurgical junctions. A more rigorous
definition of these two points, as the points of intersection of dp/dJc and
dn/dJc , is given in [88]. This definition is, however, difficult to implement
in a 2D device simulator and has not been used.
The values of differential carrier densities ∆n(x) and ∆p(x) can be
computed by perturbing the dc bias by a small amount, to induce a
small change in collector current density ∆Jc . The value of emitter–
collector transit time τec , computed using this method, is comparable (but
not exactly identical) to the value of the SPICE parameter τF obtained
from the y-intercept of the graph of 1/(2πfT ) versus 1/Ic as defined in
equation (3.31) [89].
However, it should be borne in mind that all components of τec will
vary to some extent with bias condition, whereas τF is an absolute value
defined as 1/Ic → 0. Both emitter and base transit times are relatively
insensitive to collector current but increase as expected at the onset of
high injection leading to a fall in fT [90].
Figure 4.19 shows the relative magnitudes of the components of transit
time based on a simulation of a state-of-the-art HBT with a base width
of 40 nm, a Gaussian base doping profile with peak 1.5 × 1019 cm−3 and
a low-doped emitter of 1018 cm−3 . The transit times were evaluated as a
function of bias condition using equations (4.74)–(4.78).
The simulated maximum unity gain cut-off frequency for this transistor
based on h21 is 38 GHz, while the corresponding value of τF from figure 4.20
is 3.6 ps. For comparison, if transit times are computed directly the
Figure 4.19. Variation of transit time components with collector current.

Figure 4.20. Extraction of SPICE parameter, τF from variation of fT with

collector current.
minimum value of τec before onset of high injection is 3.75 ps at a collector

current of 7 mA. It should also be pointed out that, while the y-intercept of
the extrapolated straight line in figure 4.20 gives τF , its slope represents the
sum of the depletion capacitance Cje + Cjc as defined in equation (3.35).
This represents an alternative method for the determination of parasitic
capacitance to the use of y-parameters.
4.7.3. ECL gate delay

Unlike the frequencies fT and fmax , there is no standard analytical
expression universally accepted for the propagation delay of an ECL gate.
This gate delay, which normally represents a performance measure for
digital circuits, depends not only on the intrinsic characteristics of the
transistor, but also on the circuit configuration and the values of load
resistance and capacitance. The unloaded ECL gate delay exhibits a
similar sensitivity to intrinsic device transit time, parasitic resistance and
capacitance as fmax . At low switching current levels, the gate delay is
dominated by the base–collector capacitance, which is dependent on the
device structure and layout geometry, whereas at high current levels the
delay is more strongly coupled to the total base resistance and the transit
time of the device.
Approximate expressions for the gate delay for specific circuits have
been used by Kroemer [91] and by Shafi et al [92] for the ECL circuits
employing SiGe HBTs. The expression used by Kroemer is given by
5 rbb
τdel = rbb Cbc + τF + (3Cbc + CL ) RL (4.79)
2 RL
where RL is the load resistance and CL is the load capacitance of the

circuit. The importance of reducing the base resistance to improve the
speed is obvious from this equation (4.79). It is clear that a reduction in
rbb will improve the switching time until the first two terms become small
and the final term involving RL dominates. Further improvement can only
be obtained by reducing base–collector capacitance. The importance of the
above result lies not in the actual numerical values of different terms but
in that it demonstrates the relative importance of the various transistor
parameters in determining its speed.
Shafi et al [92] have used a different approach to calculate the gate
delay in an ECL circuit. Their calculations are based on the weighting
factors developed by Fang [93]. The calculations using this method were
compared with direct SPICE simulations and the two results agreed within
5% for the specific technology considered. The propagation delay is
expressed as a sum of RC time constants and stored charge elements:
τdel = Ki Ri Ci + Kj τec (4.80)

i
where summation over i includes all the resistances and capacitances of the
logic gate and those associated with the emitter, base and collector of all
the transistors in the circuit.
Shafi et al [92] calculated the numerical values of gate delay for SiGe
HBTs and compared these with similar computations for homojunction
devices. A Ge concentration of 12% was shown to be required in the SiGe
base to provide sufficient gain enhancement to allow the reversal of the
usual emitter and base doping concentrations. This results in a transistor
with a low base resistance and low emitter–base depletion capacitance. For
a fully optimized device, predicted propagation delays were 15 ps for the
SiGe HBT and 29 ps for the Si BJT. Subsequently, as SiGe technology
has developed over the last decade, bipolar scaling to ultrathin base and
0.2 µm self-aligned technology has given rise to a propagation delay as low
as 6.7 ps by a research group from Hitachi [75].
In order to simulate ECL delay, circuit simulation using SPICE must
be used. If the two-dimensional structure of the transistor is known, device
simulation can be used to extract key SPICE parameters such as τF , Cje , Cjc
and rbb from small-signal ac analysis, as illustrated in the previous section.
These SPICE parameters can then be used in a circuit simulation to predict
variation in ECL gate delay with collector current. The advantage of this
approach is that it provides insight into how the process can affect the
circuit performance.
Table 4.1 presents a representative sample of key SPICE parameters
extracted for a scaled SiGe HBT process based on silicon-on-insulator (SOI)
technology [94]. The technology, outlined more fully in chapter 5, utilizes
an epitaxial base and lightly-doped emitter. To allow for effects of boron
out-diffusion the base profile is assumed to be Gaussian. In table 4.1, two

sets of process parameters are considered. In the set labelled (a) the emitter
doping is 1018 cm−3 , while in the set labelled (b), the emitter doping is
reduced to 1016 cm−3 .
The key issue illustrated by table 4.1 is to examine whether use of
a lower doping density in the emitter spacer layer can improve ECL gate
delay. A more lightly-doped emitter will of course degrade the overall
transit time and hence fT , but does yield a significantly lower emitter–
base junction capacitance. This lower junction capacitance gives a marked
improvement in ECL gate delay particularly at lower collector currents,
Table 4.1. SPICE parameters for a SiGe HBT.

Transistor parameters (a) (b)
Base dose 1.2 × 1013 cm−2 1.2 × 1013 cm−2
Emitter doping (n-type) 1 × 1018 cm−3 1 × 1016 cm−3
Collector doping 1 × 1017 cm−3 5 × 1016 cm−3
Mask alignment tolerances 0.25 µm 0.25 µm
Ge fraction x 0.1 0.1
Low-doped emitter width Wepi 0.05 µm 0.03 µm
Base width Wb 0.038 µm 0.045 µm
Extracted SPICE parameters
Forward current gain (β) 356 190
Transit time τF 3.0 ps 4.2 ps
Base resistance rbb at 1 mA 81 Ω 68 Ω
Collector resistance rcc 42 Ω 63 Ω
Emitter junction capacitance Cje 50.8 fF 14.7 fF
Collector junction capacitance Cjc 13.5 fF 10.0 fF
Collector substrate capacitance Cjs 2.2 fF 2.2 fF
Early voltage VA 75 V 101 V
Extracted small-signal parameters
Cut-off frequency fT from h21 38 GHz 29 GHz
Maximum oscillation frequency fmax
48 GHz 56 GHz
(MAG)
SPICE circuit simulations
Cut-off frequency fT at Ic = 5 mA 36.2 GHz 31.0 GHz
Maximum oscillation frequency fmax SOI 35.1 GHz 38.3 GHz
Maximum oscillation frequency fmax Si 29.8 GHz 30.6 GHz
ECL gate delay at 0.5 mA 39.0 ps 24.3 ps
ECL gate delay at 1 mA 21.7 ps 16.7 ps
ECL gate delay at 5 mA 18.4 ps 15.5 ps
Figure 4.21. Dependence of fmax on emitter–polySi length.
well below the current level at which peak fT is predicted. In addition, the
creation of the bipolar transistor in an SOI rather than a silicon substrate
yields approximately 20% improvement in fmax due to lower collector–
substrate capacitance in the SOI substrate, as shown in figure 4.21. In this
figure, circuit simulation using SPICE parameters extracted from ATLAS
has been used to determine fmax .
With the simulated values of base resistance as an input parameter
for SPICE, ECL gate delays have been computed as a function of base
resistance and are tabulated in table 4.2. It is seen that, as expected, the
ECL gate delay decreases with the decrease in rbb and the minimum value
is comparable to the experimentally reported values for a SiGe HBT of
comparable dimensions [95].
Table 4.2. The dependence of ECL gate delay on base resistance. SPICE
parameters used: VAF = 130 V, Cje = 7.5 pF, Cjs = 13 pF, Cjc = 5.5 pF.
Base resistance Gate delay (ps)

200 17.1
100 14.7
50 13.3
25 12.5
Summary 145
4.8. SUMMARY
This chapter has considered how a SiGe HBT can be modelled in a device
simulator. The relevant equations, relating to current flow in a structure
where the bandgap is varying, were considered. Basic concepts employed
in a simulation program were given. Key material parameters for SiGe,
in so far as they differ from silicon, were outlined. A more accurate
strained layer SiGe mobility model should be used to take into account the
different mobilities (parallel and perpendicular to the growth direction) of
the strained-SiGe layer.
The way in which ac simulation can be utilized to determine small-
signal y-parameters was considered. Knowledge of y-parameters then
permits any other small-signal parameter to be evaluated. In this way,
both fT and fmax can be determined. A specific study of the design of an
HBT with a base width of approximately 60 nm was fully described. Base,
emitter and collector profile design issues were discussed in detail. High
βVA product necessary for analogue applications is of special interest, as
it is achievable using SiGe HBTs. Devices with three different Ge profiles
(flat, triangular and trapezoid) were considered. The optimum Ge profile in
the base was shown to be a trapezoidal profile. A retrograde collector profile
allowed the condition fT = fmax to be optimized, whilst still achieving
acceptable BVceo .
The significance of the ECL gate delay and the way in which device
simulation can be used to predict ECL gate delay was outlined. Gate
delays of ECL circuits involving SiGe HBTs were computed using SPICE
parameters extracted using small-signal analysis.
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Chapter 5
SIMULATION OF SIGE HBTS
In chapter 3, we discussed the operating principle of a SiGe HBT, while

in chapter 4 we focused on the basics of physical device simulation
and gave some examples of its application. In particular, it has been
shown that 2D simulations may be used with confidence for an accurate
prediction of device performance. In this chapter, we develop this
concept further by considering the simulation of some state-of-the-art SiGe
HBTs, concentrating on those that have given particularly noteworthy
performance. As SiGe technology continues to develop with device scaling,
performance will naturally tend to improve, so we are only endeavouring
to present particular examples in some detail.
In section 5.2, we consider the device described by Meister et al
[1]. This device was noteworthy in 1995 as the epitaxial-base (epi-base)
bipolar technology was extended to SiGe technology, leading to a maximum
oscillation frequency of 74 GHz and a CML gate delay time of 11 ps.
In section 5.3, a later generation device [2] is simulated. In this device,
particular attention has been paid to reproducing the two-dimensional
structure. Excellent agreement in both fT and fmax has been achieved. In
section 5.4, we show how, in a transistor with a very thin base, conventional
drift–diffusion simulation tends to overestimate the transit time and a
hydrodynamic simulation can in principle give a more accurate result for a
transistor when fT exceeds 100 GHz.
If SOI material is used as a substrate in a bipolar transistor,
significant reduction in collector–substrate capacitance can be achieved
with consequent improvement in fmax [3]. However, self-heating of the
silicon island in which the HBT is formed can be problematic [4, 5]. In
section 5.5, a thermal simulation of a SiGe HBT fabricated in an SOI
substrate is presented.
Problems encountered for the low-temperature operation of Si BJTs
can be solved effectively by using heterojunction technology. Section 5.6
describes examples of low-temperature simulation. Because of its bandgap-
152
Simulation of SiGe HBTs 153
engineered base, the SiGe HBT is particularly suitable for operation

at cryogenic temperature [6–12]. Since the bandgap of the emitter is
larger than that of the base, therefore the current gain increases at low
temperature. Since doping in the base of an HBT can be very high, carriers
do not freeze at low temperature.
While most digital applications involve the use of ECL technology,
SiGe technology offers the potential for reducing the delay of an integrated
injection logic (I2 L) gate. I2 L is a low-power bipolar technology suitable
for VLSI which traditionally has suffered from a relatively poor dynamic
performance. There has been renewed interest in I2 L, motivated by the
impressive performance reported for SiGe HBTs [13,14]. The gate delay of
I2 L circuits is primarily determined by stored charge in parasitic diodes
Figure 5.1. Doping profile and Ge profile (graded base) of a SiGe HBT.
154 Simulation of SiGe HBTs
associated with the extrinsic base region [15]. The lower bandgap of
SiGe therefore has a great impact on the propagation delay of integrated
injection logic. It is shown by simulation in section 5.7 that that
SiGe I2 L may be a useful technology in high-performance and low-power
applications, such as portable electronic systems [16].
As SiGe HBT technology appears to be exceptionally promising for RF
and microwave analogue applications, the low-frequency noise performance,
a key figure-of-merit, needs to be studied in detail. Section 5.8 presents
a comprehensive study on the noise performance of SiGe HBTs with
Figure 5.2. Gummel plot of a graded base SiGe HBT.

Epitaxial-base SiGe HBT (1995) 155
comparison to AlGaAs/GaAs HBTs and conventional Si BJTs fabricated

in different technologies. Finally, in section 5.9, the potential for SiGe
technology in a radiation intensive environment is considered.
5.1. EPITAXIAL-BASE SIGE HBT (1995)
In chapter 4, we established that, to design a high-performance HBT, it was

desirable to use a low-doped emitter, thin base with a graded Ge profile and
retrograde collector profile. In this section, the accuracy of the simulation
is assessed, by comparison with devices recently reported in the literature.
To optimize the high-frequency performance of a device, a nominal target
of fT ∼ fmax was used.
Figure 5.3. The dc current gain of a graded base SiGe HBT.

Epi-base technology has many advantages over ion-implanted

technology. An implantation tail can be avoided and the resultant box-like
doping profile provides independent control over base width and doping
concentration. Using epi-base technology, Meister et al [1] have reported
an experimental SiGe HBT. A base width of about 500 Å and a peak base
doping concentration (6 × 1018 cm−3 ) were used. The structure, including
the Ge and doping profiles used in simulation, is shown in figure 5.1. The
Ge concentration in the base has been graded from 0% at the emitter–base
junction to 12% at the centre of the base.
Figure 5.4. Typical output characteristics of a graded base SiGe HBT as a

function of collector doping.
Epitaxial-base SiGe HBT (1995) 157
Figure 5.2 shows the simulated Gummel plot and it is seen that almost
ideal base current characteristics are observed, with a peak dc current gain
of approximately 210, as shown in figure 5.3. A unilateral power gain of
22 dB at 10 GHz was achieved at a base–collector voltage of 2 V. Even
for a base width of about 500 Å, a high base doping (> 6 × 1018 cm−3 )
maintains a low base resistance and avoids punch-through.
In particular, the high fmax of 74 GHz originates from the integration
of the SiGe base, providing high cut-off frequency at low intrinsic base
resistance. The design can be tailored for optimum ECL or CML
performance by obtaining high fT at low base resistance leading to a CML
gate delay time of 11 ps.
The effect of collector doping on the Early voltage obtained from
the simulated output characteristics is shown in figure 5.4. These
characteristics are obtained by utilizing a constant base current, (Ib =
15 nA), as opposed to the more usual fixed base voltage boundary
conditions. It is seen that as the collector doping concentration increases,
the Early voltage decreases. This reduction in Early voltage with the
increase in collector doping density is expected from the consideration of
equation (3.25) in chapter 3, as a higher collector concentration gives a
higher base–collector capacitance and hence lower Early voltage. The Early
voltage for the lowest collector doping of 5 × 1016 cm−3 is 110 V, leading
to a βVA product of 22 000. A Ge fraction of 12% at the base–collector
junction has helped to provide a high Early voltage.
The dependence of cut-off frequency on the collector current is shown
in figure 5.5 for two different base–collector voltages, while figure 5.6 shows
Figure 5.5. Effect of base–collector reverse bias voltage on the cut-off frequency
of a graded base SiGe HBT.
Figure 5.6. Cut-off frequency versus Ic of a graded base SiGe HBT.
a comparison of simulated and measured fT with collector current. It is

evident that while the overall match is good, indicating good agreement
of emitter–base and base–collector capacitance, the simulated values are
slightly below the measured values. It is believed that this may be due to a
small inaccuracy in the drift–diffusion model in predicting base transit time
in thin base transistors. This point is more fully discussed in section 5.3.
A direct comparison of major experimental and simulated figures-of-merit
is shown in table 5.1. While excellent agreement has been obtained for
fT , the simulation overestimates fmax , possibly due to an underestimate of
base resistance.
Table 5.1. Comparison of simulated device parameters.

Parameter Experimental [1] Simulation
Emitter size, Ae 0.27 × 2.5 µm
Current gain, β 220 210
Breakdown voltage, BVceo 3.0 3.0
Early voltage, VA 130 V 120 V
Cut-off frequency, fT 61 GHz 57 GHz
Maximum frequency oscillation, fmax 74 GHz 105 GHz
Double polysilicon self-aligned SiGe HBT (1998) 159
5.2. DOUBLE POLYSILICON SELF-ALIGNED SIGE HBT (1998)
In this section we consider an alternative SiGe HBT, discussed by Kondo

et al [2]. The device structure is illustrated in detail in figure 5.7. It has
the same structure as a conventional double polysilicon bipolar transistor.
A borophosphosilicate (BPSG) refilled trench is used for isolation. Since
the dielectric constant of BPSG is about one third that of silicon, substrate
capacitance is therefore minimized. A wedge-shaped CVD silicon dioxide
isolation structure below the p+ -polySi base electrode helps reduce base–
collector capacitance. Both SiGe base and polySi SiGe contact are self-
aligned on the n-collector and p+ -polySi SiGe sidewall inside the window.
Hence, the width of the base–collector junction has been reduced to that
of the 0.5 µm emitter window.
The intrinsic base consists of a 200 Å undoped SiGe layer, a 300 Å
p− -type graded SiGe layer and a 150 Å undoped silicon layer. A SIMS
plot is shown in figure 5.8. For ATLAS simulation, the peak emitter
doping of 1020 cm−3 (n+ -type), the peak base doping of 5 × 1018 cm−3
(p-type) and the collector doping of 5×1016 cm−3 (n-type) were considered.
The characteristic length of the Gaussian base profile is 0.0145 µm. The
germanium fraction x is graded linearly, from a peak value of 0.145, down
to zero at the emitter–base junction. Full details of the simulation are given
in [17].
Figure 5.7. Schematic cross section of the ultra low-power SiGe base bipolar
transistor with a wedge-shaped CVD-SiO2 isolation and a BPSG-refilled trench.
(After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)
Figure 5.8. A SIMS impurity profile of the emitter and the base in the intrinsic
region. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)
Figure 5.9. Comparison of Gummel plot for a SiGe HBT. (After Hamel J S and
Tang Y T 2000 Proc. ESSDERC pp 620–3.)
The Gummel plot simulated by ATLAS is shown in figure 5.9, along

with the published result for comparison. Since great care has been
taken to model both the doping profile and two-dimensional structure,
excellent agreement has been achieved for the collector current. The higher
Double polysilicon self-aligned SiGe HBT (1998) 161
Figure 5.10. Comparison of simulated and experimental fmax and fT as a

function of collector current. (After Hamel J S and Tang Y T 2000 Proc.
ESSDERC pp 620–3.)
base current simulated by ATLAS could be due to lower hole lifetime in

the emitter, but insufficient detail regarding the polysilicon interface is
available in the original paper [2] to enable more precise modelling.
The respective simulated and published values of fT and fmax have
been compared in figure 5.10. The agreement is excellent with the
simulation showing a peak fmax of 70 GHz and a peak fT of 40 GHz at
around 200 µA. It would appear therefore that inaccuracy in the simulated
base current does not affect the accuracy of the high-frequency modelling.
Subsequently, this transistor has been used as the basis of a simulation
study which offers a comparison between vertical and lateral HBTs [18].
The simulation predicts a potential twofold improvement in fmax , and
at significantly lower bias current compared to the vertical SiGe HBT,
for a given minimum lithography. The relevant comparison is shown in
figure 5.11. The improved fmax is attributed to an order of magnitude
improvement in the rbb Cbc time constant in the lateral HBT. Although
specific device structures were utilized, the same active region profiles
and identical minimum lithography ensured a meaningful comparison.
The factor of two improvement predicted for lateral SiGe HBT on SOI
technology gives a general indication as to how bipolar technology is likely
to evolve over the next decade. As minimum lithography decreases, the
SOI layer thickness in the lateral HBT can be made thinner to continue to
provide improvement in performance.
Figure 5.11. Comparison of frequency performance versus dc collector current

between vertical and lateral SiGe HBTs. (After Hamel J S and Tang Y T 2000
Proc. ESSDERC pp 620–3.)
5.3. ENERGY BALANCE SIMULATION
As discussed in chapter 4, the drift–diffusion approximation can lead to

inaccuracy in the prediction of device characteristics, particularly when the
width of the base is reduced below 30 nm. In this instance, it is necessary
to perform a simulation involving energy balance [19], where the equations
for current flow must be modified as given in equations (4.18)–(4.21).
The conventional drift–diffusion model of charge transport neglects
non-local transport effects such as velocity overshoot, diffusion associated
with carrier temperature gradients and dependence of ionization rates
on carrier energy distribution. The drift–diffusion approximation is a
low-order approximation of the Boltzmann transport equation (BTE).
Device simulation based on the solution of the full BTE is possible
but requires significant computing resources. A simpler intermediate
level approximation, which offers potential for improved accuracy, is
therefore attractive. Essentially, the energy balance model predicts
velocity overshoot relative to the carrier saturation velocity defined in
equation (4.28). Velocity peaks occur in regions of the device where carrier
temperature is a maximum e.g., base–collector junction. High velocity gives
rise to reduced transit time compared to the drift–diffusion model.
The device considered for simulation [20] is a state-of-the-art SiGe
HBT, designed to give a very high fT by incorporating a high dose selective
collector implant of peak concentration of the order of 1018 cm−3 . The
Energy balance simulation 163
Figure 5.12. Germanium and doping profile for a SiGe HBT with 15% Ge
content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)
SIMS profile of the transistor, with a 15% graded Ge profile is shown

in figure 5.12. This profile has been accurately reproduced in the input
datafile for ATLAS simulation. This transistor is very similar to that
described in the previous section. It only differs in two respects: a much
higher doping density in the collector and the location of the peak collector
doping lying closer to the base–collector. It was reported that the measured
peak fT ranges from 110 GHz for a peak Ge content (x = 0.1) to 130 GHz
(x = 0.25), as shown in figure 5.13.
The simulated maximum cut-off frequency has been plotted as a
function of peak collector doping in figure 5.14. It is clear that the drift–
diffusion model predicts a maximum fT of less than 100 GHz, irrespective
of the value of peak collector doping. It seems that in order to predict
an fT of more than 100 GHz to match the measured value, the energy
balance model appears to be required. This conclusion is in line with the
observations in figure 5.6, where once again the simulated fT is less than
the measured value.
The differences between the energy balance and drift–diffusion models
on emitter and base transit times are shown in figure 5.15. It is clear
that the EB model predicts significantly lower values of base transit times,
sufficient to account for the higher measured values of fT .
A comparison of extracted carrier velocity for the DD and EB models,
Figure 5.13. Maximum cut-off frequency as a function of Ge content. (After

Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)
Figure 5.14. Cut-off frequency versus peak collector doping in a graded base
SiGe HBT.
Energy balance simulation 165
Figure 5.15. Simulated emitter and base transit time of a SiGe HBT, as a
function of collector current for both drift–diffusion and energy balance models
for Ge mole fraction x = 0.1.
Figure 5.16. Extracted carrier velocity using drift–diffusion and energy balance
models.
Figure 5.17. Simulated electron temperature in a SiGe HBT.
as a function of base bias, for two Ge fractions (x = 0.1 and 0.2), is shown in
figure 5.16. The EB model shows a significant overshoot in the saturation
velocity, sufficient to account for the lower base transit time in figure 5.15,
while the maximum velocity possible with the DD model is limited by
the saturation velocity, vsat = 8 × 106 cm s−1 . A plot of the simulated
electron temperature in figure 5.17, taken as a one-dimensional section
through the active device, shows the expected carrier heating associated
with the high-field region at the base–collector junction. The maximum
of the temperature profile is, however, shifted into the collector region,
as the carriers are accelerated through the high-field region to reach the
maximum temperature. Velocity overshoot occurs in the base region, where
the electric field is high and the temperature is only beginning to rise.
5.4. SIGE HBTS ON SOI SUBSTRATES
In Si bipolar technology, the two well-known disadvantages are: high

power dissipation and low density. High power dissipation is a result
of the high parasitic junction capacitance associated with using silicon
as the substrate. Previously, silicon-on-insulator has been used for
high-performance deep submicron CMOS, as discussed more fully in
section 10.3. The advantages of utilizing a composite substrate comprising
a monocrystalline semiconductor layer, such as silicon, epitaxially deposited
SiGe HBTs on SOI substrates 167
on a supporting insulating substrate, are well recognized. Major advantages

include the substantial reduction of parasitic capacitance between charged
active regions and the substrate, and the effective elimination of leakage
currents flowing between adjacent active devices. Modern communication
devices also present greater difficulties in high level integration because
they require digital computing capability (logic and memory) along with
analogue and RF circuitry. The need to reduce power consumption in
battery powered wireless communication systems is a need which has not
previously been met. While bipolar transistors fabricated on SOI substrates
have been shown to offer lower parasitic capacitance [21], they do have a
greater susceptibility to self-heating [4, 5].
Investigations on the impact of self-heating on transistor performance
and effect of introduction of thermal vias to reduce temperature rise have
been performed by Armstrong and Gamble [22]. Lattice heating in the
SiGe HBT has been simulated by coupling the solution of the heat flow
equation along with the semiconductor equations:
∂TL
C = ∇ (κ∇TL ) + H (5.1)
∂t
where TL represents the lattice temperature, C the heat capacitance per
unit volume and κ the thermal conductivity. The Joule heating term
H, which provides the coupling between the heat flow equation and the
semiconductor equations, is given by
Jn2 Jp2
H= + (5.2)
qµn n qµp p
where Jn,p and µn,p represent current density and carrier mobility of
electrons and holes, respectively. The temperature dependence of κ in
the semiconductor is modelled by [23]
1
κ= (5.3)
a + bTL + cTL2
where for silicon and polysilicon, a = 0.03, b = 1.56×10−3 , c = 1.65×10−6 ,

while for silicon dioxide κ = 0.014.
The SiGe HBT transistor considered for simulation (see figure 5.18) is
based on SiGe technology developed at Southampton University [24]. The
novel feature of this technology is selective growth of a silicon collector in
an anisotropically etched oxide window, followed by non-selective growth
of a SiGe base and low-doped SiGe emitter in the same growth sequence.
A key aspect of the technology is the very low junction capacitance at both
emitter–base and base–collector junctions. In addition, the fabrication of
the transistor in a bonded substrate offers the possibility of including a
buried silicide layer to reduce collector resistance. Simulations indicate
Figure 5.18. Structure of a SiGe HBT on SOI used for simulation.
Figure 5.19. SiGe HBT doping profile used for simulation.

Figure 5.20. A schematic diagram of a SiGe HBT showing different regions.

(After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and
Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment
(Pennington, NJ: Electrochemical Society) pp 249–54.)
that the predicted performance of an optimized Si0.9 Ge0.1 heterojunction

transistor produced in SOI material utilizing minimum lithography is fmax
in excess of 100 GHz and ECL gate delay of less than 10 ps. To achieve
this level of performance, a minimal feature size with an emitter polysilicon
width of 0.25 µm and 0.125 µm mask alignment is required. A typical base
doping considered for simulation is shown in figure 5.19.
Figure 5.20 illustrates a simplified structure, representative of the oxide
isolated technology, with extended base and collector regions. The buried
collector is shown to be thinner than would normally be used, to emphasize
any potential heating effect due to collector resistance. Electrical boundary
conditions are applied at the emitter, base and collector contacts in the
normal way. The substrate (not shown below the oxide) is assumed to be
held at a fixed ambient temperature. Figure 5.20 also shows the inclusion
of a thermal via through the buried oxide. This via, which is created prior
to bonding, acts as a heat conduction path. A thermal boundary condition
Figure 5.21. Simulated Gummel plot with and without inclusion of the heat
equation. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator
Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3,
ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)
is defined at all three electrical contacts such that

∂TL 1
−κ = (TL − Text ) (5.4)
∂n Rth
where Rth represents thermal resistance in K mW−1 .

Figure 5.21 shows the Gummel plots, with and without the inclusion
of the heat equation for the lattice heating modelling. Due to poor thermal
conductivity in the buried oxide, the junction temperature rises, leading to
a deviation from linearity. In the lower curve, heating has caused a 25 K
rise in temperature above the ambient. The consequent increase in collector
current is consistent with that value of collector current, which would occur
for the same increase in ambient temperature. A comparison between the
maximum temperature rise in a transistor on an SOI substrate, with two
different thicknesses of buried oxide, and the maximum temperature rise
on a silicon substrate is shown in figure 5.22.
For different thermal boundary conditions (Rth ranging from
2–20 K mW−1 ), the sensitivity of the maximum temperature rise to
thermal resistance, for a buried oxide of 0.4 µm, and a collector voltage
of 3 V, is shown in figure 5.23. The impact of the thermal via in providing
a heat conduction path through the buried oxide is shown in figure 5.24.
Figure 5.22. Comparison of heating effect between SOI and silicon substrates.
(After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and
Figure 5.23. Dependence of maximum temperature rise on thermal

resistance in a SiGe HBT fabricated in a bonded SOI substrate. (After
Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and
Figure 5.24. Contour plots of temperature in a SiGe HBT. (After

Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and
The peak temperature occurs, as expected, within the active area of the
transistor. However, it is clear that the thermal via is effective in providing
a heat conduction path to the silicon substrate.
Although an attempt has been made to predict the thermal behaviour
of HBT transistors fabricated on SOI substrates, absolute accuracy is
difficult to achieve because of the error in estimating the degree of
external heat loss, which has been approximated using a thermal resistance
boundary condition at the electrical contacts. The variation in temperature
within the transistor and the dependence of the maximum temperature
rise on thermal resistance have been demonstrated. The reduction in
temperature, which occurs if a thermal via is included, depends on its
alignment relative to the active area.
5.5. LOW-TEMPERATURE SIMULATION
The outstanding performance advantages of a SiGe HBT for low-

temperature operation have been demonstrated experimentally in a state-
of-the-art silicon bipolar process [7–10]. However, the design and
optimization issues associated with the low-temperature operation of SiGe
Low-temperature simulation 173
HBTs remain unclear. Because of its bandgap-engineered base, a SiGe

HBT is particularly suitable for operation at cryogenic temperature,
where the exponential gain enhancement factor becomes very large. In
addition, the built-in drift field in the base is more effective at low
temperature, compensating for the degradation in base diffusivity, resulting
in improvement in the cut-off frequency. It has been demonstrated [7] that
present SiGe technology is capable of providing transistors with higher
current gain at 77 K than at room temperature, and unloaded ECL circuits
which are as fast at 77 K as they are at room temperature. The key design
issues for the low operation of SiGe HBTs may be identified as follows [25]:
• minimization of carrier freeze-out in the base;

• control of increased parasitic emitter–base tunnelling current at low
temperature;
• design of collector profile to leverage the increase in Kirk knee current
density with cooling; and
• effect of Ge grading on current gain and cut-off frequency.
Low-temperature semiconductor device simulation is a difficult task

because parameters, often assumed constant in conventional simulators,
may actually be complex functions of temperature. Phenomena unique
to low-temperature operation, such as carrier freeze-out, are typically not
accounted for in simulators designed for room temperature use. In addition,
the system of equations to be solved for low temperature is much more ill-
conditioned numerically than at room temperature, due to terms having
stronger exponential temperature dependency. For these reasons, available
simulation programs can have difficulty in converging to a solution at
77 K [26, 27].
5.5.1. Low-temperature SiGe HBTs

Patton et al [28] studied the low-temperature operation of a SiGe HBT
fabricated in a poly-emitter bipolar process. The devices showed improved
low-temperature behaviour with extremely high current gains of 1600 at
77 K for devices having 7.5 kΩ/square base resistivity. Crabbe et al [6]
investigated the low-temperature behaviour of Si BJTs and SiGe HBTs
fabricated and optimized for room temperature operation. The authors
demonstrated that introducing a spacer layer in the emitter–base junction
reduced the low level parasitic emitter–base tunnelling (leakage current) at
low temperature, but gave rise to carrier freeze-out and increase of base
resistance at 77 K. The respective current gains were 20–40 for an Si BJT,
and 100–140 for a SiGe HBT for the temperature range from 77–300 K. The
graded Ge profile in the base improved both the low-temperature current
gain and base transit time, resulting in a peak cut-off frequency of 94 GHz
at 85 K, compared to 75 GHz at 298 K.
A much improved low-temperature SiGe HBT [29], specifically

designed for low-temperature operation, was fabricated using self-aligned
epi-base technology [30]. Lightly-doped spacers were used at both the
junctions to reduce the electric field. The base width was approximately
59 nm and the peak concentration of the graded Ge profile was 9%. For a
high-power design (about 10 mW), the ECL gate delay at 84 K was 28.1 ps,
roughly the same as at 310 K, yet a factor of two better than the best value
obtained at that time with a low-temperature Si BJT. Low power ECL
circuits showed a power delay product of 112 fJ at 84 K. The measured gate
delays were in reasonable agreement with the theoretical predictions [31].
At that time, these results represented a significant advance in performance
of silicon-based bipolar technology at 77 K.
During the 1990s, the research group at IBM [7, 9, 10] reported
progressive further improvements in the low-temperature performance of
SiGe HBTs. A low thermal budget allowed a sharp transition from a low-
doped emitter to a heavily-doped base, making the base immune to carrier
freeze-out at 77 K. At 84 K, transistors showed a current gain of 500, fT
of 61 GHz and ECL gate delay of 21.9 ps, 3.5 ps faster than at room
temperature. Typical parameters and performance of the transistors at
310 and 84 K for the epitaxial emitter-cap (no spacer) design and an i–p–i
(with spacers) design, are given in table 5.2.
The effect of introducing lightly-doped spacer layers at both the
emitter–base and base–collector junctions was studied in detail [9]. The
Table 5.2. Typical SiGe HBT parameters at 310 and 84 K at the wafer level.
(After Cressler et al 1994 IEEE Electron Device Lett. 15 472–4.)
Temperature 310 K 84 K 310 K 84 K

SiGe profile Emitter-cap design i–p–i design
βmax 102 498 105 82
β at 1.0 mA 94 99 96 34
Peak gm (mS) 62 113 74 83
Rbi (kΩ/square) 7.7 11.0 8.2 15.9
Re (Ω) 14.3 11.0 82 15.9
Ieb (nA) 8.44 × 104 1.91 × 103 2.89 1.11
BVceo (V) 3.1 2.1 3.2 3.2
BVcbo (V) 10.8 9.6 10.8 9.5
Cbe (fF µm−2 ) 5.47 5.13 6.30 5.90
Cbc (fF µm−2 ) 0.46 0.40 1.04 0.93
Peak fT (GHz) 43 61 53 59
Peak fmax (GHz) 40 50 37 48
ECL delay (ps) 25.4 21.9 26.0 30.4
spacer layer reduced the low level parasitic base leakage but gave rise to
carrier freeze-out and an increase of base resistance at 77 K. However, it was
shown that a thin abrupt base profile attainable with epitaxial processing is
particularly useful for low-temperature operation since the resultant profile
is less sensitive to base freeze-out than ion-implanted profiles. The authors
also fabricated homojunction Si BJTs and showed that properly designed
homojunction transistors also have sufficient current gain and switching
speed at 77 K for many digital applications. In several applications,
however, the flexibility offered by using SiGe for base layer yields great
benefits.
Gruhle et al [12] have reported a high-performance SiGe HBT,
fabricated using MBE, having a base doping of 2 × 1019 cm−3 , largely
exceeding the emitter impurity level and a base sheet resistance of about
1 kΩ/square. The device exhibited an Early voltage of 500 V, a maximum
room temperature current gain of 550 rising to 13 000 at 77 K. Devices
built on buried-layer substrates exhibited an fmax of 40 GHz and an fT of
42 GHz.
Sturm et al [32] also fabricated high-quality SiGe HBTs using rapid
thermal chemical vapour deposition. Both graded-base and uniform Ge
profiles in the base were considered. In a transistor with 20% uniform Ge
concentration in the base, currents gain of about 2000 at room temperature
and 11 000 at 133 K were observed. The performance of SiGe HBTs at
liquid helium temperature has been reported by Joseph et al [8]. The
current gain of a self-aligned, UHVCVD-grown SiGe HBT showed an
increase in current gain from 110 at 300 K to 1045 at 5.85 K, although
parasitic base current leakage limits the useful operating current to above
about 1.0 µA at 5.84 K. A very high base doping (peak at 8 × 1018 cm−3 )
was used to suppress the base freeze-out at 4.48 K and resulted in a base
sheet resistance of 18.3 kΩ/square.
5.5.2. Low-temperature simulation using ATLAS

In order to understand the impact of the Ge profile and base doping in the
design of a low-temperature SiGe HBT, simulations were performed using
ATLAS 2D device simulator on two separate base doping profiles, and two
different Ge profile shapes:
(i) a box Ge profile (uniform Ge content, x = 0.20, not shown)

(ii) a graded Ge profile (see figure 5.25).
Figure 5.26 shows Gummel plots at 300 and 100 K, respectively, for
constant Ge concentration. The simulated collector current characteristic
is ideal over more than ten decades of current. As the temperature is
lowered, the intrinsic carrier concentration decreases exponentially, and for
an observable current to flow at low temperature, the emitter–base voltage
Figure 5.25. Doping profile and Ge profile (graded case) in a SiGe HBT.
must be increased substantially, as may be seen from figure 5.26. As the

dc current gain depends exponentially on the bandgap narrowing present
at the emitter edge of the neutral base [33], the box Ge profile (x = 0.2)
produces a larger enhancement in β, in figure 5.27, than the graded profile
in figure 5.25. In the former diagram, a peak dc current gain as high as
11 000 is predicted at 100 K, compared to the more moderate enhancement
for the graded Ge. In the latter case, the predicted current gain at 150 K
of 900 is more than adequate for successful circuit operation at such a
low temperature. A contributory factor to the high current gain at low
temperature is the low level of bandgap narrowing in the relatively lightly-
doped 5 × 1018 cm−3 single-crystal emitter.
Richey et al [34] have shown close agreement with measurements for
low-temperature SiGe HBT simulations, using a calibrated doping profile
based on SIMS data. The authors have used the 1D simulator SCORPIO
to examine the effects of Ge profile shape and base profile scaling on
temperature. Some of these results are presented below. It has been
Figure 5.26. Gummel plots of a SiGe HBT (flat base) at 300 and 100 K.
shown in chapter 4 that a triangular Ge profile in the base produces more

enhancement in cut-off frequency and βVA product than a box Ge profile.
The bandgap grading associated with the triangular Ge profile induces a
drift field that helps accelerate electrons across the base, decreasing the
base transit time. Figures 5.28–5.30 show dependence of cut-off frequency
fT , relative improvement in fmax and βVA product on temperature, for
box and graded Ge profiles, at different dc bias points. Three separate
sets of base doping profile are used and, for each set, two Ge profiles—a
box profile and a linearly graded profile—are considered. Each Ge profile
has the same stability point as defined by Matthews and Blakeslee [35, 36],
i.e. the integrated Ge concentration is held constant. Three stability points
are referenced. Stability point 1 refers to a state-of-the-art device, with an
effective Ge thickness of 120 nm and a base width of 90 nm. For the second
stability point, the base profile has been scaled by one half while base
Figure 5.27. The dc current gain of a flat base SiGe HBT at different
temperatures. For comparison, dc current gain at 150 K for a graded base
transistor is shown.
Figure 5.28. Cut-off frequency comparisons over temperature. (After

Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)
Figure 5.29. Enhancements in maximum oscillation frequency. (After

Figure 5.30. Current gain–Early voltage product enhancements. (After

doping is increased to maintain the same pinched base resistance. Stability

point 3 is identical to the previous case, except that the Ge content is
doubled. For all three scaled profiles, both the collector profile and emitter
depth are unaltered.
For all parameters, the enhancement factor increases significantly as
the temperature is reduced. The relative improvement for the graded Ge
profile at low temperature is due to the greater effectiveness of the drift field
in compensating for degradation in diffusivity. The simulation suggests that
for low-temperature operation, a box Ge profile may be used for maximizing
dc current gain and fT , but this is a more sensitive function of temperature
than the triangular profile. In conclusion, the box Ge profile produces
the greatest enhancement in β, fT and fmax over temperature, while the
triangular Ge profile produces the greatest enhancement in βVA product.
5.6. I2 L CIRCUITS USING SIGE HBTS
High-performance bipolar logic circuits are usually realized using emitter

coupled logic (ECL) which has a relatively low packing density and high
power dissipation. The gate delay of I2 L circuits is primarily determined
by stored charge in parasitic diodes associated with the extrinsic base
regions of the I2 L gate [15]. SiGe technology offers the prospect of using
bandgap engineering to minimize the stored charge in the parasitic diodes
associated with the I2 L gate. Hence, the use of a heterojunction can add
high speed to the other well-known advantages of I2 L technology, namely
high packing density, low voltage and low power dissipation. Experimental
results on SiGe integrated injection logic circuits (surface-fed and substrate-
fed variants) have been reported [16].
Figure 5.31(a) shows the cross section of an I2 L gate and figure 5.31(b)
a circuit diagram. The cross section shows the merged structure of the I2 L
gate, with the SiGe layer used both as the base of the npn transistor and
the collector of the pnp transistor. The npn switching transistor operates
Figure 5.31. Schematic cross-section (a) and circuit diagram (b) of an I2 L.

(After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)
I2 L circuits using SiGe HBTs 181
in the inverse mode, which allows multiple collectors to be produced using

n+ -polySi contacts to the top n-type silicon layer. A polysilicon contact is
also used to connect to the base of the pnp injector transistor. The emitter
(injector) of the pnp transistor is formed in the top 300 nm n-type silicon
layer using a BF2 implant through a 50 nm screen oxide. This SiGe I2 L
technology therefore uses a vertical pnp transistor in contrast to the lateral
pnp transistor used in conventional silicon I2 L technologies.
A Gummel plot of a 3 µm npn switching transistor, operated in upward
mode in an I2 L gate with three collectors, gave a maximum current gain
of 14. The collector current characteristic was ideal over several decades
of current, while the ideality factor of the base current was 1.28. The
measured output characteristic is shown in figure 5.32 and indicates a
breakdown voltage BVceo of about 2.9 V. A low gain of 1.4 for the pnp
transistor was not deemed to be important for the operation of the I2 L
gate, provided that the ratio of saturation currents for the pnp and the
npn transistors was much greater than unity. Figure 5.33 compares the
measured and modelled [37] switching time as a function of injector current
per gate. The measured and modelled values agree quite closely, with the
measured values being about 40% faster.
For optimization of SiGe integrated injection logic (I2 L) circuits, a
quasi two-dimensional stored charge model has been developed [16]. It has
Figure 5.32. Output characteristics (upward mode) of the npn SiGe HBT.
(After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)
Figure 5.33. Comparison of measured and modelled I2 L gate delay. (After

Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)
been shown that at low injector currents, the use of SiGe offers only a
marginal benefit, since the switching speed is dominated by depletion region
charge. However, at high injection currents, where the switching speed
is dominated by stored minority carrier charge, the use of SiGe in I2 L
technology has been shown to have important benefits. The inclusion of
16% Ge in the substrate-fed I2 L gate leads to a decrease in the dominant
stored charge by a factor of more than ten, which suggests that gate
delays well below 100 ps should be achievable, even at a geometry of
3 µm. The model has also been applied to predictions of the performance
of a self-aligned structure, specifically optimized for SiGe I2 L. For a Ge
concentration of 16% in the base, a maximum delay of 34 ps was predicted
using 1.4 µm design rules.
5.7. NOISE PERFORMANCE
Different types of noise mechanisms are found to be present in

semiconductors [38]. Among them the low-frequency noise, typically
observed to exhibit a dependence on frequency, is very important for
analogue and mixed-signal applications. Low-frequency noise is known
to degrade the spectral purity of nonlinear radio frequency (RF) and
Noise performance 183
microwave circuits, such as oscillators and mixers, where the low-frequency,

baseband noise generates noise sidebands around the RF or microwave
carrier signal [39].
Low-frequency noise in UHVCVD-grown Si and SiGe bipolar
transistors has been studied by Vempati et al [40]. The authors have
made a comprehensive study by comparing different technologies and
have demonstrated that the SiGe devices have excellent noise properties
compared to AlGaAs/GaAs HBTs and conventional Si bipolar junction
transistors. Low-frequency noise has been characterized as a function of
bias, geometry and temperature [41, 42].
The transistors used were fully integrated, self-aligned devices, with
shallow and deep trench isolation, silicided extrinsic base and contacts,
two levels of metallization and a conventional poly-emitter contact. Two
different bias configurations were used to distinguish the various noise
sources contributing to noise in the Si and SiGe bipolar transistors. The
devices were biased in low injection (Ib ∼ 2.25 µA) in order to eliminate
any second-order parasitic resistance effects and spurious noise due to
weak impact ionization. The collector current was also limited to several
milliamps, so that the shot noise due to the collector current was negligible
compared to the base current shot noise. Common-emitter configuration
with high input impedance was used for measuring the base noise. In
order to determine the collector noise and the contributions, if any, of the
parasitic series resistances, the devices were biased in the common-collector
configuration.
Typical curves of the equivalent input-referred base current noise
spectra for Si and SiGe devices are shown in figure 5.34. At low frequencies,
the noise rises over the shot noise and thermal noise background and
exhibits an expected spectrum for frequencies below 1 kHz. Within the
scatter of data (approximately 50 devices for both Si and SiGe combined
were measured) the slope of the spectrum varies as 1/f . The roll-off of the
spectra above 10 kHz is due to the Miller capacitance associated with the
device and packaging.
As temperature excursions are important in analogue applications,
noise measurements were made over the range of −55 ◦ C to 85 ◦ C.
Figure 5.35 shows the temperature dependence of the noise spectra of Si
and SiGe transistors at a fixed base current of 2.25 µA. It is observed
that the noise spectral density exhibits a clear 1/f behaviour without
any anomalous behaviour in the slope across this temperature range.
The noise spectra for Si and SiGe devices are similar, and have no
significant temperature dependence. The authors concluded that the
combination of an inverse of area dependence on geometry and near-
quadratic dependence on base current suggests that the noise sources are
homogeneously distributed over the entire emitter area and not restricted
only to the emitter periphery. Comparisons with different technologies
Figure 5.34. Equivalent input-referred base noise current spectral density at a

base current of 2.25 µA for multi-stripe Si and SiGe transistors with an emitter
area 3 × 0.5 µm and comparable doping profiles. The inferred 1/f to shot noise
corner frequencies are 480 Hz and 373 Hz for Si and SiGe transistors, respectively.
(After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)
Figure 5.35. Noise spectral density at two different temperature points (358
and 218 K) of Si and SiGe devices of an emitter area of 3 × 0.5 µm. (After
Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)
Noise performance 185
demonstrate that the Ge incorporated in the base does not degrade the
noise performance and that SiGe HBTs have better noise performance than
AlGaAs/GaAs HBTs and conventional ion-implanted Si BJTs.
Even though SiGe HBTs have demonstrated better noise performance
over Si BJTs at low frequency, even better high-frequency noise
characteristics may be expected if the Ge profile is optimized specifically
to address this issue. The SiGe HBT design issues associated with
minimization of broadband noise have been considered by Ansley et al [43].
Using the 1D simulator SCORPIO, the effect of the Ge profile in the base on
the minimum noise figure at high frequency was theoretically investigated.
The analysis was based on an equivalent circuit noise model originally
formulated by Hawkins [44], as shown in figure 5.36. The model accounts
for thermal noise in the source (vs ), base resistance (vb ), shot noise in the
emitter (ve ) and collector partition noise (icp ). The resulting expression
for noise factor may be approximated with sufficient accuracy by

Rb Re (1 − (2πf )Cje Xs )2 2

F 1+ + + (2πf )Cje Rs
Rs 2 Rs

1 + (2πf )2 τb2 Rs Xs2
+ −1 + (5.5)
α0 2Re 2Re Rs
where Rs is the source resistance, Xs is the source reactance, Re is the
dynamic emitter resistance (thermal voltage divided by emitter current)
and Cje is the emitter–base depletion capacitance, α0 is the common base
dc current gain and f is the frequency at which the noise factor is evaluated.
This formulation helps in determining the relative contribution of each of
the terms which control the noise factor. As a guide, the presence of Ge
Figure 5.36. Equivalent circuit schematic of Hawkin’s noise model for bipolar
transistors. (After Hawkins R J 1977 Solid-State Electron. 20 191–6.)
reduces the noise factor by decreasing τb , decreasing base resistance Rb

and allowing the possibility of increased current gain. The minimum noise
figure, NFmin is given by 10 log(F) when Rs is set to the optimum source
resistance Ropt which may be approximated as

2Rb Re Re2 2
Ropt ≈ + − Xopt (5.6)
a 2
and the optimum source reactance Xopt is given by
(2πf )2 Cje Re2

Xopt ≈ (5.7)
a
where
2 2
1 ((2πf )τb ) ((2πf )τje )
a≈ + + . (5.8)
β α0 α0
When considering the Ge profile, the best noise performance is achieved
with the greatest amount of Ge in the neutral base region, subject to
the maximum acceptable β and the strained layer stability constraints.
In what was essentially a theoretical study, a novel optimized Ge profile
to achieve minimum noise figure was developed, as shown in figure 5.37,
which compares the new profile with a traditional trapezoidal profile of
the same average Ge content. Simulations using this profile at 10 GHz
indicated an improvement of almost 1 dB in the minimum noise figure over
an equivalent Si BJT control, and 0.4 dB over the equivalent SiGe HBT
with the traditional profile.
Base doping has a direct impact on β, intrinsic base resistance Rbi
and fT , with all values decreasing as doping increases. The decrease in
β and fT (with increases in both base and emitter transit time) would
give the impression that NFmin will increase. However, the decrease in the
base resistance suggests there may be a decrease in NFmin . Figure 5.38
shows the effect of increasing base doping on the major components of
noise factor, as a function of collector current, for a 90 nm base HBT
with the calibrated Ge profile of figure 5.37. An additional extrinsic base
sheet resistance of 500 ohms/square has been included in the calculation.
It is apparent that an increase in base doping increases NFmin because β
decreases and τb increases. Even though an increase in doping reduces Rb ,
Ropt also decreases which partially offsets the impact of reduction in base
thermal noise.
5.8. RADIATION EFFECTS ON SIGE HBTS

In the following, we describe briefly the effects of proton and gamma
radiation on SiGe HBTs fabricated in IBM SiGe BiCMOS technology.
Radiation effects on SiGe HBTs 187
Figure 5.37. Ge profile which allows optimization for NFmin compared to the
conventional graded Ge profile. Emitter and base carrier concentrations are
shown for reference from polySi interface in emitter to base–collector junction
(at right edge). (After Ansley W E et al 1998 IEEE Trans. Microw. Theory
Tech. 46 653–60.)
Figure 5.38. Effect of base doping level on the noise factor sources for the
scaled base profile using a base link sheet resistance of 500 ohms/square. (After
Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)
Dose-rate effects and proton energy effects have been studied in detail for
this technology, mainly by Cressler and his group [45–47]. Characteristics of
proton and gamma irradiated SiGe HBTs and gated lateral pnp transistors
(GLPNPs) have been reported [48].
MOS devices respond to ionizing radiation in several ways, depending

on whether the damage occurs in silicon or in the oxide. In the oxide,
charge-generation in the gate/oxide interface or the oxide/silicon interface
causes changes in the threshold voltage (VT ), transconductance (gm ), and
the leakage current. Two kinds of charges are observed: oxide trapped
charge and interface trapped charge, each having different effects on device
parameters. The major effects of radiation-induced interface states on
MOS devices are lowering of transconductance and distortion of I–V
characteristics. The generation of electron–hole pairs after a radiation
burst is not a long-lived phenomenon because the electrons tunnel into
the bulk of the device and the trapped hole charge can lead to significant
device degradation.
For most bipolar devices, the effects of radiation and subsequent

performance degradation due to surface states are not as catastrophic as for
MOSFETs. Bipolar transistors are, in general, more radiation tolerant than
CMOS as they depend on junctions for operation, while MOSFETs depend
on surface effects and the interfaces. Also, bipolar transistors are doped
up to three orders of magnitude higher than MOSFETs. When irradiated,
degradation of current gain and an increase in leakage current are found to
occur in the case of bipolar devices. Gain degradation occurs mainly due
to the atomic displacement in the bulk of the device. The displacement
results in an increase in the number of recombination centres, which reduces
the minority-carrier lifetime, and therefore an increase in the base current
takes place. The other cause of gain degradation is due to the ionization
of the oxide passivation layer, mainly in the emitter–base junction region
where charge trapping and the generation of new interface traps occur.
The trapped surface charge and the interface states cause an increase in
minority-carrier surface recombination velocity, which reduces the gain.
Another important effect in bipolar transistors is the increase in the

junction leakage currents resulting from ionization in the surface oxide,
mainly the region over the base–collector junction. This increase in base–
collector leakage current (typically ∼1 nA) is usually due to charge build-up
in the oxide layer over the junction producing a surface channel which
conducts strongly. Figure 5.39 shows a schematic device cross section
of a SiGe HBT and sources of degradation. The SiGe HBT has been
successfully integrated with conventional Si CMOS technology to realize
a SiGe BiCMOS technology. This technology is more fully discussed in
chapter 10.
Figure 5.39. Schematic cross section of a self-aligned UHVCVD SiGe HBT.

Sources of degradation are shown in the structure. (After Banerjee G 1999
Master’s Thesis Auburn University.)
5.8.1. Low dose-rate effects
Low dose-rate (LDR) effects have been investigated in the state-of-the-art

SiGe HBTs (see figure 5.39) which were fabricated using a self-aligned,
planar structure with deep and shallow trench isolation and a conventional
poly-emitter contact. These SiGe HBTs have 70 GHz fmax frequency
response and have been fully integrated into a 0.35 µm SiGe BiCMOS
technology for system-on-a-chip applications [49].
The LDR effects on these vertical SiGe HBTs were contrasted with
high dose-rate (HDR) data, as well as data from gated lateral pnp
transistors from this SiGe BiCMOS process, in order to shed light on the
damage mechanisms. In contrast to reports of strongly enhanced LDR
degradation in conventional Si bipolar transistors, LDR effects in the SiGe
HBTs were found to be nearly non-existent [50]. Figure 5.40 shows the
dependence of dc current gain on the energy of protons. A peak β of about
105 is observed which degrades to 100 for 44 MeV and 95 for 196 MeV.
Clearly, the β degradation is much larger for the higher energy. It has
been observed that an increase in the base current occurs when collector
current is more or less independent of radiation. However, the degradation
in current gain is not as large in the high current region of the transistor,
where it will be biased for most of the high-frequency and high-power RF
applications. The LDR effects have been found to be very technology-
dependent.
Figure 5.40. Current gain degradation as a function of energy. (After

Banerjee G 1999 Master’s Thesis Auburn University.)
5.8.2. Simulation of radiation hardness
The effects of proton radiation in a gate-assisted lateral pnp (GLPNP) in

an advanced SiGe BiCMOS technology have been studied by Niu et al [48].
The GLPNP is essentially a p-MOSFET whose source and drain serve as
the emitter and collector of the lateral bipolar transistor. These transistors
avoid the current gain limitation by combining both MOSFET and bipolar
operational modes, and thus are commonly used in BiCMOS circuits [51].
Radiation-induced surface and bulk traps were electrically probed using a
combination of dc measurements and 2D simulation. Figure 5.41 shows
the schematic top view and cross section of a GLPNP, along with the SiGe
HBT in the BiCMOS process studied.
To understand the physics underlying radiation degradation, extensive
2D simulations using MEDICI [52] were performed by the authors, by
placing positive charges in the oxide and introducing a thin surface layer
of traps. The simulations show that the radiation-induced threshold
voltage increases and the carrier lifetime at the surface decreases. Different
combinations of trap density and spatial distributions of traps were used,
and only those with higher surface trap densities can reproduce the
experimentally observed data. Figure 5.42 shows the evolution of the
simulated electron and hole densities versus depth with VGB change at
Vbe = 0.45 V.
Figure 5.41. Device cross section for the gated lateral pnp transistor and SiGe
HBT. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.)
Figure 5.42. Simulated electron (solid curve) and hole (dashed curve) densities
versus depth with VGB (gate-to-base bias) change at Vbe = 0.45 V. (After Niu G
et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.
5.9. SUMMARY
In this chapter, further examples of device simulation employing SiGe HBT

technology have been considered. Attention has been given to simulation
of various advanced technologies leading to high cut-off frequency and/or
low transit time. Good agreement between simulation and measurement
provides confidence in the use of device simulation for future development.
Simulation of the low-temperature operation of a SiGe HBT has been
shown to be applicable for a wide range of applications in low-temperature
electronics. Other more specialist applications of SiGe technology in I2 L
circuits and radiation hard environment have been considered.
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Chapter 6
STRAINED-SI
HETEROSTRUCTURE FETS
In conventional Si technology, the complementary metal–oxide semi-

conductor dominates the integrated circuit market. Its popularity comes
from the simplicity in processing, as well as high input impedance.
However, p-channel devices are inferior to n-channel ones in terms of
current drive capability and speed performance. This is a consequence of
the lower mobility of holes compared to electrons in Si. In order to match
the current drive capability of n-channel (n-MOS), p-channel (p-MOS)
devices are designed to be about 2–3 times larger than that of n-MOS.
This adversely affects the level of integration and device speed.
In order to improve the speed of VLSI/ULSI circuits, new materials
and device structures are being proposed. The advances in the growth of
strained silicon (strained-Si) layers on relaxed-SiGe buffer layers, combined
with higher values of both the hole and electron mobilities in strained-Si,
have led to increased interest in silicon-based heterojunction field-effect
transistors (HFETs) using conventional Si-processing technology.
Heteroepitaxy of semiconductor materials has been an active area of
research for the last two decades. Interest is driven by the possibility
of creating novel electronic and optical devices, as well as integrating
existing devices in different material systems, leading to the production
of integrated circuits with increased functionality and lower cost. The
foundation of heteroepitaxy was laid by two important contributions. The
first, by Frank and van der Merwe in 1949 [1], showed theoretically that if
a lattice mismatched layer is grown on a thick substrate, the layer will
be pseudomorphic, provided that the mismatch is small and thickness
of the layer is not large. The second by Shockley [2] suggested the use
of semiconductors of different bandgaps for fabrication of heterostructure
devices.
The lattice mismatch in the SiGe material system is 4.2%, resulting in
a very high misfit and threading dislocation density. Most of the research
196
Strained-Si heterostructure FETs 197
Figure 6.1. Band alignments between Si and Si0.70 Ge0.30 on two substrates:
(a) Si and (b) Si0.70 Ge0.30 .
has concentrated on devices having strained layers with thicknesses below

the critical thickness. Si1−x Gex strained layer heterostructure devices were
fabricated on an Si substrate only in the late 1980s. The key features of
the growth and electronic properties of the strained-SiGe alloy system and
their applications have been described in chapter 2 of this book, and also
in more detail in several excellent reviews [3–7].
When a thin film with a larger lattice constant (e.g., Si1−x Gex ) is
grown on a substrate with a smaller lattice constant (e.g. silicon), the film
maintains the in-plane lattice constant of the substrate and is under a
biaxially compressive strain. Figure 6.1 shows the band offset between a
strained-Si0.7 Ge0.3 film grown on silicon. This is known as the type I band
alignment where virtually all the entire band offset occurs in the valence
band (figure 6.1(a)) with minimal band offset in the conduction band. This
type of structure, favourable for hole confinement, has been exploited in
several novel heterostructure devices, namely buried channel p-MOSFETs,
p-MODFETs and HBTs (see, for example, excellent reviews by Paul [8]
and Konig and Daembkes [9]).
Similarly, a smaller lattice constant silicon epilayer will be under
biaxial tension when grown on a larger lattice constant relaxed-Si1−x Gex
substrate. Figure 6.1(b) shows the band offset for a strained-Si epilayer
grown on a relaxed Si0.70 Ge0.30 . In this case, type II band offset occurs
and the structure has several advantages over the more common type I band
alignment, as a large band offset is obtained in both the conduction and
valence bands, relative to the relaxed-Si1−x Gex layer [10]. This allows both
electron and hole confinements, making it useful for both n- and p-type
devices for strained-Si/SiGe based CMOS technology. Since strained-Si
provides both larger conduction and valence band offsets and does not suffer
from alloy scattering (mobility degradation) [11], a significant improvement
in carrier mobility can be achieved. Strained-Si is more difficult to grow as
compared to strained-Si1−x Gex , since an Si1−x Gex substrate is currently
not available and, until recently, the growth of relaxed-Si1−x Gex without
forming a large concentration of defects due to dislocation was difficult.
198 Strained-Si heterostructure FETs
Studies of the incorporation of a small amount of C atoms into the Si/SiGe

material system to develop new types of buffer layers with reduced misfit
dislocations may be useful [12].
However, the ability to achieve both n-MOS and p-MOS devices
using strained-Si provides a promising alternative for next generation high-
performance SiGe CMOS technology (see, for example, reviews [5, 13] and
references therein). Strained-SiGe channel p-MOSFET designs are more
fully covered in chapter 7. In this chapter, we discuss the present trends
and applications of strained-Si films in SiGe-based CMOS technology. In-
depth discussion will cover the film growth, electronic properties of the
strained-Si layers on virtual substrates, design and simulation of strained-
Si channel HFETs and MODFETs. Recent progress made in integration
issues and the future prospects of strained-Si/SiGe-based high-performance
HFETs, which may be integrated into Si VLSI/ULSI production, are also
discussed.
6.1. MOBILITY IN STRAINED-SI
Optimum semiconductor device design is ultimately based upon a full

understanding and accurate modelling of charge-carrier transport in
semiconductors. Due to their relevance for both basic understanding and
for device applications, there has always been a strong interest in accurate
model descriptions of the mobility as a function of strain, temperature
and dopant concentration. For the estimation of maximum theoretical
mobilities that can be achieved in strained-Si/SiGe heterostructures,
several theoretical studies incorporating various scattering mechanisms
have been reported [14–16]. The main scattering mechanisms to be
considered in the strained-Si/SiGe material system are [17]:
(i) lattice scattering;

(ii) ionized impurity scattering;
(iii) neutral impurity scattering; and
(iv) alloy scattering.
In addition, the strain distribution in the lattice mismatched SiGe

layer affects the relative importance of intra- and inter-valley scattering,
due to strain-induced changes in the conduction and valence bands.
6.1.1. Theoretical mobility

Stern and Laux [14] considered the dependence of electron mobility
on remote doping and background doping in the channel, as well as
the contribution of interface roughness and interface charges. Their
results are in good agreement with the experimental data when
realistic background acceptor densities between 1014 and 1015 cm−3 were
Mobility in strained-Si 199
considered [18–20]. Monroe et al [21] have studied the limitations of

various parameters including scattering from remote dopants, background
impurities, interface roughness, alloy fluctuations, strain, morphology and
threading dislocations on the mobility. Considering all potential scattering
mechanisms which are reasonable, the authors predicted a low-temperature
electron mobility over 1 000 000 cm2 V−1 s−1 , which is comparable to those
reached in GaAs/AlGaAs heterostructures.
Several other workers have calculated the expected electron mobility
enhancements in strained-Si layers relative to bulk-Si [22–24, 26, 27].
Vogelsang and Hofmann [23] have calculated the in-plane electron drift
velocities and mobilities in strained-Si for 300 and 77 K. High-field drift
velocities were calculated by Monte Carlo (MC) simulations and low-field
mobilities by the numerical solution of Boltzmann’s equation including
intra- and inter-valley phonon and impurity scattering mechanisms. A
mobility enhancement of 74% was obtained at 300 K, compared to 36% at
77 K, and a significant improvement of the drift velocity relative to bulk-Si
was reported. Yamada et al [27] have reported a Monte Carlo study of
the low-temperature mobility of electrons. For a device structure having
2×1018 cm−3 doping, mobility values of 2.5×105 cm2 V−1 s−1 at 4.2 K and
3.1 × 105 cm2 V−1 s−1 at 1.5 K for an electron density of 7.5 × 1011 cm−2
were obtained. Peak mobility values of 5.0 × 105 cm2 V−1 s−1 at 4.2 K and
7.6 × 105 cm2 V−1 s−1 at 1.5 K were predicted for a lower channel electron
density.
Rashed et al [22] have studied electron transport in the inversion
layer of strained-Si channel n-MOSFETs using an MC tool, taking into
account scattering mechanisms, namely phonon, surface roughness and
alloy scattering. Table 6.1 shows the computed low-field electron mobility
enhancement factors for strained-Si, along with some reported experimental
device data. For a low level of strain at low electric field, the electron
mobility increases with increasing strain.
High-field velocity saturation and overshoot of electrons in strained-
Si [24] show only a slight increase in the saturation velocity at both room
temperature and 77 K. As the electric field parallel to the current flow is
increased, the drift velocity of the electron increases and approaches the
saturation velocity. These high electric fields are common in short-channel
devices, and thus the saturation velocity, rather than low-field mobility,
may ultimately limit the performance of scaled devices [23, 28].
Electron velocity overshoot in strained-Si/Si1−x Gex MOSFETs has
also been studied using an MC simulator by Gamiz et al [29] for steady-
state and non-steady-state for high longitudinal field transport regimes.
It was concluded that at high longitudinal fields, the electron velocity
overshoot effects, due mainly to the reduction of the inter-valley scattering
rates as the Ge mole fraction increases, improve MOSFET drain current
and transconductance.
Table 6.1. Low-field electron mobility: dependence on strain level in Si.

Ge concentration Strain in Si Temperature Computed mobility
in the buffer (%) (%) (K) enhancement factor Ref
10 0.4 300 1.6 [22]
20 0.8 1.8
30 1.33 1.9
2.5 0.1 300 1.14 [23]
5 0.2 1.27
10 0.4 1.5
15 0.6 1.65
20 0.8 1.73
25 1 1.74
2.5 0.1 77 1.28
5 0.2 1.36
10 0.4 1.36
16.6 0.66 300 2.67 [24]
33.3 1.33 2.67
16.6 0.66 77 1.35
33.3 1.33 1.35
Experimental mobility
enhancement factor
10 0.4 300 1.45 [25]
20 0.8 1.67
29 1.3 1.75
29 1.3 77 1.35
However, the progress in the study of hole mobility in strained-Si has

been relatively slow. Nayak and Chun [11] have calculated the low-field
hole mobility of strained-Si. At room temperature, in-plane hole mobilities
were found to be 1103 and 2747 cm2 V−1 s−1 for Ge content of 10%
and 20%, several times higher than that of bulk-Si. Table 6.2 shows the
computed low-field hole mobility for strained-Si, along with some reported
experimental hole mobility enhancement factors obtained from device data.
6.1.2. Experimental mobility

Low-temperature Hall mobility measurements are commonly used to
determine the overall quality of a heterostructure and are used to
optimize the growth parameters. At low temperature, where thermal
effects and scattering by phonons are dramatically reduced, the electron
Mobility in strained-Si 201
Table 6.2. Low-field hole mobility: dependence on strain level in Si.

Ge concentration Strain in Si Temperature Computed mobility
in the buffer (%) (%) (K) cm2 V−1 s−1 Ref
10 0.4 300 1100 [11]
15 0.6 1950
20 0.8 2700
25 1 3500
Experimental mobility
enhancement factor
29 1.33 300 1.2 [30]
18 0.8 300 1.4 [31]
18 0.8 77 2.0
25 1.0 300 1.5 [32]
mobility becomes very sensitive to residual scattering mechanisms due to

background charge impurities, roughness and dislocation.
Experimental electron mobility data from strained-Si/SiGe modulation-
doped structures may be divided into two categories:
(i) data from devices with the uniform composition buffer, and
(ii) devices with the compositionally graded buffer.
Figure 6.2 shows the range of values for Hall mobility [18, 28, 33–38]
using both uniform composition and graded buffer layers. In the case of the
uniform composition buffer [33, 36, 38], strain relief is a function of buffer
layer thickness. In order to achieve a strain level of 1% in Si, a partially
relaxed 0.2 µm Si0.68 Ge0.32 uniform composition buffer is required [39].
For an effective strain level of 1% in Si on a uniform composition buffer,
record high electron mobilities of 1280 cm2 V−1 s−1 at 300 K [38] and
17 000 cm2 V−1 s−1 at 1.5 K [36] have been reported. In this type of
buffer, mobility is limited by the presence of a large number of defects
(109 –1010 cm−2 ) in the buffer layer. The effect of dislocations on electron
mobility has been reported by Ismail [40]. It has been found that electron
mobility is sensitive to threading dislocations when their density exceeds
3×108 cm−2 , and decreases by two orders of magnitude when the threading
dislocation density is 1 × 1011 cm−2 .
The introduction of graded buffer layers has made a great impact
on the electron mobility enhancement. The upper curve in figure 6.2
represents very high (around 200 000 cm2 V−1 s−1 ) low-temperature
mobilities but underestimates the two-dimensional electron gas mobility
Figure 6.2. Measured electron Hall mobility versus temperature in

modulation-doped strained-Si. The solid symbols are for strained-Si grown on
high-quality, graded Si1−x Gex buffer layers, while the open symbols refer to films
with constant Ge content. (After Maiti C K et al 1998 Semicond. Sci. Technol.
13 1225–46.)
at room temperature. This is due to parasitic parallel channels of low

mobility and an unknown carrier concentration, which freeze out at a low
temperature, but lead to a reduced average value of the Hall mobility at a
higher temperature. By carefully designing the doping concentration in a
series of samples, Nelson et al [41] could separate the contribution of the
2DEG at room temperature, and extracted room temperature mobility in
excess of 2500 cm2 V−1 s−1 for the limiting case of a vanishing parasitic
channel. The room temperature mobility enhancement factor is almost
twice that of bulk-Si, and a factor of more than three greater than that of
an Si-MOSFET.
The extremely high electron mobility obtained in modulation-doped
layered structures, grown using MBE and UHVCVD, indicates that
a similar buffer layer quality has been obtained. By optimizing the
modulation-doped layer sequence and thickness of strained-Si well [42], the
highest mobility values between 300 000 and 400 000 cm2 V−1 s−1 have been
Band structure of strained-Si 203
obtained. Additional wave functioning by front and back gating of some

of the structures led to a record low-temperature (0.4 K) electron channel
mobility beyond 500 000 cm2 V−1 s−1 [43, 44], which is an improvement
of more than a factor of ten compared to the best Si MOSFETs reported.
Typical values of room temperature mobility, however, are between 2000
and 2800 cm2 V−1 s−1 for n-channels [28,45], which exceed those in bulk-Si
MOSFETs by a factor of four to six.
A high hole mobility in excess of 9300 cm2 V−1 s−1 at 4 K in
a p-type modulation-doped Si/Si0.87 Ge0.13 /Si heterostructure has been
reported by Whall [46]. At room temperature, values between 1400 and
1800 cm2 V−1 s−1 are more typical, still a factor of at least six to nine
above that of a bulk-Si p-MOSFET [47].
6.2. BAND STRUCTURE OF STRAINED-SI
The effect of both strain and alloying on the bandgap of the strained-
Si/SiGe material system has been reported in detail by People [10]. In
particular, the computed conduction and valence band discontinuities have
been based on the calculations of van de Walle and Martin [48]. The
extracted valence and conduction band offsets between the strained-Si and
relaxed-Si1−x Gex layers [49] are plotted against theoretically estimated
values in figure 6.3, showing a good match, particularly at low Ge
concentration. Substituting the extracted conduction and valence band
offset values, the overall bandgap of the strained-Si can be obtained and is
shown in figure 6.4, along with the theoretical calculations of People [10].
The heterojunction band offsets (∆Ec , ∆Ev ) in a strained-Si/SiGe
heterostructure have also been determined from measurement of the
threshold voltages of a surface channel strained-Si p-MOSFET structure
(see figure 6.5(a)) [50]. To determine the threshold voltage at the strained-
Si/SiGe interface (VTH ) and the threshold voltage at the strained-Si/SiO2
√
interface (VTS ), the zero current intercept of the IDS –VGS and IDS / gm
characteristics were used. The measured values of threshold voltages VTH
and VTS were −1.0 V and −1.7 V, respectively [50, 51]. The extracted
experimental valence band offset ∆Ev was found to be 160 meV. Using
the valence band offset value, conduction band offset was obtained from
equations (2.11) and (2.12) where x is the Ge concentration in the top part
of a completely relaxed-SiGe buffer cap. The conduction band offset ∆Ec
was found to be about 126 meV for a Ge mole fraction x = 0.18 in the
relaxed-SiGe layer, and agreement with reported results was found to be
good [10, 33].
Figure 6.3. Band offsets: (a) valence band and (b) conduction band for
strained-Si to relaxed Si1−x Gex . Calculated curves are from People R 1986 IEEE
J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958
Phys. Rev. 109 695–710.
6.3. DEVICE APPLICATIONS
Silicon complementary metal–oxide semiconductor transistors are the most

important building blocks in digital integrated circuits due to low power
consumption and mature technology. The use of strained-Si/SiGe materials
promises to improve the speed-power performance of CMOS by offering
higher electron and hole mobilities. Device applications of strained-Si/SiGe
with special emphasis on heterostructure metal–oxide semiconductor field-
effect transistors are described in this section, while the alternative
approach of a Schottky gate modulation-doped field-effect transistor is
discussed in section 6.5.
Device applications 205
Figure 6.4. Bandgap of strained-Si grown on a relaxed-Si1−x Gex buffer layer.

Calculated curves are from People R 1986 IEEE J. Quantum Electron. 22
1696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.
Figure 6.5. Device structures for strained-Si MOSFETs with (a) Si on the
surface, (b) Si buried and (c) dual strained-Si channels.
6.3.1. Strained-Si n-MOSFETs
Very high electron mobilities demonstrated in strained-Si layer suggest a

great potential for this material in high transconductance n-MOSFETs.
To date, in-plane electron mobilities approaching 3000 cm2 V−1 s−1
have been reported in long-channel MOSFETs with both surface and
buried channels [52]. Figure 6.5 shows the schematic diagrams of several
possible configurations of strained-Si MOSFETs. All the structures have
thick, relaxed-Si1−x Gex buffer layers, consisting of a layer with linearly-
graded Ge, followed by a constant Ge layer. The surface channel device
(figure 6.5(a)) has a single layer of thin strained-Si grown on top of the
relaxed buffer layer. This layer is oxidized to form a gate oxide. The buried
strained-Si channel device (figure 6.5(b)) has a layer of strained-Si buried
beneath a thin layer of relaxed Si1−x Gex . An additional layer of strained-Si
is necessary to form a gate oxide on top of the Si1−x Gex , but ideally this
additional Si layer (sacrificial layer) should be consumed during oxidation.
If this sacrificial layer is not consumed fully, then a very thin layer of Si,
left between the gate oxide and the Si1−x Gex barrier layer (figure 6.5c) can
act as a parallel conducting channel, strongly affecting device performance.
Depending on the dopant type in the layers, these structures can be used
for n- or p-MOSFETs.
Welser et al [52, 53] have fabricated both p- and n-MOSFETs using
all these device structures and some of their results on n-MOSFETs are
presented below. Long-channel (L × W = 10 µm × 168 µm) surface and
buried n-MOSFET devices fabricated on relaxed-Si0.7 Ge0.3 buffer layers
have shown well-behaved output characteristics. The effective low-field
mobilities for these device structures are shown in figure 6.6. For the
surface-channel strained-Si device µeff is enhanced compared to the bulk-Si
control device and has a similar dependence on the effective electric field.
The peak mobility is 1000 cm2 V−1 s−1 , which shows an 80% enhancement
over Si-control (550 cm2 V−1 s−1 ). The peak mobility value for the buried
channel device is over 1600 cm2 V−1 s−1 , which is almost three times that
of Si-control device. Room temperature effective mobility versus electric
field curves of surface-channel, strained-Si n-MOSFETs with different Ge
content in the buffer layer are shown in figure 6.7, along with the mobility
extracted from a bulk-Si control device. Strained-Si mobility increases with
increasing strain (more Ge content in the relaxed buffer layer) and has little
dependence on the effective electric field.
Rim et al [54] have reported measurements on deep submicron
(0.1 µm) strained-Si n-MOSFETs. An electron mobility enhancement by
75%, compared to typical Si MOSFET mobilities, has been reported in
spite of the high channel doping and vertical effective field present in the
device. The ac measurements, used to reduce self-heating effects, have
shown an extrinsic transconductance increase by 45% for a channel length
Figure 6.6. Effective low-field mobility versus effective field for different
n-MOSFETs. The surface channel strained-Si mobility shows a fairly constant
mobility enhancement compared to that of the control-Si device, while the
buried strained-Si mobility peaks at low fields, but decreases rapidly at higher
fields. (After Welser J J 1994 The application of strained-silicon/relaxed-silicon
germanium heterostructures to metal–oxide semiconductor field-effect transistors
(Stanford University).)
Figure 6.7. Effective mobility of surface-channel, strained-Si n-MOSFETs

at room temperature. Strained-Si mobility increases with increasing strain
(more Ge content in the relaxed buffer layer). (After Welser J J 1994 The
application of strained-silicon/relaxed-silicon germanium heterostructures to
metal–oxide-semiconductor field-effect transistors (Stanford University).)
Figure 6.8. Effective mobility, µeff versus vertical effective field, Eeff . For
high Eeff , µeff is enhanced by 75% for strained-Si compared to the epi control-Si
device and state-of-the-art universal MOSFET mobility. Data from Welser J et
al 1994 IEEE IEDM Tech. Dig. pp 373–6, Takagi S et al 1994 IEEE Trans.
Electron Devices 41 2357–62. (After Rim K et al 1998 IEEE IEDM Tech. Dig.
pp 707–10.)
of 0.1 µm. In figure 6.8, the effective mobility µeff , measured on large
devices, is shown as a function of vertical effective field Eeff . Even for high
Eeff (>0.5 MV cm−1 ), the effective mobility µeff for the strained-Si device
is enhanced by ∼75% compared to the epi control-Si.
Electron mobility enhancements observed at lower Eeff [25] are thus
sustained at higher effective fields, as predicted theoretically for the
phonon-limited mobility in strained-Si MOS inversion layers [16]. The
measured µeff for strained-Si (peak µeff ∼ 575 cm2 V−1 s−1 ) is also
enhanced over the state-of-the-art n-MOSFET mobility [55]. These results
demonstrate that, unlike conventional Si which is constrained to the
universal MOSFET mobility curve (figure 6.8, dotted curve), strained-Si
provides mobility improvement at a given Eeff . Such an enhancement in µeff
at high channel doping and Eeff enables fabrication of high mobility, deep
submicron devices with channel doping suitable to counter short-channel
effects (SCE).
6.3.2. Strained-Si p-MOSFETs

Exploiting the demonstrated higher mobility for holes, efforts have been
made to fabricate strained-Si p-MOSFETs. Various research groups
working on the problem were able to achieve better performance with
strained-Si compared to control-Si devices. The tensile strain in silicon
grown on a relaxed-SiGe buffer raises the light-hole band and lowers the
heavy-hole band, leading to a significant increase in the low-field hole
mobility. Observation of hole mobility enhancement in strained-Si p-
MOSFETs was demonstrated by Nayak et al [32]. The initial devices were
fabricated on a 1 µm uniform composition partially relaxed-SiGe buffer,
which is known to have a very high defect density [56] and this resulted in
a limited performance (subthreshold slope 111 mV/decade).
An improved device structure and process to fabricate high
performance strained-Si p-MOSFETs has been reported, with a high-
quality (defect density <105 cm−2 ) step-graded completely-relaxed thick
(3 µm) SiGe buffer layer, a low thermal budget (maximum temperature
700 ◦ C) and a high-quality (100 Å) gate oxide [31,50]. The device structure
used is shown in figure 6.9(a). It was shown that the high-field channel
mobilities of a device, with a germanium concentration of 0.18 in the SiGe
buffer, were 40% and 200% higher at 300 K and 77 K respectively, compared
to those of a similarly processed bulk-Si p-MOSFET. Rim et al [30] have
also reported enhanced hole mobility in a surface-channel p-MOSFET (see
figure 6.9(b)) employing strained-Si on pseudomorphic Si1−y Gey on a fully
relaxed-Si1−x Gex buffer layer.
Figure 6.10 shows the variation of low VDS (−0.1 and −0.3 V)
transconductance of strained-Si and control-Si p-MOSFETs at 300 K, for
the device structure shown in figure 6.9(a). The gate voltage at which peak
transconductance occurs depends on the value of VDS and the device type,
namely control-Si or strained-Si. The control-Si device shows one large
peak at −1.7 V. But, for the strained-Si devices, two peaks are perceptible
at −1.5 V and −1.9 V at 300 K. The peak at −1.5 V corresponds to
hole confinement at strained-Si/SiGe–buffer interface. At a higher gate
voltage, however, the holes at the SiO2 /strained-Si interface dominate the
channel conduction and the device becomes a surface channel device. The
transition from buried channel to surface channel is clearly seen from the
transconductance plot at 77 K (figure 6.11). The two peaks (−1.55 V and
−2.7 V) are clearly seen. The IDS –VGS characteristics at 77 K for both the
strained-Si and control-Si devices are also shown in this figure 6.11. It will
be noticed that there is substantial current at VGS close to zero, particularly
for the control-Si device. For the strained-Si device the characteristics
indicate an accumulation current threshold of about −1 V. When the
temperature is reduced to 77 K, the mobility improves in both silicon
and strained-Si, the factor of improvement depending on the scattering
mechanisms operating at the applied gate voltage.
Figure 6.9. Schematic diagram of a strained-Si p-MOSFET: (a) strained-Si

grown on a fully relaxed-SiGe buffer layer (abrupt) and (b) strained-Si grown on
a grade-back Si1−y Gey layer (graded).
Figure 6.10. Linear transconductance of a long channel (L×W = 100×300 µm)

strained-Si (on an 18% Ge buffer layer) and control-Si p-MOSFETs at 300 K.
(After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)
Figure 6.11. Linear transconductance of a long channel (L×W = 100×300 µm)

strained-Si and control-Si p-MOSFETs at 77 K. Drain currents for the devices
are also shown (right scale). (After Maiti C K et al 1997 Solid-State Electron.
41 1863–9.)
The transverse field dependence of MOS device parameters has

assumed a greater importance because the thinner gate dielectrics and
higher doping levels used in submicron MOSFETs lead to very high
transverse electric fields well above 0.5 MV cm−1 . It is well known that such
high fields cause a degradation in device performance. The variation of the
effective mobility with electric field is often used as a basis of comparison of
MOS devices developed for computer-aided design. The transconductance
factor, field-effect mobility and effective mobility computed from IDS –
VGS characteristics at room and liquid nitrogen temperature have been
compared for strained-Si and control-Si accumulation p-MOSFET devices
[50]. Figure 6.12 shows the variation of computed field-effect mobility and
effective mobility for strained-Si and control-Si at 77 K. The effective field
values assume a flat band voltage of −1 V. The presence of the surface
and parasitic channels at the strained-Si/SiO2 and SiGe/Si interfaces is
Figure 6.12. Comparison of the field-effect and effective hole mobility of long
channel strained-Si and control-Si p-MOSFETs at 77 K: (a) µfe of strained-Si; (b)
µfe of control-Si; (c) µeff of strained-Si; and (d) µeff of control-Si. The effective
electric field values applicable at 77 K for a current threshold value of −1.0 V are
also indicated. (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)
Simulation of strained-Si HFETs 213
indicated by the transconductance (see figure 6.11). Above VGS = −2.5 V,

the strained-Si device shows an improvement in both.
6.4. SIMULATION OF STRAINED-SI HFETS
Abramo et al [57] have presented a study of a novel Si/SiGe n-MOSFET

structure simulated by means of a one-dimensional quantum mechanical
approach which accounts for the quantum nature of two-dimensional
electron gas. In simulation, energy splitting between degenerate conduction
band valleys of strained-Si layer, optical and elastic acoustic phonon
scattering among subbands, and surface roughness scattering were
implemented. The non-parabolicity effect on the scattering rates and
velocities was included by first-order perturbation theory following [58].
Room temperature low-field peak electron mobility values greater than
2800 cm2 V−1 s−1 were predicted. The authors also showed good turn-
on characteristics and linear transconductance behaviour for the structure
considered.
Although two research groups have demonstrated high-performance
strained-Si channel n- and p-MOSFETs [30, 31, 50, 52], until recently very
little information on the design issues was available in the literature.
Careful design considerations are necessary for gate oxide, strained-Si
and graded SiGe layer thicknesses, Ge content and profile, and substrate
doping required to control the threshold voltage to optimize the device
performance. A simulation study of strained-Si short-channel p-MOSFETs
has been presented by Armstrong and Maiti [59, 60] and verified by
comparison with experimental device measurements. Analytical models for
both electron and hole mobilities in strained-Si and SiGe were incorporated
into the ATLAS device simulator to evaluate the strain dependence of
transconductance on temperature. In the case of a p-MOSFET, the use
of a graded SiGe buffer layer reduced the valence band discontinuity
at the strained-Si/SiGe interface and decreased the hole concentration
in the buried parasitic SiGe channel to give an overall increase in
transconductance.
The basic device structures considered for simulation are similar to
those shown in figure 6.9 and the device data used in simulation are given
in table 6.3. A 0.8 µm strained-Si channel p-MOSFET (figure 6.9(a),
abrupt case) on an Si1−x Gex buffer cap (0.9 µm) grown on top of a step-
graded 2.1 µm relaxed-SiGe buffer layer, having a 100 Å gate oxide and a
135 Å thick strained-Si layer was considered. However, in this structure,
a parasitic buried channel is formed at the strained-Si/SiGe interface
and leads to device performance degradation due to lower hole mobility
in the relaxed-SiGe channel. In the other device structure considered
(figure 6.9(b), graded case), a thin (300–400 Å) graded strained-Si1−y Gey
buffer cap (grade-back layer) was sandwiched between the strained-Si layer
Table 6.3. Strained-Si channel p-MOSFET device data used in simulation.

Device type Abrupt Graded
structure structure
Strained-Si channel (Å) 100 150–220
Gate length (µm) 0.8 0.8
Oxide thickness (Å) 100 135
Ge concentration (x) 0.1–0.3 0.04
Buffer cap (µm) 0.9 –
Grade-back layer (Å) – 300–400
Relaxed-SiGe layer (µm) 2.1 0.7
(150 Å) and relaxed-Si1−x Gex layer (0.7 µm) to avoid the problem of
hole confinement at the strained-Si/SiGe interface, as the valence band
discontinuity is reduced because of Ge grading. For simulation, a channel
length of 0.8 µm and a 130 Å gate oxide thickness were considered.
To account for the enhanced mobility both in strained-Si and SiGe
layers, the low-field hole mobility for Si1−x Gex was modelled following
[61]. The doping concentration and temperature-dependent mobility due
to Arora [62] was modified by using an analytic expression involving Ge
content, x, as

µ(x, T, N ) = µArora (T, N ) 1 + 4.31x − 2.28x2 (6.1)
and µArora is given by

αp β
T µ2p (T /300) p
µArora (T, N ) = µ1p + γ (6.2)
300 1 + N/Ncp (T /300) p
where µ1p = 54.3 cm2 V−1 s−1 , µ2p = 407.0 cm2 V−1 s−1 , αp = −0.57,
βp = −2.23, γp = 2.546 and Ncp = 2.67 × 1017 cm−3 . Mobility due to alloy
scattering is given by [61]
−1
[µalloy ] = x(1 − x) exp(−7.68x)/124.1 (6.3)
for x ≤ 0.2 and

−1
[µalloy ] = exp(−2.58x)/2150 (6.4)
for 0.2 < x < 0.6.
The modified Arora mobility and the mobility due to alloy scattering
were combined using Mathiessen’s rule and implemented for SiGe regions
in the ATLAS simulator. As the low-field hole mobility in strained-Si
increases with increasing strain (i.e., with Ge mole fraction, x, in the
Simulation of strained-Si HFETs 215
substrate [61]) and due to the absence of alloy scattering in strained-

Si [11], the enhancement in hole mobility in strained-Si was considered to
be the same as in SiGe (but without alloy scattering) in accordance with
equation (6.1). This model was implemented for the strained-Si region
through an external C function, which is accessible to ATLAS through its
C-interpreter interface.
The effect of Ge content x on the transconductance at low drain voltage
is shown in figure 6.13 and compared with a control bulk-Si device. A
strained-Si device with an abrupt SiGe cap layer shows a transconductance
(mobility) enhancement factor up to 1.6 for x = 0.3, comparable with the
theoretically predicted hole mobility enhancement [31].
Figure 6.13. Simulated linear transconductance at 300 K (VDS = −0.1 V) for

an n+ -gate strained-Si p-MOSFET (abrupt case) with Ge content (x = 0.10,
0.20 and 0.30) and control-Si device. (After Armstrong G A and Maiti C K 1998
Solid-State Electron. 42 487–98.)
When a grade-back layer is introduced (see figure 6.9(b)) the problem

of confinement of holes at the strained-Si/SiGe interface can be avoided, as
valence band discontinuity is reduced because of Ge grading. It has been
shown that for a graded cap layer thickness of 40 nm, the discontinuity
in the valence band is almost zero. Hence, confinement of holes and
subsequent formation of a parasitic buried channel is reduced and the device
becomes a surface channel device. The simulations showed agreement with
the experimental results of Rim et al [30], who concluded that the optimal
confinement of holes occurs for a graded Si0.7 Ge0.3 buffer cap thickness of
40 nm, and gives rise to an enhancement in transconductance of 30%.
A separate simulation of a surface-channel long-channel strained-Si
n-MOSFET (see figure 6.5(a) for a typical device structure) has been
reported by Armstrong et al [60]. The channel doping was 1016 cm−3 .
Figure 6.14(a) shows the simulated output characteristics for a transistor
having a gate length of 2 µm and a width of 7.5 µm at room temperature for
different gate bias. The experimental output characteristics are also shown,
in figure 6.14(b); the data are reproduced from figure 3(a) in [53]. A good
agreement between the simulated and experimental data is observed.
A hydrodynamic (HD) simulation using TMA–MEDICI [63] has been
used to simulate the deep-submicron (0.1 µm) strained-Si n-MOSFETS
[54]. Low lateral field mobility models fitted to the measured mobilities
(see figure 6.8) for the strained-Si and epi-Si control devices. In the
simulations, high-field transport was modelled using a Caughey–Thomas-
like mobility expression, modified to account for the velocity overshoot
which results from a local solution of the energy balance equation [63, 64].
Figure 6.14. Output characteristics of a surface channel strained-Si

n-MOSFET: (a) simulated and (b) experimental data. (After Welser J J et al
1992 IEEE IEDM Tech. Dig. pp 1000–3.)
MODFETs 217
Figure 6.15. Electron velocity in the channel of a 0.1 µm n-MOSFET calculated

by hydrodynamic simulation. Higher mobility in strained-Si enhances the carrier
velocity. Use of higher values of τω and vsat for strained-Si in hydrodynamic
modelling further increases the velocity (see text). (After Rim K et al 1998
IEEE IEDM Tech. Dig. pp 707–10.)
An energy relaxation time of 0.1 ps was obtained by fitting the measured

transconductance for the unstrained Si MOSFETs [65]. A small increase
in saturation velocity for strained-Si was observed. Figure 6.15 shows the
electron velocity along the channel. Comparison of the HD simulations
to the measured data indicates that carrier transport is improved in
strained-Si MOSFETs by both enhanced low-field mobility, and reduced
carrier scattering at high field and energy. This is consistent with the
trends predicted by MC calculations for steady-state and transient carrier
transport in strained-Si.
6.5. MODFETS
In a modulation-doped FET, carriers are separated from their parent donor

or acceptor atoms as they fall across a heterojunction to a lower energy
undoped layer. A typical MODFET structure consists of a thin (5–30 nm)
well with quantized states in which the carriers move collision-free (two-
dimensional electron or hole gas (2DEG or 2DHG)); n-wells are strained-
Si [66, 67], while p-wells are SiGe (typically up to 30% Ge) [68, 69]. Doping
Figure 6.16. Typical layer sequence (a) n-MODFETs with Si channel on a

relaxed-SiGe buffer, (b) p-MODFET with SiGe channel and (c) p-MODFET
with Ge channel on a relaxed-SiGe buffer. (After Schaffler F 1997 Semicond.
Sci. Technol. 12 1515–49.)
is accommodated in a neighbouring SiGe layer or in an Si layer separated

from the well by a thin undoped spacer (2–20 nm). The doped layer can
be several nm thin or only a sub-atomic δ-doped layer.
Figure 6.16 shows the layer sequence typically used for n-MODFETs
with an Si-channel and graded-SiGe buffer layer. The creation of high-
quality quantum wells requires a careful adjustment of the layer thicknesses,
composition, strain states and the doping levels. A detailed discussion
on design strategy and layer sequence of a MODFET is given in [13].
Extensive experimental work on the modulation-doped structures (mostly
n-MODFETs) involving strained-Si on relaxed-Si1−x Gex layers has been
performed by several groups [41, 66].
Early work used a uniform composition SiGe buffer, while recent work
uses a compositionally graded buffer. Linear or step-grading is essential
to minimize dislocation faults and buffer layers have to be thick (3 µm)
for strained-Si channels. Device fabrication steps include low-temperature
processing to avoid degradation of the abruptness of the heterointerfaces,
mesa etching and a Pt/Ti/Au Schottky gate with a barrier height of about
0.9 eV. Table 6.4 summarizes important parameters of some of the n-
MODFETs reported in the literature. The dependence of n-MODFET
performance on strain in the Si well and the quality of the SiGe buffer
layer at different temperatures are indicated.
The improvement in transconductance obtained in employing a
compositionally graded buffer layer with optimized layer design occurs
principally by minimizing the distance between the 2DEG and the Schottky
gate. For 1.2% strain in Si, a room temperature transconductance of
MODFETs 219
Table 6.4. Dependence of n-MODFET performance on strain in Si and quality

of SiGe buffer layer at different temperatures.
Type of Gate Low-field gm (mS mm−1 )

SiGe buffer length Temp. mobility (∗∗ extrinsic)
used (µm) (K) (cm2 V−1 s−1 ) (∗ intrinsic) Ref
1% strain in Si channel
Uniform comp. 1.6 300 1550 40∗∗ [67]
Si0.75 Ge0.25 70∗
0.2 µm
1.3% strain in Si channel
Uniform comp. 1.4 300 1090 80∗∗ [70]
Si0.68 Ge0.32 88∗ [71]
0.3 µm
Si0.5 Ge0.5 /Si 155∗∗
Comp. graded 1.4 300 60–72∗∗ [72]
Si0.7 Ge0.3 77 100–133∗∗
1.5 µm
300 340∗∗
300 380∗
77 670∗∗
77 800∗
Step graded 0.25 300 1500 330∗∗ [66]
Si0.7 Ge0.03 77 9500 600∗∗
(defect density
104 cm−2 )
Step graded 0.5 300 2600 390∗∗ [73]
Si0.7 Ge0.3 77 520∗∗
340 mS mm−1 for a 1.4 µm gate length [72], 390 mS mm−1 for a 0.5 µm
gate device [66], and 330 mS mm−1 for a 0.25 µm gate device [73] have
been obtained. At room temperature, the highest reported Hall mobility
was 2830 cm2 V−1 s−1 [72]. At 77 K and for 1.2% strain, transconductance
of 670 mS mm−1 for a 1.4 µm gate device [72], 520 mS mm−1 for a 0.5 µm
gate device [73] and 600 mS mm−1 for a 0.25 µm gate device [66], have been
measured. Ismail et al [73] have also shown an improved gate design that
resulted in a lower leakage at high temperature. These encouraging results

are comparable to those reported for high electron mobility transistors
(HEMTs) fabricated in GaAs [74].
The first reported p-channel MODFET in strained-Si grown on a
relaxed-SiGe buffer was with a TiSi2 Schottky-barrier gate contact [68].
Transconductances of 2.5 and 3.2 mS mm−1 were measured at 300 K for
enhancement- and depletion-mode devices, respectively. Arafa et al [75,76]
have described a very high-speed p-type SiGe MODFET using Si1−x Gex
channel with x ∼ 0.70 and mesa separation with Ti/Pt/Au Schottky gate.
The structure is shown in figure 6.17, where an inverted layer sequence
is used. For the channel, the Ge is graded from x = 0.70 to x = 0.55
(from bottom to top) to prevent holes from being pulled to the upper
heterointerface under negative gate bias. These structures have resulted
in a hole mobility of 800–1000 cm2 V−1 s−1 at room temperature and of
3300–3500 cm2 V−1 s−1 at 77 K. For a gate length of 0.25 µm, a peak
transconductance of 230 mS mm−1 (almost double that of an equivalent
silicon p-MOSFET), has led to a unity current gain cut-off frequency
of 24 GHz and a maximum oscillation frequency of 37 GHz at room
temperature. Further improvements may be expected in shorter gate
Figure 6.17. Device structures for a high-mobility p-MODFET with a SiGe

channel on a relaxed-SiGe buffer. (After Arafa M et al 1996 IEEE Electron
Device Lett. 17 124–6.)
MODFETs 221
Table 6.5. Si/SiGe n-MODFET device structure data used in simulation.
Layer sequence Thickness (Å) Doping (cm−3 )

Si cap 50 1014
SiGe buffer 100 –
Top supply layer 40 1.5 × 1019
Spacer (SiGe) layer 30 –
Strained-Si channel 90 –
Spacer (SiGe) layer 30 –
Bottom supply layer 40 8 × 1018
SiGe buffer 100 –
Gate length (µm) 0.18 –
Ge concentration (x) 0.4 –
length devices by introducing self-aligned gate technology for a reduction

in gate/source series resistance.
In the following, we consider the Si/SiGe n-MODFET described by
Gluck et al [77]. This device was noteworthy (in 1997) as a high-
performance MODFET could be realized in SiGe technology, leading
to a maximum oscillation frequency of 81 GHz. In the following, we
present some results on the high-frequency performance of Si/SiGe n-
MODFETs investigated using a computer simulation for Schottky gate
devices. The SiGe MODFET device layer sequence, thickness and doping
used in simulation are shown in table 6.5. The device is depletion mode
and operates with the formation of an inversion layer at the heterojunction
in strained-Si.
The spacer layer (30 Å) and strained-Si channel (90 Å) are assumed
to be nominally undoped (∼ 1014 cm−3 ) but the substrate (relaxed-SiGe
buffer) is doped p-type (1000 Ω cm). The top and bottom SiGe supply
layers (with doping levels 1.5 × 1019 cm−3 and 8 × 1018 cm−3 , respectively)
supply carriers to the channel. The supply layers are separated by spacer
layers (30 Å) from the heterojunction to prevent ionized impurity scattering
in the channel. The variables for simulation are the substrate doping,
spacer layer thickness, supply layer doping and source-to-drain separation.
The strained-Si channel is maintained at a thickness of 90 Å throughout
and is nominally undoped. A constant gate length of 0.18 µm has been
used. The material parameters and models needed for the simulation are
similar to those of the SiGe HBTs as discussed in chapter 4.
Most of the relevant transistor parameters, such as transconductance,
transit frequency and maximum oscillation frequency, are determined from
simulation. Figure 6.18 shows the simulated and experimental room
Figure 6.18. Simulated and experimental dc output characteristics of a 0.18 µm

gate length SiGe MODFET. Experimental data is from Gluck M et al 1997
Electron. Lett. 33 335–7.)
temperature dc output characteristics of a 0.18 µm gate length SiGe

MODFET. A comparison of experimental and simulated current gain and
maximum unilateral power gain (MUG) is shown in figure 6.19. The
predicted unity gain cut-off frequency of 46 GHz and maximum oscillation
frequency of 80 GHz well match the experimental measurement.
In figure 6.20, it is clear from the simulated transconductance that
the quantum well channel is not completely depleted at zero gate bias.
Figure 6.21 shows the gate bias dependence of cut-off frequency of a typical
device. The frequency maximum appears at almost the same gate bias
as the transconductance maximum. The drain-source voltage dependence
of the device (see figure 6.22) shows that high cut-off frequency is even
obtained at low voltages (VDS ≥ 1–1.5 V). As good performance is achieved
at reduced drain bias, these devices are attractive for low-power circuit
applications with reduced supply voltages.
Over the last few years, SiGe heterostructure FET devices with
outstanding RF performance have been demonstrated. Schottky gate
MODFETs, with fmax of up to 92 GHz (the highest maximum frequency
of oscillation reported so far for any Si-based FET) and a peak
transconductance of 470 mS mm−1 , have been achieved [78]. The n-SiGe
MODFET combines the advantages of a heterodevice with well-established
Si technology. For p-SiGe MODFETs, cut-off frequencies of 70 GHz and
fmax of 84 GHz have been measured.
MODFETs 223
Figure 6.19. Simulated and experimental current gain and maximum unilateral
gain (MUG) as a function of frequency. Experimental data is from Gluck M et
al 1997 Electron. Lett. 33 335–7.)
Figure 6.20. Transconductance of a 0.18 µm n-MODFET.

Figure 6.21. fT as function of gate voltage for a 0.18 µm n-MODFET.
Figure 6.22. fT as function of drain-source voltage for a 0.18 µm n-MODFET.
Figure 6.23 shows computed cut-off frequency for an n-SiGe MODFET

as a function of gate length [78]. The factor of improvement ranges from
around four for a 1 µm gate length down to a limiting value of two for
the shortest gate length. Much of the projected improvement is due to
higher mobility, but a part is attributed to the higher saturation velocity
of the SiGe MODFET (107 cm s−1 compared to 6 × 106 cm s−1 for the
Si-MOSFET) [79, 80]. Figure 6.24 shows transit and maximum oscillation
MODFETs 225
Figure 6.23. Computed performance potential for n-type HFETs with and
without velocity overshoot. (After Konig U et al 1998 J. Vac. Sci. Technol. B
16 2609–14.)
Figure 6.24. RF performance potential for SiGe HFETs. fT and fmax as a

function of gate length for n- and p-SiGe MODFETs are shown. (After Konig U
et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)
Figure 6.25. Calculated gate delays of SiGe hetero-CMOS circuits as a function

of gate length and width. Experimental results from n-type SiGe HFET devices
are also shown. (After Konig U et al 1998 J. Vac. Sci. Technol. B 16 2609–14.)
frequencies as a function of gate length for measured results on wide

ranging devices of both n- and p-SiGe MODFETs manufactured by IBM
and Daimler–Benz [78].
A test chip for digital applications containing inverters, level shifters
and ring oscillators has been realized [81]. For digital logic design using
SiGe HFET inverters, a second stage to shift the output stage to the input
levels is required. Large signal measurements at a supply voltage of 2 V
have shown a gate delay of 70 ps for a device with a gate length of 0.3 µm
and a delay of 25 ps for a 0.15 µm gate length, after correcting the RC
delays of the test set using appropriate on-wafer calibration structures.
Simulations (figure 6.25) predict gate delays below 10 ps even at high loads
and even for gate lengths exceeding 0.1 µm. A demonstration chip set,
including ring oscillators, inverters, differential amplifiers and different test
devices, has also been developed [82].
6.6. HETEROJUNCTION SI/SIGE CMOS
The demonstration of the superior performances of strained-Si MODFETs

and MOSFETs has led to the proposal of combining n- and p-channel
devices in a CMOS circuit. Owing to a barrier confined carrier transport in
quantum wells with higher mobility, higher vsat and higher carrier density,
Heterojunction Si/SiGe CMOS 227
one can expect higher transconductance, higher speed, lower gate delay,
lower noise and low power consumption. Due to the enhanced performance
of p-HFETs, equally sized p- and n-FETs can be designed for higher
packing density. While standard CMOS need a gate length below 0.2 µm
for transconductance around 400 mS mm−1 [83, 84], these are even found
at gate lengths of 1.2–1.4 µm with HFETs.
The advantages to be gained by using strained-Si/SiGe in conventional
Si-CMOS technology have been examined by several workers [64,85–88]. As
high electron mobility (2200–3000 cm2 V−1 s−1 ) [28] in strained-Si channels
under tensile strain and hole mobility (800–1500 cm2 V−1 s−1 ) [89] in
compressively strained SiGe channels have been achieved, both n- and p-
type modulation-doped FETs have been fabricated using both strained-Si
and SiGe layers.
For the n-MODFET, the n-doped (phosphorus, 25 keV, 5×1014 cm−2 )
Si0.7 Ge0.3 layer was separated from the Si channel by a spacer of 30 Å thick
Si0.7 Ge0.3 . The Schottky gate was formed by Pt. At a 0.4 µm gate length,
the measured peak transconductance of 420 mS mm−1 was a factor of
two higher than an equivalent Si n-MOSFET, and comparable to GaAs
technology. The microwave performance was also impressive, with an fT
of 40 GHz and an fmax of 56 GHz for a 0.4 µm gate length [85]. This level
of performance is comparable to that of a GaAs/AlGaAs HEMT, and may
potentially be further improved if an insulating SOI substrate is used [90].
For the corresponding p-MODFET, the Si0.7 Ge0.3 layer was doped
with boron, followed by a 25 Å thick spacer, and then a strained 40 Å
Si0.3 Ge0.7 channel, which was finally capped with a 200 Å thick Si0.7 Ge0.3
layer. The peak intrinsic transconductance of 280 mS mm−1 at a 0.23 µm
gate length was more than double the value of the equivalent Si p-MOSFET
at the same gate length, with corresponding high values of fT of 30 GHz
and fmax of 45 GHz [85].
It has been predicted that sub-0.2 µm SiGe HFETs will yield more
than 800 mS mm−1 at room temperature and above 1000 mS mm−1
at 77 K [9]. Figure 6.26 shows the predicted transconductance for
HCMOS extrapolated from measurements on 1.2–1.4 µm MODFETs in
comparison to the best Si-MOSFETs. These results are corroborated by
experimental demonstrations [77,85], which are both based on s-parameter
measurements on mesa-type devices with submicron gates defined by e-
beam lithography.
Based on the above experimental demonstration, using computer
simulation, O’Neill and Antoniadis [64, 87] have investigated the high-
frequency (microwave) performance of submicron p- and n-channel
Si/SiGe-based FETs suitable for CMOS technology. Two-dimensional
simulation of devices, having gate lengths down to 0.1 µm using a
hydrodynamic model, demonstrated an enhancement in fT of around 50%
for n-channel devices and more than 100% for p-channel devices.
Figure 6.26. Predicted transconductance of high-performance HCMOS

extrapolated from measurements on 1.2–1.4 µm MODFETs, in comparison with
best Si-MOSFETs. (After Konig U and Daembkes H 1995 Solid-State Electron.
38 1595–602.)
Ismail [85] has modelled the performance of Schottky gate

complementary MODFET structures, where electrons flow through a
strained-Si channel and the holes through a strained-SiGe layer, both
channels being epitaxially grown on Si substrates (see figure 6.27). For
a 0.1 µm gate length, the calculated peak transconductance of the n-
MODFET was 820 mS mm−1 , whereas that of the p-MODFET was
610 mS mm−1 . The predicted delay for an inverter was 11 ps at a power
dissipation/stage of 0.07 mW. The power delay product of Si/SiGe CMOS
is evidently lower than Si CMOS or SOI technology while operating at a
lower supply voltage.
Due to inherent problems, such as nonplanarity, higher leakage
current, difficulty in threshold voltage adjustment and reproducibility for
manufacturing associated with Schottky gates, the authors also studied
Si/SiGe CMOS structures, as shown in figure 6.28. The structure is planar
and uses SiO2 as a gate insulator and polySi as the gate material. In this
case, an Si cap layer was used, on which either a low-temperature oxide
(LTO) was deposited, or a gate oxide was thermally grown. For an effective
gate length of 0.1 µm and with an oxide thickness of 50 Å, the predicted
transconductances of n- and p-MOSFETs are 750 and 600 mS mm−1 ,
respectively.
Several authors [86, 88] have proposed the design for an Si/SiGe
heterojunction CMOS which is planar and avoids inversion of the parasitic
surface channel within the operating voltage range. The schematic cross
Heterojunction Si/SiGe CMOS 229
Figure 6.27. Complementary Si/SiGe MODFET cross section. (After Ismail K

Figure 6.28. Complementary Si/SiGe MOSFET cross section. (After Ismail K

(a)
(b)
Figure 6.29. (a) Cross section of a proposed Si/SiGe HCMOS technology and
(b) schematic diagram of channel layers and conduction and valence band for
gate bias just above VT . (After Armstrong M A et al 1995 IEEE IEDM Tech.
Dig. pp 761–4.)
section of such a proposed structure is shown in figure 6.29. As discussed

above, the design provides for both a compressively strained-SiGe hole
channel and a tensile strained-Si electron channel in a planar structure.
The layers are grown on a low defect density (1 × 105 cm−2 ) relaxed graded
SiGe buffer. The p-well is in situ doped during growth of the relaxed
buffer, while the n-well is created by ion implantation prior to growth of
the channel layers. An undoped spacer is grown above the well doping
in order to adjust the threshold voltage. An n-type δ-doped layer is used
to bend the energy bands so as to avoid inversion of the low-mobility Si
surface channel. The strained-Si electron channel is separated from the
δ-doped layer by an undoped setback layer to minimize ionized impurity
Summary 231
Figure 6.30. Power delay product versus stage delay for Si/SiGe HCMOS and
bulk-Si CMOS. The corresponding drain bias values are indicated on the curves.
(After Armstrong M A et al 1995 IEEE IEDM Tech. Dig. pp 761–4.)
scattering. A graded Ge content is used in the strained-SiGe hole channel

to minimize the surface roughness scattering by pushing the carriers away
from the oxide interface. A thin Si cap layer allows a high-quality gate
oxide to be grown. An in situ doped p+ -polySi gate is used for the devices.
Device and circuit simulations show the performance advantage of
the proposed technology over bulk-Si CMOS for an effective gate length
of 0.2 µm. Figure 6.30 shows the simulated power delay product versus
stage delay of an 11-stage inverter ring oscillator, comparing Leff = 0.2 µm
Si/SiGe HCMOS to bulk-Si CMOS, for unloaded and loaded (CL = 10 fF)
cases. The higher carrier mobility of the HCMOS results in a sixfold
improvement in the power delay product at a stage delay of 28 ps for
the unloaded case and a fourfold improvement at a delay of 55 ps for the
loaded case. A minimum delay of 22 ps is predicted for unloaded Si/SiGe
HCMOS running at 1.5 V.
6.7. SUMMARY
In this chapter, recent progress in strained-Si on relaxed-SiGe buffer has

been reviewed. Progress in design and fabrication of high mobility n-
and p-channel strained-Si/SiGe devices (MOSFETs and MODFETs) were
presented, as well as some of the materials and processing issues related

to the fabrication of these heterostructures. Due to their compatibility
with conventional Si-processing technology, mobility enhanced HFETs
are expected to provide performance advantage, when down scaling
in device dimensions will no longer be possible in bulk-Si. Since
low-power mixed-mode circuits are becoming increasingly important for
mobile communications, Si/SiGe heterojunction CMOS technology will
be useful for the improvement of high-frequency performance. However,
from a manufacturing point of view, several issues of concern, such as
device isolation, interconnects and reliability, require further experimental
investigation in order to assess the true potential of Si/SiGe HCMOS.
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Chapter 7
SIGE HETEROSTRUCTURE FETS
Over the past 20 years, the channel length of MOS transistors has halved at
intervals of approximately three or four years. This continual shrinking of
the size of MOS transistors has led to increasing performance in electronic
systems and increasing packing density. The question that arises now is
‘how long can this trend continue?’ A number of factors are posing a threat
to the evolution of CMOS technology. Firstly, the channel length of the
MOS transistor is defined using optical lithography, which is limited by
the wavelength of the radiation used. The current thinking is that optical
lithography can reach channel lengths of around 0.15 µm, but it is not clear
that it can meet the challenge of smaller geometries. Other lithography
techniques exist, such as electron beam and x-ray lithography, but these
have associated problems that remain to be solved.
Improvements in MOSFET saturated drain current have been achieved
by shrinking the source-to-drain separation or effective gate length (Leff )
and through the use of thinner gate oxides to increase the gate capacitance
to improve inversion charge density. Predictions for static random access
memory (SRAM) technology anticipate gate oxide thicknesses of the order
of 4 nm and gate lengths of 0.15 µm (see table 7.1) [1]. However, the
requirement for highly uniform gate oxide films across a large wafer calls
into question the continuous reduction of gate oxide thickness to improve
inversion charge density. Also, below 0.35 µm gate lengths, the carriers
in the channel of the MOSFET attain a saturated velocity that is nearly
independent of Leff . As a result of these two limits—oxide scaling and
carrier velocity saturation—it appears that the MOSFET saturated drain
current is approaching a fundamental physical limit.
In chapter 6, on strained-Si, it has been shown that electron or hole
confinement structures (n-HFET or p-HFET) require more complex growth
techniques for strained-Si on relaxed thick SiGe layers, and are limited in
terms of processing thermal budget. In contrast, the p-HFET is more easily
realized, since it involves the growth of strained-Si1−x Gex epitaxial films
238
SiGe heterostructure FETs 239
Table 7.1. CMOS scaling guidelines. (After Davari B 1996 IEEE IEDM Tech.
Dig. pp 555–8.)
1995 1998 2001 2004

Lithography resolution µm
General 0.5 0.35 0.25 0.18
Gate level for short L 0.35 0.25 0.18 0.13
Channel length (µm) 0.35/0.25 0.2/0.15 0.1 0.07
Gate insulator thickness (nm) 9/7 6/5 3.5 2.5
Supply Voltage (V)
High performance 3.3/2.5 2.5/1.8 1.5 1.2
Low power 2.5/1.5 1.5/1.2 1.0 0.8
Relative speed
Low power 2.0/2.4 3.2/3.5 4.5 5.8
Relative power/function
Low power 0.20/0.09 0.08/0.056 0.036 0.027
on an Si substrate. In this device, the Si1−x Gex quantum well acts as a

channel for holes between the source and drain regions of the device, as
shown in figure 7.1. Improved electrical characteristics of this device over
the conventional surface channel Si p-MOSFET are the results of improved
carrier transport, quantum confinement and buried channel operation.
p-HFETs provide quantum confined carrier conduction with high carrier
mobility, which is critical for high-frequency Si-based integrated circuits.
Some of the key parameters of several reported SiGe-channel devices are
shown in table 7.2.
High saturated drift velocity of holes, due to strain-induced transport
enhancements in SiGe, allows for equivalently sized n- and p-channel
devices and, consequently, increased circuit densities. Coupled to this, the
ability to produce quantum devices on the same chip gives SiGe substantial
potential for advanced circuits. SiGe channel p-HFETs have the following
potential advantages:
• large carrier population in the channel at low gate biases due to

quantum confinement;
• buried channel operation to suppress hot carrier effects;
• low defect density using conventional Si substrates; and
• process compatibility with existing CMOS process lines.
240 SiGe heterostructure FETs
Figure 7.1. Device structure for a typical SiGe-channel p-HFET fabricated in

a strained-SiGe layer with an Si-cap layer. Layer thicknesses shown are typical.
Table 7.2. Some of the reported results for SiGe p-HFETs.

gm,ext (mS mm−1 )
Gate
Leff Channel Gate
300 K 77 K tox (Tech.) Ref
µm (mode) material
buried-SiGe
0.18 – – 45 Å Ther. n+ poly [2]
(enhanced)
buried-SiGe
0.25 167 201 71 Å Ther. TiSi2 [3]
(enhanced)
buried-SiGe
0.7 64 – 50 Å Ther. polySi [4]
(enhanced)
buried-SiGe
0.9 – – 70 Å PECVD n+ poly [5]
(enhanced)
surface-SiGe
1.0 48 60 100 Å ECR n+ poly [6]
(enhanced)
buried-SiGe
1.0 80 – 65 Å WRTO p+ poly [7]
(depletion)
buried-Ge
4.0 – 50 500 Å CVD Al [8]
(enhanced)
HFETs: structures and operation 241
In this chapter, a review on the present status of silicon heterostructure

field effect transistors in the SiGe and SiGeC material systems is presented.
The physics and modelling of submicron p-HFETs are explored using
numerical simulation to determine the potential applications in ULSI
circuits. The key design issues such as Ge mole fraction, gate oxide
thickness and choice of gate contact material have been considered in
detail. The choice of the cap layer thickness for a buried SiGe channel
is an important issue, having a bearing on the performance of a p-HFET,
and due consideration is given.
Also considered are a number of variants of the basic SiGe HFET, p-
HFETs built on SOI substrates and SiC/SiGeC channel devices. Vertical
SiGe and SiGeC p-HFETs are also attractive for ultra-short channel devices
because the channel length is determined by the thickness of an epitaxial
layer and not by the lithography resolution. Vertical channel and scaling
issues are considered. Poly-Si1−x Gex has shown great potential as a
gate material due to its tunable work function, process compatibility and
favourable electrical properties, such as low sheet resistance and high
dopant activation rate. It can also be used in place of polySi in thin-
film transistors on glass. Finally the noise properties of SiGe p-HFETs are
considered.
7.1. HFETS: STRUCTURES AND OPERATION
A SiGe p-HFET with a general structure similar to a conventional

MOSFET is shown in figure 7.1. It has an n+ (or p+ )-polySi or poly-
SiGe gate over a thin gate oxide, with p+ source/drain regions in an n-
type body. The main distinctive features are the buried SiGe layer and
the optional p+ doping spike (δ-doping) located below it. The SiGe layer
actually constitutes a sub-surface quantum well channel for holes between
the source/drain regions. It is required to be buried below an Si-cap
because a high-quality gate oxide directly on SiGe using thermal techniques
is difficult to obtain. If such a direct oxidation of SiGe is attempted, the
Si is preferentially oxidized, leading to a pile-up of Ge at the SiGe/SiO2
interface [9, 10]. Plasma enhanced chemical vapour deposited (PECVD)
oxides do not have significantly lower interface state densities, since the
initial stages of this process consist of oxide growth and not deposition [11].
The interface state density of such oxides is greater than 1012 cm−2 eV−1 , a
figure unsuitable for proper operation of a field-effect device. Stoichiometric
oxides formed directly on SiGe using low-temperature plasma techniques
have been reported [12,13] and microwave/ECR plasma grown oxides have
been used for device fabrication [6].
The use of an Si-cap layer has been customary as oxidation of the Si-
cap assures formation of a high-quality gate oxide. But this requirement
reduces the efficiency of the device, to which the high mobility carriers in
the SiGe layer can be modulated, due to the increased physical separation
from the gate potential and the presence of a surface inversion layer
that forms at high gate overdrive. However, the buried channel provides
benefits, such as the suppression of hot carrier injection into the gate
oxide and reduced carrier surface scattering, which tend to enhance device
performance and reliability. The next important feature of the device is
the presence of an optional δ-doping spike, which is generally realized using
boron. The doping spike is separated from the SiGe channel by an Si spacer
to reduce ionized acceptor scattering which occurs if the spike is placed
too close to the channel. Furthermore, the doping spike is placed below
the SiGe channel, so that the application of a negative gate bias draws
holes upward towards the SiGe channel. The doping spike has two major
functions:
(i) it creates a retarding electric field for holes at zero gate bias to
suppress source/drain leakage current (threshold adjust); and
(ii) it provides holes for the SiGe quantum well for improved device
transconductance.
For high-speed operation, the p-HFET should be operated under bias

conditions in which the hole density in the SiGe well exceeds that in the
Si-cap. Determining this bias range requires the calculation of the hole
density in the two inversion layers as a function of gate bias.
7.1.1. Experimental HFETs

Several research groups have fabricated SiGe-channel p-HFETs, mostly
using conventional Si-processing technology, and performance enhancement
compared to bulk-Si devices has been reported [2–8]. In some designs, the
Ge profile was graded to optimize the hole confinement and modulation
doping (δ-doping) was used to adjust the threshold voltage. The cross
section of such a SiGe-channel p-HFET, also known as a modulation-doped
SiGe p-MOSFET (MODMOS), is shown in figure 7.2 [5].
In table 7.2, some of the key parameters are compared for some of
the reported p-HFETs including those fabricated on Ge substrate [8] and
on SIMOX [7]. Deep submicron (gate length 0.18 µm) SiGe-channel p-
HFETs using strained-Si1−x Gex films in a standard CMOS process have
been reported by Bouillon et al [2]. The channel architecture of the p+ -
polySi gate Si0.85 Ge0.15 channel p-HFET is shown in figure 7.3. Several
0.18 µm transistors with different architectures were fabricated. Retrograde
channel profile, heavy ion implant (HI) using P and As, followed by
intrinsic Si epitaxy and conventional processing techniques, were employed.
The enhancement of hole mobility in the direction perpendicular to the
growth plane of strained-Si1−x Gex , and grading the SiGe channel, are
both effective in the enhancement of the drive current. Figure 7.4
HFETs: structures and operation 243
Figure 7.2. Schematic cross section of the modulation-doped SiGe p-MOSFET.

An n+ -gate, together with a boron-doped layer placed underneath the SiGe
channel, is used to enhance the carrier confinement while obtaining the correct
threshold voltage. Devices with three different channel gradings are fabricated:
(a) the abrupt; (b) the graded; and (c) the retrograded profile. (After
Verdonckt-Vandebroek S et al 1994 IEEE Trans. Electron Devices 41 90–102.)
Figure 7.3. Cross section of a 0.18 µm p+ -polySi gate Si0.85 Ge0.15 -channel
p-HFET. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)
Figure 7.4. Output characteristics of a 0.18 µm p-HFET with an Si0.85 Ge0.15

channel. Implantation conditions were: AS2, arsenic 200 keV/1E13; AS4, arsenic
120 keV/4E12; AS1+40, arsenic 120 keV/1E13 + 40 nm cap layer. (After
Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)
Figure 7.5. Subthreshold characteristics of a 0.18 µm p+ -polySi gate

Si0.85 Ge0.15 -channel p-HFET. Implantation conditions were: AS2, arsenic
200 keV/1E13; AS4, arsenic 120 keV/4E12; AS1+40, arsenic 120 keV/1E13 +
40 nm cap layer. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)
Design of SiGe p-HFETs 245
shows the output characteristics, while figure 7.5 compares short-channel

subthreshold characteristics.
7.2. DESIGN OF SIGE P-HFETS
The SiGe HFET design objective is to maximize the device

transconductance. This can be accomplished by maximizing the number
of high-mobility holes in the SiGe channel, while minimizing the density
of low-mobility holes which flow at the Si/SiO2 interface. The critical
SiGe HFET design parameters include the choice of gate material, layer
thicknesses and SiGe channel profile. The type of gate material used
strongly influences the degree of hole confinement to the SiGe channel
p-HFETs [14].
State-of-the-art CMOS technologies are characterized by dual work
function polysilicon gates, such that both the n- and p-channel MOSFETs
are surface-channel devices [15, 16]. A single work function CMOS
technology leads, however, to significant process simplification. The impact
of each of these design parameters on device performance is investigated
with the use of a simulation tool. For the design of deep submicron p-
MOSFETs necessary for ULSI, two-dimensional numerical modelling is
necessary to accurately quantify short-channel effects. Once again the
Silvaco–ATLAS device simulation tool has been used.
7.2.1. SiGe: MOS capacitor simulation

A typical Si/strained-SiGe/Si p-HFET structure, as shown in figure 7.1, is
chosen and subsequent variations in this structure are studied to maximize
the hole concentration in the SiGe quantum well over the realizable gate
bias swing. It is instructive to see the distribution of the hole density in
the Si-cap and SiGe-channel for n+ - and p+ -poly gate contacts. This can
be accomplished using a 1D Poisson solver. A 1D self-consistent solution of
the Schrodinger and Poisson equations have been reported [17]. However,
the use of the Schrodinger–Poisson solver is very time-consuming, so the
simple 1D Poisson solver is deemed to be adequate to illustrate the main
concept. Quantum effects are therefore neglected.
In figure 7.6 the integrated density (cm−2 ) of holes in both the Si-cap
and SiGe quantum well is plotted as a function of gate bias. From this figure
it is seen that, as the negative gate bias is increased, the Si1−x Gex channel
turns on first, and the hole density in the SiGe quantum well increases,
revealing a very interesting effect associated with the buried channel p-
HFET—charge screening. For a p+ -poly contact, a gate bias in excess of
−1.5 V results in a saturation of the hole density in the SiGe quantum
well, while the carrier density in the Si-cap continues to increase. This
saturation of the SiGe hole population is due to the build-up of holes in
Figure 7.6. One-dimensional Poisson simulations of the Si-cap and SiGe-channel

charges for n+ - and p+ -poly gate SiGe HFETs. The channel is 300 Å wide with a
flat 30% Ge profile, oxide thickness is 70 Å and substrate doping is 5 × 1016 cm−3
n-type.
the Si-cap with increasing gate bias. As more holes populate the Si-cap
inversion layer, the effect of the gate potential is screened out and the
quantum well effectively ‘sees’ no increase in the gate potential. The point
at which the number of holes in the SiGe well equals the number in the
Si-cap is termed the ‘cross-over point’.
7.2.2. Si-cap/oxide thickness variation
Figure 7.7 is a plot of the integrated hole density in the SiGe well and Si-
cap layer as a function of cap thickness, for two oxide (tox = 70 and 140 Å)
thicknesses. The plot reveals that when VG = −2.0 V, for tox = 140 Å, the
hole density in the well decreases slightly as the cap thickness is increased,
while the hole density in the Si-cap shows a modest increase. The hole
density in the well drops more dramatically (for tox = 70 Å) as the cap
thickness is increased while the hole density in the cap increases. Therefore,
it is advantageous to keep the cap thickness as small as possible to keep the
hole population in the Si cap low and reduce the effects of charge screening
on the SiGe quantum well.
If the gate oxide is kept thin (∼100 Å), then an initial Si-cap thickness
of 50 Å is sufficient for a uniform oxide to be grown across a wafer surface.
However, it should be noted that a remaining cap thickness of only 10 Å is
enough to support an inversion layer. Hence, the charge screening problem
Figure 7.7. One-dimensional Poisson simulation of areal hole density in the

SiGe well and the Si-cap as a function of cap thickness and oxide thickness.
will still be present with such a structure. Consequently, the device can
be operated at low gate voltages, where the SiGe quantum well dominates
device electrical characteristics. A thinner gate oxide results in a higher
current drive and gm due to the improved capacitive coupling between
gate and channel charges. These improvements in performance will always
overcome the disadvantage of the small reduction in VG arising with the
thinner oxide.
7.2.3. Germanium mole fraction

A higher Ge mole fraction in the channel is desirable from a transport
viewpoint, since the hole mobility in pseudomorphic Si1−x Gex films
increases with increasing Ge content [18]. Figure 7.8 is a plot of integrated
hole density as a function of Ge content. From the figure, it is seen
that hole density in the quantum well increases almost linearly with Ge
content x, once the cross-over point is reached. A capacitance–voltage
(C–V ) measurement of a SiGe HFET is an accurate method to confirm
the presence of the 2DHG in the SiGe quantum well and characterize the
electrical quality of the gate oxide [19].
Figure 7.9 displays the simulated low-frequency and high-frequency
C–V characteristics of a p-HFET at room temperature. The kink in the
characteristics between gate biases of −1 and −2 V is a result of the
quantum well. Initially, during inversion, holes reside in the SiGe quantum
Figure 7.8. Simulated Si-cap and SiGe-channel hole density for n+ -poly gate
SiGe HFETs as a function of mole fraction for a flat Ge profile.
Figure 7.9. Simulated high-frequency (x = 0.2, 0.3 and 0.4) and low-frequency
(x = 0.40) capacitance–voltage characteristics showing the hole confinement in
a p+ -poly gate SiGe HFET with an Si-cap (70 Å), oxide thickness (65 Å) and
a SiGe channel 100 Å wide as a function of Ge mole fraction, x, with a flat Ge
profile.
well. Hence, the structure exhibits a lower effective capacitance due to the
series combination of the oxide and Si-cap capacitances. As the structure
is biased more negatively, the inversion layer in the Si-cap forms and the
capacitance of the structure approaches the oxide capacitance, Cox .
7.2.4. Choice of gate material

The choice of gate material has a significant effect on the turn-
on characteristics of a p-MOSFET. Typically for surface channel Si
p-MOSFETs, a p+ -polySi gate is employed to place the MOSFET threshold
voltage close to −0.5 V. If a p+ -polySi gate is used with a buried
channel, then the device operates in depletion mode. However, if an n+ -
polySi gate is used, then the device threshold voltage is shifted towards
negative by about 1 V. Consequently, the buried channel device operates
in enhancement mode, with the buried channel carrier transport properties
determining the MOSFET electrical characteristics at low gate biases. The
difference between n+ - and p+ -polySi gates for the p-HFET structure is
illustrated in figure 7.10. For the n+ -polySi gate, the SiGe layer dominates
channel conduction for gate biases up to −1.5 V, after which the Si-cap
inversion layer forms. For the p+ -polySi gate, the Si-cap inversion layer
is already present at 0 V gate bias, hence the device operates in depletion
mode. Hence, an n+ gate design is favourable for the p-HFET, because it
promotes SiGe quantum well operation for low gate biases.
Figure 7.10. Threshold voltage versus substrate doping for p+ - and n+ -poly
gate SiGe-channel p-HFETs.
Clearly, based on the foregoing discussions, the cap layer should be

made as thin as possible. However, a minimum value may be obtained by
considering the two primary limitations: avoidance of high interface state
densities (a minimum thickness of silicon cap layer of the order of 50–60 Å
may be required [11]) and the avoidance of remote carrier scattering (by the
insulator–semiconductor interface). Some experimental evidence suggests
the latter limitation may require a cap layer thickness of the order of
100 Å [20]. To enable significant benefit to be gained from the use of buried
strained layer channels in submicron p-HFETs, two options exist: increase
the offset potential between the cap and channel layers or reduce the peak
field in the semiconductor. Growth of the SiGe-channel HFETs on silicon-
on-insulator (SIMOX) substrates is one approach to field reduction [7]. A
simpler alternative to increase transconductance is to use a p+ doping spike
(δ-doping) below the SiGe quantum well.
7.2.5. Current–voltage characteristics

The use of a buried channel (see figure 7.1) is expected to improve carrier
mobility and noise performance by reducing the interaction of carriers with
the oxide interface. As previously discussed, a major constraint on HFET
performance is the onset of parasitic inversion at the Si-cap and oxide
interface, where the carriers face mobility degradation. This limits the
degree of inversion in the strained channel layer by electrostatic screening
and hence degrades the small-signal transconductance.
The material parameters and models needed for the simulation of
p-HFETs are similar to those of SiGe HBTs discussed in chapter 4. A
reduced effective density of state (DOS) in the valence band, Nv , is
inherent in the use of compressively strained SiGe channels on Si [21],
being intimately linked to the enhanced hole mobility [22, 23]. The lower
DOS effective hole mass and the reduced carrier scattering due to the lifting
of the valence band degeneracy are both thought to contribute to higher
mobility. As the Ge fraction x in a strained SiGe layer is increased, Nv is
predicted to fall monotonically [23] by a factor of 5.6 at x = 0.3, an effect
that cannot not be ignored in modelling HFETs. The carrier mobility in
the surface channel was assumed to be degraded with increasing transverse
and longitudinal fields in a similar manner to a conventional MOSFET
using the special purpose (CVT) MOS mobility model [24]. The mobility
in the buried SiGe channel was assumed to be insensitive to the transverse
field and solely a function of doping and longitudinal field.
Fermi–Dirac statistics for the computation of carrier density and a
dense mesh specification for the thin epitaxial layers are required for
accurate modelling of charge distributions and drift–diffusion-based current
formulations have been found to be sufficient for the range of channel
lengths investigated (down to 0.1 µm). An epitaxial Si-cap layer (30 Å)
and a SiGe layer (300 Å) are defined to be doped (1 × 1016 cm−3 and
1 × 1017 cm−3 , respectively), and the underlying substrate (or n-well),
uniformly doped to 1 × 1016 cm−3 . The oxide layer thickness is 80 Å
and interface states are neglected. An n+ -polySi gate is used and the
threshold voltage is allowed to shift freely according to channel doping
and layer thicknesses. The dc output characteristics and small-signal
transconductance have been generated and the respective inversion layer
carrier populations in the Si cap and SiGe channel have been extracted by
integrating the carrier profiles across the depths of the respective layer.
The effect of Ge content on the linear transconductance is shown in
figure 7.11 as a function of gate voltage. When compared to an Si device,
the enhanced mobility in the SiGe-channel p-HFETs gives rise to higher
transconductance, which increases further with Ge content x. The effect
of Ge content on the output characteristics is shown in figure 7.12. As
expected, the drain current increases with Ge content x in a similar manner.
A useful measure for characterizing the subthreshold behaviour of a
MOSFET is its subthreshold swing, S, which is defined as the slope of
the log (ID ) versus VG characteristic, just prior to the threshold voltage,
VT . A low value of subthreshold slope is desirable in submicron gate
length p-HFETs to achieve low threshold voltage and a negligible off-state
leakage. Figure 7.13 illustrates that the incorporation of Ge merely shifts
Figure 7.11. Simulated linear transconductance of a SiGe p-HFET at 300 K

(VDS = 0.1 V) as a function of Ge content in the SiGe channel.
Figure 7.12. Simulated I–V characteristics of a SiGe-channel p-HFET at 300 K

for different Ge content in the SiGe channel.
the threshold voltage and has a negligible effect on the subthreshold slope.
If a δ-doping spike is placed below the active Si1−x Gex channel separated
by a spacer, then the subthreshold characteristic can be significantly
improved [17]. The doping spike creates an electric field that repels holes
for gate voltages below the threshold voltage, significantly improving the
subthreshold swing of the p-HFET.
7.2.6. δ-doped p-HFETs

The δ-doped layer is separated from the SiGe quantum well by a thin
spacer to reduce the effects of ionized impurity scattering. The purpose of
using a δ-doping spike is primarily to reduce the number of holes at zero
bias by creating a retarding electric field which improves the subthreshold
characteristic of the device. However, the doping spike does not contribute
a large number of holes to the SiGe quantum well. The contribution is
a function of the spacer thickness, and generally increases with decreasing
spacer thickness. It has been shown experimentally that a δ-doped acceptor
layer below (but in close proximity to) the SiGe channel allows the inversion
layer carrier concentration in the SiGe channel to be increased [11, 25]. In
addition, the δ-doping layer reduces the threshold voltage for inversion of
the channel and increases VGS . However, locating a narrow highly-doped
boron layer immediately underneath the channel of the n+ gate SiGe HFET
Figure 7.13. Simulated subthreshold characteristics of a SiGe-channel p-HFET

at 300 K for different Ge content in the SiGe channel.
Figure 7.14. Simulated dc characteristics of an Si0.7 Ge0.3 p-HFET with a

δ-doping layer.
places severe limitations on its fabrication since the SiGe channel should
remain undoped.
Figure 7.14 shows the output characteristics of a device with a 30 Å
thick Si cap and effective gate length of 0.5 µm is enhanced by the addition
of a 50 Å thick δ-doping layer (Nδ of 2 × 1018 cm−3 ) with a spacer of 30 Å
below the channel. This very significant increase in the device current
demonstrates the improvement in performance possible through epitaxial
growth capabilities, such as in situ modulation doping, apart from gains
achieved through increased mobility. Note that, in this case, an n+ -polySi
gate is required to ensure enhancement mode operation (negative VT ) in
the same manner as for a conventional buried channel p-MOSFET. The
increase in VGS is largely due to the reduction in the transverse field
achieved by the presence of the fully depleted δ-doped layer.
7.3. SIGE P-HFETS ON SOI
As described in the previous section, a SiGe quantum well p-channel HFET

has been shown to have a higher channel mobility compared to that of a
bulk-Si MOSFET. In order to further improve the channel mobility, the hole
confinement in the quantum well must be enhanced. This is particularly
difficult to achieve at a higher gate voltage, because the surface channel
at the SiO2 /Si interface dominates conduction. As discussed more fully in
chapter 10, fully-depleted SOI (FDSOI) devices have been considered for
ULSI applications because of improved device isolation, reduced parasitic
capacitance and higher circuit speed [26,27]. Due to the presence of a thick
buried oxide layer in an FDSOI device, the vertical electric field and the
band bending at the Si surface are significantly reduced, compared to that
of a bulk-Si device [26]. This property of reduced band bending of an SOI
structure can be used to improve the hole confinement in the buried SiGe
quantum well, and hence improve device performance.
Schematic diagrams of a device used in simulation for bulk-Si and SiGe
SIMOX are shown in figure 7.15. The SiGe SIMOX substrate consists of a
Figure 7.15. Schematic diagrams of a bulk SIMOX substrate and a SiGe SIMOX
substrate in which a p+ -poly gate SiGe-channel HFETs are fabricated. (After
Nayak D K et al 1993 IEEE Electron Device Lett. 14 520–2.)
SiGe p-HFETs on SOI 255
Figure 7.16. Comparison of 1D Poisson simulations of the low-frequency

capacitance–voltage characteristics (showing the hole confinement) in a p+ -poly
gate SiGe HFET on an Si-substrate and on a SIMOX. The simulation was carried
out with an Si-cap (70 Å), the oxide thickness (65 Å) and a SiGe channel 100 Å
wide with a flat Ge profile (x = 0.30).
conventional SIMOX substrate, a 100 Å Si layer, a 100 Å Si0.7 Ge0.3 strained

layer and a 100 Å Si-cap layer. As discussed earlier, one way to verify
the hole confinement in the quantum well is to study the low-frequency
capacitance, where a plateau in the inversion capacitance signifies the hole
confinement [28]. Figure 7.16 shows that the plateau in low-frequency
capacitance associated with the buried channel region extends for a wider
range of gate voltage for the SIMOX substrate, when compared to the SiGe
bulk-Si substrate.
Room temperature hole density profiles for n+ -poly gate SiGe-channel
HFETs on Si and SIMOX substrates are compared in figure 7.17. It is
seen that the hole concentration at the Si surface for the SiGe SIMOX
device is about two orders of magnitude smaller than that for the SiGe
bulk device. This means that the channel conduction through the parasitic
surface channel is significantly diminished, due to reduced band bending
at the surface. The reduced band bending results in a more uniform hole
concentration in the quantum well for the SiGe SIMOX device, a conclusion
that has been confirmed by experiment [7].
It has been shown that the linear transconductance remains near its
peak value for a wide range of gate voltages at 300 K due to significant
hole confinement in the quantum well near the threshold, which is not
observed for SiGe bulk devices. The centroid of the hole distribution in
Figure 7.17. Comparison of 1D Poisson simulations of hole density profiles at

room temperature for a n+ -poly gate SiGe-channel HFETs on Si and SIMOX
substrates. The simulation was carried out with VG –VT = −0.5 V, an Si-cap
(70 Å), the oxide thickness (65 Å) and a SiGe channel 100 Å wide with a flat Ge
profile (x = 0.30).
the Si0.7 Ge0.3 quantum well of the SiGe SIMOX device is located farther
away from the Si/SiO2 interface when compared to that in the SiGe bulk
device, which reduces Si/SiO2 surface scattering for the SiGe SIMOX device
and results in a further improvement in channel mobility. Experimentally
verified improvement in channel mobility of a SiGe SIMOX device over that
of an identically processed SIMOX device is 90% at 300 K [7], whereas the
maximum improvement in channel mobility of a SiGe bulk device over that
of an Si device has been found to be 50% [3, 4]. This large enhancement
of channel mobility for the SiGe SIMOX device is believed to be due to
improved hole confinement in the buried quantum well of this device.
Silicon-on-sapphire (SOS) technology, which integrates both the
microwave and the VLSI digital/analogue signal processing functions, is
ideally suited for microwave circuits since it has a low dielectric loss
substrate, low noise figure, excellent radiation hardness and reduced
punch-through effects. Recent studies of SiGe CMOS on sapphire
technology [29, 30] have shown improvements in p-MOSFET mobility and
transconductance at 300 and 77 K, compared to Si. Both cut-off frequency
and low-field mobility, µeff improve with the integrated Ge dose in the
SiGe channel. Table 7.3 compares the performances of several devices
while figure 7.18 shows a comparison of the measured and simulated linear
transconductance of a SiGe p-HFET (flat Ge 20%) fabricated in sapphire
technology at 300 and 85 K.
SiGeC p-HFETs 257
Table 7.3. Summary of room temperature electrical parameters of SiGe HFETs

and Si MOSFETs on SOS. (After Mathew S J et al 1999 IEEE Electron Device
Lett. 20 173–5.)
Device Flat Graded Flat Si

parameters Ge 20% Ge 20% Ge 15%
VT (V) −0.77 −0.80 −0.82 −0.97
sub-VT slope (mV dec−1 ) 82.8 80.8 80.6 93.4
2 −1 −1
µeff (cm V s ) 201 177 192 130
Leff µm 1.30 1.25 1.25 1.04
Peak fT L2eff (GHz) µm 2
7.8 7.0 7.4 5.0
Hooge constant (×10−6 ) 94 81 129 294
at VGS − VT = −1 V
Figure 7.18. Comparison of measured linear transconductance versus 2D

simulation using TMA–MEDICI of the flat Ge 20% p-HFET at 300 and 85 K.
(After Mathew S J et al 1999 IEEE Electron Device Lett. 20 173–5.)
7.4. SIGEC P-HFETS
Since the increase in the Ge content leads to a larger strain and reduced
thermal stability in the pseudomorphic SiGe films, limitations exist in
the application of the binary SiGe alloys. By incorporating smaller-
sized C atoms substitutionally to form Si1−x−y Gex Cy , the strain can
be compensated, extending the Si-based heterostructures to allow more
Figure 7.19. Room temperature IDS –VGS for epitaxial Si, Si0.8 Ge0.2 SiGe and
Si0.793 Ge0.2 C0.007 SiGeC p-HFETs for linear and saturation values of VDS for
10 × 10 µm devices. Inset shows IDS versus VDS for increasing values of VGS –VT .
The curves have been normalized for oxide thickness variations between the
samples. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)
flexible device design [31, 32]. The ternary alloys are promising for p-
channel HFETs, since the addition of C increases the stability of the
material and reduces the amount of process-induced strain relaxation
[33, 34].
Figure 7.19 shows the normalized room temperature characteristics of
10 µm gate length Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 , and control Si transistors
with the same doping. The respective subthreshold slopes are 101, 90 and
75 mV dec−1 for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 and control Si devices. All
devices exhibit good saturation and turn-off characteristics. However, the
Si0.793 Ge0.2 C0.007 transistor exhibits a higher drive current at the same
effective gate voltage, as shown in the inset.
In figure 7.20, the field-effect mobilities for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007
epitaxial Si and lightly-doped bulk Czochralski–Si (CZ–Si) p-MOS are plot-
ted at room and liquid nitrogen temperatures. The peak mobility at 300 K
is enhanced to 190 cm2 V−1 s−1 for Si0.793 Ge0.2 C0.007 in comparison to
140 cm2 V−1 s−1 for the Si0.8 Ge0.2 devices. The ternary alloy sample
Devices using poly-SiGe 259
Figure 7.20. Linear field-effect mobility (µFE ) for 1.3 × 1015 cm−3 doped
bulk-Si, 2.3 × 1017 cm−3 doped epitaxial Si/Si0.8 Ge0.2 and Si0.793 Ge0.2 C0.007
SiGeC p-HFETs as a function of VGS –VT for 10 × 10 µm devices at room
temperature and 77 K. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)
shows the highest peak mobility, whereas the mobility for the Si0.8 Ge0.2
devices is only slightly higher than that of epitaxial Si and lower than that
of a bulk doped CZ–Si device. It is known that the in-plane hole mobility
in compressively strained Si1−x Gex is enhanced due to the lifting of valence
band degeneracy and modification of the band structure.
Although performance enhancement has been demonstrated in
partially strain-compensated Si1−x−y Gex Cy channel p-HFETs over
Si1−x Gex channels as a result of less process-induced relaxation in the
Si1−x−y Gex Cy layer, complete strain compensation of the SiGe layers,
however, degrades the performance of p-HFET devices. The incorporation
of a controlled amount of C can provide a wider process window for device
fabrication.
7.5. DEVICES USING POLY-SIGE
In bipolar transistors, SiGe is used to form a narrow bandgap base

region, while in a field-effect device it has been used as a channel
material. Polycrystalline silicon (polySi) finds wide applications in all
types of silicon integrated circuit technology. Poly-Si1−x Gex is a promising

alternative to polySi as a gate material due to its process compatibility
and favourable electrical properties, such as lower sheet resistance, higher
dopant activation rate and tunable work function [35, 36]. While
considerable research has been carried out on epitaxial SiGe, relatively
less work has been done on polycrystalline SiGe (poly-SiGe) and even
less on other group IV polycrystalline materials. Potential applications
of polycrystalline SiGe or SiGeC include:
• CMOS—tuning of the work function by 200–300 meV towards midgap

and reduced gate depletion due to enhanced dopant activation at low
temperature;
• TFTs—higher mobility and lower thermal budget processing than
amorphous or polycrystalline silicon;
• BiCMOS—lower thermal budget polysilicon emitters and increased
gain in wide bandgap polycrystalline SiGeC or SiC emitters;
• resistors—tuning of temperature coefficient of resistance in
polycrystalline SiGe or SiGeC resistors.
7.5.1. Poly-SiGe gate MOSFETs
Poly-Si0:75 Ge0:25 -gated p-MOS transistors with a very thin gate oxide
have been fabricated. In addition to reduced gate-depletion effect (GDE)
and reduced boron penetration, an enhancement in performance has been
reported [37]. As a p+ -poly-SiGe film has a tunable work function; the
carrier mobility which is affected by the vertical electric field differs from
that in the device with a conventional polySi gate [38]. Due its superior hole
mobility and smaller work function, which leads to a lower effective field
in the inversion layer, an improved current drive is obtained for poly-SiGe.
The output characteristics for both p+ -polySi and poly-SiGe gate devices
with various gate biases are shown in figure 7.21. For each gate voltage,
the drain current of the poly-SiGe gated device is higher than that of the
polySi gated device. Given its compatibility with current VLSI fabrication
processes, incorporating SiGe into existing CMOS processing should be
relatively easy and should lead to higher performance of MOSFET devices
[37]. The gate tunnelling currents (hole and electron) in p+ -polySi and
poly-SiGe gated p-MOS transistors with ultrathin gate oxides of 25 and
29 Å have been measured by employing the charge-separation measurement
techniques [39]. The authors have concluded that the hole direct tunnelling
is the dominant gate leakage mechanism under normal operating conditions
for p+ -polySi gated p-MOS devices with very thin gate oxide.
Devices using poly-SiGe 261
Figure 7.21. IDS –VDS characteristics for both p+ -polySi and poly-SiGe gated
devices with various gate biases. For the same VDS and VGS , the drain current of
the poly-SiGe gated device is always higher than that of the polySi gated device.
(After Lee W-C et al 1999 IEEE Electron Device Lett. 20 232–4.)
7.5.2. Poly-SiGe thin-film transistors
Thin-film transistors (TFTs) find wide applications in active matrix liquid

crystal displays (AMLCD) and static memory (SRAM) and there has been
great interest in the possibility of developing a low-cost, glass-compatible
polycrystalline TFT process, which will enable a high-performance flat
panel displays with integrated drivers. SiGe is of great promise for
achieving this goal, due to its lower processing temperature and thermal
budget requirements [40, 41].
TFT processes have several characteristics which make them different
from the standard Si process. For a glass-compatible technology, all
processing is done at or below 600 ◦ C, and deposited gate dielectrics is
used. Active layers are also deposited, usually by LPCVD or PECVD.
The deposition conditions of the active layer and the related process
parameters greatly affect the device performance, as does the quality of the
gate dielectrics, which is generally inferior in quality to thermally oxidized
dielectrics.
To enable the rapid optimization of SiGe TFTs for AMLCD
applications, a response surface characterization of the SiGe deposition
system has been performed [42]. Controlled nucleation and grain growth
have enabled the fabrication of large-grain high-performance TFTs. Ge has
been deposited selectively through an oxide mask onto the source/drain
regions. The film is then crystallized at low temperature. The Ge and Si

react to form SiGe at the interface, which crystallizes first, and then grows
out laterally, resulting in spatially specified large-grain polysilicon. This
process is called germanium-seeded lateral crystallization. The fabricated
poly-SiGe TFTs have shown much higher mobility than comparable polySi
TFTs, as indicated in figure 7.21. A comparison of transfer characteristics
of n-MOS and p-MOS TFTS at low and high drain voltages is shown in
figure 7.22.
Figure 7.22. Comparison of poly-SiGe TFT transfer characteristics. (After

Subramanian V and Saraswat K C 1998 IEEE Trans. Electron Devices 45
1690–5.)
Vertical FETs 263
7.6. VERTICAL FETS
With increasing chip size, the delay introduced by metal lines

interconnecting the various parts of a chip is rapidly becoming a limiting
factor for speed and performance. A solution to this problem is a
reduction in chip size, which can be accomplished through the use of
vertical integration of active devices. MOSFET channel lengths are being
continuously scaled down to improve performance and packing density.
Extrapolating the critical device dimensions for silicon ICs to the future,
it is anticipated that MOS transistors with gate lengths of about 70 nm
will be required to realize the 64 GB DRAM around the year 2010 [43].
However, in the vertical transistor technology, channel length scaling is not
limited by the minimum lithographic resolution. It has been shown that
the package density of the vertical transistor is doubled [44].
7.6.1. Vertical SiGe HFETs

The advances in the growth of device quality SiGe epitaxial layers on silicon,
combined with the higher values of hole mobility, have led to an increased
interest in heterojunction vertical FETs [45, 46]. In the design of the
vertical heterojunction p-MOSFET, the SiGe layer and, more specifically,
Figure 7.23. Schematic diagram of vertical heterostructure field-effect

transistor. (After Collaert N and De Meyer K 1999 IEEE Trans. Electron Devices
46 933–9.)
the gate influence on the effective barrier height seen by the carriers play
an important role in the device operation. It consists of a source layer,
a graded SiGe source layer, a lightly-doped SiGe source layer, an n-type
doped channel region and finally a p-type doped drain layer (as shown in
figure 7.23). The gate dielectrics consists of an oxide grown on the vertical
sidewalls and the gate electrode is an in situ doped p-type polysilicon layer.
The basic principle of operation of this novel device is: in the on-
state, the barrier is decreased by using the gate action on the lightly-doped
source layer. In the case of a p-channel device, a strained-SiGe layer on
top of an Si substrate is used to create a barrier for the holes [21]. For the
n-channel devices, the barrier for the electrons will be formed by a strained-
Si source layer on top of a SiGe buffer layer, leading to a band alignment
of type II [21]. In that case, SiGe will also be used for the channel and
drain layers. Using the Si/SiGe layer stack for both p- and n-MOSFETs,
it is possible to include source engineering in the vertical transistor design.
This is an important improvement to vertical Si-only devices, which lack the
possibility of channel engineering that has pushed their planar counterparts
toward the deep submicron regime. Vertical MOSFETs suffer from drain-
induced barrier lowering (DIBL), causing reduction threshold voltage roll-
off and an increase in subthreshold slope. By using ultrathin pillars (width
100 nm), the channel region can be fully depleted by surrounding gates,
resulting in an improved subthreshold slope and a suppression of short-
channel effects [47, 48]. To reduce the DIBL effect, a material-dependent
barrier between source and channel may also be introduced [45, 49].
Enhanced in-plane hole mobility in strained-SiGe alloys, compared to
bulk-Si has been employed for the fabrication of planar SiGe-channel p-
HFETs [5, 14, 50]. The enhancement of hole mobility in a direction normal
to the growth plane of the strained-Si1−x Gex and graded SiGe channel has
also been found to be effective in the enhancement of the drive current
in implanted-channel MOSFETs. As the vertical structures combine the
merits of a very short channel and enhanced hole mobility in strained-SiGe
layers, the results are very promising in terms of the possibilities offered
by the SiGe technology. Indeed, a deep submicron vertical SiGe-channel
p-HFET using strained-Si1−x Gex grown using solid phase epitaxy and the
standard CMOS process has been reported [46].
The scaling of vertical p-MOSFETs with the source and drain doped
with boron during low-temperature epitaxy is limited by the diffusion
of boron during subsequent side wall gate oxidation. By introducing
SiGeC diffusion barrier layers, boron diffusion from source and drain into
the channel region has been suppressed during the gate oxidation. The
characteristics of scaled vertical p-MOSFETs down to 25 nm in channel
length [51] are shown in figure 7.24. These devices suffer from the onset of
punch-through, but the gate can still control the drain current in the linear
region.
Noise in p-HFETs 265
Figure 7.24. (a) Output I–V and (b) subthreshold drain current versus gate
voltage for devices with L = 25 nm with a gate oxide thickness of 10 nm. (After
Yang M et al 1999 IEEE Electron Device Lett. 20 301–3.)
An analytical model for the threshold voltage of the p-SiGe

channel vertical MOSFET has demonstrated its unique characteristics
in suppressing DIBL in sub-100 nm channel length devices [45]. The
dependence of the threshold voltage on Ge concentration, channel length,
channel doping and SiGe source doping was evaluated. It was shown that
with the introduction of a material-dependent barrier between source and
channel, roll-off in threshold voltage can be substantially reduced.
7.7. NOISE IN P-HFETS
Low-frequency noise is important in RF and microwave circuit applications,

because it is upconverted to phase noise and thus sets a fundamental limit
on the spectral purity of high-speed communication systems. Although
much work has been done on noise in MOSFETs [52], little attention has
Figure 7.25. Spectral density of the input-referred gate voltage noise for the
flat Ge 20% and the Si p-MOSFET in saturation. (After Mathew S J et al 1999
IEEE Electron Device Lett. 20 173–5.)
been given to the noise properties of SiGe p-HFETs [29, 53]. The noise
in MOSFETs is generally related to the fluctuations in the inversion layer
carrier density due to traps located at the Si–SiO2 interface. SiGe p-HFETs
are bandgap-engineered such that the holes confined to the SiGe channel
are physically separated from the Si–oxide interface by an Si-cap layer.
Intuitively, one would expect lower noise in SiGe p-HFETs because of such
a physical separation. However, an examination of the trapping-based noise
theory [54] shows that this separation changes only the frequency range over
which the noise shows a dependence, but not the magnitude of the noise.
Figure 7.25 shows the input referred gate voltage noise for Si/SiGe
p-HFETs on SOS and bulk-Si. It is observed that all SiGe p-HFETs
consistently show a lower noise than Si p-MOSFETs at all gate biases.
The SiGe p-HFETs show a 70% lower noise than the Si p-MOSFETs, due
to the enlarged separation between the hole quasi-Fermi level and valence
band edge, which results in the sampling of a lower density of traps. Thus,
the SiGe p-HFETs should have an intrinsic advantage in microwave circuit
applications.
Collaert et al [55] have measured the low-frequency noise
characteristics for several vertical SiGe-channel HFETs. Figures 7.26(a)–
7.26(d) show the noise spectra measured between 3 Hz and 100 KHz for
devices with source top and drain top configurations at constant drain
current. As can be seen from the figures, the source top configuration
exhibits a dominant generation–recombination (g–r) noise behaviour while
the drain top measurements show 1/f γ -type noise behaviour with γ
between 0.9 and 1.5.
Summary 267
Figure 7.26. Low-frequency noise characteristics for (a) an Si0.90 Ge0.10 device;
(b) an Si0.80 Ge0.20 device, Nsub = 5 × 1017 cm−3 ; (c) an Si0.90 Ge0.10 device; and
(d) a bulk-Si device, Nsub = 1 × 1018 cm−3 . (After Collaert N et al 1999 Proc.
ESSDERC pp 308–11.)
7.8. SUMMARY
In this chapter, the electrical operation and modelling of the SiGe p-

HFET are presented to provide the device designer with guidelines as to
epitaxial layer structure and placement. A range of parameter space has
been explored using device simulation to determine the charge distribution
within the device under various gate bias conditions.
The key design issues for SiGe HFETs have been addressed in detail.
The selection of the gate material plays a dominant role, especially for
designs with threshold voltages in the range of −0.6 V where the use of
n+ -polySi is preferable over p+ -polySi. With a graded Ge profile, a higher
valence band discontinuity can be obtained at the top of the SiGe channel
leading to an increase in transconductance for a given integrated Ge dose.
It has been shown that for maximum utilization of the strained-Si1−x Gex
quantum well, the p-HFET should have the following characteristics:
(i) a thin Si-cap layer,;

(ii) a high Ge mole fraction for a large 2DHG population in the quantum
well;
(iii) an n+ -polySi gate to promote buried channel operation for low-
voltage applications; and
(iv) a p+ -δ-doping below the SiGe channel to enhance subthreshold
properties of the device.
A number of possibilities have been shown to enhance performance

of SiGe HFETs. From a design point of view, the SiGe p-HFET on
an insulating substrate offers better hole confinement in the quantum
well. The incorporation of a controlled amount of carbon in a partially
strain-compensated SiGeC channel p-HFET can provide a wider process
window. A vertical SiGe HFET offers higher packing density, lower DIBL
and substrate bias effect, more flexible channel engineering and a simpler
fabrication process.
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Chapter 8
METALLIZATION AND
HETEROSTRUCTURE SCHOTTKY
DIODES
Semiconductor–semiconductor and metal–semiconductor interfaces play

a crucial role in modern electronic and optoelectronic devices.
SiGe heterostructure materials and devices are expected to play an
important role due to their compatibility with Si-processing technology.
Microelectronic circuit fabrication requires metallization and the study of
the metal/SiGe interface is therefore very important. For applications
of poly-SiGe as gate material, the interaction of SiGe alloys with
noble/refractory metals should also be investigated, as both refractory and
noble metal-silicides are widely used for ohmic contacts, Schottky barrier
diodes, diffusion barriers, low resistivity gates and interconnects.
As new devices and structures are being contemplated using group IV
alloy films, a good control of the metal/semiconductor interface, low or
high barriers, are required to improve the device performance. There are
two types of metal–semiconductor contacts, one is ohmic and the other is
Schottky. Schottky contacts are needed for rectification of electrical signals,
mixing of microwave signals and optical detection. Silicide/Si1−x Gex
Schottky diodes have also been proposed for detection of far-infrared
radiation, which will be discussed in chapter 9. In table 8.1, important
material properties of commonly used metals for microelectronic device
fabrication are presented.
During the last few years, several research groups have studied the
electrical properties and chemical phase formation of metal/group IV alloy
layers. Two approaches to the formation of ohmic contacts with SiGe
and other alloy layers have been proposed [1]. The first approach involves
adding Ge and Si to a thin Al film to avoid known substrate dissolution
and spiking problems. An Al film (3000 Å) is deposited over the strained
layer, followed by the deposition of thin layers of Si (20 Å) and Ge (60 Å).
272
Metallization and heterostructure Schottky diodes 273
Table 8.1. Material properties of metals commonly used in microelectronic

applications.
Property Al Au Pt Ni Cr
Molecular weight (amu) 26.98 196.96 195.09 58.69 52.02
Density (g cm−3 ) 2.699 19.288 21.452 8.903 7.19
◦
Melting point ( C) 659.4 1062.2 1768 1454 1875
does not does not does not
Oxidation potential (V) 1.66 0.25
oxidize oxidize oxidize
Work function
4.25 5.1 5.7 5.1 4.5
at vacuum (eV)
Schottky barrier
0.69 0.79 0.9 0.61 0.61
to n-Si (eV)
Schottky barrier
0.38 0.25 0.51 0.50
to p-Si (eV)
Schottky barrier
0.48 0.59 0.49
to n-Ge (eV)
Schottky barrier
0.3
to p-Ge (eV)
A 350 ◦ C anneal for 1 h was used to alloy the capping Si and Ge layers
into the Al. Contact resistivity measurements between room temperature
and 400 ◦ C demonstrated the stability of the contacts. However, the room
temperature contact resistivity of 0.01 Ω cm−2 was considered too high for
device applications.
The second approach to contact formation involved deposition of a
layer of Pd:Si (3:1, 600 Å) on the SiGe, followed by a layer of pure Ge
(1000 Å). The contacts were annealed for 1 h at 350 ◦ C. During annealing
the Pd3 Si phase was formed. Concurrently, the surface Ge layer diffused
through the silicide and grew epitaxially on the underlying SiGe layer.
Contact resistances for these films were typically 5 × 10−4 Ω cm−2 at room
temperature.
Liou et al [2] reported the interfacial reactions of Pt and Pd with
epitaxial Si1−x Gex alloys and the effects of these reactions on Schottky
barrier height. They reported that the barrier heights of Pd and Pt
on n-Si0.8 Ge0.2 were the same, about 0.68 eV, and were not modified
significantly when annealed at a temperature below 550 ◦ C. This value is
close to that previously reported by Buxbaum et al [3] for Pd on n-Si1−x Gex
films.
Kanaya et al [4] reported the Schottky barrier height of Pd(Pt)/p-SiGe
contacts for infrared detection. It was shown that the barrier height
274 Metallization and heterostructure Schottky diodes
decreased with increasing Ge concentration, and that the barrier height

of a relaxed film was higher than that of a strained-Si1−x Gex film. Hong
and Mayer [5] studied the Pt/Si1−x Gex system and found a similar
behaviour except for the formation of germanide. Thompson et al [6]
studied the Ni/Si1−x Gex interfacial reaction and found that Ni was the
dominant diffusion species below 400 ◦ C and that layers of Ni2 (Si1−x Gex ),
Ni(Si1−x Gex ) and NiSi formed in sequence. Above 400 ◦ C, homogenization
between NiSi and Ni(Si1−x Gex ) occurs due to interdiffusion of Si and Ge.
Aubry et al [7] studied the Si1−x Gex /W metal–semiconductor
Schottky junction rather than a silicide junction. The authors reported
the effects of composition and thickness on the Schottky barrier height of
W/p-Si1−x Gex relaxed films and showed that the barrier height decreased
with the increasing Ge fraction and followed the rate of strain relaxation.
Thomas et al [8] investigated the Ti/Si1−x Gex contacts with contact
resistance measurements and reported that Si and Ge were the dominant
moving species during the reaction. The resistance of contacts was stable
and low due to the formation of TiSi2 , Ti(Si1−x Gex )2 and TiGe2 after
annealing at 650 ◦ C for 1 h.
The above studies revealed that during the metal–Si1−x Gex reaction,
Pd and Pt preferentially react with Si, resulting in Ge segregation [2, 9].
These create defects that pin the Fermi level near the midgap leading to
a high Schottky barrier height [2]. To avoid Ge segregation, a silicon
sacrificial layer was used on top of the SiGe film [10]. The important
applications of silicide junctions are in IR detectors and will be discussed
in chapter 9.
In this chapter, the formation and characterization of silicides (using
Pt, Pd and Ti on SiGe, SiGeC, Si and strained-Si) using various analytical
tools, such as x-ray diffraction (XRD), Rutherford backscattering (RBS)
and Auger electron spectroscopy, will be discussed. We describe Schottky
barrier diodes (SBDs) using Ti, Pt and Pd on p-type SiGe, SiGeC, strained-
Si films and Si. Experimental results on barrier heights, the ideality factor
and energy distribution of the interface state density for various diodes
and simulation results using SEMICAD [11] on forward current–voltage
characteristics of Schottky diodes are presented.
8.1. DEPOSITION OF METAL FILMS
One of the various techniques used for metal thin-film deposition is

ultrahigh vacuum (UHV) electron beam deposition. The schematic
diagram of an electron beam evaporation system used for deposition of
metals is shown in figure 8.1. The deposition system consists of a single
electron gun (typically 2 kW) and several crucibles, capable of evaporating
different materials sequentially. A base pressure of about 1 × 10−11 Torr is
achieved in the chamber with the help of three kinds of vacuum pumps, e.g.,
Deposition of metal films 275
Figure 8.1. Schematic diagram of an e-beam evaporation system.
vac-sorb, ion and titanium sublimation pumps. As there are no oil-based

vacuum pumps (rotary and diffusion) in the system, the UHV e-beam is
free from hydrocarbon contaminations.
The vacuum chamber consists of a rotating substrate holder, a crystal
monitor for monitoring the deposition rate and thickness of the film, a
quartz-lamp radiation heater with a heating control unit to maintain the
substrate temperature up to 300 ◦ C and an ion gauge to monitor the
pressure. The whole system is separated into upper and lower chambers
by an isolation valve. The lower chamber houses a series of ion pumps and
a liquid nitrogen cryo panel and is maintained at a vacuum of 10−6 Torr
or greater by continuous operation of the ion pumps.
In a typical deposition process, the upper chamber was vented by
passing liquid nitrogen, followed by loading of the pre-cleaned substrates
in the chamber. A sufficient amount of high-purity source materials in
the form of small pellets was put into the crucibles and the electron
gun filament was aligned to it. Initial evacuation of the chamber was
carried out by vac-sorb pumps from atmospheric pressure to a minimum
pressure of 10 mTorr. Finally, pumping to a pressure of 10−9 Torr was

achieved by the combination of sputter ion and titanium sublimation
pumps. After attaining the desired base vacuum, deposition was initiated
by evaporating metal by applying power to the electron gun (e-gun) from its
control unit. The evaporation rate was controlled by changing the filament
current in the e-gun. Thin films of Ti, Pt and Pd of required thicknesses
were deposited on strained-Si1−x Gex , partially strained compensated
Si1−x−y Gex Cy , strained-Si and Si at the desired pressure level.
8.2. FABRICATION OF SCHOTTKY DIODES
In the fabrication of Schottky diodes, surface preparation for metal

deposition is very important. In most cases, the departure of the ideality
factor of the diodes from unity is due to the presence of an interfacial layer
between the metal and the semiconductor [12, 13]. Another reason may
be the existence of a laterally varying potential barrier height, caused by
a nonuniform interface of the heterostructures [14]. The nonidealities are
mostly due to the states associated with the defects near the surface of the
semiconductor. These defects act as recombination centres giving rise to
excess current which causes deviation from the ideal thermionic emission
behaviour at low voltage and low temperature. The growth temperatures
of strained-Si1−x Gex and partially strain-compensated Si1−x−y Gex Cy
samples are typically around 600 ◦ C. In order to avoid strain relaxation, the
silicidation temperature should not exceed the film growth temperature.
8.3. SILICIDATION OF GROUP IV ALLOY FILMS
More than half of the elements in the periodic table react with silicon to
form one or more intermetallic compounds (silicides). In Si technology,
uniform and stable contacts are achieved by reacting metal films with Si
until the most Si-rich silicides are formed. These silicides not only offer a
choice in electrical barrier heights but also serve as protective layers against
oxidation. Al is commonly used as the ohmic contact metal in Si technology.
The solid solubility of Si at 525 ◦ C is 1.5% and Si molecules from the
substrate dissolve into Al to satisfy its solubility. Though Al and Al–Si
have been successfully used in Si devices, they do not make good contacts to
group IV alloy films. The choice of metals for ohmic contacts should satisfy
several requirements. Firstly, the composition of the unreacted alloys must
remain unchanged after contact reactions. Secondly, a single compound,
not a mixture of compounds (e.g., silicides and germanides), should be in
contact with the alloy films. Thirdly, the consumption of alloy films during
the reaction must be small since the thicknesses of the strained layers are
limited by the critical thickness.
Silicidation of group IV alloy films 277
The metallization of SiGe and other group IV alloys is complicated

compared to that of bulk-Si. In a metal–SiGe reaction, metals react
preferentially with one component of the alloy, leading to a compositional
change in the unreacted alloy. The compositional change results from the
formation of a ternary compound within a narrow range of homogeneity.
Ternary metal–SiGe phase diagrams are also required to predict the final
phases of metal/SiGeC ternary reactions.
In a ternary reaction, the identity of moving species is very important
in determining the elemental distribution. For example, in a refractory–
noble metal alloy, a reaction (with Si) produces a noble metal silicide inner
layer and a mixture of noble and refractory silicide outer layer. However, no
layered phase separation has been observed in refractory–refractory metal
alloy/Si reactions. This has been attributed to the different moving species
involved in the reactions. Noble metals are known to be highly mobile
in silicides at low temperature, while Si is the dominant moving species
during reactions with refractory metals. Therefore, in a refractory–noble
metal/Si reaction, the noble metal moves first to react with Si leaving
behind a metallic alloy enriched with the refractory component. At high
temperature, Si atoms from the substrate move to react with the metallic
alloy to form a mixture of silicides. On the other hand, layered phase
separation is absent in the refractory–refractory/Si reactions since Si is the
only moving species in the entire temperature range. In the light of the
above arguments, the composition of SiGe alloys would remain unchanged
if a mobile species was chosen as the contact material or the transport of
Ge and Si is similar during the reaction with the refractory metal.
It has been reported from the kinetic studies of Ti/SiGe systems that
Si and Ge are the dominant moving species during thermal reactions.
Resistance of the resulting silicide formed at about 650 ◦ C is stable and low
due to the formation of C54 of TiSi2 , along with the Ti(SiGe)2 and TiGe2
phases [8]. Strain relaxation has also been observed during the thermal
reaction between Ti and Si1−x−y Gex Cy [15]. Carbon is found to inhibit
the strain relaxation process as well as to delay the formation of the C54
phase of TiSi2 . Upon complete silicidation, a decrease of Ge concentration
in silicide–germanide/epilayer and an accumulation of C atoms at the
interface have been found. To avoid such complexities associated with
the thermal reactions between metal and group IV alloy films, the use of
a thin Si sacrificial layer on top of the strained SiGe or SiGeC layer is
common [10].
For Schottky contacts, the general requirement is to adjust the junction
parameters, such as barrier height and ideality factor, and to control their
reproducibility and stability. Thermal annealing influences the interface
and pinning position of the Fermi level which in turn affects the barrier
height of the Schottky junctions [16]. For the Ti–Si system, the Fermi
level pins at the midgap region. But incorporation of Ge in Si changes
the pinning position of the Fermi level [7]. In Si, reproducible rectifying
and low resistance ohmic contacts can be achieved by choosing appropriate
transition metals with various Schottky barrier heights and by doping the
semiconductor with the desired level. Transition metals react with Si
at low temperature so that no liquid phase forms. As a result, uniform
silicide layers with reproducible compositions at the silicide/Si interface
are formed. The electrical properties of Schottky junctions require the
understanding of chemical reactions at the metal–semiconductor interface.
In the following, we discuss the formation and characterization of silicides
of various group IV alloy films with Ti, Pt and Pd.
8.4. SILICIDATION WITH TITANIUM
Refractory metal silicides, such as TiSi2 , WSi2 , TaSi2 and MoSi2 ,

have attracted much attention in microelectronic devices due to their
low resistivity and high-temperature stability, which are required for
VLSI/ULSI interconnects. Among various refractory metal silicides, TiSi2
possesses the lowest resistivity (∼12.4 µΩ cm−1 ) [17], high-temperature
stability and excellent compatibility with Si-processing technology, and is
widely used for submicron CMOS contacts.
Titanium disilicide (TiSi2 ) is a polymorphic material which is formed
by thin-film reactions between Ti and 100 Si, polySi or amorphous silicon.
TiSi2 has two different structures: the base-centred orthorhombic C49
structure which forms in the temperature range 450–650 ◦ C and the face-
centred orthorhombic C54 structure which forms above 650 ◦ C. The C49
TiSi2 is a metastable phase [18] while C54 is the stable phase with lower
resistivity than the C49 phase. But the transformation of C49 TiSi2 to C54
TiSi2 is dependent on the doping level and the thicknesses of the film [19].
Both the crystal structures exhibit similar arrangements of atoms in the
atomic planes with a hexagonal array of Si atoms around the centre, but
the unit cell of each phase shows a different stacking arrangement. The
C54 phase exhibits lower Schottky barrier heights on both p- and n-type
silicon as compared to the C49 phase [20].
The reaction mechanism for the formation of C54 TiSi2 is as follows.
First, the Ti layer reacts with crystalline silicon producing an amorphous
TiSix phase at a temperature ranging from 400–500 ◦ C. With further
heating, the amorphous phase, together with the silicon and Ti, forms
C49 TiSi2 between 500–700 ◦ C which eventually transforms into C54 at a
temperature above 700 ◦ C [21]. The determination of the chemical phase
formation during annealing requires in situ characterization tools, while
the final phase formation is generally studied ex situ using XPS.
Silicidation with titanium 279
8.4.1. Rutherford backscattering characterization

Rutherford backscattering (RBS) analysis is carried out to estimate the
composition and thickness of the deposited films. The advantages of RBS
are the following:
(i) speed;
(ii) ability to perceive depth distribution of atomic species below the
surface;
(iii) the quantitative nature of the results and the technique is
nondestructive.
The 1–2 MeV He+2 beam is normally used for RBS and channelling
measurements.
The random incident backscattering spectra of Ti on Si samples
annealed at 600 ◦ C for 20 min is shown in figure 8.2 with a 2.551 MeV
Figure 8.2. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si sample
annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation.
Figure 8.3. The 2.551 MeV 4 He++ backscattering spectra of the

TiSi/Si0.81 Ge0.19 sample annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental
and (——) simulation.
4
He+2 ion beam. The scattered He+2 from the TiSi2 layer appears at
higher energies (channel nos 576–541) while those from the Si substrate
appear at lower energies (channel nos 445–100). Computer simulation of
the backscattered spectra (using the GISA-3.95 program) is usually done
to obtain the thickness and composition of different layers.
Figure 8.3 shows the RBS spectrum for a Ti/SiGe sample annealed
at 600 ◦ C. It is evident from figure 8.3 that the scattered He+2 from Ge
appears at a higher energy (channel nos 643–591) and the scattered atoms
from Ti and Si appear at relatively lower energies (channel nos 576–543
and 445–200, respectively). From the simulation, it is found that the total
Ti signal is contributed partly from the TiSi layer and a part from the
unreacted Ti. Similarly, the Si fraction is contributed partly from the
TiSi layer and partly from the SiGe epitaxial layer as well as from the Si
substrate.

TiSi/Si0.79 Ge0.20 C0.01 sample (with Si-cap) annealed at 600 ◦ C for 20 min:
(· · · · · ·) experimental and (——) simulation.
RBS spectra of Ti–Si–Si0.79 Ge0.20 C0.01 and Ti–Si0.79 Ge0.20 C0.01

samples (annealed at 600 ◦ C for 30 min) are shown in figures 8.4 and
8.5, respectively. From the simulation, it is found that the Ti peak is
contributed by the unreacted Ti and the TiSi layer. Similarly, the Si edge
comes from both the TiSi layer and Si1−x−y Gex Cy (x = 0.2, y = 0.01)
epitaxial layer and also from the Si substrate. For all silicide samples,
the Ge peak occurs at a higher energy compared to those of Ti and Si.
Generally, the Ge peak occurs in the channel region of 645–600 and the Ti
peak occurs in the channel range of 576–550 while Si shows a peak around
the channel no 445 and below.

TiSi/Si0.79 Ge0.20 C0.01 sample (without Si-cap) annealed at 600 ◦ C for 20 min:
(· · · · · ·) experimental and (——) simulation.
8.4.2. Auger electron spectroscopy characterization

In Auger electron spectroscopy (AES), a focused beam of electrons in the
energy range 2–20 keV irradiates the sample. Atoms up to a depth of
1 µm are ionized in an inner core level, e.g., the K level, and subsequently
de-excited by an electron falling from a higher level L1 , with the balance
energy removing a third electron from level L3 . The electron emitted with
an energy EA is given by
EA = EK (Z) − EL1 (Z) − EL2 (Z + ∆) − ξ (8.1)
where Z is the atomic number of the atom and ξ is the work function
of the surface. The third term on the right-hand side of equation (8.1)
has an extra component ∆ which is included to take account of the fact
that the atom is in a charged state when the final electron is ejected.
Experimentally, ∆ is found to have a value between 12 and 32 .
In sputter depth profiling analysis of thin films, an ion beam is used
to etch the surface at rates up to 2 µm h−1 . For AES depth profiles, the
electron beam is placed in the middle of the ion beam crater and, if the
system alignment is suitable, the crater size may be limited to 100 µm or
less. If a monoenergetic argon ion of current density Ji is used to sputter
a target with a sputtering yield of S atoms per ion, the rate of removal is
given by
dz Ji SM
= (8.2)
dt qρNA na
where M is molecular weight of the material with na atoms per molecule,
q is electronic charge, ρ is density and NA is Avogadro’s number. In the
above equation, dz/dt is the sputter rate. Thus, for a given material, the
removal rate may be determined if Ji and S are known.
Figure 8.6 shows typical AES depth profiles for Ti, Si and Ge of the
Ti/Si/Si1−x Gex sample having a Ti thickness of 700 Å annealed at 600 ◦ C
for 20 min. The spot size of the beam was 0.5 µm and the etch rate for
profiling was 5 Å min−1 . As seen from the depth profile, about 600 Å of Ti
remains unreacted and only 100 Å of Ti takes part in silicide formation. It is
clear from the profile that TiSi formation is observed up to a depth of about
100 Å below the interface. An accumulation of Ge atoms is also observed
below the interfacial region. It is desirable to consume the sacrificial Si-cap
layer completely by Ti to obtain a pure TiSi/Si1−x Gex interface.
Figure 8.6. AES depth profiles of Ti, Si and Ge for the TiSi/Si0.81 Ge0.19 sample
annealed at 600 ◦ C for 20 min.
8.4.3. Sheet resistivity
The effects of the alloy composition on the annealing temperature and

the electrical resistivities of C54 titanium germano–silicide formed during
the Ti/Si1−x Gex (x = 0.0, 0.3, 0.4, 0.7, 1) solid-state reaction have been
investigated [22]. The resistivities of C54 Ti(Si1−x Gex )2 were measured to
be in the range of 15–20 µΩ cm−1 . The electrical resistivities of alloys
are influenced by the difference of atomic size, atomic disorder, strain
and band structure effects. From electrical measurement, the instability
of titanium germano–silicide is manifested by the increase in the resistance
with the annealing temperature. The increase has been attributed to both
the segregation of Si1−x Gex and the agglomeration and spheroidization
of the germanide and germano–silicide and are correlated with the phase
transformation. The sheet resistances fell drastically (see figure 8.7) at 600,
650, 650 and 700 ◦ C in the annealed Ti/Ge, Ti/Si0.3 Ge0.7 , Ti/Si0.6 Ge0.4
and Ti/Si0.7 Ge0.3 samples, respectively. The lowest electrical resistivities
which appeared for smooth thin films of C54 Ti(Si1−x Gex )2 were found
to be 20, 20, 17 and 15 µΩ cm−1 for the 800 ◦ C annealed Ti/Si0.7 Ge0.3 ,
Ti/Si0.6 Ge0.4 , Ti/Si0.3 Ge0.7 and Ti/Ge samples, respectively. The values
of x were estimated to be 0.19, 0.28, 0.55 and 0.98, respectively, by EDS
analysis, as shown in figure 8.8.
Figure 8.7. Sheet resistance versus annealing temperature curves for the
Ti/Si1−x Gex and Ti/Ge samples. (After Lai J B and Chen L J 1999 J. Appl.
Phys. 86 1340–5.)
Silicidation using Pt and Pd 285
Figure 8.8. The lowest electrical resistivity versus concentration of Ge data in

Ti(Si1−x Gex )2 . (After Lai J B and Chen L J 1999 J. Appl. Phys. 86 1340–5.)
8.5. SILICIDATION USING PT AND PD
During the metal–Si1−x Gex reaction, Pd and Pt react preferentially with Si

resulting in Ge segregation. This creates defects which pin the Fermi level
near the midgap leading to a high Schottky barrier height [2]. Generally,
silicidation studies of Pt and Pd with SiGe alloys are carried out in the
temperature range of 300–500 ◦ C. It has been reported that Pt or Pd reacts
with SiGe alloys to form ternary compounds such as Pt2 (Si0.8 Ge0.2 )1 or
Pt1 (Si0.8 Ge0.2 )1 at 300 and 400 ◦ C for different durations of annealing [23].
Thermodynamically, Si is more reactive than Ge with Pt. At 350 ◦ C, the
reaction between Pt and Si1−x Gex consists of interdiffusion of Pt, Si and Ge
with Pt as the dominant diffusion species, and while Pt diffuses in some Ge
diffuse out [2, 24]. As Pt atoms reach the silicide/Si1−x Gex interface, they
react preferentially with Si to form silicide, and the Ge atoms which are
left behind diffuse out and pile up at the surface. Experimental evidence
suggests that Pt selectively bonds with Si, the bonding between Pt–Si
is stronger than that of Pt–Ge, and the formation of PtSi is favoured.
Microscopically it creates a nonuniform interface at the PtSi/Si interfacial
layer [23]. Annealing at a lower temperature shows some fraction of Ge
segregation at the silicide–SiGe interface. However, during annealing at
a higher temperature, Ge is repelled from the surface layer and forms a
Ge-rich layer underneath the interface.
Transmission electron microscope (TEM) analyses of low-temperature
annealed Pd-strained Si1−x Gex alloys show the formation of hexagonal
Pd2 Si or Pd2 Ge with a measured plane symmetry of 5.5 Å. There is also
a report of strain relaxation in the underlying Si1−x Gex layer due to high-
temperature annealing of Pd at about 550 ◦ C [25,26]. In these compounds,
a decrease in the vertical lattice parameter has been observed. Annealing
of Pd–Si1−x Gex at about 550 ◦ C results in the formation of a double layer
structure: the top layer contains a relatively small amount of Ge and the
adjacent Si1−x Gex layer is enriched with Ge. Hong et al [5] have studied
Pt/SiGe systems and have observed the formation of PtGe2 at annealing
temperatures beyond 450 ◦ C.
XRD spectra for the SiGe sample annealed at 400 ◦ C for 30 min
containing 19% Ge and a 50 Å Si sacrificial layer are shown in figure 8.9.
The resulting silicide peaks are oriented along the (200), (021), (1̄15) and
(222) directions. Figure 8.10 shows the XRD pattern of the SiGe sample
with 29% Ge and a 50 Å thick cap layer. As seen in figure 8.10, the PtSi
peak is oriented in the (200), (2̄22) and (1̄15) directions along with the
Figure 8.9. XRD spectrum for PtSi/Si0.81 Ge0.19 film annealed at 400 ◦ C for
20 min.
Heterostructure Schottky diodes 287
Figure 8.10. XRD spectrum for PtSi/Si0.71 Ge0.29 film annealed at 400 ◦ C for
20 min.
peak arising from the Si(400) plane. It is observed from x-ray analysis that
there is no evidence of germanide formation.
8.6. HETEROSTRUCTURE SCHOTTKY DIODES
Schottky contacts play an important role in determining the performance

of semiconductor devices required for various electronic and optoelectronic
applications. Barrier heights of Schottky junctions depend strongly on
the chemical phases formed by thermal reactions between the metal and
semiconductor. Details of the chemical phase formation of Ti, Pt and Pd
with group IV alloys have been described earlier. The barrier heights of
metal/(SiGe, SiGeC or strained-Si) Schottky junctions are predicted to be
lower than the corresponding metal/Si junctions.
According to the Schottky–Mott model [27], the barrier height

of a p-type Schottky junction depends on the metal work function,
semiconductor bandgap and electron affinity of the semiconductor. In
the drift–diffusion emission model, hole current density across the metal–
semiconductor interface is usually given by [27, 28]
Jp = qvrp (po − ps ) (8.3)
where vrp is the effective hole surface recombination velocity, ps is the

density of holes near the interface in the semiconductor and po is hole
density that would be there if the potential distribution could remain the
same while the hole quasi-Fermi level came into equilibrium with the metal
Fermi level. Moreover, due to image force lowering and thermionic field
emission, which usually occur in a practical Schottky diode, the barrier
height can be modelled using the term [14]
! 2/3
qEmax 3 h −1/3
∆φb = + Emax (2qm∗ ) (8.4)
4πs 4 2π
where Emax is the electric field at the metal–semiconductor interface, s is

the dielectric constant of the semiconductor and m∗ is the effective hole
mass. In the above expression, the first term corresponds to the image
force lowering while the second term is responsible for the thermionic field
emission. Considering these effects, the current in a Schottky barrier diode
can be expressed as

q∆φb
Jp = qvrp (po − ps ) exp (8.5)
kT
and
−qφb
po = Nv exp (8.6)
kT
where k is the Boltzmann constant and Nv is the effective density of state
in the valence band.
Assuming thermionic emission as the main mechanism of current flow
across a Schottky junction, the barrier height can be calculated using the
relation
kT AA∗ T 2
φb = ln (8.7)
q I0
where A∗ is the effective Richardson constant, A is the area of the diode
and I0 is the saturation current. The ideality factor, m, is obtained from
the relation [28]
q ∂v
m= (8.8)
kT ∂ (ln I)
Heterostructure Schottky diodes 289
Figure 8.11. Forward and reverse current–voltage characteristics of a

PtSi/Si0.81 Ge0.19 Schottky diode at different temperatures.
∂v
where ∂(ln I) is the slope of the linear extrapolated part of the current–
voltage characteristics.
The barrier height of a Schottky junction can also be determined from
the measured reverse capacitance value. The determination of the Schottky
barrier height by the capacitance–voltage method is based upon the voltage
dependence of the charge in depletion region of the diode. Capacitance per
unit area of a reverse biased Schottky junction is expressed as [27]

qs Na s
CD = = (8.9)
2(Vbi − V − kT /q) W
where s is the dielectric constant of the semiconductor, Na is the acceptor

concentration of the diode, V is the applied reverse bias, Vbi is the built-in
potential and W is the depletion width. It is evident from equation (8.9)
that the plot of 1/CD 2 versus applied reverse voltage for an ideal Schottky
Figure 8.12. Forward and reverse current–voltage characteristics of a

PtSi/Si0.71 Ge0.29 Schottky diode at different temperatures.
diode will be a straight line. From the intercept on the voltage axis, the
barrier height is determined from the relation
kT
φb = Vi + ψp + (8.10)
q
where Vi is the voltage intercept and ψp is the potential difference between
the hole quasi-Fermi level and the top of the valence band, which can be
computed from the doping concentration and is given by

kT Nv
ψp = ln . (8.11)
q Na
The C–V method measures the electrostatic properties of the Schottky

barrier and is insensitive to transport effects such as tunnelling and
image force lowering. For an inhomogeneous interface, the C–V method
Schottky diodes on strained-Si1−x Gex 291
averages over the whole sample area and measures the mean barrier
height. Using the C–V technique, the energy distribution of the interface
state density at a metal–semiconductor interface has been measured by
Chattopadhyay et al [29].
8.7. SCHOTTKY DIODES ON STRAINED-SI1−X GEX
The forward and reverse logarithmic current–voltage characteristics at

different temperatures of PtSi/Si0.81 Ge0.19 and PtSi/Si0.71 Ge0.29 Schottky
diodes are shown in figures 8.11 and 8.12, respectively. It is seen from
the figures that the diode with a higher Ge concentration shows a higher
current. It is also seen from figures 8.11 and 8.12 that reverse currents
do not saturate for PtSi/Si1−x Gex Schottky diodes. The simulated band
diagram of a PtSi/Si1−x Gex Schottky diode is shown in figure 8.13,
considering the effect of interface states and the associated series resistance.
For simulation, a thin interfacial oxide layer of 10 Å was taken into
account. It is seen from the simulated band diagram that the valence
band discontinuity is in close proximity to the interface. This happens
Figure 8.13. Simulated energy band diagram of a metal-silicide/strained

Si1−x Gex Schottky barrier diode with an interfacial layer and a series resistance.
as the thickness of the SiGe layer is small (limited by the critical layer
thickness) to retain the strain in the epitaxial layer. Moreover, the layers
get unintentionally doped during film growth in an MBE system. As the
valence band discontinuity is in close proximity to the Schottky junction,
the total effective barrier can be changed by changing the applied reverse
bias. The sensitivity of the barrier height change can be controlled by
changing the SiGe layer thickness. As a result, the barrier height decreases
with the applied reverse bias [30].
Room temperature experimental and simulated forward current–
voltage characteristics of PtSi/Si1−x Gex (x = 0.19 and x = 0.29) Schottky
diodes are shown in figure 8.14 [31]. For simulation of forward current–
voltage characteristics, thermionic emission, image force lowering and
thermionic field emission models were considered. Since the existence of a
Figure 8.14. Experimental and simulated current–voltage characteristics of

PtSi/Si1−x Gex (x = 0.19 and 0.29) Schottky diodes.
thin interfacial layer (typically a few atomic layers) between the Schottky
contact and the semiconductor affects the current–voltage characteristics
significantly, interfacial layers of a thickness of 8 Å and 10 Å were included
in the simulation of the current–voltage characteristics of PtSi/Si0.81 Ge0.19
and PtSi/Si0.71 Ge0.29 Schottky diodes, respectively. The interfacial layer
was assumed to be transparent to the carriers, so that they tunnel through
it without any reflection, but able to withstand a potential drop across
it. Associated series resistances were computed to be 12.2 Ω cm−2 and
0.70 Ω cm−2 , respectively. Fermi level pinning was also incorporated in
the model. To fit the experimental current–voltage characteristics, the
interface state density for both the diodes was taken to be the same,
1 × 1012 cm−2 eV−1 . The simulated current–voltage characteristics agree
well with the experimental data for both the heterostructure Schottky
diodes, as shown in figure 8.14.
8.7.1. Barrier height and ideality factor

The saturation current density of a Schottky diode (J0 ) at zero bias is
usually obtained by extrapolating the linear portion of the forward current–
voltage characteristics to zero applied bias. Using the saturation current,
important parameters such as the barrier height and ideality factor for a
Figure 8.15. Schematic structures of Schottky diodes fabricated on solid source

MBE grown Si0.81 Ge0.19 and Si0.71 Ge0.29 films. (After Dentel D et al 1998
Semicond. Sci. Technol. 13 214–9.)
Schottky diode can be determined. However, it is difficult to apply at

large biases where the voltage drop across the series resistance of the diode
may become a significant proportion of the applied voltage. To avoid this
difficulty, the saturation current and ideality factor are calculated by using
a least-squares fitting method [32].
Dentel et al [24] have measured the barrier heights of platinum–silicide
Schottky diodes on p-type Si1−x Gex (x = 0.19 and x = 0.29) films.
The device structures are shown in figure 8.15. The barrier height and
ideality factor were extracted using equations (8.7) and (8.8), respectively.
The variation of the barrier height as a function of temperature is shown
in figures 8.16 and 8.17. It is seen from the figures that the Schottky
barrier height (SBH) increases with the increase in temperature. The
room temperature SBH values of PtSi/strained Si1−x Gex Schottky diodes
extracted were 0.57 eV (x = 0.19) and 0.52 eV (x = 0.29). When the
temperature was lowered to 95 K, barrier heights decreased to 0.20 eV and
Figure 8.16. Variation of Schottky barrier heights with temperature of

PtSi/Si0.81 Ge0.19 , PdSi/Si0.81 Ge0.19 and TiSi/Si0.81 Ge0.19 Si diodes.
Figure 8.17. Variation of Schottky barrier heights with temperature of

PtSi/Si0.71 Ge0.29 , PdSi/Si0.71 Ge0.29 and TiSi/Si0.71 Ge0.29 Si diodes.
0.19 eV, respectively. For comparison, the temperature dependences of the

barrier height of the PtSi/Si Schottky diode are shown in figure 8.18. The
same trend of barrier height variation with temperature is also observed
for Si. Such a strong dependence of the barrier height on temperature is
due to the fact that the measured current through a Schottky junction
is a combination of thermionic and recombination currents. As a result,
barrier height values calculated using the thermionic emission model show
temperature dependence, since deviation from ideal behaviour due to
recombination becomes more pronounced as the temperature is lowered
[16, 33, 34]. Also the presence of a thin native oxide layer on the Si surface
strongly influences the temperature dependence of the barrier height [35].
At a particular temperature, the barrier heights of the PtSi/Si1−x Gex
(x = 0.19 and 0.29) Schottky diodes are smaller than those of the PtSi/p-Si
Schottky diode. The biaxial strain in Si1−x Gex causes a change in the
bandgap which is empirically expressed as Eg (x) = 1.11–0.74x eV, where
Figure 8.18. Variation of barrier heights with temperature of PtSi/Si, PdSi/Si

and TiSi/Si Schottky diodes.
x is the Ge concentration [36]. The bandgap reduction for 19% Ge

concentration is 0.13 eV, while it is 0.20 eV for a 29% Ge concentration
with respect to Si. This bandgap reduction is the reason for the smaller
barrier height obtained for Schottky diodes on p-SiGe films with a higher
Ge concentration.
The room temperature ideality factor, extracted from the experimental
I–V characteristics were found to be 1.10 and 1.15 for PtSi/Si1−x Gex
diodes for x = 0.19 and 0.29, respectively. The current–voltage
characteristics depend on the interface quality. In a Schottky diode, even
with a good surface treatment, an interfacial oxide layer, of a thickness
of about 5–10 Å with a considerable amount of surface states, is present.
According to the Bardeen limit [27], surface states pin the Fermi level
at the mid energy gap of the energy band and make the barrier height
less sensitive to the metal work function. The greater than unity ideality
factor shows the deviation of Schottky diode characteristics from their ideal
behaviour.
2
Figure 8.19. Plots of 1/CD versus applied reverse bias at room temperature for
(a) TiSi/Si0.81 Ge0.19 and (b) TiSi/Si0.71 Ge0.29 Schottky diodes.
In thermionic emission theory, which models the ideal Schottky

current–voltage characteristics, there is no satisfactory explanation for the
greater than unity ideality factor [37, 38]. The departure of the ideality
factor from unity may be due to the presence of an interfacial layer between
the metal and semiconductor [14] and also due to the existence of a laterally
varying potential barrier height, caused by a nonuniform interface [39].
Image force lowering has also been shown to be responsible for a greater
than unity ideality factor [27]. The dependence of the ideality factor on
temperature is due to thermionic field emission and also recombination in
the depletion region. As the bias voltage increases, the electric field at
the Schottky boundary decreases the potential drop across the interface.
The bias voltage at which current–voltage characteristics become strongly
nonideal depend more on the potential drop across the interfacial layer
than on series resistances present in the diodes [35].
Table 8.2. Schottky barrier height and ideality factor of group IV alloy layers
with Pt, Pd and Ti.
Parameter Film Si0.71 Ge0.29 Si0.79 Ge0.20 C0.01
with Si-cap with Si-cap
Metal Pt Pd Ti Pt Pd Ti
Ideality 300 K 1.15 1.12 1.03 1.11 1.20 1.20
factor (n) 100 K 1.32 1.52 1.53 1.48 1.47 1.30
Barrier 300 K 0.52 0.54 0.56 0.56 0.57 0.58
height (eV) 100 K 0.19 0.23 0.27 0.21 0.22 0.23
Figure 8.20. Plot of forward capacitance–voltage characteristics of a

PtSi/Si0.81 Ge0.19 Schottky diode at different frequencies.
Figure 8.21. Forward capacitance–voltage characteristics of a PtSi/Si Schottky

diode at different frequencies.
From the forward and reverse currents of PdSi/strained Si1−x Gex

and TiSi/strained Si1−x Gex Schottky diodes barrier heights have been
extracted by Maiti and Chattopadhyay [40]. The variation of the barrier
heights of the diodes with temperature is shown in figures 8.16 and 8.17. In
the case of PdSi/strained Si1−x Gex and TiSi/strained Si1−x Gex Schottky
diodes, the barrier height increases with the increase in temperature. The
room temperature values of the barrier heights for PdSi/strained Si1−x Gex
Schottky diodes with x = 0.19 and 0.29 Ge are 0.58 eV and 0.54 eV,
respectively. At 100 K, these values reduce to 0.28 eV and 0.23 eV,
respectively. The values of the ideality factor of the diodes were within
1.03–1.50. Table 8.2 shows the extracted values of SBH and ideality factors
of various metal–film combinations at room temperature and 100 K.
Barrier heights may also be determined from reverse capacitance–
voltage measurements. When a small ac voltage is superimposed upon the
dc bias, charges of one sign are induced on the metal surface and charges of
Figure 8.22. Forward capacitance–voltage characteristics of PtSi/Si1−x Gex

(x = 0.19 and 0.29) Schottky diodes at 10 kHz (LF) and at 1 MHz (HF).
opposite sign in the semiconductor. The relationship between capacitance

and reverse applied voltage is given by equation (8.9). Figure 8.19 shows
2
typical plots of 1/CD versus applied reverse voltage of TiSi/Si1−x Gex
(x = 0.19 and 0.29) Schottky diodes measured at a frequency of 1 MHz.
Using the voltage intercepts (on the x-axis) of 0.35 V and 0.28 V for the
samples containing 19% and 29% Ge, the barrier heights extracted were
0.61 eV and 0.56 eV. The difference in the Schottky barrier height values
deduced from current–voltage and C–V measurements is attributed to the
effect of inhomogeneities at the interface of the diodes.
8.7.2. Interface state density distribution
The Schottky barrier diode characteristics deviate from their ideal

behaviour due to the presence of an interfacial layer at the junction
and the associated interface states. The distribution of the interface
state density in metal/SiGe Schottky diodes has been reported by
Chattopadhyay et al [29].
Figure 8.23. Energy distribution of interface state density of TiSi/Si0.81 Ge0.19 ,

PdSi/Si0.81 Ge0.19 and PtSi/Si0.81 Ge0.19 Schottky diodes.
The distribution of the interface state density in a Schottky diode is

determined from capacitance–voltage measurements. Figure 8.20 shows
the plots of forward C–V characteristics of the PtSi/Si0.81 Ge0.19 Schottky
diode in the frequency range of 10 kHz to 1 MHz. At high frequency, the
capacitance value becomes almost constant but in the low-frequency range
the capacitance value shows a peak. The peak arises from the contribution
of interface states present in the Schottky junction and partly due to the
injection of minority carriers from the non-ohmic back side [41]. The
corresponding plot for a PtSi/Si Schottky diode is shown in figure 8.21.
It is seen that the variation of capacitance is of same nature as that of
PtSi/Si1−x Gex diodes. Figure 8.22 shows only the plots of measured C–
V data at 10 kHz and 1 MHz for PtSi/Si0.81 Ge0.19 and PtSi/Si0.71 Ge0.29
diodes. Taking CLF (10 kHz) and CHF (1 MHz) values, the interface state
density Dit is extracted.
Figure 8.24. Energy distribution of interface state density of TiSi/Si0.71 Ge0.29

and PtSi/Si0.71 Ge0.29 Schottky diodes.
The energy distribution of the interface states of Si1−x Gex (x = 0.19

and 0.29) Schottky diodes using Pt, Pd and Ti are shown in figures 8.23
and 8.24, respectively. In figures 8.23 and 8.24, the energy has been plotted
from the valence band edge. It is seen that the distribution of the interface
state densities for all cases is maximum near the valence band edge and
decreases (and remains almost constant) with energy from the valence band
edge to the midgap. The minimum value of the interface state density for
all the diodes lies in the energy range from 0.5–0.6 eV and has a value in
the range of 6 × 1011 cm−2 eV−1 to 4.5 × 1012 cm−2 eV−1 [29]. It is seen
from figures 8.23 and 8.24 that the PtSi/Si1−x Gex Schottky interface has
the lowest interface state density as compared to PdSi and TiSi Schottky
diodes on Si1−x Gex .
The energy distributions of the interface state densities of TiSi/Si and
PdSi/Si Schottky diodes are shown in figure 8.25. It is seen that the
Schottky diodes on strained-Si 303
Figure 8.25. Energy distribution of interface state density of TiSi/Si, PtSi/Si

and PdSi/Si Schottky diodes.
distribution of the interface state density with energy is maximum near

the valence band edge and it decreases with energy from the band edge to
midgap energy for all Schottky diodes. The minimum value of the interface
state density for all diodes is in the energy range from 0.50–0.60 eV and
its value lies in the range of 1 × 1011 cm−2 eV−1 to 8 × 1011 cm−2 eV−1 .
It is also evident from figure 8.25 that the energy distribution of interface
states near the midgap is almost constant for all the diodes.
8.8. SCHOTTKY DIODES ON STRAINED-SI
Schottky diodes on p-type strained-Si on graded relaxed Si1−x Gex have

been characterized by Chattopadhyay et al [13]. The forward logarithmic
current–voltage characteristics of as-deposited Pt/strained-Si Schottky
diodes at different temperatures are shown in figure 8.26. The current–
voltage characteristics of the heterostructure Schottky diodes have also
Figure 8.26. Forward current–voltage characteristics of a Pt/strained-Si

Schottky diode (as-deposited) at different temperatures.
been simulated [35]. The simulated current–voltage characteristics for 95,

150 and 300 K are shown in figure 8.27.
Among Pt, Pd and Ti, Pt shows the lowest barrier height and is not so
sensitive to the metal work function. As discussed earlier, this is attributed
to Fermi level pinning by the interface states or by metal-induced gap
2
states. Figure 8.28 shows a typical plot of 1/CD versus applied reverse
voltage which is a straight line for Ti/strained-Si Schottky diodes. It is
seen from the figure that the intercept on the voltage axis is 0.38 eV and,
for a substrate doping concentration of 5 × 1015 cm−3 , the barrier height
is found to be 0.60 eV.
Summary 305
Figure 8.27. Experimental and simulated current–voltage characteristics of

Pt/strained-Si Schottky diode at 95, 150 and 300 K.
8.9. SUMMARY
Formation and characterization of noble/refractory metal silicides (Pt,

Pd and Ti on SiGe, SiGeC, Si and strained-Si) using x-ray diffraction,
Rutherford backscattering and Auger electron spectroscopy have been
discussed. Different phase transformations are observed during silicide
formation on SiGe and other alloys. Among all (Pt, Pd and Ti on
SiGe, SiGeC and strained-Si), the PtSi/Si1−x Gex Schottky diodes exhibit
a minimum barrier height with excellent interfacial quality and are
therefore, preferable for far-infrared detector applications, as has also
been demonstrated experimentally. Electrical characterization, over a
2
Figure 8.28. Plot of 1/CD versus applied reverse bias of Ti/strained-Si Schottky
diode at room temperature.
wide range of temperatures to determine Schottky diode parameters, has

shown that the barrier heights decrease with the decrease in temperature
and increase in Ge mole fraction in the epilayer. Extracted ideality
factors have values slightly greater than unity and are found to increase
with decrease in temperature for all metal-material systems discussed.
The interface state density decreases with increase in energy from the
valence band edge for all diodes. The barrier height values determined
from the reverse C–V characteristics at room temperature are found to
be slightly higher than that extracted from the forward current–voltage
characteristics. PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors have
been simulated in the wavelength range of 2–8 µm for detector applications
and the simulation results compare favourably with reported experimental
results as will be presented in chapter 9.
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[30] Jimenez J R, Xiao X, Sturm J C and Pellegrini P W 1995 Tunable, long-
wavelength PtSi/SiGe/Si Schottky diode infrared detectors Appl. Phys.
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[31] Chattopadhyay S, Bera L K, Ray S K, Bose P K, Dentel D, Kubler L,
Bischoff J L and Maiti C K 1998 Determination of interface state density
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[32] Bennett R J 1987 Interpretation of forward bias behaviour of Schottky
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[39] Schneider M V, Cho A Y, Kollberg E and Zirath H 1983 Characteristics of
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Chapter 9
SIGE OPTOELECTRONIC
DEVICES
Elemental silicon and germanium have long been used as photodetectors.

The tunability provided by SiGe and SiGeC alloys has recently been
exploited for extending the range of application. The fabrication and
performance of several classes of photodetector based on a heterostructure
are examined in this chapter. Methods of meeting the limitations of
indirect band-gap and small allowable thickness of stable strained alloy
layers are described. Silicon based optical waveguides and prospects of
device integration receive special emphasis.
The demand for optoelectronic technology is increasing rapidly
and is being driven by the exponential growth in personal computers,
high-speed computer interconnections, high-speed telecommunications
and other commercial optoelectronic products. Optical communication
systems are the most promising candidate for achieving large capacity
transmission over high-speed local area networks (LANs) using fibre
channel and optical interconnection systems. The wide spread use
of multimedia communications will require over 1 Gbit s−1 capacity
transmission, even in LANs. Optical communications offer a wide variety
of applications toward building the information superhighway, ranging
from short distance chip-to-chip communication, LAN, fibre-to-home, to
overseas telecommunications. Furthermore, with optical communication
systems, optoelectronic integrated circuits (OEICs) have the potential to
overcome the limitations in electronic integrated circuits for high speed,
wide bandwidth, and high density interconnects as device dimensions
shrink to the deep submicron regime.
Although silicon is the dominant material in electronics, its indirect
bandgap physically restricts its application in electro-optical devices. Most
of the high-performance devices in optoelectronics are made from III–V
compound semiconductor heterostructures, such as AlGaAs/GaAs and
310
SiGe optoelectronic devices 311
Table 9.1. Optical properties for Si and Ge.

Property Si Ge
Transparent regions (µm) 1.1–6.5 1.8–15
(absorption coefficient <1 cm−1 )
Dielectric constant 11.9 16
Refractive index (optical) 3.455 4.001
Optical–phonon energy (eV) 0.063 0.037
Phonon mean free path (Å) 76 (electron) 105
55 (hole)
InGaAsP/InP, because of their direct bandgap and high quantum efficiency.

There are also several III–V compound semiconductor pairs with excellent
lattice matching capability (≤1%), which is favourable for advanced
heterostructures and bandgap-engineered devices. However, there are some
inherent disadvantages of III–V semiconductors, such as poor mechanical
and thermal properties, difficulty in processing, incompatibility with silicon
and, more importantly, high cost.
Cost-effective silicon-based optoelectronics has attracted a great deal
of research effort and significant progress has been made [1–5]. If the
optical properties of silicon-based materials could be enhanced, in both the
visible and infrared regions, especially at wavelengths of 1.3 and 1.55 µm,
which are beyond the limitation of the Si bandgap but correspond to
minimum values of absorption and dispersion in glass optical fibres used for
long distance telecommunications, very powerful optoelectronic integrated
circuits could be realized entirely in silicon. Incorporation of Ge in Si
reduces the bandgap of the resulting SiGe alloys, shifting their absorption
wavelengths towards red compared to Si. SiGe strained layer superlattices
(SLS) offer the possibility of a fundamental change in optical properties of
Si. The important optical properties of Si and Ge are presented in table 9.1.
Optical communication systems with a Gbit s−1 capacity require the
development of high-speed, highly reliable, low-cost and compact optical
terminal ICs, such as Si-based optoelectronics integrated circuits. By
incorporating future Si-based optical devices (emitters and detectors) with
existing Si-based electronic circuitry all on a single silicon ‘superchip’ (see
figure 1.10), these Si-based OEICs would represent a great cost reduction
compared to their III–V counterparts and with added computational power.
Efforts to realize silicon-based optoelectronic devices include III–V
on-chip light sources grown on silicon [6] or bonded to silicon [7], porous
silicon [8–10], erbium-doped silicon [11, 12] and group IV semiconductor
heterostructures [4]. In hybrid optoelectronic integration on Si, III–V
photonic devices and Si or SiGe electronic devices are bonded on an Si
312 SiGe optoelectronic devices
Table 9.2. ICs for optical fibre communication systems fabricated by using
SiGe HBTs.
Circuit Maximum speed/bandwidth

Multiplexer 40 Gb s−1
Pre-amplifier 35.1 GHz
AGC amplifier 31.6–32.7 GHz
Decision circuit 40 Gb s−1
Demultiplexer 40 Gb s−1
Static frequency divider 50 GHz
chip. This approach combines the high-speed and light emission advantages
of III–V semiconductors and the mature and reliable Si technology. It is
practical and has achieved some success for optoelectronic signal processing
in the last few years [7, 13]. However, the fabrication of hybrid OEICs is
more complicated, expensive and less reliable than monolithic OEICs. Also,
interconnection density and speed in hybrid OEICs are limited.
As applications of SiGe HBTs, various ICs for optical-fibre-link
systems, have been developed (see table 9.2) [14, 15]. These include both
digital ICs of a static frequency divider and a time-division multiplexer
(MUX), demultiplexer (DEMUX) and analogue ICs of a pre-amplifier, an
AGC amplifier core and a decision circuit. A maximum operating frequency
of up to 50 GHz for a 1/8 static frequency divider has been achieved. A
2:1 time-division MUX and a 1:2 DEMUX built from basic circuit core
modules operated at 40 Gb s−1 . In a pre-amplifier with an input stage
consisting of a common base transistor, a bandwidth of 35 GHz was also
achieved. In an AGC amplifier core, a bandwidth of about 32 GHz with a
dynamic range of 19 dB was obtained by using a transimpedance amplifier
as an active load circuit and a peaking capacitor.
Highly porous silicon (PS) has attracted much attention because it
exhibits strong photoluminescence (PL) from the near-infrared to visible
green–blue range by varying the porosity at room temperature [9, 16]. The
external quantum efficiencies of light emission of highly porous silicon can
be as high as 1–10%. There is still a debate in the scientific community
regarding the physics of this phenomenon. The common views of the origin
of light emission are:
(i) the two-dimensional quantum-size effects;

(ii) surface molecular species coating the porous skeleton;
(iii) radiative decay at surface/interface states; and
(iv) hydrogenated amorphous silicon as a product of the invasive
electrochemistry [10].
SiGe optoelectronic devices 313
Similar observations of strong visible PL from MBE grown B-doped porous

Si0.7 Ge0.3 grown on p-type Si wafers have been reported [17]. The porous
layers were formed by an electrochemical etching process. A significant
shift in the emission energy of porous Si0.7 Ge0.3 grown on Si has been
observed for various anodization conditions and the temperature range
78–295 K. The PL emission energy has been found to remain almost
unchanged on varying excitation energy, and to increase linearly with
reciprocal temperature. The position of the PL emission, however, was
observed to be strongly dependent upon the anodization current density
and the duration of the etching process. The origin of visible PL of the
porous MBE grown SiGe films is interpreted by considering the quantum
confinement effect, as in the interpretation of PL from porous Si. Despite
its high efficiency, highly porous silicon has a problem with integration due
to mechanical fragility and poor thermal conductivity and ohmic contacts.
When doped with rare earth ions, silicon produces intense PL [11, 18].
Erbium is of great interest among these rare earth ions, because its
luminescence spectrum, due to the transitions from the first excited spin-
orbit state to the first ground state, is centred around 1.54 µm which is
the absorption window in silica-based optical fibres. However, coupling
between Er and the host Si remains a problem.
Absorption of infrared radiation of 8–12 µm in atmosphere is small
and this wavelength range is important for night vision applications. The
group II–VI compound semiconductor (HgCdTe) IR sensor is most sensitive
in this wavelength range. But monolithic integration on Si substrates for
large scale use with charge coupled devices is difficult. PtSi/p-Si Schottky
diodes are presently being used but operate only in the 3–5 µm wavelength
range. IrSi/p-Si Schottky diodes have a low barrier height with a cut-off
wavelength of about 7.3 µm [19]. PtSi/Si1−x Gex Schottky diodes are also
promising for sensing far-infrared radiation due to its smaller barrier height
compared to PtSi/Si or IrSi/Si Schottky diodes.
SiGe alloys have led to the realization of many novel bandgap-
engineered high-speed optoelectronic devices with significantly improved
performance and are easily integrated with conventional Si technology
[1, 2, 5]. For compatibility with Si technology, strained layer superlattices
are generally grown on an Si substrate. Using Si/SiGe/Si SLS, it is
possible to convert the indirect bandgap of Si to a quasi-direct bandgap via
Brillouin zone folding and to exploit the new optical properties in terms
of Si-based optical devices. The aim is the fabrication of Si-based active
and passive optical devices (light emitters and receivers such as LEDs
and photodetectors) which could be integrated in silicon together with
the electronic driver circuits [20]. Experimental studies have shown that
infrared (>1.2 µm) light can be waveguided, detected, emitted, modulated
and switched in Si and in binary group IV alloy films [21].
However, a 4.2% lattice mismatch between silicon and germanium is
a serious constraint in the design of SiGe heterostructures necessary for

optical applications [22–25]. Most of the earlier investigations have involved
SiGe heterostructures with a limited Ge content (<30%). In order to
obtain a reasonable photoresponse in the 1.3 µm wavelength region, the
Ge concentration should be more than 50%, whereas the critical thickness
for a strained pseudomorphic SiGe epilayer with x = 0.5 is limited to only
100 Å or less [4]. As described in chapter 2, for epilayers with a thickness
greater than the critical thickness, misfit dislocations are introduced at
the interface and the quality of the epilayer is degraded, affecting the
performance of the devices.
In general, the group IV alloy system includes three binary alloys:
SiGe, SiC and GeC. By adding a small substitutional C to the SiGe
system, it is possible to adjust the lattice constant and strain (from
compressive to tensile) and obtain an adjustable bandgap (from 0.67 eV
to 5.48 eV by varying the composition) [26]. Ternary SiGeC and
quarternary SiGeSnC systems offer an additional degree of freedom for
strain and bandgap engineering in Si-based alloys. Guarin et al [27] have
reported the growth of ternary Si0.955 Sn0.03 C0.015 alloys up to 4500 Å
in thickness and quarternaries of composition in the neighbourhood of
Si0.835 Ge0.125 Sn0.03 C0.01 . Infrared absorption spectroscopy and PL data
have provided evidence of the potential for significant bandgap modification
in these alloys. For this reason, renewed attention has shifted to the novel
ternary Si1−x−y Gex Cy and SiGeSnC material systems [28, 29].
The other group IV alloy material with a potential for applications
in the fabrication of Si-based infrared devices is metastable Snx Ge1−x
films [30]. Band structure calculations have suggested that the Snx Ge1−x
alloys have direct energy gaps continuously tunable from 0.55 eV to 0 eV
for compositions x from 0.2 to 0.6 with very small electron effective masses.
The relatively low growth temperature of Snx Ge1−x (∼200 ◦ C) opens
the possibility of direct monolithic integration of detector arrays on Si
integrated circuits.
The bandgap of a–SiGe:H can be varied from 1.75 to 1.0 eV by
changing the Ge content, and makes the material suitable for detection of
light emitted from commercial laser diodes or LED. Films can be deposited
at a low temperature of about 250 ◦ C on glass as well. Hydrogenated
a–SiGe:H has been used for implementing phototransistors in the infrared
range, solar cells, for optical detection and image sensing. Dilution
with hydrogen causes a small decrease of the bandgap and improves the
structural and electronic properties [31]. However, a simulation study of
carrier multiplication in the Si1−x Gex material system shows that only a
small increase of solar cell efficiency is expected from the impact ionization
of hot carriers [32].
The objective of this chapter is to review the recent developments
and the possible applications of group IV (SiGe, GeC, SiGeC, SiGeSnC
Optoelectronic devices in silicon 315
and strained-Si) alloys in optoelectronics for integrated circuits entirely

on silicon. Photoresponsivity and refractive index data obtained from
experimental SiGe, SiGeC and GeC photodiodes are presented. Simulation
of PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors in the wavelength
range of 2–8 µm, p-doped/intrinsic/n-doped (p–i–n) photodetectors,
photoresponse characteristics of Si1−x Gex metal–semiconductor–metal
(MSM) photodetectors and Si1−x Gex /Si waveguide photodetectors will be
considered.
9.1. OPTOELECTRONIC DEVICES IN SILICON
A photodetector converts an incident optical signal to an electrical signal

that can be processed electronically to extract the required information
carried by the incident optical signal. Semiconductor photodetectors are
made by forming a p–n junction within the semiconductor or by forming a
metal–semiconductor junction. On application of a suitable reverse bias to
the device, an electric field is created which separates the photogenerated
electron–hole pairs. The device can operate either in photovoltaic or
photoconductive mode. Photodetectors play an important role in optical
fibre communication systems and are generally used in optical receivers.
The requirements for a good photodetector include high quantum efficiency
at the operating wavelength, high speed, wide bandwidth, high reliability,
low noise and low cost.
An optical transmission and processing system consists of light
sources (LED), photodetectors, modulators, electronic devices, and other
passive or quasi-passive optical components. In a photoreceiver, a
photodetector is monolithically integrated with a pre-amplifier which
uses an FET or an HBT. Different types of photodetectors proposed
for optical fibre communication are: p–n junction photodiodes (PN-
PDs), p–i–n photodiodes (PIN-PDs), avalanche photodetectors (APDs),
optical field effect transistors (OPFETs), MSM photodetectors (MSM-
PDs), p-heterojunction bipolar transistors (PHBTs) and photoconductors.
Electron–hole pairs can be produced in a semiconductor by incident
light through two different processes. For incident radiation with an energy
hν > Eg , where ν is the frequency of light and Eg is the semiconductor
bandgap. The intrinsic photoexcitation process occurs where electron–hole
pairs are generated by band-to-band transitions. In the other process, the
extrinsic excitation process, the incident photon excites an electron from
a donor level into the conduction band, or an electron is excited from the
valence band to an acceptor level creating a hole in the semiconductor.
Most photodiodes are of the intrinsic type.
For intrinsic excitation processes, the long wavelength cut-off λc is
given by
hc 1.24
λc = = (9.1)
Eg Eg
where c is the velocity of light. The external quantum efficiency of the
photodiode is defined as the number of electron–hole pairs generated per
incident photon and is given by
Ip /q
η= (9.2)
Popt /hν
where Ip is the photogenerated current, Popt is the incident optical power,

and hν is the photon energy with a wavelength of λ. A related figure-of-
merit is photoresponsivity, which is given by
Ip ηq ηλ
Rphoto = = = . (9.3)
Popt hν 1.24
The most common type of photodetection device is the depletion layer

photodiode, which includes a p–n junction diode or a p–i–n diode. Another
common type which exhibits gain is the avalanche photodiode. The other
members of the photodiode family are Schottky barrier and MSM diodes.
9.1.1. p–n junction photodiode

A p–n junction photodiode is the simplest type of junction diode. It
works under relatively large reverse bias, which is substantially below
the avalanche breakdown voltage. The incident optical signal produces
electron–hole pairs in the photodiode, but only the carriers created
within the depletion region or within a diffusion length of the depletion
edge contribute. The reverse bias field in the depletion region sweeps
the photogenerated carriers towards the contacts and gives rise to a
photocurrent in the external circuit. The holes and electrons, separated by
the electrical field, travel at different velocities towards the contacts due to
their different effective masses. A large reverse bias reduces the transit time
through the depletion region as well as the depletion region capacitance,
thus improving the diode capability for high-frequency operation.
Free carriers generated by incident photons move by drift and diffusion
and the total current density through the reverse biased depletion layer is
Jtot = Jdrift + Jdiff (9.4)
where Jdrift and Jdiff are the drift and diffusion components, respectively.
For a p+ –n junction diode, the total current is given by

e−αW Dp
Jtot = qφopt 1 − + qpn0 (9.5)
(1 + αLp ) Lp
where φopt is the total photon flux, W is the width of the depletion
layer, q is the free electron charge, α is the optical inter-band absorption
coefficient, pn0 is the equilibrium hole density, and Lp and Dp are the
diffusion length and the diffusion constant, respectively, for holes. The last
term in equation (9.5) represents the reverse leakage current (dark current).
When the reverse leakage current is very small, then the quantum efficiency,
η is given by
Ip /q e−αW
η= =1− . (9.6)
Popt /hν 1 + αLp
It is clear that the quantum efficiency is determined mainly by the
absorption coefficient, α, of the semiconductor. In order to maximize η, it
is desirable to make the products αW and αLp as large as possible, i.e.,
the depletion layer must be sufficiently wide to allow a large fraction of
the incident light to be absorbed. On the other hand, the depletion region
must be kept narrow to reduce the transit time for high-speed devices.
The avalanche photodiode is essentially a p–n junction operated in
a reverse bias condition at or above the avalanche breakdown voltage.
Photogenerated carriers in the depletion region travel at their saturation
velocities. When these photogenerated carriers acquire enough energy
from the electric field, impact ionization occurs and results in avalanche
multiplication of the carriers. Therefore, the gain of the APD can be
substantially increased over conventional p–i–n photodiodes, but with
elevated noise inherent to the avalanche process.
9.1.2. Schottky barrier photodiode

Metal–semiconductor contacts (Schottky diodes) are used as very efficient
photodetectors as these are majority carrier devices. The barrier height,
φb depends on the particular metal–semiconductor combination. As these
devices do not suffer from minority carrier storage and removal problems,
one can expect high speed and operation bandwidth. The temporal
response, speed and frequency bandwidth of detectors are controlled by
the transit time of the carriers through the absorption region and external
circuit parameters. In high-speed diodes, the absorption region is between
0.2–0.5 µm which ensures full depletion of the region even at low values
of reverse bias, and both electrons and holes can travel at their respective
saturation velocities. Schottky barrier photodetectors can operate in two
modes.
(i) When qφb < hν < Eg , i.e., the energy of incident photon flux is higher
than the corresponding Schottky barrier height but smaller than the
bandgap energy of the semiconductor, electrons will be photoexcited
in metal and surmount the barrier by thermionic emission. Emitted
electrons transit through the semiconductor and are collected at the
contact electrodes. The process extends the spectral range towards

red (as it absorbs an energy lower than the bandgap energy) but
decreases device speed as thermionic process is a slow one.
(ii) When hν > Eg , the photon flux penetrates through the semi-
transparent metal layer and gets absorbed in the semiconductor. The
photogenerated electron–hole (e–h) pairs move in opposite directions
due to the existing electric field with their respective saturation
velocities and are collected at the electrodes. This is a very efficient
mode of operation of Schottky diodes and is similar to that of a high-
speed p–i–n diode. The fabrication of a Schottky barrier photodiode
is also easy and lends itself for integrated applications.
9.1.3. p–i–n photodetectors

p–i–n photodetectors are finding extensive applications in long haul and
high bit rate optical communication systems and in local area networks
for operation in the infrared region (0.8–1.6 µm). In addition to optical
communication, these devices are also useful for sensing applications as they
have superior electro-optical characteristics, namely low dark current, high
quantum efficiency, greater sensitivity and high speed of response [33–35].
An important mode of operation of a p–i–n photodiode under the
exposure of photon flux is the reverse biased configuration. In order to
maximize the quantum efficiency of the diode, an intrinsic layer (i-layer) is
inserted between two heavily-doped p+ - and n+ -layers and the resulting
structure is a p–i–n diode. When a reverse bias is applied across the
device, entire i-region becomes depleted. Due to high resistivity and
total depletion of the i-layer, almost all the electric field appears across
it. The applied reverse bias should not be so high that breakdown can
take place. The dark current is independent of applied reverse bias.
As light impinges from the top surface, most of the photon flux passes
through the relatively thin top layer. The absorbed photons generate
electron–hole pairs which drift towards the electrodes due to the existing
electric field to give rise to a photocurrent in the external circuit. One
of the advantages of heterojunction p–i–n photodiodes is that the device
characteristics are tunable by changing the composition of the i-layer.
Another is the resonant–cavity effect, due to the refractive index change
at the heterojunction, which increases the photoresponsivity of the diode
without affecting the transit-time-limited bandwidth [36].
9.1.4. Metal–semiconductor–metal photodetectors

Metal–semiconductor–metal photodetectors (MSM-PDs) are made up of
interdigitated metal fingers forming back-to-back Schottky diodes on
an undoped semiconductor surface (see figure 9.1). These detectors
Figure 9.1. (a) Schematic structure of an MSM photodiode and (b) analysing
area. (After Chattopadhyay S and Maiti C K, unpublished data.)
are very attractive for many optoelectronic applications, particularly for

high-frequency wideband operation and are used in multi-gigabit optical
communication with high sensitivity. MSM devices can be integrated in
conventional IC-processing technology. On application of the bias, one
junction becomes forward-biased while the other becomes reverse-biased.
It can be designed so that the region between the two electrodes is almost
depleted. When the incident photon flux impinges on the photo-active
area (interdigitated area), the diode responds as a Schottky photodetector
discussed above. Some of the important design parameters for MSM-PDs
are responsivity, dark current and capacitance, which are discussed below.
The dark current (which decides the minimum detectable power) of
a photodetector significantly contributes to the noise at the input of an
optical receiver, which in turn plays a crucial role in deciding the sensitivity
of a receiver. Excess carriers responsible for dark current increase the
capacitance and decrease the response speed of a detector. The detector
noise associated with its dark current is a shot noise and its mean square
value is given by
i2d = 2qId ∆f. (9.7)
Furthermore, the minimum optical power required to achieve a
photocurrent equal to the noise current id is usually regarded as the
minimum detectable power of a detector. In an MSM structure, the dark
current is a metal/semiconductor interface phenomenon and is attributed
to thermionic emission of the carriers across the Schottky barriers [37].
Usually, thermionic emission of the carriers across a reverse-biased Schottky
junction accounts for the dark current in MSM photodiodes [38] and the
dark current density is given by
J = A∗n T 2 e−q(φb −∆φb )/kT . (9.8)
It is noted that a low Schottky barrier height would result in excess carrier
injection in the semiconductor from the cathode and would lead to a large
dark current. It has been proposed that equation (9.8) is valid until the
conduction band profile of an MSM photodiode does not reach the flat band
condition at the forward-biased contact [39]. When the conduction band
at the anode reaches the flat band condition, thermionic emission of holes
across the barrier at anode starts and is accounted for the dark current
which is given by
J = A∗n T 2 e−q(φb −∆φb )/kT + A∗p T 2 e−q(φb −∆φb )/kT (9.9)
where A∗ are the respective Richardson constants and ∆φ are the respective
barrier height lowering due to image force. The flatband voltage VFB can
be expressed as [37]
qNd S 2
VFB = (9.10)
2s 0
where S is the electrode spacing and Nd is the donor concentration in the
layer.
The dark capacitance of an MSM photodetector is contributed by the
electrostatic field around the alternatively charged parallel metal fingers.
The speed of an MSM detector is limited by RL C time constant if it is
longer than the transit time or recombination time. Here, RL consists
of the load resistance and series resistance of the metal fingers. The
detector capacitance can be estimated by using a model based on conformal
Optical properties of SiGe and SiGeC films 321
mapping [40]. If W is the finger width and P is the finger pitch (sum of
width and spacing, i.e., P = W +S), the total detector capacitance is given
by
C0 A
Ctotal = (9.11)
P
where A is active area of the detector.
9.2. OPTICAL PROPERTIES OF SIGE AND SIGEC FILMS
It has been shown that quantum efficiency is determined mainly by

the absorption coefficient of the semiconductor. The measured optical
absorption coefficient, α, and refractive indices of Si and Si1−x Gex for
different values of the Ge fraction, x, are shown in figures 9.2 and 9.3. The
Figure 9.2. Optical absorption coefficients of Si, Ge and undoped SiGe alloys.
Figure 9.3. Refractive indices of Si, Ge and undoped SiGe alloys.
data are taken from [41]. It is seen from figure 9.2 that Si is transparent
in the wavelength region 1.20–1.60 µm, while the SiGe absorption edge
shifts towards the red with increasing Ge concentration in the alloy. The
shift offers a means for absorbing 1.3–1.6 µm light, by choosing x > 0.3 for
1.3 µm and x > 0.85 for 1.55 µm. From figure 9.3, it may be noted that
the refractive index increases with the increase in Ge concentration. While
intrinsic Si and Ge are transparent from near-infrared up to 20 µm and
beyond, the optical transmission of group IV alloys is found to reduce by
heavy doping [2]. For unstrained (bulk) SiGe alloys, the absorption data
have been provided by Braunstein et al [42].
Orner et al [43] have measured the optical absorption at phonon
energies near the bandgap of a Ge-rich SiGeC (x ≈ 0.90, y ≤ 0.02) film
by employing Fourier transform infrared (FTIR) spectroscopy. As the film
Optical properties of SiGe and SiGeC films 323
Figure 9.4. Optical absorption coefficient (α) of a Ge-rich Si0.11 Ge0.88 C0.01
film: (a) C is primarily substitutional and (b) C is primarily interstitial. (After
Orner B A et al 1996 Appl. Phys. Lett. 69 2557–9.)
was Ge-rich, their bandgap energies are less than that of Si. Absorption
data and the best fit curves are as shown in figure 9.4. Figure 9.4(b)
shows a comparison between two films with carbon at the interstitial and
substitutional sites. In both cases the infrared absorption edge of the alloy
shifts towards the red.
Figure 9.5 shows the refractive index of the epitaxial Ge1−x Cx as a
function of donor concentration and compares it to Ge epitaxial layers
grown under identical conditions. Introducing carbon into epitaxial Ge
films doped with P decreases the refractive index near the absorption
edge. Figure 9.6 illustrates the absorption coefficient, α, of phosphorus-
Figure 9.5. Refractive index versus donor concentration for Ge1−y Cy and Ge
epitaxial films on Si(100). (After Dashiell M W et al 1998 Thin Solid Films 321
47–50.)
Figure 9.6. Absorption coefficient versus photon energy of Ge1−y Cy layers on

Si(100) for ND = 7 × 1019 cm−3 , ND = 2 × 1018 cm−3 and undoped. Included are
values for intrinsic bulk-Ge. (After Dashiell M W et al 1998 Thin Solid Films
321 47–50.)
Optical devices using SiGe alloys 325
doped Ge1−y Cy films grown epitaxially on Si(100) for α > 100 cm−1 .
The absorption edge experiences a redshift with increasing phosphorus
concentrations for both Ge1−y Cy and Ge films. High-purity Ge data are
also included in the figure. Note that undoped Ge1−y Cy epitaxial layers
exhibit the same absorption coefficient as does intrinsic bulk germanium
for α > 100 cm−1 . Thus, a significant band structure modification was not
observed by optical absorption for these C concentrations.
9.3. OPTICAL DEVICES USING SIGE ALLOYS
The main aims of SiGe optoelectronics are: high responsivity, low

noise, fast response and integration with the conventional Si-processing
technology. Most of the reported studies include:
(i) p–i–n diode for 1.3 µm wavelength with 50% internal quantum
efficiency, 200 ps impulse response and 10 pA µm−2 dark current
at 15 V bias [2, 44–46];
(ii) waveguided p–i–n photodetectors with 50% internal quantum
efficiency at 1.3 µm and 200 nA dark current at −15 V in a 10×750 µm
device [25, 47]; and
(iii) a waveguided metal–semiconductor–metal photodiode [48].
A responsivity of 0.2 A W−1 was measured at 1.3 µm over a 1 nm
detector length with a 500 pA µm−2 dark current at 5 V bias. Si1−x Gex
rib waveguide avalanche photodetectors for operation at 1.3 µm and
strained layer superlattice waveguide photodetectors have also been
reported [49–52].
Silicide/Si1−x Gex Schottky diodes have been proposed for detecting
far-infrared radiation, taking advantage of the controllable bandgap of
SiGe. For such diodes, the general requirement is to adjust the parameters
such as the barrier height and ideality factor. PtSi/Si1−x Gex Schottky
photodetectors have been proposed for detection of infrared radiation
of wavelengths up to 10 µm [19]. Xiao et al [53] have demonstrated
Pd2 Si/Si1−x Gex and PtSi/Si1−x Gex Schottky-barrier long-wavelength
infrared detectors The cut-off wavelength is found to be dependent on
the amount of Ge present in the strained layer. Figure 9.7(a) shows the
measured Fowler plots for three Pd2 Si/Si1−x Gex (x = 0, 0.20 and 0.35)
detectors using an FTIR spectrometer at 77 K. As expected, the cut-off
wavelength clearly increases with the increasing Ge fraction, x, for the
Pd2 Si/Si1−x Gex detectors.
The spectral response of a PtSi/Si0.85 Ge0.15 detector is shown in
figure 9.7(b) along with that of a PtSi/Si control device. The cut-off
wavelength is extended from 5.2 to 8.8 µm with only 15% Ge in the alloy,
corresponding to a barrier height reduction of 100 meV. By extrapolation, a
cut-off wavelength beyond 10 µm is expected for a PtSi/Si1−x Gex detector
Figure 9.7. Infrared photoresponse at 77 K of (a) Pd2 Si/Si1−x Gex and (b)
PtSi/Si1−x Gex Schottky barrier detectors. (After Xiao X et al 1993 IEEE
Electron Device Lett. 14 199–201.)
Figure 9.8. Comparison of measured external responsivities of PtSi/Si0.80 Ge0.15

and PtSi/Si infrared detectors. The points represent data obtained with a
calibrated infrared monochromator (40 K), while the lines are scaled results from
FTIR measurements. (After Xiao X et al 1993 IEEE Electron Device Lett. 14
199–201.)
with as little as 18% Ge in the alloy. The measured external responsivities

(40 K) of the PtSi/Si0.85 Ge0.15 detector and the PtSi/Si control device
are shown in figure 9.8. Although the actual measurement was limited
to 4 µm, extrapolated full responsivity curves for the PtSi/Si0.85 Ge0.15
detector showed superior responsivity to the conventional PtSi/Si detector
over the whole wavelength range.
Low-loss waveguides have been proposed using group IV alloy films.
Light can propagate in four types of group IV waveguides: lightly-
doped silicon on heavily-doped silicon [54–57], epitaxial Si1−x Gex on
Si [58–62], silicon-on-sapphire [63] and silicon-on-insulator [64–68]. In
addition to epitaxial SiGe, SiC or SiGeC can be used as waveguide cores.
Crystallographic defects such as threading dislocations need to be kept
below 104 defects/cm2 in order to keep losses below 1 dB cm−1 in silicon-on-
insulator and SiGe/Si waveguides [68]. A loss of 0.5 dB cm−1 for transverse
electric (TE) and 0.6 dB cm−1 for transverse magnetic (TM) modes at
1.32 µm have been reported in chemical vapour deposited Si0.99 Ge0.01 ribs
on Si [60]. The propagation loss in a polarization independent single-mode
rib made from Ge-diffused Si has been found to be 0.3 dB/cm at 1.3 and
Figure 9.9. Schematic view of integrated SiGe/Si planar photodetector with

trench for optical fibre guide. The optical fibre is attached to the trench and the
core of optical fibre is coupled to the photodetector with alignment-free. (After
Tashiro T et al 1997 IEEE Trans. Electron Devices 44 545–50.)
1.55 µm. In a single-mode SOI/SIMOX rib, the reported propagation loss

is about 0.4 dB cm−1 for polarization independent 1.3 and 1.55 µm infrared
radiations [65].
An integrated p–i–n SiGe/Si-superlattice photodetector (as shown in
figure 9.9) with a planar structure has been developed on a bonded silicon-
on-insulator for Si-based optoelectronic integrated circuits [69, 70]. An Si,
30 periods, superlattice absorption layer, a 0.1 µm p-Si buffer layer and a
0.2 p+ –Si contact layer were deposited on a bonded SOI. The bonded SOI is
used to increase the external quantum efficiency, ηext of the photodetector.
Moreover, to achieve simple and stable coupling of an optical fibre to the
photodetector, a 63 µm deep and 128 µm wide trench is formed in the silicon
chip. The p–i–n planar photodetector exhibits a high ηext of 25–29% with
a low dark current of 0.5 pA m−2 and a high-frequency photoresponse of
10.5 GHz (3 dB bandwidth) at a wavelength of 0.98 µm. A vertical-cavity
p–i–n SiGe/Si photodetector in bonded SOI substrate has been reported to
exhibit a high external quantum efficiency of 60% with a low dark current
of 0.5 pA µm−2 and a high photoresponse of 7.8 Gbit s−1 at λ = 980 nm
as shown in figure 9.10.
Light emission has been observed in various structures, such as rare
earth metal-doped Si, strained-SiGe quantum wells, porous-Si, quasi-direct
gap short period SiGe superlattices and Si quantum wires [71,72]. Si1−x Gex
quantum well structures exhibit type I band alignment, where most of the
band offset occurs in the valence band when the Ge concentration is low.
This type of structure allows for only holes to be effectively confined in
Figure 9.10. Frequency response of a photodetector at an area of 5000 µm2 .

A 3 dB bandwidth of 7.8 GHz is confirmed at 5 V reverse bias at λ = 980 nm.
(After Morikawa T et al 1996 IEEE IEDM Tech. Dig. pp 661–4.)
the quantum wells, whereas to form a light emitter, it is necessary to have

an asymmetric type II structure which confines electrons in the conduction
band. Neighbouring confinement structures (NCS) using Si1−x Gex have
been developed [73]. NCS structures consist of a thick (>3 µm) Si0.82 Ge0.18
buffer in which a step-graded Si1−x Gex layer with x ranging from 0 to 0.18
is grown, and then capped with a uniform 2.5 µm Si0.82 Ge0.18 layer. The
NCS structure is then grown on Si0.82 Ge0.18 in which a tensile strained 10 Å
Si-only QW is grown for electron confinement, and a 10 Å Si0.64 Ge0.36 QW
is grown for hole confinement. This structure allows for a nearly ‘direct’
transition as evidenced by orders of magnitude enhancement of no-phonon
low-temperature PL, as compared to SiGe QWs using type I and symmetric
type II QWs. The NCS technique, when coupled with growth on relaxed-
SiGe buffers, is a promising approach in the production of Si-based light
emitters [71].
Some reports on Si1−x Gex /Si quantum well infrared photodetectors
(QWIP) have appeared [1, 74]. An integrated waveguide photodetector, as
shown in figure 9.11, deposited on a SIMOX substrate, has been fabricated
and an external quantum efficiency of 11% with an impulse response time
of 400 ps has been observed. For the mid-IR range (3–5 µm) highly p-doped
Figure 9.11. Schematic layout of a waveguide/detector device on a SIMOX

substrate. (After Presting H 1998 Thin Solid Films 321 186–95.)
Si/SiGe QW detectors have been deposited on an undoped, double-sided

polished Si substrate based on hetero-internal photoemission (HIP) over
the Si/SiGe barrier. The absorption and photocurrent spectra have been
measured from fabricated mesa detectors at 77 K. The photoresponse
spectrum of the HIP detectors is found to be widely tunable in the
technological important wavelength band of 3–5 µm by choice of Ge
content, well thickness and doping level. Quantum efficiencies of 1% at
4 µm and 77 K have been achieved from SiGe HIP structures, dark currents
as low as 10 × 10−8 A cm−2 can be obtained by modulation doping.
The key features of a p-Si1−x Gex /Si QWIP are shown in figure 9.12.
The alloy layers are grown pseudomorphically on an Si substrate, and are
compressively strained. The alloy bandgap is smaller than that of Si for a
fully strained layer [75]. The higher density of states in SiGe subbands
suggests that SiGe QWIPs are inherently superior to AlGaAs QWIPs.
Valence band technology is preferred for 8–14 µm SiGe/Si QWIPs because
it allows normal incidence of light on the detectors. The polarization of
normal light is always perpendicular to the growth direction of the QW
layers. Although low noise and good responsivity have been realized, a
Figure 9.12. Energy band diagram showing the shift of the absorption edges in a
symmetrically strained-Si1−x Gex /Si multiple quantum wells (MQWs). Electrons
are confined in the wider bandgap of Si layers and holes are confined in the
narrower bandgap of Si1−x Gex layers. E1 and HH1 are the minimum electron
and hole energy levels in the quantum wells. L is the width of the quantum well.
long length in the waveguided diode is needed due to a low absorption

coefficient. This long length tends to raise the parasitic capacitance of the
distributed diodes. It becomes difficult to obtain better responsivity at
higher wavelengths as the stability of strained-SiGe QWs decreases rapidly
as the Ge fraction increases.
Photocurrent and absorption characteristics of SiGe QWs and Sim Gen
SLS have been measured at room temperature by Presting [1]. The
wavelength-dependent photocurrent spectrum has been measured using a
grating monochromator illuminated by a tungsten lamp, and the electrical
signal has been detected by a lock-in amplifier technique. When comparing
the absorption characteristics of the SLS and QW structures, it is evident
that substantial absorption at 1.3 µm occurs for both structures. The
different long wavelength absorption limits between the two were explained
Figure 9.13. Circuit diagram of a SiGe–Si p–i–n HBT photoreceiver. (After

Rieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)
by taking into account the different buffer layer thicknesses and Ge content
in the structures.
A monolithic SiGe/Si p–i–n HBT front-end transimpedance
photoreceiver circuit, as shown in figure 9.13, has been fabricated by Rieh et
al [76]. Figure 9.13 shows the circuit diagram with a transimpedance
amplifier which consists of a photodiode, common-emitter gain stages, two
emitter follower buffers and a resistive feedback loop. For fabrication, a
mesa-type SiGe/Si p–i–n HBT technology was used. Fabricated HBTs
showed an fmax of 34 GHz with dc gain of 25. SiGe/Si p–i–n photodiodes,
which share base and collector layers of HBTs, demonstrated a responsivity
of 0.3 A W−1 at λ = 850 nm (incident optical power of 22 mW) at
a reverse bias of 5 V, and steadily increased as the reverse bias was
increased. The corresponding external quantum efficiency was 43%. The
bandwidth of the photodiode was about 450 MHz (see figure 9.14(a)).
The frequency response of the monolithically integrated single-feedback
p–i–n HBT photoreceiver, excited with λ = 850 nm light, is shown in
figure 9.14(b) and exhibited a bandwidth of about 460 MHz, which is
limited by the bandwidth of p–i–n photodiode.
The integration of Ge photodetectors on silicon substrates is
also advantageous for various Si-based optoelectronics applications [77].
Figure 9.15 shows the schematic diagram of an integrated p–n mesa
Figure 9.14. (a) Measured frequency response of the SiGe p–i–n photodiode
and (b) measured frequency response of the SiGe photoreceiver. The solid curves
show the fit to the measured response. (After Rieh J-S et al 1997 IEEE Photonics
Technol. Lett. 10 415–7.)
Figure 9.15. A schematic diagram showing the optimized relaxed graded buffer
growth sequence with the Ge mesa photodiode on top. (After Samavedam S B et
al 1998 Appl. Phys. Lett. 73 2125–7.)
photodiode. Integrated mesa Ge photodiodes on an optimized graded

relaxed-SiGe buffer on Si showed a very low dark current of 0.15 mA cm−2 .
Capacitance measurements indicate that the detectors are capable of
operating at high frequencies (2.35 GHz). The photodiodes showed an
external quantum efficiency of 12.6% at 1.3 µm wavelength laser excitation
in the photodiodes.
9.4. OPTICAL DEVICES WITH SIGEC AND GEC ALLOYS
Conventional Si Schottky photodiodes and MSM photodetectors operate

at wavelengths in the UV and visible region (<700 nm) of the spectrum
[78, 79]. Si photodetectors operating at an 830 nm wavelength have been
reported [80]. Normal incidence strained or relaxed SiGe and SiGeC
p–i–n photodiodes have been studied by several researchers [46, 81, 82].
Although these devices used a thin intrinsic layer of 800–4000 Å, the
Optical devices with SiGeC and GeC alloys 335
external quantum efficiencies were less than 1%. These results show that
Ge-rich SiGeC diodes have a higher photoresponse to 1.3 µm excitation
than Si-rich SiGeC diodes, because of the narrower bandgap of Ge-rich
SiGeC, and hence the larger absorption coefficient at a 1.3 µm wavelength.
It was observed that the C blueshifted the photoresponse edge from the
spectral response, suggesting that carbon increased the bandgap of the Ge-
rich SiGeC alloys. This is consistent with the decrease of quantum efficiency
with the increase of carbon composition in p-GeC/n-Si photodiodes, which
agrees with the absorption studies [43]. However, SiGe and/or SiGeC MSM
photodiodes operating in the near-infrared or infrared wavelength region
have not yet been explored.
p–n heterojunction photodiodes on epitaxial p-type Ge1−x Cx films
with carbon percentages of 0.2, 0.8, 1.4 and 2% on n-Si substrates
have also been studied. Photoresponse characteristics of the diodes are
shown in figure 9.16. The photocurrents of the p-Ge0.992 C0.008 /n-Si, p-
Ge0.986 C0.014 /n-Si, and p-Ge0.98 C0.02 /n-Si photodiodes under an applied
reverse bias of −20 V are 4.4, 4.0 and 2.6 µA, respectively, corresponding
to external quantum efficiencies of 2.2%, 2% and 1.3%, respectively, for an
incident power of 192 µW. The measured external quantum efficiencies at
λ = 1.3 µm for different diodes are shown in figure 9.17. For the purposes
of ηext comparison, data of a p–i–n diode using SiGeC films are shown.
Figure 9.16. The photoresponsivity of p-type Ge0.992 C0.008 , p-type

Ge0.986 C0.014 and p-type Ge0.98 C0.02 on n-Si photodiodes. (After Shao X 1997
Structural and electrical characterization of SiGeC and GeC alloys and their
application to optical detectors PhD Dissertation University of Delaware.)
Figure 9.17. The measured external quantum efficiency at λ = 1.3 µm

for the p-Ge1−x Cx /n-Si photodiodes and compared to a SiGeC p–i–n diode.
(After Shao X 1997 Structural and electrical characterization of SiGeC and GeC
alloys and their application to optical detectors PhD Dissertation University of
Delaware.)
9.5. SIMULATION OF OPTOELECTRONIC DEVICES
For the design and simulation of photodetectors, an understanding of

the behaviour of photogenerated carriers under the influence of drift and
diffusion is essential. The basic semiconductor equations, namely Poisson’s
and current continuity equations for electrons and holes, are solved, along
with a rate equation for the charged traps. Additionally, the optical
generation term Gopt and recombination term Ropt are incorporated in
the current continuity equations.
A general purpose two-dimensional drift–diffusion simulator, SEMICAD,
capable of simulating a wide range of semiconductor devices, has been used
for simulation purposes. Important optical parameters, namely the absorp-
tion coefficient and refractive indices, were supplied. Several additional
mechanisms particularly applicable to optoelectronic devices are incorpo-
rated. These comprise:
(i) dynamic capture and emission of carriers by multiple trap levels of

bulk and surface traps;
(ii) carrier generation due to light or other ionizing radiation; and
(iii) quantum-mechanical tunnelling between traps.
Simulation of optoelectronic devices 337
The performance of a photodetector depends on the material

parameters, device structure and configuration, thickness of different layers,
doping levels, ohmic contact at electrode boundaries and anti-reflection
coating. The selected material should have a high absorption coefficient
at wavelengths of interest, high carrier mobility, direct bandgap and the
possibility to tailor the bandgap for high quantum efficiency and wide
bandwidth.
Besides the material selection, other important issues include:
(i) reduction of surface reflection loss by using a transparent anti-
reflective coating on the incident surface;
(ii) for high detection efficiency, absorption at the depletion layer should
be large by increasing the depletion width;
(iii) to improve the efficiency and noise performance, generation
recombination of the carriers in the depletion region should be small;
(iv) to minimize the transit time, depletion width should be narrow; and
(v) to reduce the capacitance, detector area should be small.
Clearly an element of design trade-off is necessary to balance
these somewhat conflicting requirements. In addition to the above
considerations, the device time response is controlled by the external circuit
components. For a good frequency response, both the capacitance and
resistance need to be minimized, by reduction in area. However, if the
depletion width is increased too much, the device is limited by the transit
time effects. The transit time, ttr is controlled by the width of depletion
region and the saturation velocity, vs of the carriers, and is given by
W
ttr = . (9.12)
vs
For a high-frequency response, optimization of the depletion width is
necessary. In simulation, the basic semiconductor equations—Poisson’s,
the current continuity equations for electrons and holes and a rate
equation for the charged traps—need to be solved for the determination
of electrostatic potential and total carrier concentration in the structure.
These have been discussed in detail in chapter 4. Additionally, an
optical generation term Gopt and the recombination term Ropt must
be incorporated in the continuity equations for the analysis of p–i–n
photodetectors. Two of the three recombination mechanisms, Shockley–
Read–Hall (SRH) and Auger recombination, have been considered in
chapter 4. The additional optical recombination rate term in the current
continuity equations due to the creation of photons is given by

Ropt = Ccopt np − n2io (9.13)
where Ccopt is the optical capture rate.

The rate of carrier generation due to photon absorption is calculated

from the rate of decay of the photon flux. For a spatially uniform absorption
coefficient, the photon flux, φopt decreases exponentially with distance as
φ = φopt exp (−αy) . (9.14)
The initial photon flux can be calculated from the incident optical power
density and from the wavelength as
Popt
φopt = (9.15)
hν
where h is Planck’s constant and ν is the optical frequency.
The generation rate of photo carriers can be expressed as
dφ
Gopt = − = αφ (9.16)
dy
where dy is the differential distance along the direction of propagation of the
incident beam and α is the absorption coefficient. The quantum efficiency, η
is calculated from the equivalent beam current at unity quantum efficiency
[83] and is given by
Ia
η= (9.17)
Ieq
where Ia is the p–i–n diode terminal current and Ieq is the equivalent
beam current at unity quantum efficiency. The responsivity is the ratio of
photocurrent and incident optical power and is obtained from the external
quantum efficiency. The diode capacitance can be computed from small-
signal ac analysis using y-parameters in a similar manner to that described
in chapter 4.
9.5.1. PtSi/SiGe Schottky photodetectors

In this section, we compare the performance of a PtSi/Si1−x Gex Schottky
diode with that of a PtSi/Si Schottky diode. The structure considered
for simulation is a cylindrical Schottky diode of 1 µm radius. The top
Si1−x Gex epitaxial layer is grown on a graded Si1−y Gey (y : 0 → x) layer.
The graded layer prevents the formation of a parasitic hole barrier at the
substrate/Si1−x Gex interface. The thicknesses of both graded and epitaxial
layers are 500 Å. An ohmic contact has been taken from the back side of
the photodetector. The power of the incident beam normal to the front
side of the diode has been taken to be 10 µW.
Figure 9.18 shows the simulated photoresponse characteristics of a
PtSi–Si1−x Gex Schottky diode with that of a PtSi/Si Schottky diode of
identical geometry, in the wavelength range of 2–8 µm. It is seen from
figure 9.18 that the maximum value of responsivity in the wavelength range
Figure 9.18. Simulated photoresponse of PtSi/Si1−x Gex and PtSi/Si infrared

Schottky photodetectors. (After Chattopadhyay S and Maiti C K, unpublished
data.)
considered here is 0.106 A W−1 , and in the 8 µm wavelength region the

diode has a responsivity of approximately 0.032 A W−1 . For comparison,
the spectral response of a PtSi/Si Schottky diode has also been simulated.
It is seen from figure 9.18 that a PtSi/Si1−x Gex Schottky diode has a higher
responsivity than a PtSi/Si Schottky diode. Above a wavelength of 5 µm,
the responsivity of the PtSi/Si Schottky diode is negligible. The cut-off
wavelength of PtSi/Si1−x Gex is also higher than that of a PtSi/Si Schottky
diode. This is expected as the PtSi/Si1−x Gex diode has a lower barrier
height. The reduction of barrier height of the PtSi/Si1−x Gex Schottky
diode is responsible for the detection of a longer wavelength.
It is also evident in figure 9.18 that the computed results agree well
with the reported experimental results for a similar structure [53]. Also, the
simulated responsivity is comparable to the highest reported responsivities
found in Si/Si1−x Gex hetero-internal photodetectors [84, 85].
Figure 9.19. (a) Schematic structure of Si0.7 Ge0.3 p–i–n diode; (b) computed
band diagram; (c) doping profile; (d) electric field; and (e) optical generation.
(After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)
Figure 9.20. p+ –Si–n− (SiGe)–n− (SiGe) photodiode structure. (After Lee J et

al 1995 Appl. Phys. Lett. 66 204–5.)
Figure 9.21. Dark current versus reverse voltage characteristics of Si1−x Gex
p–i–n photodiodes: (a) x = 0; (b) x = 0.2; (c) x = 0.3. (After Chattopadhyay S et
al 1999 Solid-State Electron. 43 1741–5.)
9.5.2. SiGe p–i–n photodetectors
A schematic structure of a SiGe p–i–n photodiode considered for simulation

is shown in figure 9.19(a). The diode has a Si1−x Gex cylindrical-shaped
intrinsic layer typically 1–3 µm thick on an n+ –Si substrate. The top and
bottom surfaces have radii of 70 µm and 90 µm, respectively, with an
average area of 2 µm × 104 µm. Electrical contacts are taken from the top
and bottom surfaces [86]. The structure shown in figure 9.20 was considered
for simulation as there are reliable experimental data for a similar structure
[87,88]. At a reverse bias of 5 V, the computed energy band diagram for an
Si1−x Gex (x = 0.30) photodiode is shown in figure 9.19(b). Figures 9.19(c)
and (d) show the doping concentration and electrical field across the diode,
respectively. The optical carrier generation in the photodiode is shown in
figure 9.19(e).
Figure 9.22. Computed spectral response of Si1−x Gex p–i–n photodiodes for:
(a) x = 0; (b) x = 0.1; (c) x = 0.2; (d) x = 0.3; (e) x = 0.5; (f ) x = 0.75. (After
Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)
Figure 9.21 shows the dark currents in three photodiodes (Si, Si0.8 Ge0.2
and Si0.7 Ge0.3 ) of identical geometry with a 1 µm thick intrinsic layer. It
is seen from figure 9.21 that the dark current increases as the Ge mole
fraction is increased. This is attributed to the decrease of bandgap due to
the increase in Ge content in the intrinsic layer. For a 30% Ge content in
the i-layer, the value of the dark current is in the nA range and saturates
at a reverse bias of about 3 V or above.
Figure 9.22 shows the computed responsivities of Si1−x Gex
photodiodes of different Ge concentrations (x = 0.0, 0.1, 0.2, 0.3, 0.5 and
0.75) as a function of wavelength (0.6–1.5 µm). It is seen from figure 9.22
that the cut-off wavelength of the photoresponse curves increases as Ge
content in the absorbing i-layer increases. It is observed that the cut-off
wavelengths for x = 0.0 (i.e., for Si) and for x = 0.75 are about 1.10 µm
and 1.50 µm, respectively. This is due to the fact that, as the Ge content
Figure 9.23. Simulated photoresponse of an Si1−x Gex p–i–n photodiode for:

(a) x = 0.1 and (b) x = 0.3. (- - - -) computed and (——) experimental. (After
Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)
is increased in the i-layer, the bandgap decreases which in turn extends the
absorption tail towards the higher wavelength region.
The reported experimental value of the photoresponse for Si1−x Gex
p–i–n photodiodes (x = 0.08–0.69) in this wavelength range is about
0.4–0.5 A W−1 [87, 88] and is compared with simulation results in
figure 9.23 for x = 0.1 and 0.3. The agreement is found to be very
good. Photoresponse characteristics of a constant Ge content (x = 0.30)
photodiode as a function of i-layer thickness (1.0, 1.5, 2.0 and 2.5 µm) are
shown in figure 9.24 in the wavelength range of 0.6–1.4 µm. It is seen that,
for a particular wavelength of the incident photon, responsivity increases
with the thickness of i-layer. This is obvious because as the i-layer thickness
increases, more incident photons get absorbed in the thicker i-layer region
which in turn generates more photo-carriers.
Figure 9.24. Plot of photoresponse versus wavelength of an Si0.7 Ge0.3 p–i–n

diode for different i-layer thicknesses. (After Chattopadhyay S et al 1999
Solid-State Electron. 43 1741–5.)
Figure 9.25 shows the variation of the reverse capacitance of a 30% Ge

content photodiode as a function of i-layer thickness. The capacitance
decreases with the increase in i-layer thickness at a particular reverse
bias. Figure 9.26 shows the variation of computed dark capacitance of
an Si1−x Gex p–i–n photodiode having a 1 µm i-layer thickness for different
Ge mole fractions (x = 0.10, 0.20 and 0.30). It is seen that for a particular
i-layer thickness, the dark capacitance increases as the Ge content in the
i-layer increases, as expected. The capacitance of a p–i–n diode is basically
the depletion capacitance and it is clear from figure 9.26 that above 1 V
reverse bias, the diode has a capacitance in the range 2.3–2.5 pF. Such a low
value of depletion capacitance is essential for ultra high-speed applications.
Figure 9.25. Variation of capacitance with applied reverse bias of an Si0.7 Ge0.3
p–i–n diode for: (a) W = 1.0 µm; (b) W = 1.2 µm; (c) W = 1.5 µm and
(d) W = 2.0 µm. (After Chattopadhyay S et al 1999 Solid-State Electron. 43
1741–5.)
9.5.3. MSM photodetectors
The schematic view of an interdigitated MSM photodiode considered

for simulation is shown in figure 9.1(a). Due to the symmetry of the
structure of the MSM photodiode, the region chosen for analysis is shown
in figure 9.1(b). Spacing between the positive electrode (anode) and the
grounded electrode (cathode) is 2 µm and the finger widths are taken
to be 1.5 µm. The responsivity and other important parameters of a
representative unit cell of the device, in which the illumination is uniform,
have been simulated. The responsivity has been calculated assuming
the beam to be centred within the unit cell and the metallic fingers are
completely transparent.
Figure 9.26. Variation of capacitance with applied reverse bias of an Si1−x Gex
p–i–n diode for: (a) x = 0.1; (b) x = 0.2 and (c) x = 0.3. (After
Chattopadhyay S et al Solid-State Electron. 43 1741–5.)
Metal fingers on the surface of MSM photodetectors form a Schottky

barrier between the metal and semiconductor and therefore there will be a
voltage-dependent depletion region beneath the metal fingers. Figure 9.27
shows the computed depletion layer capacitance as a function of bias
voltage for Si and Si0.80 Ge0.20 MSM photodetectors. An active area of
500 × 500 µm of the photodetector was considered. The capacitance values
computed at 1 MHz for both detectors show an increase in depletion
capacitance with increasing bias voltage, due to the fact that the absorption
length exceeds the depletion layer width. At high bias voltage, the
dependence of capacitance on voltage is weak. As seen from figure 9.27, the
variation of capacitance with voltage of Si0.80 Ge0.20 MSM photodetector
is similar to that of Si MSM-PDs. Si0.80 Ge0.20 MSM photodetectors show
a slightly higher capacitance because of the higher dielectric constant of
Si0.80 Ge0.20 .
Figure 9.27. Computed capacitance versus applied voltage for (a) Si and (b)
Si0.80 Ge0.20 MSM photodetectors. Detectors have an active area of 500 × 500 µm
with 1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S and
Maiti C K, unpublished data.)
Computed dark and photo currents for Si, Si0.80 Ge0.20 and Si0.70 Ge0.30
MSM-PDs are shown in figure 9.28. The dark current I–V characteristics
are typical for a back-to-back Schottky contact. The Si0.80 Ge0.20 MSM-PDs
have higher dark current compared to Si, increasing with the increase in
Ge concentration in the Si1−x Gex epitaxial layer. Si has a dark current of
15 µA at 8 V and Si1−x Gex has a dark current of 60 µA (x = 0.2) and
95 µA (x = 0.3) at 6 V.
Figure 9.29 shows the plot of computed responsivities of an Si
MSM-PD in the wavelength range 0.4–1.20 µm for different voltages (1, 3
and 5 V). An active area of 500 Kc ×500 µm, a finger spacing of 2 µm and
a finger width of 1.5 µm were simulated. It is seen that the photoresponses
are strongly dependent on applied reverse bias. It is expected that the
cut-off wavelength of an Si MSM-PD will correspond to its bandgap energy.
Figure 9.30 shows the plot of computed responsivities of an Si1−x Gex MSM-
PD in the wavelength range 0.4–1.40 µm, for different values of x (0.10, 0.20
and 0.30) at 3 V. As shown in figure 9.30, the responsivity drops rapidly
Figure 9.28. Dark and photo currents versus applied voltage of Si and Si1−x Gex
MSM photodetectors. The detectors have an active area of 500 × 500 µm with
1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S and
Maiti C K, unpublished data.)
as photon energy decreases close to bandgap energy, while at a particular

wavelength responsivity increases with increasing Ge content.
Figure 9.31 shows the variation of computed responsivity with
wavelength for different finger widths and spacings. Curve a shows the
responsivity of an Si0.8 Ge0.2 MSM photodiode for a finger width of 1.5 µm
and spacing 2 µm while curve b shows the responsivity a for finger width
and spacing of 2 µm and 1 µm, respectively. From curves a and b, one
notices that the responsivity does not change much. Curve c shows the
responsivity of an MSM-PD with the same Ge content but the finger
width and spacing were 2 µm and 1 µm, respectively. We see that the
responsivity has increased significantly. This is due to the increase of the
active area, which in turn increases the depletion area underneath the metal
Figure 9.29. Plots of responsivity versus wavelength of an Si MSM

photodetector at different voltages. The area of the detector is 500 × 500 µm
with a finger width of 1.5 µm and a spacing of 2 µm. (After Chattopadhyay S
and Maiti C K, unpublished data.)
fingers. Figure 9.32 shows the responsivity variation of an Si0.8 Ge0.2 MSM-
PD with different thicknesses of top absorbing layer. It is seen that the
responsivity increases as the top absorbing layer thickness under the metal
fingers increases. This is expected because a thicker layer will absorb more
photons, which in turn increases the photocurrents.
The Si1−x Gex MSM-PDs have a dark current which increases with the
increase in Ge concentration. Si has a dark current of 10 µA at 6 V and
Si1−x Gex has dark currents of 60 µA (x = 0.2) and 90 µA (x = 0.3, not
shown in figure 9.32) at 6 V. Si MSM-PDs have a peak photoresponsivity
of 0.60 A W−1 at 0.72 µm at an applied voltage 5 V. Si0.80 Ge0.20 PDs
have peak responsivities of 0.76 A W−1 at 0.80 µm at an applied voltage
of 3 V while Si0.70 Ge0.30 MSM-PDs have the responsivity of 0.88 A W−1
Figure 9.30. Plot of responsivity versus wavelength of an Si1−x Gex MSM

photodiode at 1 V for different Ge mole fractions: (a) x = 0.1; (b) x = 0.2;
(c) x = 0.3. The area of the diode is 500 × 500 µm with finger width and spacing
of 1.5 µm and 2 µm, respectively. (After Chattopadhyay S and Maiti C K,
unpublished data.)
at the same conditions. Si PDs have a cut-off wavelength of 1.10 µm which

corresponds to its bandgap energy. The cut-off wavelength of SiGe PDs
varies with Ge mole fraction. For a 30% Ge content, the cut-off wavelength
is about 1.3 µm.
9.5.4. SiGe/Si waveguide photodetectors
The influence of various design parameters in determining the external

quantum efficiency of waveguide detectors based on Si/Si1−x Gex /Si
strained layer superlattices, for use in optical communications at λ =
1.3 µm has been studied in detail by Naval et al [89]. The authors have
presented an algorithm that automatically generates structurally stable
Figure 9.31. Photoresponse characteristics of an Si0.80 Ge0.20 MSM-PD for

different geometry: (a) W = 1.5 µm, S = 2.0 µm; (b) W = 2.0 µm, S = 1.0 µm;
(c) W = 2.0 µm, S = 2.0 µm, with an active area of 500 × 500 µm. (After
Chattopadhyay S and Maiti C K, unpublished data.)
SLS. The simulation includes various design parameters such as optical

waveguiding, absorption, quantum size effect as well as thermodynamics
of the strained layers. A conservative model for the critical thickness, hc ,
corresponding to the equilibrium regime has been shown to be important
for relatively high Ge content, necessary to achieve moderate efficiency.
Limiting the superlattice thickness and detector length to 1 µm and 1 mm,
respectively, yielded discrete maximum values for ηext (around 12%) and
ηint (around 30%) that were mainly dependent on the alloy absorption.
A more optimistic model for hc , corresponding to the metastable regime,
produced considerably higher ηext (around 60%), which shows the great
importance of fibre-to-waveguide coupling efficiency. The importance of
the passive waveguide coupler geometry was investigated using the beam
propagation method.
Figure 9.32. Photoresponse characteristics of an Si0.80 Ge0.20 MSM photodiode

for different absorbing layer thicknesses at 1 V applied bias. (After
Chattopadhyay S and Maiti C K, unpublished data.)
9.6. SUMMARY
The highly-developed Si technology makes SiGe and other group IV alloys,

ideal materials for realizing optical devices in the near-IR as well as
in the mid- to far-IR regime, monolithically integrated with electronic
driver circuits for optical communication systems. In this chapter, recent
developments and the possible applications of group IV (SiGe, GeC, SiGeC,
SiGeSnC and strained-Si) alloys in optoelectronics for integrated circuits
entirely on silicon have been discussed. Photoresponsivity and refractive
index data obtained from experimental SiGe, SiGeC and GeC photodiodes
were presented. Simulation results, obtained using a 2D heterostructure
device simulator, for PtSi/Si1−x Gex and PtSi/Si Schottky photodetectors
in the wavelength range of 2–8 µm, have been presented. It was found
Bibliography 353
that the PtSi/Si1−x Gex photodetectors offer superior responsivity and

higher cut-off wavelength compared to conventional PtSi/Si Schottky
photodetectors. Simulation results compare favourably with reported
experimental results.
Responsivity, dark current and cut-off wavelength of an Si1−x Gex
p–i–n photodetector increase with increasing Ge mole fraction in the
absorbing i-layer and cover a wavelength range of 1.10–1.50 µm as the Ge
mole fraction increases from 0.0 to 0.75. Simulated high responsivity, low
dark current (in the range of nA) and low capacitance suggest that these
detectors are good candidates for infrared light detection in the wavelength
range of 1.30–1.50 µm. The photoresponse of Si1−x Gex MSM-PDs has
been found to increase with increasing Ge mole fraction. However, the
dark current of a SiGe detector is higher than that of an Si photodetector.
Due to lack of experimental data, no comparison could be made for SiGe
MSM-PDs. It was also observed that the responsivity increases with the
increase of the absorption layer thickness underneath the metal fingers.
However, the main hindrance for a total Si-based integrated optic solution
is the lack of a sufficiently intense Si-based transmitter at 1.3 µm.
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Chapter 10
RF APPLICATIONS OF SIGE
HBTS
The revolution in wireless communications has been brought about by

the recent advances made in the areas of digital integrated circuits, radio
frequency components and circuits, digital communications and networking
techniques. Mobile communication is now the fastest growing consumer
electronics segment in all parts of the world. Digital services, internet
and multimedia are all becoming mobile. The last few years have seen
a remarkable expansion in the use of cellular and cordless phones and
other personal communication systems and, as a result, the demand for
transceivers with small size, fewer off-chip components, better integration
and low operating voltage has increased dramatically. According to the
market research firm Dataquest, the production of wireless devices is
expected to grow to over 450 million units annually by the year 2002. The
opportunity for chips that process radio frequency signals alone is expected
to reach $7 billion by 2002. A recent US Department of Commerce report
indicates that global positioning satellite (GPS) equipment sales will reach
$16 billion in 2003.
RF communication systems can be broadly classified into two sectors,
namely ‘low-end’, such as pagers, cordless phones etc, and ‘high-end’,
such as PCS, GSM, IS-136 etc. DECT (digital enhanced cordless
telecommunications) is also an acknowledged standard in many countries
all over the world, replacing conventional analogue systems for wired
and cordless telephones. DECT holds substantial promise for residential
cordless, wireless PBX and wireless local loop (WLL) applications. This
high-performance micro-cellular technology is a particularly attractive
WLL alternative in areas where laying a wired infrastructure poses
problems, or in urban areas where traditional cordless telephones are
overburdened. The DECT standard specifies that communications will
be done in a frequency band with a bandwidth of 17 MHz centred at
359
360 RF applications of SiGe HBTs
Table 10.1. Comparison of wireless communications standards.

Frequency Channel Maximum user Power
Standard System band BW/SP average peak
GSM Cellular 900 MHz 200 kHz 250 mW 2W
AMPS Cellular 800 MHz 30 kHz 600 mW 600 mW
PACS PCS-TAG-3 1.9 GHz 300 kHz 25 mW 200 mW
PCS-1900 PCS-TAG-5 1.9 GHz 200 kHz 125 mW 1W
IS-136 PCS-TAG-4 1.9 GHz 30 kHz 200 mW 600 mW
approximately 1.89 GHz, making it a narrowband communications system

which requires a peak output power of 250 mW.
In the United States and Canada, the 902–928 MHz ISM (industrial–
scientific–medical) frequency band has been established as a licence-free
spectrum, for use by low-power communication devices such as cordless
telephones. The ISM standard specifies operation from 902–928 MHz
and 1 mW transmitted power. Table 10.1 summarizes the specifications
for some of the wireless communications systems presently in use. It is
clear that a variety of frequencies, modulation schemes and output power
requirements have proliferated on a worldwide basis, and that no one single
standard or frequency can be expected to dominate wireless data systems
for the foreseeable future. Instead, in order to address a broad market,
radio transceivers must increasingly satisfy the competing constraints of
flexibility and low cost [1].
Present wireless communication systems, in the frequency range
0.8–2.5 GHz, will require integrated low-noise front-end circuits, active
filters, wideband AGC amplifiers, AD/DA converters, mixers, synthesizers
with voltage controlled oscillators and power amplifiers. The circuits are
battery operated and must function at relatively high currents and low
voltages. While integration in the baseband has been pursued relentlessly
resulting in very high density circuits, attention has only recently been
focused on radio frequency integrated circuits (RFICs) for communication.
The standard transceiver architecture for most wireless systems has
so far been based on the superheterodyne principle since its initial
development by E Armstrong in the early 1900s. In this configuration, the
radio signal received at the receiving antenna is sent to a low-noise amplifier
(LNA), whose purpose is to boost the signal level without reducing
the signal-to-noise ratio significantly. Following the LNA, the signal is
passed through a mixer, which essentially multiplies the input signal by a
local oscillator signal of constant frequency, producing an output signal,
whose frequency is the difference between the two inputs, the so-called
RF applications of SiGe HBTs 361
‘intermediate frequency’ (IF), the amplitude of which is proportional to the

original input signal. Preceding the mixer, an analogue filter eliminates
the response to an undesired input signal at (2flo –frf ) that would also
downconvert to the intermediate frequency. This ‘image reject’ filter is
typically implemented with a physically large surface acoustic wave (SAW)
filter.
The basic limitation of the traditional frequency translating mixers
and the heterodyne architecture is their sensitivity to ‘spurious responses’
resulting from nonlinearities in the preceding amplifier and mixer. In
highly integrated transceivers, one may allow these filters to be dispensed
with, significantly reducing the power dissipation and the physical size.
The spurious responses must be carefully controlled through bulky and
expensive off-chip filters which are not suitable for monolithic integration,
the key to lower power operation.
Significant improvements in the area of receiver architecture have
been made recently by the use of quadrature signal processing techniques,
also known as the Hartley phasing method and ‘direct downconversion’
or homodyne approaches for wireless receivers, which eliminate the
need for image rejection filters and are better suited to monolithic
integration. However, the direct conversion receiver has not gained
widespread acceptance due to its intrinsic sensitivity to dc offset problems,
even order harmonics of the input signal that interfere with the desired
signal, and local oscillator leakage problems back to the antenna which
are being actively pursued by several research groups. Several excellent
reviews of research in this field are presented in [2, 3]. Rudell et al [4]
have reported an interesting variation in the superheterodyne/homodyne
receiver architecture using the wide band IF double conversion technique.
Field-effect transistors in III–V semiconductors have so far been the
workhorse of the microwave industry because of their excellent high-
frequency performance and, with the introduction of heterojunction FETs,
low noise figures. The integration of highly complex digital circuits on
GaAs is often prohibitive because of cost, limited wafer sizes, processing
complexities and poor yield. A current solution to this problem is to mix
GaAs and Si technologies using a multichip module (MCM) platform. But
GaAs monolithic microwave integrated circuits (MMICs) are expensive and
there are difficulties associated with high pin count flip-chip solder bonding.
Silicon, although not traditionally the material of choice for RF
and microwave applications, has become a serious challenger to other
semiconductor technologies for high-frequency applications. Passive
microwave components have been demonstrated on high resistivity silicon
substrates. Arnold and Pedder [5] reported transmission lines and spiral
inductors working at microwave frequencies on high resistivity substrates.
Fine-line electron beam and photolithographic techniques are now capable
of fabricating geometries as small as 0.1 µm while high resistivity silicon
wafers support low loss microwave transmission lines.

An integrated Si-based MMIC technology circumvents some of the
difficulties encountered in III–V material systems, offers improved thermal
management by virtue of a higher thermal conductivity, and the design
capabilities of CMOS for complex logic circuits and more compact modules.
All-Si MMIC technologies have been investigated previously. Hanes et al [6]
have reported such a technology, based on the SIMOX process with high
resistivity substrates, and obtained a maximum frequency of oscillation of
32 GHz.
Evidence from the literature suggests that the impedance of a high
resistivity (104 Ω cm−1 ) Si substrate will allow microwave/millimetre
wave operation, although it is anticipated to be a more difficult design
consideration than the GaAs MMICs. Surface pinning, which is a feature
of GaAs, does not occur in Si which may offer some advantage in terms of
reducing parasitic capacitances.
These advances, coupled with SiGe, open the possibility of silicon
integrated circuits (ICs) with the speed required for increasingly higher-
frequency applications. Manufacturing costs are the key to SiGe success,
which are about one fifth of the costs of GaAs for equivalent performance
[7]. Applying SiGe does not mean using a completely new process as the
technology and manufacturing are very similar to well-proven methods, but
have considerably extended features.
A complete RF transceiver (see figure 10.1), including VCO and
synthesizer, has been integrated on one chip. A second IC, implemented
Figure 10.1. A schematic diagram of an RF transceiver including SiGe

front-end. (After Bopp M et al 1999 IEEE ISSCC Tech. Dig. pp 68–9.)
SiGe: perspective for wireless communication 363
in SiGe technology, includes an LNA in the receive path as well as a power

amplifier for the transmit path and a driver for an external PIN diode
switch [8].
The circuit configurations for the LNA, oscillator, mixer and the
devices selected must be such as to ensure low power and low noise. Since in
a portable wireless environment all circuits are drawing power from a small
battery, it is clear that one of the most important aspects of the circuits
that needs to be optimized is power consumption. Additionally, since these
devices must be used in a low-cost product, the cost of the circuits must
be lowered as well.
High-quality microwave switches are a key building block of
communication systems as they perform the crucial task of switching
between the transmit and receive modes. Microwave switches are
commonly realized with high-quality p–i–n diodes. However, the large
control currents required by these devices have traditionally necessitated
the use of GaAs FET-based switches for most hand-held applications, due
to their low dc power consumption [9]. In contrast, a SiGe switch designed
to be part of a transceiver front-end for DECT and DCS-1800 applications,
requires no external dc bias and gives 25 dB receiver insertion loss at the
operating frequency, with 25 dB isolation [10].
Discrete passive components dominate in the RF part. More
than 90% of all components are passive, and roughly 70% of the cost
comes from these. The level of integration is increasing, but the
most space consuming components—filters, resonators, matching circuitry,
oscillators—are difficult to integrate. Capacitors, resistors and inductors
are needed for biasing, bypassing, and interference filtering. The use of
integrated spiral inductors in many RF applications can reduce the number
of external elements and, by using the appropriate design technique, the
overall noise behaviour of the circuit is minimized.
10.1. SIGE: PERSPECTIVE FOR WIRELESS COMMUNICATION
In the beginning, SiGe HBT technology was investigated with a view

to high-speed digital applications, which is the area that best fits SiGe
HBTs with low base resistance, low noise, excellent high-frequency response
and large gain-bandwidth product. A 12-bit digital-to-analogue converter,
designed and produced jointly by IBM and Analog Devices [11,12] was the
first commercially available SiGe IC until 1997. At that time, it matched
the speed of the best such circuits built using GaAs technology, while
operating at a lower voltage. This 1 Giga samples/s chip utilized 2854 SiGe
HBTs and 1465 polysilicon resistors with three levels of metallization.
In the intervening years, other companies such as TEMIC
Semiconductors, Daimler–Chrysler and Hitachi have clearly demonstrated
a high-performance SiGe HBT technology, now capable of mass production.
As of 2000, SiGe-based HBTs exhibiting fT and fmax values above 100 GHz
(values which are 50% higher than the best Si BJTs, but some two to six
times lower than the best GaAs devices). Only five years previously, many
applications such as optical networks and wireless RF technology in the
1–20 GHz range, which had been difficult to achieve with conventional
CMOS and bipolar technologies, were demonstrated with SiGe HBT
technology, as evidenced by reports of circuits for 20 Gb s−1 optical
networks [13] and RF wireless circuits up to 24 GHz [14–17]. At that
time, the availability of SiGe BiCMOS technology [18], with both very
high-performance HBTs with fmax of 60 GHz and 0.25 µm Leff CMOS for
logic and memory, offered the possibility of combining analogue and digital
components on the same chip in a new ‘single chip’ architecture.
The first evidence that SiGe HBT technology can successfully compete
with GaAs technology in the rapidly emerging wireless communication
market, with comparable performance in high volume production, was first
demonstrated by Harame et al [19] using a commercial UHVCVD system
for SiGe film growth. Within five years, this technology has matured to
a volume production, very high-performance SiGe BiCMOS process [20]
which can be tailored for low-voltage, low-power RF and mixed-signal
applications. The utilization of SiGe has modified the original market
split between silicon and GaAs technology and allows for a silicon-based
technology to address existing wireless communication market applications,
as well as future requirements in the 5700–5800 MHz ISM band.
The figures-of-merit that apply to SiGe HBTs for use in wireless
communication ICs are:
• cut-off frequencies beyond 100 GHz are possible;

• maximum frequency of oscillation beyond 100 GHz demonstrated;
• high transconductance and output resistance provide high voltage
gain;
• high current density and high breakdown voltage combine for high
output powers, particularly under pulsed condition;
• low 1/f corner frequency, low noise, and high nonlinearity provide
excellent oscillator and mixer performance;
• high power added efficiency.
The SiGe process provides the designer with additional benefits:
• vertical npn HBTs having a small emitter size;

• lateral homojunction pnp;
• three types of resistors;
• nitride capacitors with high specific capacitance;
• on-chip spiral inductors with high-quality factors for the 1–10 GHz
range;
• ESD structures to avoid damage to the IC;
SiGe: perspective for wireless communication 365
• cost-effective solutions as SiGe does not sacrifice the economies of

silicon manufacturing; and
• high power output makes designs feasible which are now possible in
GaAs only.
SiGe HBT bipolar/BiCMOS technology has a unique opportunity

in the wireless marketplace because of its high-performance and
integration/cost benefits of silicon bipolar/BiCMOS [21]. It has been shown
that low-noise operation, unparallelled in other bipolar devices, can be
obtained in Si/SiGe double HBTs. A microwave noise figure below 1 dB at
10 GHz has been reported [22, 23]. Typical applications include integrated
RF front-ends where low-noise amplification is desired in addition to low
phase-noise oscillation and mixing which typically benefit from bipolar
devices.
SiGe HBT technology is also ideally suited to other analogue
applications. These include high bandwidth amplifiers, mixers and voltage
controlled oscillators, all key functions for radio frequency and low-end
microwave communication systems. Power added efficiency (PAE), a key
figure-of-merit for high bandwidth amplifier design, has been measured to
be as high as 70% in SiGe HBTs, nearly double that of silicon junction
transistors and comparable to the figure-of-merit for GaAs MESFETs.
Transistor noise often constrains the design of communication systems.
Measurements of SiGe HBTs indicate that for low-frequency (less than
10 kHz) and high-frequency (2–10 GHz) noise, they are comparable to
the best available GaAs devices. The microwave noise performance of
SiGe HBTs has been evaluated on-wafer, for frequencies ranging from 2
to 26 GHz with corner frequencies as low as 300–400 Hz. Noise figures of
0.6 dB at 2 GHz and 1.2 dB at 10 GHz were found to be among the lowest
reported for bipolar transistors in general.
SiGe technology provides easy access to different integrated active and
passive devices. For high-frequency applications, most important are the
SiGe HBT itself and the passive inductor, capacitor, and transmission line
elements that are the key to RF design. Current gain, Early voltage
and noise properties of SiGe HBTs are better compared to FETs and
other bipolar technologies, resulting in a better phase noise performance in
mixers and VCOs. The 1/f noise has an extremely low corner frequency
for SiGe HBTs. For high-power applications, high gain, good efficiency
and linearity are also obtained in SiGe. Table 10.2 shows a wide variety
of circuits that have been demonstrated in the SiGe technology, showing
the versatility of the technology and demonstrating performance and/or
power improvement compared to other fabrications. BiCMOS also reduces
component count and improves overall system performance by combining
optimized functional blocks using either bipolar or CMOS [9].
Table 10.2. Demonstrated circuits using SiGe technology. (After Subbanna S et

al 1999 IEEE ISSCC Tech. Dig. pp 66–7.)
Circuit type
Performance Year Process
D/A converter
12-bit, 1.2 Gbits s−1 , 750 mW 1994 ADI/IBM
Frequency divider
Divide-by-128, 6.4–23 GHz, 1.5W 1995 NORTEL/IBM
Divide-by-8, up to 50 GHz, 226 mW FF−1 , 5.5 V 1998 Hitachi
Return-to-zero comparator
5 GHz, 1.5 V, 89 mW 1995 NORTEL/IBM
Monolithic VCO
12 GHz, l9 dBm, 5% tuning, −80 dBc phase noise 1996 Hughes/IBM
17 GHz, −110 dBc, on-chip LC resonator 1997 IBM
Active mixer
12 GHz, >0 dB gain @ +3 dBm LO 1996 Hughes/IBM
ECL ring oscillator

6.7 ps, 0.25 V swing at 1.3 mA, 400 mV swing 1999 Hitachi
ECL ring oscillator

13.7 ps, 8 mA/stage, 200 mV swing 1995 Philips
LNA
2.4 GHz, 10.5 dB gain, 0.95 dB NF 1996 NORTEL/IBM
PCS CDMA, 12 dB gain, 13 dB NF, 3 V/5 mA, 1999 IBM
IIP3 > +10 dBm
DECT, 1.8 GHz, 20 dB gain, 1.8 dB NF 1998 TEMIC
Broadband amplifier
8 dB gain, 17 GHz BW, 16.8 mA @ 2.5 V 1996 NORTEL/IBM
35 GHz BW, 270 mW 1998 Hitachi
Timing circuit
10 Gb s−1 , 150 mA @ 5 V 1996 NORTEL/IBM
Power transmitter
2.4 GHz, 1W Pout , 48% PAE, 1998 IBM
3.5 V, @ 1.5 V 150 mW Pout W, 47% PAE
Technology comparison 367
Table 10.2. (continued)

Circuit type
Performance Year Process
Power amplifier
Tx, 900 MHz, 70%PAE, 16 dB gain 1997 IBM
30 dBm, 16 dB gain, 75% PAE, 3.5 V 1999 IBM
27 dBm, 26 dB gain, 1998 TEMIC
45% PAE, 3.6 V, 1.9 GHz
CMOS ASIC
chip 1998 IBM
Multiplexer
2:1, 40 Gb s−1 output 1998 Hitachi
Demultiplexer
1:2, 60 Gb s−1 output 1997 Siemens
5.5 GHz LNA

14.1 dB gain, 2 dB NF 1998 IBM
Mixer, VCO
Mixer: 16.4 dB Power conversion gain,
IIP3 11.1 dBm, NF 6.6 dB, <10 mA/3 V
VCO:differential, 15% tuning range,
−90 dBc Hz−1 @ 100 kHz offset, 22 mW/3 V
I/Q modulator/demodulator synthesizer chip

11 MBits s−1 radio bit rate 1999 IBM
10.2. TECHNOLOGY COMPARISON
Silicon bipolar IC processes tailored for low-voltage, low-power RF and

mixed-signal applications have reached the performance and cost required
for mass production of RF transceivers operating in the 1–2 GHz range.
GaAs, which initially was the only contender above 2 GHz, is being
challenged by small geometry SiGe HBTs.
Table 10.3 summarizes the performance of competing technologies for
RFIC applications. It is seen that Si technology compares extremely
well with GaAs in terms of performance, with the advantage of
providing an existing low-cost, high-volume production base. Also,
miniaturization of CMOS devices has significantly improved the CMOS
Table 10.3. Comparison of key figures-of-merit for different technologies.

(After Kermarrec C et al 1997 IEEE RFIC Symp. Dig. pp 65–8.)
SiGe Si AlGaAs/ GaAs Si BJT

HBT BJT GaAs HBT MESFET BiCMOS
Emitter size (µm) 0.5 × 1 0.5 × 1 2×5 0.5 × 5 1.2 × 1.5
BVceo /BVDS (V) 4 4 15 8 6
fT (GHz) 50 32 50 30 13
fmax (GHz) 55 35 70 60 11
Gmax (dB) @2 GHz 28 24 19 20 17
@10 GHz 16 11 13 13 1
Fmin (dB) @2 GHz 0.5 1.5 0.3
@10 GHz 0.9 0.9
IIP3/P1dB 9 9 16 12 9
PAE(%) @3 V 70 60 @ 5 V 70 40
1/f corner 0.1–1 0.1–1 1–10 10 000 0.1–1
frequency (kHz)
IIP3: third-order input intercept point.

PAE: power added efficiency.
RF characteristics [24]. Submicron low-voltage CMOS technologies have

attained fT and fmax in excess of 40 GHz, less than 2 dB noise figure at
2 GHz, and excellent linearity up to 2 GHz. These will be discussed in
section 10.3.
SiGe HBTs offer the high performance of GaAs devices with lower
power consumption. In addition, these provide higher gain and less noise
than silicon BJTs. These powerful features, combined with a cost and
complexity level comparable to a silicon process, make SiGe BiCMOS
technology an ideal solution for high-frequency applications, including
cellular telephones and radio transceivers. The key to the replacement
of GaAs with SiGe HBTs lies in the fact that SiGe not only offers high
speed, it also enables high levels of integration. For example, chips
containing voltage controlled oscillator circuits are fully monolithic and
contain no external components, such as inductors and varactor diodes.
Fully differential architecture, which minimizes noise coupling from digital
parts of a highly-integrated chip into a sensitive analogue VCO, has been
possible in SiGe technology with minimum increase in power consumption.
Noise is a very important parameter for telecommunication circuits
and a minimum noise figure is commonly used to compare the noise
performance of a technology [25]. For the realization of mobile
communication products in the low GHz range, several technologies
MOS versus bipolar 369
Figure 10.2. Comparison of minimum noise figures of different technologies.

(After Plouchart J-O et al 1999 IEEE CICC Proc. pp 217–20.)
are available. The well-known GaAs technologies with MESFETs and

heterostructures are in keen competition with Si and SiGe bipolar and
CMOS technologies. Thus, an evaluation of the different technologies with
respect to noise performance is important. A comparison of minimum
noise figures reported in various technologies is shown in figure 10.2. The
minimum noise figure is close to that of a 0.5 µm MESFET technology and,
due to lower parasitic, is better than that of GaAs HBT technology [26,27].
10.3. MOS VERSUS BIPOLAR
The availability of inexpensive, high-quality silicon wafers and an extensive

manufacturing experience favours standard CMOS for most applications.
At present, complex integrated circuits are fabricated almost exclusively in
CMOS on standard silicon substrates. Low power consumption, high input
impedance, excellent noise immunity, high integration levels and proven
reliability are amongst the MOS attributes. With each new generation,
there are improvements in speed, current drive and noise performance along
with reductions in supply voltage.
Recently, much attention has been paid to the development of
dedicated RF CMOS technologies [28]. Building blocks implementing the
RF and baseband circuits in a 900 MHz wireless transceiver have been
developed. Many of the problem areas in the quest for a one-chip solution
to cellular phones using CMOS technology are being researched with some
success, but the design bottleneck, preventing further integration, is the
RF section, where the key issue is high-frequency performance.

In 1996, a 1 µm CMOS circuit for a 900 MHz spread-spectrum
wireless transceiver was demonstrated, showing the operation of an entire
transceiver on a single-chip, to give a level of performance previously only
possible by combining advanced silicon bipolar technology with specialized
passive components [29]. However, recent miniaturization of CMOS devices
has significantly improved the CMOS RF characteristics. For example,
typical values of fT and fmax for 0.25 µm n-MOSFETs already exceed
40 GHz, and those for 0.1 µm n-MOSFETs are more than 100 GHz [30].
The RF noise figure of the MOSFETs is less than 1 dB at 2 GHz operation.
Modern wireless systems increasingly blend digital blocks into
conventional analogue front-ends for frequency synthesis, adaptivity, multi-
mode operation and detection. This raises questions such as how well
digital CMOS circuits can coexist on the same chip as the RF front-end,
or whether there is sufficient on-chip isolation. In conventional CMOS
processes, circuits are built on silicon wafers about 500 microns thick,
but all the circuitry is actually formed in the top 1 µm thick layer of the
substrate. These standard silicon devices are far from ideal as the circuits
interact with the conductive silicon substrate, causing many parasitic
effects. In particular, capacitance between the circuitry and the substrate
causes power consumption to increase with switching speed and creates
undesirable coupling between circuits. The bulk substrate’s dispersion of
high-frequency signals precludes the construction of microwave devices.
These effects become more pronounced as advances in manufacturing
technology lead to smaller transistor dimensions and lower operating
voltages. Nevertheless, in the long run, CMOS technology is expected
to overcome many of these problems by using alternative technologies and
Si bipolar and GaAs technologies will find themselves increasingly pressed
by competition with CMOS in the 1–2.5 GHz frequency range.
When transistors are fabricated in a very thin layer of silicon near-
ideal devices can be realized. This is the reason for the surge in interest
in silicon-on-insulator technology. SOI circuits are attractive because of
their enhanced performance for deep submicron CMOS. Over the past
twenty years, a variety of possible structures based on the concept of a
buried oxide have been researched, with the aim of separating the active
device area from the silicon substrate. An early SOI process was silicon-
on-sapphire (SOS), in which a thin film of silicon is grown on a sapphire
wafer. SOS is an established technology used primarily in military and
space applications, where its inherent resistance to the effects of radiation
is essential. While SOS has been proven manufacturable and has significant
performance advantages, it has seen little commercial use because it is
unsuitable to the fabrication of the deep submicron transistors needed for
modern, high-density circuits, principally because of the high density of
defects at the silicon–sapphire interface.
Alternative technologies, such as wafer bonding or separation by

implanted oxygen (SIMOX) [31], have been proposed to produce a thin
silicon layer on top of a silicon–dioxide layer, on a bulk-Si substrate.
However, crystalline silicon cannot be grown on amorphous silicon dioxide
and both methods need an insulating oxide layer between the existing layers
of silicon. In the wafer bonding process, two oxidized bulk wafers are
bonded together. Polishing or etching the top wafer leaves a thin layer of
silicon supported by the bottom wafer, but insulated from it by an oxide
layer. This is a mechanical process, requiring an extremely clean wafer
surface to prevent voids. Doping procedures used to control the etching of
the thick upper wafer increase the defect density in the final silicon layer.
In the SIMOX process, oxygen atoms implanted just beneath the wafer
surface create a thin, buried layer of silicon dioxide. High implant energies
and multiple implant-and-anneal cycles are required, since the implantation
process severely damages the silicon surface.
The recent novel UNIBOND process uses deep implantation of
hydrogen. After bonding and annealing, the wafers separate naturally
at a depth defined by the location of hydrogen microcavities. This
mechanism has been given the acronym SMART-CUT [32]. SMART-
CUT has a number of advantages as a production process. Perhaps the
most significant, from a CMOS scaling viewpoint, is the relative simplicity
in realizing a specific combination of buried oxide thickness and Si layer
thickness.
All SOI technologies have been used for the fabrication of smaller
transistors, particular deep submicron CMOS. It is in the highly
competitive field of low-power circuits that SOI is most attractive. SOI
offers the possibility to achieve the almost ideal subthreshold slope of
60 mV per decade at room temperature and consequent lower threshold
voltage. Low leakage currents limit static power dissipation while the
combined effects of lower parasitic capacitance and reduced supply voltage
minimize dynamic power dissipation. Some compromises in performance
are however, inevitable. As silicon dioxide is a poor thermal conductor, self-
heating effects degrade transistor performance, as discussed in chapter 5.
Although circuits in SOI material are better electrically isolated from
the conductive silicon below, than those produced in bulk-Si wafers, they
remain subject to many of the parasitic effects seen in conventional bulk-
silicon circuits, although the reduced capacitance from the active device
area to the substrate is a particular benefit. However, high-frequency
dispersion losses still persist.
It is still a matter of considerable controversy whether or not SOI will
hold the key to the future successful implementation of CMOS circuits
when the gate length is shrunk even further. An excellent review of the
state of the art and future of SOI technology, material and devices is given
in [33]. Particularly novel applications of SOI in the future are likely to
include buried ground planes for reduction in cross talk [34], ultrathin layer
MOSFETs [35] and eventually double gate transistors [36] for realization
of volume inversion, leading to enhanced mobility, subthreshold swing and
reduced 1/f noise.
SiGe HBTs have also recently been successfully produced on SOI
substrates fabricated using wafer bonding. Associated with this approach is
the creation of thermal vias to remove heat from the SOI islands. Thermal
vias have been produced with high breakdown voltage, and a factor of four
improvement in thermal conductivity over a conventional buried oxide. The
wafer bonding approach [37] can also permit the incorporation of a buried
silicide layer above the insulator layer, to minimize collector resistance.
Such is the flexibility of this approach that the buried silicide can be
created below the insulator layer (GPSOI). This substrate is intended for
use as a buried ground plane in electronic systems that combine digital
and analogue circuitry on the same chip. Measurements of cross talk on
patterned GPSOI ground planes show world record suppression of cross
talk at frequencies in the range 1–50 GHz [34].
The trade-off between the use of GaAs, Si bipolar and/or MOS devices
for RF applications is a very complicated task due a number of factors. RF
transceiver circuits have a very broad range of requirements, including noise
figure, linearity, gain, phase noise and power dissipation. The advantages
and disadvantages of each of the competing technologies Si-CMOS, BJTs,
Si/SiGe HBTs, and GaAs MESFETs, p-HEMTs and HBTs has been
examined recently by Larson in the light of these requirements [9].
CMOS technology development proceeds at a rapid pace, so any
comparisons can only relate to the state of the art at a particular time.
However, as an example, in a 1995 CMOS process, a 0.5 µm n-MOS
device exhibited peak fT and fmax of approximately 20 and 40 GHz,
respectively. By comparison, the peak fT and fmax of the corresponding
npn bipolar transistor fabricated in a comparable process are 20 and
28 GHz, respectively. The improvement in microwave gain of MOS devices
is primarily due to the lower gate resistance compared to the base resistance
of a bipolar device. MOS devices exhibit a substantial speed advantage at
low currents compared to bipolar devices, but bipolar devices exhibit better
performance at low voltages as shown in figure 10.3.
When properly scaled for width and normalized for power dissipation,
MOS devices exhibit a slightly lower minimum noise figure than bipolar
devices, but their associated optimum source resistance is not well matched
to 50 Ω (close to an open circuit because of the low equivalent input noise
current), making optimum low-noise impedance matching difficult. The
optimum source impedance can be moved closer to 50 Ω in a MOS device,
but only at the expense of increased power dissipation or noise figure [38].
With SiGe, there are excellent prospects of rejuvenating CMOS
technology. The major potential market for heterostructure FETs
Figure 10.3. Measured high-frequency performance of Si BJT and n-MOS

devices: (a) fT and fmax versus collector/drain current; (b) fT = fmax versus
collector/drain voltage. (After Larson L E 1998 IEEE J. Solid-State Circuits 33
387–99.)
(discussed in chapters 6 and 7) is for low-power applications. The enhanced

carrier mobility in strained group IV alloy layers, particularly at low vertical
fields, is useful for high-speed low-voltage and low-power circuits involving
MOSFETs [39]. The ability to integrate SiGe-channel p-MOSFETs with
CMOS is a great advantage over III–V technologies and opens up the
possibility of SiGe ultimately receiving a larger market share than III–Vs.
Higher mobility improves the p-MOSFET performance, and gives rise
to better linearity, higher current drive, better noise performance and
reductions in the supply voltage. Figures 10.4, 10.5 and 10.6 compare
the enhanced effective hole and electron mobilities measured in various
MOSFET/MODFET structures demonstrated in SiGe technology.
It is possible to design layer structures with both electron and hole
channels with balanced conductance, therefore allowing high-performance
heterostructure CMOS designs. The possibility of matched n- and p-
channel performance in CMOS considerably facilitates the design of
amplifiers, mixers and filters. Major problems of integration of strained
Figure 10.4. Reported experimental hole effective mobilities at room

temperature obtained in pseudomorphic Si/Si1−x Gex /Si structures plotted
against effective field (Eeff ). The bars indicate the range of Eeff values present
in micropower, 1 and 0.1 µm CMOS technologies. (After Parker E H C and
Whall T E 1999 Solid-State Electron. 43 1497–506.)
SiGe BiCMOS technology 375
Figure 10.5. Reported experimental hole effective mobilities at room

temperature in compressively strained Si1−x Gex and tensile strained-Si grown
on virtual substrates with terminating composition Si1−y Gey . The upper section
shows mobilities for remote-doped hetero-interface and the lower section for
oxide-gated/strained-Si (tensile) interfaces. (After Parker E H C and Whall T E
1999 Solid-State Electron. 43 1497–506.)
layers into a CMOS production line are:
(i) the structures should be as far as possible compatible with

conventional processing;
(ii) the high thermal budgets used in present CMOS production are not
ideal for strained layers and may cause strain relaxation or diffusion;
(iii) any strained layer incorporated must be below the equilibrium critical
thickness, otherwise dislocations and defects will result reducing
performance and yield.
10.4. SIGE BICMOS TECHNOLOGY
To retain the yield in the basic CMOS process, it is important to

keep the actual physical process steps the same, as far as possible (see
figure 10.7). Several SiGe bipolar-only processes have been proposed or
are in development. Robust and manufacturable SiGe HBT technologies,
potentially suitable for commercial applications, now exist in the US,
Europe and Japan [13, 19, 26, 40–44]. SiGe HBTs can be integrated with
Figure 10.6. Reported experimental electron effective mobilities at room

temperature in strained-Si grown on virtual substrates with terminating
composition Si1−y Gey . The upper section shows mobilities at remote-doped
hetero-interface and the lower section refers to oxide-gated/strained-Si (tensile)
interfaces. (After Parker E H C and Whall T E 1999 Solid-State Electron. 43
1497–506.)
Figure 10.7. SiGe BiCMOS process modules in comparison to CMOS. (After

Subbanna S et al 1999 IEEE ISSCC Tech. Dig. pp 66–7.)
SiGe BiCMOS technology 377
conventional CMOS silicon circuits to form a BiCMOS technology in which

the bipolar transistors. SiGe HBTs can be exploited for critical high-
speed analogue or digital functions and the silicon CMOS can serve for
very high-density memory or compact on-chip signal processing functions
in system-on-a-chip (SOC) applications. This ability sets SiGe HBT
technology apart from the competing III–V technologies, which cannot
supply the high-quality native oxide essential to implementations in
CMOS. At the time of completing this book, IBM [45] have developed
and reported a production technology, based on 15 years research and
development and four generations of scaling CMOS compatible SiGe
technology. Performance of the SiGe HBT can be optimized to a particular
application, and both fT and fmax of 90 GHz have been simultaneously
achieved in a single transistor, with 0.18 µm lithography [46].
IBM’s SiGe BiCMOS technology with 3.3 V, 0.5 µm CMOS is a unique
and versatile process integrating high-performance SiGe HBTs [20]. The
standard device (3.3 V/50 GHz) is targeted at high-speed, small-signal
applications, while a high breakdown device (5.8 V/30 GHz) is targeted
at power amplifier applications. Table 10.4 summarizes the key figures-
of-merit. The SiGe HBT can operate at current densities in excess of
1.5 mA µm−2 and with near perfect ideality and flat β over a current
range of seven orders of magnitude. Unique to the SiGe HBT is the fact
Table 10.4. Summary of the key figures-of-merit of the devices realized in SiGe
BiCMOS technology.
SiGe
HBTs Small-signal/low voltage High power/high voltage
(npn) high-speed device low-noise device
BVceo 3.3 V 5.5 V
Gain 100 80
fT 47 GHz 30 GHz
65 GHz @ Vbc = 1 V 55 GHz @ Vbc = 1 V
fmax
Vbe = 0.72 V Vbe = 0.72 V
VA 65 V 124 V
FETs n-FET (W/L = 10 µm/0.5 µm) p-FET (W/L = 10 µm/0.5 µm)

Tox 7.8 nm 7.8 nm
Leff 0.39 0.39
Gm,sat 103 mS mm−1 180 mS mm−1
VT,lin 0.55 V 0.6 V
Rext 500 Ω mm−1 500 Ω mm−1
ID,sat 400 µA mm−1 400 µA mm−1
that β also remains virtually flat over a broad temperature range. Because
of its large peak fT , the SiGe HBT retains significant high-frequency
performance even at low currents, allowing the designer the choice to trade-
off speed for low-power operation.
This HBT and CMOS integration, without any loss of HBT
performance, makes it possible to implement a complete system on a
chip with, for example, high-performance analogue functionality and A/D
conversion implemented using the SiGe HBT device, combined with CMOS
for digital signal processing.
10.5. RF CIRCUITS
In this section, we discuss some of the technology considerations involved

in the implementation of key wireless system building blocks.
10.5.1. Low-noise amplifiers

Low-noise amplifiers are one of the key building blocks in an RF system.
They are required to contend with a variety of signals coming from the
antenna, often of larger amplitude than the desired signal and hence
both low noise and high linearity are required simultaneously. These
requirements are often contradictory with an additional requirement for
low-power dissipation. The radio signal received at the receiving antenna
is sent to the LNA, whose purpose is to boost the signal level without
reducing the signal-to-noise ratio significantly. The signal level at the
antenna can range between 1–100 mV rms. At the low end of the signal
range, the LNA performance is fundamentally limited by thermodynamic
issues, while at the high end of the signal range, the challenge is to minimize
the effects of nonlinearities on receiver performance. The measures for
these requirements are the amplifier noise figure, which determines the
minimum detectable signal (MDS), and the third-order input intercept
point (IIP3). In addition, high gain and low dc power consumption are
other requirements of an LNA. A very simplified expression for transistor
minimum noise figure, which is applicable to both BJTs and FETs, is given
by [47]
f
NF ≈ 1 + kgm rb/g (10.1)
fT
where gm is the device transconductance, rb/g is the base or gate resistance,
depending on whether the device is a bipolar transistor or FET, and k is
a material-dependent constant. Clearly, the noise figure of the amplifier
will be improved by employing a technology that operates with as low
a resistance as possible at a given current [1]. Low-noise amplification
at microwave frequencies has been the exclusive domain of MESFETs
and HEMTs. Bipolar transistors are traditionally excluded from these
RF circuits 379
applications despite their popularity in other analogue circuits in the lower

microwave range.
The outstanding high-frequency performance of Si/SiGe HBT
technology has been well established [11, 21]. In addition, for a given
required fT or fmax , SiGe HBTs require roughly one third the collector
current of an ‘equivalent’ Si BJT for equivalently sized devices. In many
applications, this speed performance advantage can be ‘traded off’ in a very
satisfactory way for reducing the power dissipation. It is at these low-power
levels that Si/SiGe HBT technology has a distinct advantage compared to
Si BJT or CMOS technology. As a result, technology scaling will have a
significant impact on LNA performance, as has been shown in a review by
Larson [9].
Figure 10.8 plots amplifier gain/dc power dissipation (in dB mW−1 )
as a function of noise figure (in dB) for a variety of reported LNAs
in silicon and GaAs technology at 2 GHz. However, one must be
careful in comparing reported circuit performance, since it represents
an intermingling of intrinsic device performance, process features and
circuit design. Nevertheless, by comparing the best reported results
in each technology, the fundamental device performance limits can be
assessed. These results demonstrate the potential performance advantage
of SiGe technology at this frequency, if dc power dissipation is a major
consideration.
Figure 10.8. Gain-to-dc power ratio plotted versus noise figure for
state-of-the-art 2 GHz LNAs. Note that the SiGe HBT circuit provides the
best result when power dissipation is a critical factor. (After Larson L E 1998
IEEE J. Solid-State Circuits 33 387–99.)
Because of the extreme dynamic range considerations of the low-

noise front-end, linearity is an equally important figure-of-merit for
LNAs. In this case, a linearity figure-of-merit is the ratio of the input
third-order intercept point (IIP3) to the dc power dissipation. Field-
effect transistors generally exhibit improved third-order intermodulation
distortion compared with bipolar devices, due to their near square-law
current versus voltage behaviour. On the other hand, bipolar transistor
amplifiers have demonstrated outstanding linearity performance as well,
apparently due to the partial cancellation of the resistive and capacitive
nonlinearities in the emitter–base junction at certain frequencies [48].
Figure 10.9 compares this linearity figure-of-merit for a variety of
recently reported monolithic LNA circuits, all operating at approximately
2 GHz. As with the case of noise figure, the performance advantages of
SiGe and GaAs technologies are significant if dc power dissipation is a
critical parameter, although the improvement is less dramatic. The best
LNA results have a ratio of IIP3/dc power of approximately 0.15, as shown
in figure 10.9.
The gain characteristic of a SiGe LNA, with a 19 dB gain and
1.7 dB noise figure, is shown in figure 10.10. SiGe LNAs have even been
implemented at even higher frequencies. A 5.8 GHz LNA [49] with a
Figure 10.9. Amplifier linearity figure-of-merit plotted for the same

monolithic 2 GHz amplifiers. The best results fall on a line of approximately
0.15 mW mW−1 . The advantages of SiGe HBT technology are not as dramatic.
(After Larson L E 1998 J. Vac. Sci. Technol. B 16 1541–8.)
RF circuits 381
Figure 10.10. Performance characteristics of a low-noise amplifier in a SiGe

minimum noise figure of 1.65 dB and an associated gain of 15 dB dissipates

only 13 mW from a 1 V supply (with only 9 mW in the gain stages), while
a 6.25 GHz monolithic LNA [50] operating from a 2.5 V supply shows a
minimum noise figure of 2.2 dB and an associated gain of 20.4 dB.
10.5.2. Power amplifiers
The power amplifier (PA) is a component of the total RF system that

takes the signal to be transmitted and amplifies it to the necessary level
needed to drive the antenna. For applications requiring moderate-to-high
output power, the PA contributes significantly to the total transceiver
power consumption, making the PA efficiency crucial to the overall system
performance. The total power consumed by the PA is greater than the
power output, as there will always be some power consumed in the active
devices and peripheral circuitry. Because the power output specification
itself is often larger than the power consumption of the rest of the blocks
in the RF system, and the power consumption of the PA will be greater
than the specified power output, the PA is decidedly the major power
consumer of the system [51]. The integration of the PA also remains a
difficult challenge. Power amplifiers need to deliver a wide range of output
powers to the antenna, as the user moves throughout the cell site.
The efficiency defined in traditional approaches (e.g., classes A, B, AB
and C), is often optimized merely at the maximum output power. Three
different types of efficiency are generally quoted. Firstly, the collector/drain
efficiency, ηc/d which is defined as [52]
Prf,out
ηc/d = (10.2)
Pdc
where Prf,out is the power delivered to the load at the desired RF frequency
and Pdc is the total power taken from the dc supply. Secondly, the power
added efficiency (PAE) of a power amplifier is given by the well-known
expression
Prf,out − Prf,in
P AE = (10.3)
Pdc
where Prf,in is the power needed to drive the input. Thirdly, the overall
efficiency is defined as
Prf,out
η= . (10.4)
Pdc + Prf,in
Both the PAE and the overall efficiency are better gauges of the true
performance of a PA, since they include the power needed to drive the
PA in the determination of the efficiency.
The complications associated with power amplifiers for RF
applications are challenging, as in the case of LNAs. The PA must
satisfy the requirements of linearity, gain, output power and power added
efficiency. In addition, mobile applications which require a lower power
supply (3 V and even lower), have made it difficult to maintain the required
output power and efficiency due to impedance matching limitations.
Ideally, the PAE of the amplifier should not degrade significantly, as the
output power varies from near zero to its maximum value.
In the past, a host of different architectures in which a PA could be
implemented have been proposed [53]. The number of different types of
classes of power amplifiers is too numerous, and they range from entirely
linear to entirely nonlinear, as well as from quite simple to a very complex
one. A class A PA is the simplest and most basic form of power amplifier.
In a class A operation, the transistor is in its active region for the entire
input cycle, and thus is always conducting current. As such, the device
maintains approximately the same gain throughout the entire region and,
in the case of a MOS device, is linear in that region. The problem with class
A structures, however, is their inherently poor efficiency since it is on at all
times, and the current represents a continuous loss of power in the device.
The efficiency of an RF class A PA is limited to 50%. As a result, class A
amplifiers are used only in those situations where the linearity requirements
are stringent.
In a class B structure, there are two devices: one which provides
current to the load during the positive half cycle and one which removes
current from the load during the negative half cycle. The structure is
usually called a push–pull structure. When no signal is applied, however,
RF circuits 383
there is no current flowing, as both the devices are biased at their turn-on
voltages. As a result, in an ideal case, any current through either device
goes directly to the load, and thus attempts to maximize the efficiency.
Although this is generally a linear amplifier, there is an instant during
each cycle when both devices are off, which produces distortion in the
output known as crossover distortion. This architecture allows for very high
efficiencies, as theoretically the efficiency can approach 78%. Hence, this
architecture can be useful in applications where the linearity requirements
are a little less stringent. In situations where the linearity is still an
important issue, the class AB structure, a cross between a class A and
a class B structure, is used. The above classes are examples of linear
structures, where the output amplitude and phase are linearly related to
the input amplitude and phase.
In a communication system, power amplifiers are used to amplify the
signal to the proper power level to reliably transmit the signal which is often
quite high. In many applications, the amount of power consumed by the
amplifier is not critical, as long as the signal being transmitted has adequate
power. However, in a situation where there is a limited amount of energy
available, e.g., in mobile communication systems, the power consumed by
all devices must be minimized in order to maximize the length of time for
which that energy is available.
Power amplifiers are typically operated in class AB mode for most
RFIC applications, in an attempt to achieve a compromise between
linearity and power added efficiency. In this case, the factors of key
importance for amplifier performance are the transistor specification
(for high power gain), linearity (for lowest possible adjacent channel
interference) and breakdown voltage (BVceo for bipolar devices). However,
the breakdown voltage has become less critical for handsets in recent years,
due to the reduction of operating voltages in most handheld units.
In cases where linearity is not critical, and efficiency is highly critical,
class C power amplifiers are used. A class C power amplifier is the most
basic of the nonlinear power amplifiers used at RF frequencies. This
architecture is based on the idea of a class B structure, where the device
is biased at the edge of conduction and the device conduction angle is less
than 180◦ . As a result of the pulsed nature of the output current, the input
and output voltages are not linearly related, and the output of the PA will
be highly distorted if the input voltage amplitude changes.
Since gain is very critical for achieving the best performance, most
high-performance power amplifiers in the 2 GHz frequency range have been
implemented in GaAs or SiGe technology, to achieve the highest possible
power added efficiency. At lower frequencies, silicon MOS devices are
often employed for power amplifiers because of their low cost and robust
operation, despite their poor performance compared to GaAs technology.
A comparison of monolithic power amplifier performances for mobile
Table 10.5. Summary of maximum PAE, Pout at maximum PAE, gain, PAE at
3 dB compression and Pout at 3 dB compression under four biasing conditions,
tuned for maximum PAE. (After Greenberg D et al 1997 IEEE IEDM Tech. Dig.
pp 799–803.)
Bias Maximum Pout @ Gain PAE @ Pout

(mA) PAE maximum PAE (dB) 3 dB 3 dB
(%) (dBm) (%) (dBm)
2 (B) 69 15.2 24.9 67 14.2
6.5 (AB) 60 15.2 28.9 48 12.3
12.5 (AB) 52 15.2 29 42.3 12.9
25 (A) 42 15.2 30.1 26.2 12.7
telephone PHS applications at 1900 MHz, where the adjacent channel

leakage specification of 55 dBc is specified at 600 kHz from the carrier
centre, is available in [54].
Power amplifiers with high breakdown voltage (6 V) HBTs for 3 V
wireless applications have been demonstrated in IBM’s 200 mm SiGe
technology [55]. At 0.9 GHz and 1.8 GHz, excellent power densities of up
to 1.36 mW µm−2 , an outstanding PAE reaching 70% and no performance
degradation in integrating the HBT with CMOS have been observed. These
results suggest that SiGe can meet the demands of many large-signal
wireless applications. Table 10.5 summarizes the peak PAE and 3 dB
compression point load–pull data for the four biases tuned for maximum
PAE. Despite the extra processing steps associated with integrating a
SiGe HBT process with CMOS, it was observed that the BiCMOS version
achieves virtually identical performance to the device from the HBT+p-
FET process. The detail of the HBT+p-FET and BiCMOS processes used
to fabricate the devices may be found in [56].
A fully integrated RF transceiver for a DECT application [8] comprises
two bipolar ICs including a power amplifier, a low-noise amplifier and a
VCO. The SiGe HBT power amplifier has a 33 dB small-signal gain, 38%
max PAE and 26.6 dBm saturated output power at a 3 V supply. The
performance of the transceiver is shown in figure 10.11.
10.5.3. VCOs and frequency synthesizers

The voltage controlled oscillator (VCO) represents one of the most difficult
challenges for a design engineer. The ideal VCO output should exhibit
no phase noise, tune over a fixed frequency range and be insensitive to
temperature, process drift, output loading or power supply variations.
While hybrid VCOs, which typically employ discrete silicon bipolar
RF circuits 385
Figure 10.11. Performance characteristics of a power amplifier in SiGe

transistors, high-quality surface mount inductors and varactor diodes, and

are temperature compensated and laser trimmed to the proper centre
frequency, closely match these ideal conditions, monolithic integrated
VCOs suffer from low-quality monolithic inductors and varactor diodes and
a difficulty in trimming the centre frequency to accommodate its inevitable
drift due to process variations [57, 58]. The quality factor of the VCO
resonator, which is mostly determined by the inductor in the resonator, is
especially important due to its effect on the phase noise of the resulting
oscillator.
A simplified expression for oscillator phase noise, in good agreement
with experimental data over a broad range of oscillator circuits, derived by
Leeson [59] to account for flicker noise is given by
2
ωo ωc
Sφ (ωm ) = S∆θ 1 + 1+ (10.5)
2Qωm ωm
where Sφ (ωm ) is the output power spectral density at frequency ωm offset

from the oscillator centre frequency, S∆θ is the power spectral density of
the oscillator input phase error, Q is the resonator loaded quality factor,
ωo is the centre frequency of the oscillator output and ωc is the flicker noise
corner frequency.
Several VCO configurations have been implemented in SiGe
technology. Monolithically integrated 26 GHz and 40 GHz VCOs were
fabricated on high resistivity substrates using SiGe HBTs and on-chip
varactors. A hybrid 8–12 GHz VCO has also been built using a SiGe
HBT in common-emitter configuration [60]. With a tuning range of more
than 3 GHz, the output power behind an on-chip 10 dB attenuator reached
−13 dBm. The transistors had an fmax of approximately 60 GHz, and were
operated in common-emitter series feedback configuration.
A 2.4 GHz VCO for wireless local loop (WLL) applications, with a
power dissipation of 28 mW and phase noise of −110 dBc Hz−1 (at 1 MHz
off carrier), has been fabricated using RPCVD-grown SiGe HBTs and a
resonator consisting of a chip varactor and a microstrip line inductor [61].
An 11 GHz 3 V SiGe VCO with integrated resonator has been reported by
Soyuer et al [62] with a fully differential architecture. This architecture
minimizes noise coupling from digital parts of a highly-integrated chip
into a sensitive analogue VCO. The added circuitry of a fully differential
architecture typically comes at the cost of increased power levels, but
SiGe achieves this result with minimum increase in power consumption.
In the case of SiGe, the VCOs are fully monolithic and contain no
external components, such as inductors or varactor diodes. Recently, IBM
has reported a VCO operating at 17.1 GHz, an ultrahigh transmission
frequency recently allocated for wireless uses in Europe (HiperLAN). The
record setting VCO, operating on a single 3.3 V supply, could be tuned
over a 600 MHz range and exhibited a phase noise of −104 dBc Hz−1 at
a 1 MHz offset from centre frequency, with an output power of −5 dBm,
dissipating only 65 mW. Another VCO, tuned for a new American standard
of 5.x GHz (U-NII), has also performed exceptionally well, with a tuning
range of 840 MHz and a phase noise of −115 dBc Hz−1 at 1 MHz offset at
the centre frequency of 5.6 GHz [63].
10.6. PASSIVE COMPONENTS
The demands placed on portable wireless communication equipment

include low cost, low voltage, low power dissipation, low noise, high
frequency of operation and low distortion for bandwidth reduction. These
design requirements cannot be met satisfactorily without the use of
RF inductors. Spiral inductors have found an important place in the
wireless communications market, where they can be used to improve the
performance of key RF building blocks.
Since the introduction of spiral inductors, many authors have reported
higher performance inductors on Si substrates, using advances in processing
technology [64]. Inductors up to about a 10 nH range in a reasonable area,
with Q limited to about 5 at 1 GHz and 10 at 2 GHz by metal series
resistance for standard technologies have been achieved. This has included:
(i) higher conductivity metal layers to reduce the loss of the inductor;
(ii) multi-layer metal to either shunt inductors to reduce loss, or to reduce
the area;
(iii) low loss substrates to reduce losses in the substrate at high frequency;
and
(iv) thick oxide to isolate the inductor from the lossy substrate.
Passive components 387
Table 10.6. Passive components and diodes realized in SiGe BiCMOS

technology for RF communication systems. (Source: IBM.)
Spiral inductors
2-turn: Q (12 GHz) = 10, 1.5 nH
4-turn: Q (2 GHz) = 7.5, 4.2 nH
6-turn: Q (1 GHz) = 5.8, 9.8 nH
8-turn: Q (1 GHz) = 5.2, 16.6 nH
Capacitors
MIS capacitor C = 1.5 fF µm−2
MIM capacitor C = 0.7 fF µm−2
Resistors
Polysilicon resistors 340 Ω/square and 220 Ω/square
Implant resistors 1.7K Ω/square, 23 Ω/square and 8 Ω/square
Diodes
Schottky barrier diode Vf = 300 mV@100 µA
PIN Vf = 790 mV@100 µA
Varactor 1.4 fF µm−1 @ 0 V, Vf = 810 mV @ 100 µA
ESD 2000 VHBM
In table 10.6, the performances of several passive components and

diodes realized in IBM’s SiGe BiCMOS technology for RF communication
systems are shown. Self-resonance due to the large parasitic capacitance
to the substrate is a substantial problem, and Q drops to about 2 for a
10 nH inductor in a typical technology. Since the inductor is usually used
to match impedance or to tune a gate or base diffusion capacitance, the
parasitic capacitance can usually be incorporated in the design process, as
long as the self-resonant frequency is far above the frequency of interest.
The lossy silicon substrate makes the design of high Q reactive
components difficult. Despite this difficulty, the low cost of silicon IC
fabrication over GaAs IC fabrication and the potential for integration with
baseband circuits make silicon the process of choice. Accordingly, the
use of silicon spiral inductors has proliferated in recent years [65]. On-
chip inductors are necessary for matching networks and LC resonators for
silicon-based RFICs for wireless communication ICs. Transmission lines
with losses of less than 1.5 dB cm−1 measured up to 20 GHz have been
realized. This value is comparable to III–V technologies and is an order of
magnitude better than conventional silicon.
Another important issue is whether microwave transmission line

losses caused by the conductive silicon substrate will limit the high-
frequency response of SiGe HBT amplifiers. Several research groups have
explored the use of high-resistivity Si substrates for the realization of SiGe
MMICs, but very high resistivities (>20 Ω cm−1 ) of the substrate lead
to severe processing problems associated with such wafers (specifically slip
dislocations and warpage).
10.7. COMMERCIALLY AVAILABLE PRODUCTS
IBM and Daimler–Chrysler have been involved in the SiGe area for a
long time. Corporations such as Lucent, Motorola, ST-Microelectronics,
Philips, Infineon, Maxim, Temic, Hitachi and many others have recently
begun development or deployment of SiGe-based HBT processes, and are
likely to make the transition from present efforts in discrete technology to
integrated SiGe BiCMOS technology. SiGe-based mixed-signal technology
is rapidly making its way into the consumer mainstream, at the high
end of the telecommunications market. Present trends indicate that SiGe
technology will find applications in the frequency range 2–30 GHz, above
which GaAs is well established. Components for personal communication
services devices operating between 1.8–2.2 GHz are a fast growing market
segment, along with pagers and wireless local area networks. Other
wireless opportunities might include direct-broadcast satellite TV and
local multipoint distribution services (LMDS). Devices based on SiGe
technology will be able to move data across networks at speeds traditionally
considered beyond the reach of silicon technology. This will bring better
performance at low costs to fibre transport networks, high-speed cellular
voice/data phones and wireless devices such as global positioning satellite
(GPS) receivers. Another application is a differential global positioning
system (DGPS) satellite receiver that uses several GPS channels centred on
1.5 GHz. A related product is targeted for the automobile industry, which
has significant potential to use wireless technology for traffic management
and control, and collision avoidance systems. Inexpensive 24 GHz collision
warning radar systems for mainstream automobiles are also needed.
10.7.1. TEMIC Semiconductors

Temic Semiconductors supplies integrated circuits to the communications,
automotive, data processing and aerospace markets. As a leader in
SiGe technology, it provides high-performance SiGe solutions in high-
volume production. Its SiGe process is a suitable technology for RF chip
applications. It provides significant cost benefits on the component and
system level side versus GaAs and, in a market where prices are falling,
this will be the key issue for manufacturers. The SiGe process for high-
Commercially available products 389
volume production was set up on a well-proven ultrahigh-frequency (UHF)

process. The wafer fabrication uses a progressive and widely automated
6 in wafer line, high-volume quantities can be provided reliably.
Temic Semiconductors replaced the usual GaAs PA and LNA devices
by SiGe integrated solutions in the frequency range of 400–2400 MHz.
Thanks to SiGe, the U7004B, U7006B, T7024 and T0980 provide extremely
low noise figures (e.g., 1.6 dB at 1.9 GHz in 50 Ω systems) and high
integration. Figure 10.12 shows a typical application circuit using the
U7004B SiGe front-end IC. As the LNA, PA and transmit–receive switch
driver are included, a large number of external components, and thus
system cost, can be saved. They also provide very efficient power amplifiers.
The PAE of the T0980 front-end for 400 MHz reaches a typical value of
60%.
Figure 10.12. Application circuit using U7004B SiGe front-end IC. (After Temic
Semiconductors, Germany.)
Solutions using GaAs devices are expensive and normally require a

negative auxiliary voltage. The front-end ICs U7004B, U7006B, T7024 and
T0980 manufactured in SiGe technology need only a single, positive 3 V
supply voltage. This results in lower system and production costs as well
as extended talk and standby times due to the low current consumption.
The TST091x family members enable the cost-effective production of
a new mobile phone generation. End products are expected to be smaller
and lighter as 3 V operation makes use of a single battery cell. The high
PAE and low-power operation of SiGe PAs allow for longer talk times.
Since SiGe does not require negative supply voltage or a battery disconnect
switch as needed by competing devices using GaAs technology, both system
and production costs will be reduced. Temic Semiconductors offers SiGe
PAs for single-band operation in the 900 MHz frequency range (GSM 900)
and GSM 1800/1900, as well as for dual-band operation (GSM 900 and
1800/1900).
With the CW capable T0930, Temic provides a high-performance,
SiGe integrated solution with maximum efficiency for two-way pagers. A
power amplifier, RF power control and a standby circuit are included.
With SiGe, the current consumption in power-down mode is significantly
reduced, eliminating the need for a high-side switch. This results in less
external components—board space, and thus overall size can be reduced
dramatically.
The LNAs TST095x with a two-stage amplifier and switchable gain
provide the perfect combination of low noise (NF = 2.2 dB in high gain
mode), large signal capability (IIP 3 = −7 dBm in low gain mode) and high
reverse isolation (minimum −40 dB). Both the low current consumption
and power-down function help to extend battery lifetime.
10.7.2. IBM
The mainstream SiGe chips introduced by IBM include basic building
blocks—low noise amplifiers, voltage controlled oscillators, power amplifiers
and discrete transistors. SiGe is well suited to realize innovative high-
frequency products, e.g. antenna switches for the transmit/receive path,
satellite communication applications or wireless local area networks.
Several of the chips are designed as low-cost, highly-reliable direct
replacements for gallium arsenide parts for a broad spectrum of
communications applications and are listed below. Several system-level
hardware and software products [66] are now in production and a brief list
is given in table 10.7:
• SiGe 3 V GSM tri-band low-noise amplifier
• SiGe 3 V tri-band image reject mixer with low-noise amplifier
• SiGe 3 V GSM tri-band voltage controlled oscillator
• SiGe PDC linear power amplifier
Commercially available products 391
• SiGe high dynamic range 1900 MHz low-noise amplifier

• SiGe high dynamic 900 MHz low-noise amplifier
• SiGe high dynamic range low-noise transistor
IBM has also been a partner in a number of collaborative ventures,

involving application of their SiGe technology to other companies products.
Alcatel has developed several 40 Gb s−1 SONET optical data transmission
systems operating with the bit decision circuit based upon the IBM 50 GHz
SiGe technology. A Harris Prism II chip set, a low-cost wireless local
area network (WLAN) product operating on the IEEE 802.11 standard at
2.4 GHz, has been converted to SiGe technology. A factor of two reduction
in chip count and cost, a factor of four improvement in range and a fivefold
increase in bit rate have been achieved. A recent announcement by Siemens
revealed the use of the IBM SiGe technology in developing third-generation
(3G) cellular base station electronics. As 3G is a wideband CDMA protocol,
the combination of high linearity at low power makes SiGe technology
extremely well suited to this application.
Table 10.7. A brief listing of mixed-signal SiGe-based product offerings and

their market status. (After Meyerson B S 2000 IBM Res. Dev. J. 44 391–420.)
Company Product Description

category
AMCC Wired 3.2 Gb s−1 17 × 17 differential crosspoint switch
OC-192 SONET/SDH transimpedance amplifier
OC-48 multi-rate clock and data recovery solution
multi-rate OC-48 transceiver
2.5 Gb s−1 multi-rate clock recovery and limiting
amplifier device
3.3 V OC-48 transimpedance amplifier for
WDM and TDM applications
Alcatel Wired Complete 10 Gb s−1 SONET system with all
electronics
Harris Wireless PRISM II chip set 11 Mb s−1
Intersil (5 ICs 5 complete data comm radio operating at
2.4 GHz bands up to 11 Mb s−1 )
Power amplifier and detector (SiGe)
RF-to-IF converter (SiGe)
I/Q modulator/demodulator and synthesizer (SiGe)
IBM Wireless Direct-conversion digital GPS receiver and
Leica GPS engine
Siemens Wireless Third-generation mobile cellular base station
10.8. SUMMARY
In applications, SiGe-based devices and circuits represent an outstanding

extension of conventional Si technologies, opening up frequency ranges
which have previously only been the domain of III/IV compound
semiconductors such as GaAs. SiGe HBT technology has the potential
to revolutionize high-frequency transceiver design in a way comparable to
the revolution in digital integrated circuit technology brought about by
CMOS in the 1970s. Its unique combination of outstanding high-frequency
performance, low manufacturing cost and high yield will provide abundant
opportunities for new architectures and new systems in the near future.
Many semiconductor companies, other than IBM and TEMIC, have
recently begun development or deployment of SiGe-based technology and
are likely to make the transition from discrete technology, particularly
in BiCMOS applications. In the longer term, heterostructure CMOS
technology may well take over at even higher frequencies.
For mobile applications, the recent announcement of commercially
viable implementation of silicon-on-insulator technology will have far
reaching consequences in the semiconductor industry. The harnessing of
SOI technology will result in faster chips that also require less power—a
key requirement for extending the battery life of small handheld devices
that will be pervasive in the future. Research on fabricating SiGe devices
in a thin layer of silicon on top of an insulator (such as silicon oxide) has
been initiated. If it becomes successful, this breakthrough may advance
the microelectronics technology one or two years ahead of where it would
have been with conventional bulk-Si technology.
As early as 1995, IBM reported at the Bipolar/BiCMOS Circuits and
Technology Meeting (BCTM) that they believed an important application
of SiGe technology will be a ‘single chip solution’ for wireless applications.
Such a chip which will handle both RF and digital functions is now a reality!
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Index
Acoustic scattering, 60 18, 25, 153, 161, 166, 174,

Activation energy, 34, 58 370
Alloy scattering, 39, 60–62, 112, Boltzmann statistics, 108
197, 214 Boltzmann transport equation,
Atmospheric pressure CVD, 48 105, 108, 162
Auger electron spectroscopy, 44, Breakdown voltage, 99
274, 282 Buffer layer, xiv, 17, 18, 21, 40,
Auger recombination, 82, 117, 41, 50, 198, 201, 206, 213,
337 219
Avalanche Bulk recombination, 117
breakdown, 99, 316
multiplication, 82, 317 Carrier freeze-out, 173
photodiode, 316, 317 Chemical vapour deposition, 11,
42, 46, 48
Band offset, 38, 51, 52, 54, 56, 58, CMOS, 2, 16, 18, 196, 204, 226,
60, 90, 197, 203, 328 228, 238, 245, 367, 370,
Bandgap narrowing, 59, 74, 115, 372, 375
117, 118, 176 Collector
Barrier effect, 90, 95 breakdown voltage, 130
Base design, 122 design, 129
Base resistance, 4, 5, 7, 8, 13, 75, Transit time, 97, 139
82, 99, 119, 120, 125, 135, Conduction band
136, 142, 144, 157, 185, discontinuity, 32, 55, 77
186 Critical thickness, 13, 35–38, 64,
Base transit time, 8, 13, 14, 83, 88, 197, 276, 314, 351
84, 92, 100, 120, 129, 139, Cross section TEM, 41
140, 158, 165, 177 Current crowding, 136
Base width modulation effect, 85 Current gain, 7, 10, 11, 13, 74,
BICFET, 20 77, 83, 87, 89, 94, 120, 158,
BiCMOS technology, 2, 9, 24, 173–175, 365
120, 186, 188–190, 260, Cut-off frequency, 3, 14, 84, 96,
364, 365, 368, 375, 377, 110, 120, 123, 131, 140,
387, 388 143, 157, 163, 177, 222,
Bipolar technology, 3, 5, 8, 9, 13, 364
397
398 Index
δ-doping, 252 Heterojunction, 10, 13, 19, 35, 42,

Density of states, 80, 113, 116 50, 57, 58, 90, 96, 152, 180,
Deposition techniques, 42, 274 226, 232, 318
Dielectric constant, 34, 112, 117, Heterojunction bipolar transis-
159, 288, 289, 311 tor, 2, 9, 73, 76, 77, 119,
Direct bandgap, 311, 337 120
Drift–diffusion HFET, xv, 17, 196, 198, 213, 227,
equation, 108 238–242, 245, 250, 252,
model, 105, 107, 158, 162, 163 254, 257, 263, 265, 268
simulation, 152, 336 High electron mobility transistor,
17, 25, 220
Early voltage, 13, 85, 87, 143, High level injection effect, 94
157, 158, 175 Hole gas, 60, 62, 217
ECL gate delay, 9, 99, 133, 141– Hot carrier, 239, 242, 314
144, 174 Hot electron, 7, 20
Effective mass, 34, 59, 61, 116 Hydrodynamic model, 105, 107,
Electron gas, 213 216, 227
Emitter
design, 126 Ideality factor, 274, 276, 277, 288,
transit time, 84, 97, 139, 163 293, 296–298, 306
Energy balance Impact ionization, 99, 183, 314,
equation, 216 317
model, 162, 163 Impurity scattering, 111, 113, 199
simulation, 162 Inductors, 361, 363, 364, 368,
Epi-base technology, 152, 156, 385–387
174 Infrared detector, 305, 325, 327,
329
Fermi–Dirac statistics, 104, 250 Injection efficiency, 9, 10, 74, 75
Field-effect transistor, xiv, 2, 6, Input impedance, 183, 196, 369
16, 263, 361, 380 Inter-valley scattering, 198, 199
Figure-of-merit, 87, 96, 98, 99, Interface state density, 241, 274,
109, 154, 316, 365, 380 291, 293, 300–302
Flicker noise, 385 Interface traps, 188
Forward active mode, 75, 77 Intermodulation distortion, 380
Freeze-out effect, 60, 62, 175 Ionized impurity scattering, 60,
62, 198, 221, 230, 252
Gas source MBE, 46, 50 Ionizing radiation, 188, 336
GeC, 314, 315, 334
Gummel method, 104, 108 Kirk effect, 94–96, 131
Gummel–Poon model, 134
Lattice constant, 13, 32–35, 38,
HCMOS, 17, 227, 231 49, 50, 54, 112, 197, 314
Heavy doping effect, 59, 80, 82, Lattice scattering, 198
118 Limited reaction processing, 47
Index 399
Limited reaction processing CVD, Numerical methods, 108

42, 47
Low-noise amplifier, 360, 363, Ohmic contact, 272, 276, 278
378–380 Optical absorption, 58, 321–323,
Low-temperature simulation, 152, 325
172, 175 Optical detectors, 325
Optoelectronic devices, 20
Mason’s gain, 109 Optoelectronic integrated circuits,
Maximum available gain, 109, 310, 311, 315, 328
110 Out-diffusion effects, 90, 92, 120
Maximum oscillation frequency, Oxidation, 51, 241, 264, 276
xiii, 8, 75, 96, 98, 143, 152,
220, 221 p–i–n diode, 315, 318, 325, 332,
Metal–organic CVD, 10 334, 335, 341, 343, 363
Metallization, 11, 183, 272, 277, Parasitic channel, 202, 212, 213,
363 216, 228
Metastable layer, 38, 49, 51 Passive component, 25, 363, 386,
Misfit dislocation, 35, 36, 38, 41, 387
51, 52, 94, 118, 314 Phase noise, 23, 265, 365, 372,
Mobility, 59, 63, 112, 113, 198, 384–386
200 Phonon scattering, 60, 61, 63,
MODFET, xv, 17, 217, 219–222, 111, 113, 199, 200, 213
224, 374 Photoconductor, 315
Modulation-doped heterostructures, Photodetector, 306, 310, 315,
63, 201, 203, 218 317–320, 325, 328, 329,
Molecular beam epitaxy, xiii, 10, 332, 334, 336–338, 341,
37, 42, 44 345, 346, 350
Moll–Ross current relation, 79 Photodiodes, 315, 318, 320, 332,
Monolithic microwave integrated 334, 335, 342
circuit, 361, 362, 388 Photoluminescence, 50, 57, 312
Monte Carlo method, 105 Phototransistor, 314
Monte Carlo simulation, 112, 199 Plasma processing, 48, 241
MOS capacitor, 52, 57, 245 Poly-SiGe, 259–261
MOSFET, xiv, xv, 5, 7, 17, 18, Power added efficiency, 364, 365,
188, 190, 199, 206, 209, 382, 383
212, 214, 238, 249, 251, Power amplifier, 12, 23, 24, 363,
257, 260, 263–265, 374 367, 377, 381–384
MSM, 315, 316, 318, 320, 334, Power delay product, 174, 228,
345–348 231
Multiple quantum well, 58, 331 Propagation delay, 4, 99, 141,
142, 154
Neutral base recombination, 92
Noise figure, 185, 186, 365, 368, Quality factor, 385
369, 372, 378, 379 Quantum device, 20, 239
400 Index
Quantum efficiency, 316–318, 321, 264, 277, 310, 314, 321,

328, 329, 332, 334, 337, 327, 334
338, 350 SiGeSnC, 314, 352
Quantum well, 17, 44, 218, 222, Silicides, 272, 274, 276–278
239, 242, 245, 247, 255, SIMOX, 242, 250, 255, 256, 329,
328 362, 371
Small-signal analysis, 109, 134,
Radiation effect, 186 139, 338
Radiation hardness, 190, 256 SOI, 7, 142, 152, 161, 166, 172,
Raman spectroscopy, 51 241, 254, 328, 370–372,
Rapid thermal CVD, 47, 175 392
Remote plasma CVD, 48 Solid phase epitaxy, 49
Responsivity, 320, 325, 327, 331, Space-charge recombination, 36
332, 338, 343, 345, 347, Spacer layer, 92, 94, 100, 143,
348, 353 173, 174, 221
RF communication, xiii, 21, 359, SPICE parameter, 140, 142–144
387 Strain compensation, 60, 259
RFIC, 360, 367, 383 Strain relaxation, 36, 40, 258,
Rutherford backscattering spectro- 276, 277, 286, 375
metry, 279 Strained layer epitaxy, 33
Strained silicon, 36, 196
Scattering mechanisms, 105, 110, Superlattice, 311, 313, 328, 351
198, 199 Surface passivation, 47
Scattering parameters, 109 Surface recombination velocity,
Schottky barrier diode, 293, 317 188, 288
Schottky barrier height, 293 Surface scattering, 111, 242, 256
Schottky gate FET, 204, 221,
222, 228 Technology comparison, 367
Secondary ion mass spectro- Tensile strain, 60, 209
metry, 41 Thermal
Self-aligned technology, 8, 120, noise, 183, 185
142, 159, 221 stability, 52, 257
Self-heating effect, 152, 167, 206, Thermal oxidation, 51
371 Thermal stability, 51
Setback layer, 230 Thermionic emission, 276, 288,
Shockley–Read–Hall recombina- 292, 297, 317, 320
tion, 117, 337 Thermionic field emission, 288,
Shot noise, 183, 185, 320 292, 297
SiC, 1, 10, 241, 314, 327 Thin-film technology, 261, 274
SiGe, xiii, 1, 2, 9, 13–15, 35, 40, Third-order intermodulation, 380
42, 54, 59, 77, 115, 254, Transmission electron microscope,
263, 321, 325 285
SiGeC, xiv, 13, 15, 18, 32, 42, 49, Transport, 60, 105, 107, 217
50, 56, 59, 241, 257, 260, Tunnelling, 94, 99, 290, 336
Index 401
Tunnelling current, 8, 75, 173, Velocity saturation, 94, 100, 111,

260 199, 217
Vertical transistor, 181, 241, 263,
ULSI, 196, 241
264
Ultrahigh vacuum CVD, 13, 46
Very low pressure CVD, 48
Valence band, 58, 330 Voltage controlled oscillator, 24,
discontinuity, 55, 77, 203, 216, 366, 384, 386
291
Valence band offset, 39, 49, 52, Wireless communication, 363
53, 57, 58, 90, 94, 197, 203
Velocity overshoot, 162, 199, 216 X-ray diffraction, 51, 274

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C K Maiti and G A Armstrong

Indian Institute of Technology,

Institute of Physics Publishing

All rights reserved. No part of this publication may be reproduced,

British Library Cataloguing-in-Publication Data

Consultant Editor: S C Jain

Published by Institute of Physics Publishing, wholly owned by The

5.5 Low-temperature simulation 172

8 METALLIZATION AND HETEROSTRUCTURE

10.7 Commercially available products 388

Since the ﬁrst report of SiGe heterostructure bipolar transistors (HBTs) in

eventually be applicable in the frequency range above 30 GHz, where GaAs

of heterojunction ﬁeld-eﬀect transistors (HFETs). Strategies for the

carbide is a suitable emitter material, since it has a wider bandgap of

Figure 1.2. Capacity of backbone network. (After Nakamura M 1998 IEEE

weaknesses. Bipolar transistors with their high transconductance have

internet host counts doubling every ﬁve to seven months, there is a

Figure 1.4. Variation of delay components of a bipolar circuit versus collector

However, power consumption and dissipation restrictions in digital

1.1. EVOLUTION OF BIPOLAR TECHNOLOGY

The FET represents a class of devices (including MOSFETs, metal–

time in an ECL ring oscillator at a voltage swing of 250 mV has been

1.2. HETEROJUNCTION BIPOLAR TRANSISTORS

The idea of varying the bandgap in a bipolar transistor structure to increase

of the heterojunctions. The heterojunction oﬀers a larger set of device

Figure 1.7. Comparison of cut-oﬀ frequency, fT , as a function of base width

Figure 1.8. Comparison of maximum frequency of oscillation as a function of

III–V technology is a superior option. In overall radio frequency (RF)

Si BJT SiGe HBT GaAs FET

1.3. DEVELOPMENT OF SIGE/SIGEC HBT TECHNOLOGY

As silicon BJTs reach their fundamental limits on speed because of the

• reduction in base transit time—resulting in higher frequency

The design of a SiGe HBT, for a particular technology generation, is

leads to a new class of semiconducting materials (SiGeC) [49, 50]. This

Table 1.3. Possible applications of C-containing Si and SiGe ﬁlms. (After

Material advantages Possible device applications

grown pseudomorphically onto Si(001) and their applications have been

1.4. HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

The Semiconductor Industry Association (SIA) roadmap for CMOS

the most successful IGFETs are still silicon-based MOSFETs. MOSFETs

of 420 mS mm−1 , which is about a factor of two higher than Si

1.5. VERTICAL HETEROSTRUCTURE FETS

1.6. OPTOELECTRONIC DEVICES

The optoelectronics realm has traditionally been reserved to III–V

ﬁeld for SiGe devices, although development is hindered by the lack of a

1.7. APPLICATIONS OF SIGE HBTS

The revolution in wireless communications has been brought about by

Figure 1.11. Wireless system trends. (After Muraguchi M 1999 Solid-State

Figure 1.12. Selected high-frequency applications and allocated frequency

broad range of requirements including noise ﬁgure, linearity, gain, phase

Reference Circuit type Results

RF applications require circuit operation at frequencies up to 30 GHz,

An excellent review of the application-driven origins of SiGe

This introductory chapter has described the evolution of SiGe technology

and modelling of polysilicon emitter contacts for VLSI bipolar transistors

J. Electrochem. Soc. 135 1255–60

[43] Oda K, Ohue E, Tanabe M, Shimamoto H, Onai T and Washio K 1997

[77] Samavedam S B, Currie M T, Langdo T A and Fitzgerald E A 1998 High-

Stein K, Hueckel G, Kermarrec C, Tice T, Fitzgibbons G, Walter K,

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