Lecture 4

Wafer Clean and Gettering

Lecture 4: Wafer Clean <1>

 Contamination
• Particles  Oxide breakdown,
metal bridging, poly-Si
• Metallic contaminants bridging
 Low breakdown, VT
shift, low lifetimes,
junction leakage
• Organic contaminants  Change in oxidation
rates, change in
deposition rates
• Surface roughness  Low breakdown
voltages because of
Particl e s
Na Cu
high fields, low mobility
due to interface
Fe Au
Ph otore sist
scattering
N, P
S i O2 or oth e r th in fil m s In te rcon n e ct Me tal

S i li con W afe r

Lecture 4: Wafer Clean <2>

Cleaning Requirements

Lecture 4: Wafer Clean <3>

 RCA Wafer Cleaning
H2 SO4 /H2 O2 120 - 150C Strips organics
1:1 to 4:1 10 min especially photoresist

HF/H2 O Room T Strips chemical

1:10 to 1:50 1 min oxide

DI H2 O Rinse Room T

NH4 OH/H2 O2 /H2 O 80 - 90C Strips organics,

1:1:5 to 0.05:1:5 10 min metals and particles
SC-1
• RCA clean is “standard process”
used to remove organics, heavy
DI H2O Rinse Room T metals and alkali ions.

• Ultrasonic agitation is used to

HCl/H2 O2 /H2 O dislodge particles.
80 - 90C Strips alkali ions
1:1:6 10 min and metals
SC-2

DI H2 O Rinse Room T

Lecture 4: Wafer Clean <4>

 Modeling Wafer Cleaning
• Cleaning involves removing particles, organics (photoresist) and metals from
wafer surfaces.
• Particles are largely removed by ultrasonic agitation during cleaning.
• Organics like photoresists are removed in an O2 plasma or in H2SO4/H2O2 solutions.
• The “RCA clean” is used to remove metals and any remaining organics.
• Metal cleaning can be understood in terms of the following chemistry.

Si  2H 2 O  SiO 2  4H   4e  (5)

M  Mz  ze  (6)




• If we have a water solution with a Si wafer and metal atoms and ions, the
stronger reaction will dominate.
• Generally (6) is driven to the left and (5) to the right so that SiO 2 is formed
and M plates out on the wafer.
• Good cleaning solutions drive (6) to the right since M+ is soluble and will be
desorbed from the wafer surface.

Lecture 4: Wafer Clean <5>

 Oxidant/ Standard Oxidation-Reduction Reaction
Reductant Oxidation
Potential (volts)
Mn2+/Mn 1.05 2 
Mn  Mn  2e
SiO2/Si 0.84  
Si  2H 2 O  SiO2  4H  4e
3 0.71 3 
Cr /Cr Cr  Cr  3e
2 0.25 2 
Ni /Ni Ni  Ni  2e
3 0.17 3 
Fe /Fe Fe  Fe  3e
H 2 SO 4 /H2SO3 -0.20 H2 O  H2 SO3  H2SO4  2H   2e 
2 -0.34 2 
Cu /Cu Cu  Cu  2e
O 2 /H2O -1.23  
2H 2O  O 2  4H  2e
3 -1.42 3 
Au /Au Au  Au  3e
H 2 O 2 / H2 O -1.77  
2H 2O  H 2 O 2  2H  2e
O 3 /O2 -2.07 O2  H2O  O3  2H  2e 

• The strongest oxidants are at the bottom (H2O2 and O3). These reactions go to
the left grabbing e- and forcing (6) to the right.

• Fundamentally the RCA clean works by using H2O2 as a strong oxidant.

Lecture 4: Wafer Clean <6>

 Organic Removal

• Photoresist residue is one of the largest sources of

organic contamination. There are two main ways
to remove organic residue.
– Ozone/ashing→dry process that uses very strong oxidizing
agents. Essentially you burn the organic residue converting
everything to CO2
– Second method is a wet chemical process
• H2SO4:H2O2 (3:1) at 120°C (SPM)

• Both of these processes leave a chemical native

oxide on silicon.

Lecture 4: Wafer Clean <7>

 SC1
• Wafer cleaning technology has been based on RCA
clean-up technology for years.*
• Sequential cleaning process is based on H2O2
solutions at low and high pH*
• The first solution SC1 (standard cleaning 1) is based
on NH4OH:H2O2:H2O →usually 1:1:5 at 75°C.
– High pH solution removes organic materials, and some
particles, by oxidation.
– H2O2 is a very strong oxidizing agent and NH4OH acts to
solvate the oxidized material.
– The NH4+ also complexes some group I and group II metals
like Cu, Ag, Ni, and Co.

* W. Kern, Handbook of Semiconductor Wafer Cleaning Technology (1993)

Lecture 4: Wafer Clean <8>
 SC2
• The second part of the cleanup is the
low pH solution, SC2
– HCl:H2O2:H2O at 1:1:6 at 70°C.
– Solution is primarily used to remove heavy
metals
– The peroxide oxidizes the metal and the
Cl¯ complexes it

Lecture 4: Wafer Clean <9>

 Particle Removal

• The best approach is to make sure you never get

particles on the wafer
– Ultra-clean environments: Class 1 cleanrooms
• <1 particle/ft3 that is >0.12μm diameter
– FOUP box (front opening unified pod)

– Very low particle count solutions (particles / liter

of solution)
≥0.2μm ≥0.5μm
• NH4OH 200 30
• H2O2 50 10
• HF 1 0
• HCl 5 1
• H2SO4 500 50

Lecture 4: Wafer Clean <10>

 Megasonic Cleaning

• One of the more effective methods for removing

particles
• Uses a transducer operating at 850-900 kHz and up
to 300 W.
• Usually done in SC1 solution.
• High pH solutions work best for removing particles.
• Have to be careful to not let the [H2O2] get too low
because NH4OH will etch the silicon surface and
increase roughness.

Lecture 4: Wafer Clean <11>

• Other cleaning methods are
HF:H2O2:H2O and HF:H2O (≈1%HF)
– HF based cleaning solutions are
particularly good at removing Ca.
– Ca has been shown to be a bad actor in
gate oxide degradation and breakdown
– remember GOI data on Ca
– HF – last -> process leaves a H-terminated
surface which can be stable for hours, as
compared to a non-passivated Si surface
which oxidizes immediately
Lecture 4: Wafer Clean <12>
 Surface Roughness

• As gate oxide thickness is reduce to 10Ǻ (65 nm

devices), micro-roughness needs to be controlled
at the atomic level.
• SC1 is particularly bad for roughening the surface
because the NH4OH etches silicon (especially if
[H2O2] is too low).
• You can reduce the effect by reducing the amount
of NH4OH, reducing the temperature, and reducing
the time→all of which reduce the effectiveness of
cleaning.
• Micro-roughness reduces mobility (interface
scattering) and gate oxide reliability

Lecture 4: Wafer Clean <13>

 Native Oxide

• Example-clean wafer exposed to cleanroom air

containing 12% H2O will grow 6.7Ǻ in one week.
• Dissolved O2 in DI-water is also an issue in enhancing
native oxide growth.
– A wafer sitting in DI water with 9 ppm D.O. will grow 15Ǻ of
oxide in 3 hours (compared to 2Ǻ if D.O.is 0.04 ppm.)

Lecture 4: Wafer Clean <14>

 GOI: Gate Oxide Integrity
• From device
manufacturer’s point of
view : Original Interface
oxide quality affects Poly/Al
MOS device reliability
SiO2
and stability.
• From silicon
manufacturer’s point of Silicon
view: surface
defects and crystal
defects affect oxide
quality. Backside contact

Lecture 4: Wafer Clean <15>

 Surface Metal Contamination :
effect on GOI

Ca sensitivity also observed in MEMC experiments

Takiyama et al Nippon Steel, Semiconductor Silicon 1994.

Lecture 4: Wafer Clean <16>

 Surface Metal Contamination :
effect on GOI

Takiyama et al Nippon Steel, Semiconductor Silicon 1994.

Lecture 4: Wafer Clean <17>

 Modeling Particle Contamination and Yield
1
• ≈ 75% of yield loss in modern VLSI fabs
is due to particle contamination.

Probability of Particle
0.8 • Yield models depend on information

Causing Yield Loss

Particle Density

about the distribution of particles.

0.6
• Particles on the order of 0.1 - 0.3 µm are
0.4 the most troublesome:
• larger particles precipitate easily
0.2
• smaller ones coagulate into larger
particles
0.1-0.3
?0.1 - 0.3μm
祄 Particle Diameter

• Yields are described by Poisson statistics in the simplest case.

Y  exp  ACD O (3)

where AC is the critical area and DO the defect density.

 independent randomly distributed defects and often

• This model assumes
underpredicts yields.

Lecture 4: Wafer Clean <18>

• Use of negative binomial statistics eliminates these assumptions and is more
accurate.
1
Y (4)
 A C D O C
1  
 C 

where C is a measure of the particle spatial distribution (clustering factor).

1

Negative Binomial (C = 2)
0.1
Chip Yeld

Negative Binomial (C = 10)

0.01

-2
DO = 1 cm Poisson
0.001

0.0001
0 2 4 6 8 10 12
2
Chip Area (cm )

Lecture 4: Wafer Clean <19>

 19 97 20 06 20 12
1
Do = 0.01 cm-2

Do = 0.1 cm-2
Chip yield
0. 1

Do = 1 cm-2

0. 0 1
0 5 10 15 20
Chip Area (cm2)

• Vertical lines are estimated chip sizes (from the ITRS).

• Note that defect densities will need to be extremely small in the future to
achieve the high yields required for economic IC manufacturing.

Lecture 4: Wafer Clean <20>

 Contamination Reduction: Gettering
Gettering is used to remove metal ions and alkali ions from device active regions.
Noble
Period A
Gases
I Alkali Ions
1 2
1 H He
A
1.008 II III
A
IV
A
V
A A
VI VII
A 4.003
3 4 5 6 7 8 9 10
2 Li Be
Deep Level Impurites in Silicon B C N O F Ne
6.941 9.012 10.81 12.01 14.01 16.00 19.00 20.18
11 12 VIII 13 14 15 16 17 18
3 Na Mg B B B B B
Al Si P S Cl Ar
22.99 24.31 III IV V VI VII I
B B
II 26.98 28.09 30.97 32.06 35.45 39.95
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
4 K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
39.10 40.08 44.96 47.88 50.94 51.99 54.94 55.85 58.93 58.69 63.55 65.39 69.72 72.59 74.92 78.96 79.90 83.80
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
5 Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
85.47 87.62 88.91 91.22 92.91 95.94 98 101.1 102.9 106.4 107.9 112.4 114.8 118.7 121.8 127.6 126.9 131.3
55 56 57 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
6 Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
132.9 137.3 138.9 178.5 180.8 183.9 186.2 190.2 192.2 195.1 197.0 200.6 204.4 207.2 209.0 209 210 222
87 88 89 104 105 106 107

Shallow Donors
Semiconductors
Shallow Acceptors
7 Fr Ra Ac Unq Unp Unh Uns
223 226 227.0 261 262 263 262

• For the alkali ions, gettering generally uses dielectric layers on the topside
(PSG or barrier Si3N4 layers).
• For metal ions, gettering generally uses traps on the wafer backside or in the
wafer bulk.
• Backside = extrinsic gettering. Bulk = intrinsic gettering.

Lecture 4: Wafer Clean <21>

 .

PSG Layer T (C)

Devices in near 1200 1100 1000 900 800
surface region Cu
10 – 20 um 10 -4
Denuded Zone Au
I
or Epi Layer 10 -6 Fe
Cr
Interstitial
10 -8 Pt Diffusers

Diffusivity (cm 2 sec 1)

10 -10
Ti
Intrinsic 10 -12
Gettering Au
S
Region 500+ um 10 -14
B, P
10 -16 As
Si

10 -18
Dopants

10 -20

-
Backside 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Gettering 1000/T (Kelvin)
Region

• Heavy metal gettering relies on:

• Metals diffusing very rapidly in silicon.
• Metals segregating to “trap” sites.

Lecture 4: Wafer Clean <22>

 Outdiffusion
1100
Precipitation

900
T

Nucleation

500
Time

(See Chapter 3 class notes)

• “Trap” sites can be created by SiO2 precipitates

(intrinsic gettering), or by backside damage
(extrinsic gettering).

• In intrinsic gettering, CZ silicon is used and SiO2

SiO2 precipitates (white dots) in bulk precipitates are formed in the wafer bulk through
of wafer. temperature cycling at the start of the process.

Lecture 4: Wafer Clean <23>

 Modeling Gettering
• Gettering consists of
1. Making metal atoms mobile.
2. Migration of these atoms to
trapping sites.
3. Trapping of atoms.
• Step 1 generally happens by kicking
out the substitutional atom into an
interstitial site. One possible reaction is:

Au S  I  Au i
• Step 2 usually happens easily once the
metal is interstitial since most metals
diffuse rapidly in this form.
 3 happens because heavy metals
• Step
segregate preferentially to damaged
regions or to N+ regions or pair with
effective getters like P (AuP pairs).
Textbook (See text.)
P190-191 • In intrinsic gettering, the metal atoms
segregate to dislocations around SiO2
Eq. 4.19-4.26 precipitates.

Lecture 4: Wafer Clean <24>