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Chapter 2

Introduction to
Integrated Circuit Fabrication

References:
Hong Xiao, Introduction to Semiconductor Manufacturing Technology, 2nd Ed., SPIE Press, 2012
Plummer, Deal and Griffin, Silicon VLSI Technology- Fundamental, Practice and Modeling, Prentice Hall, 2000
Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford, 2001
Quirk and Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2001
C.Y. Chang and S.M. Sze, ULSI Technology, McGraw-Hill, 1996
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Wafer Process Flow

Materials IC Fab

Dielectric Test
Metallization CMP
depositio
Wafers n

Thermal Etch Packaging


Implant
Processes PR strip PR strip
Masks

Photo- Final Test


lithography

Design

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Fab Cost
 Clean room
 Equipment, usually > $2M per tool
 Materials, high purity, ultra high purity
 Facilities
 People, training and pay

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Yield
• Determine whether a fab is marking a profit or losing money.
• Related to environment, materials, equipment, processes,
and people.

• Wafer Yield

• Die Yield

• Packaging Yield

• Overall Yield
YT = YW×YD×YC

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Yield and Profit Margin

Yield and Profit Margin

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Yield and Profit Margin

• For the same IC fab, if the die yield is 90%, wafer and
packaging yield are 100%, and capacity is 20,000 wafer per
month, what is the total profit margin per month?

• If yield for every process step is 99%, what is the overall


processing yield after 500 process steps?

0.99500 = 0.0066= 0.66% (Almost no yield)

Defects and Yield

Where Y is the overall yield, D is the


killer defect density, A is the chip area, Relationship between die size and die yield
and n is the number of process step.

Wafer with (a)test die and (b) test structure in scribe lines
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Types of Contamination

• Particles
• Metallic Impurities
• Organic Contamination
• Native Oxides
• Electrostatic Discharge

Clean Room

• Artificial environment with low particle counts


• Smaller device needs higher grade clean room
• Less particle, more expensive to build

Clean Room Class


• Class 10 is defined as less than 10 particles with
diameter larger than 0.5 μm per cubic foot.
• Class 1 is defined as less than 1 such particles per
cubic foot.
• The cleanest class: M-1; less than 10 particles
larger than 0.5 μm per cubic meter or less than
0.28 particles larger than 0.5 μm per cubic foot. 10
Cleanroom Classes
100000

# of particles / ft3 10000

1000

100

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0.1
0.1 1.0 10
Particle size in micron
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Definition of Airborne Particulate Cleanliness Class


per Fed. Std. 209E

Particles/ft3
Class
0.1 μm 0.2 μm 0.3 μm 0.5 μm 5 μm

M-1 9.8 2.12 0.865 0.28

1 35 7.5 3 1

10 350 75 30 10

100 750 300 100

1000 1000 7

10000 10000 70

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Effect of Particle Contamination
on a Photomask

Mask and a Reticle 13

Effect of Particle Contamination


during Ion Implantation Process

Ion Beam

Dopant in PR
Particle

Photoresist

Screen Oxide
Partially Implanted Junctions

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Cleanroom Structure
Mini-Environment Cleanroom

HEPA Filter : high-efficiency particulate air Filter

 Keep a laminar flow is very important to achieve better than class-100 cleanliness.
 The higher-class areas have a higher pressure than the lower-class areas.
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Gowning Area

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Three Basic Strategies for Eliminating
Particles from Cleanrooms

1. Start out with a cleanroom that is free of


particles.
2. Minimize the introduction of particles into the
cleanroom through equipment, tools, personnel
and cleanroom supplies.
3. Continuously monitor the cleanroom for particles
for timely response to cleaning maintenance.

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IC Process Flow

Thin film growth, dep.


and/or CMP

Photolithography

Etching Ion Implantation

PR Stripping PR Stripping

RTA or Diffusion

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Diffusion

• Primary tools:
– High-temperature diffusion furnace
• ~ 1200 oC; for oxidation, diffusion, deposition, anneals
& alloys
– Wet cleaning station
• For removing contaminations on the wafer surface
before the high-temperature processes in the furnaces

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Simplified Schematic of High-Temperature


Furnace
Thermocouple
Temperature measurements Gas flow
Process gas
controller controller

Quartz tube

Heater 1
Temperature-
setting voltages
Heater 2
Three-zone
Heating
Heater 3 Elements

Exhaust
Pressure
controller
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Wafer Cleaning Equipment
• Cleaning station • Ultrasonic scrubbing

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Photolithography

• Purpose: photograph the image of a circuit pattern


onto the photoresist that coats the wafer surface
• Photoresist is a light-sensitive chemical that captures
the image of a mask pattern resulting from exposure
to UV light. (negative & positive)
• Photolithography bay is lighted up by the yellow
fluorescent tubes.

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Photoresist
• Negative Resist
– Wafer image is opposite to mask image
– Exposed resist hardens and is insoluble
– Developer removes unexposed resist

• Positive Resist
– Mask image is the same as wafer image
– Exposed resist softens and is soluble
– Developer removes exposed resist

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Negative Lithography

Areas exposed to light become


crosslinked and resist the
Ultraviolet light developer chemical.
Chrome island on
glass mask Island
Exposed area of
photoresist
Window
Photoresist
Shadow on
photoresist

Photoresist
Oxide Oxide
Silicon substrate Silicon substrate

Resulting pattern after


the resist is developed.

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Positive Lithography

Ultraviolet light

Areas exposed to
light are dissolved.
Chrome island Shadow on
on glass mask photoresist Island
Window

photoresist
Photoresist

Exposed area
of photoresist
photoresist
Photoresist
oxide
Oxide oxide
Oxide
silicon
Silicon substrate
substrate silicon substrate
Silicon substrate

Resulting pattern after


the resist is developed.

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Simplified Schematic of a Photolithography Processing


Module
Figure 9.4
Wafer Stepper
(Alignment/Exposure System)
Vapor Resist Develop- Edge-Bead
Load Station Prime Coat Rinse Removal Transfer Station

Wafer
Cassettes Wafer Transfer System

Soft Cool Cool Hard


Bake Plate Plate Bake

Coater/developer track Stepper

** Contamination control is important here!!


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Center of the wafer fab
Wafer Fabrication (front-end)

Wafer Start

Thin Films Polish


Unpatterned
Wafer

Completed Wafer Diffusion Photo Etch

Test/Sort
Implant

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Etch

• Purpose: creating a permanent pattern on the wafer


in areas not protected by the photoresist pattern
• Tools:
– plasma etcher
– plasma stripper: remove the photoresist
– wet cleaning station

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Simplified Schematic of Dry Plasma Etcher
Etchant gas entering
Gas distribution baffle gas inlet High-frequency energy
Anode electrode
RF coax cable
Photon
Electromagnetic field
- Glow discharge
Free electron - e λ (plasma)
e
Vacuum gauge
Ion sheath e
- Wafer

Cathode electrode
+ R
Chamber wall
Flow of byproducts and
process gases
Positive ion Radical
chemical
Exhaust to
vacuum pump
Vacuum line

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Ion Implant
Simplified Schematic of Ion Implanter

Gas cabinet
Ion source
Filament
Mass resolving slit
Plasma
Acceleration column
Extraction assembly
Beamline tube
Analyzing magnet

Ion beam
Process chamber
Lighter ions

Heavy
ions
Scanning
disk
Graphite

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Thin Films
• Purpose: deposition of dielectric and metal layers
• Operating at lower temperature than the furnaces
• Tools:
– Chemical vapor deposition (CVD)
– Metal sputtering (physical vapor deposition; PVD)
– Spin-on-glass (SOG): for planarizing the wafer surface
– Rapid thermal processor (RTP):
• annealing ion implant damage of the Si substrates & metal alloy
processing
• RTP has the ability to reach temperature quickly ~1000oC and
maintain the setpoint for several seconds
– Wet cleaning station

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Simplified Schematics of CVD Processing System

Gas inlet

Process chamber Capacitive-


coupled RF input

Chemical vapor deposition


Wafer
Susceptor

Exhaust

Heat lamps

CVD cluster tool


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Polish
Chemical Mechanical Planarization (CMP)

• Purpose: to planarize the top surface of the wafer by


lowering the high topograhy to be level with the
lower surface areas of the wafer
• CMP combines chemical etching and mechanical
abrading to remove a desired amount of the upper
layer of the wafer.
• Other tools: wafer scrubbers & cleaning stations

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Schematic of Chemical Mechanical Planarization


(CMP)

Downforce
Wafer carrier Polishing pad
Slurry dispenser
Wafer
Polishing
Rotating slurry
platen

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3D packaging
Through-Silicon Via (TSV)

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3D packaging
Through-Silicon Via (TSV)

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3D packaging
Through-Silicon Via (TSV)

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