Chapter 3

Semiconductor Basics and

Wafer Manufacturing
References:
Hong Xiao, Introduction to Semiconductor Manufacturing Technology, 2nd Ed., SPIE Press, 2012
Plummer, Deal and Griffin, Silicon VLSI Technology- Fundamental, Practice and Modeling,
Prentice Hall, 2000
Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford, 2001
Quirk and Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2001
Donald A. Neamen, Semiconductor Physics and Devices - Basic Principles 4th ed., McGraw-Hill,
2012
1
B. G. Streetman and S. Banerjee, Solid State Electronic Devices, 7th ed., Pearson, 2016

Classifying Materials
Energy Band Gaps
Electron Energy Electron Energy Electron Energy

Conduction
Band Conduction
Band
Conduction Overlapping bands
Energy Gap
Energy Gap

Band - little energy is

needed for
Valence Band conduction

Valence Band
Valence Band

Insulator Conductor Semiconductor

2
 What is Semiconductor

• Conductivity between conductor and

insulator
• Conductivity can be controlled by dopant
• Silicon and germanium
• Compound semiconductors
– SiGe, SiC
– GaAs, InP, etc.

Semiconductor Substrate and Dopants

Substrate

P-type
Dopant

N-type Dopants
4
Orbital Structure of an Atom and Energy Band

6
Schaffer, et al., The Science and Design of Engineering Materials, 2nd Ed., McGraw-Hill, 1999.
 Silicon

•Ten of fourteen electrons occupy deeplying energy levels

close to the nucleus. The four remaining valence electrons
are relatively weakly bound and are the electrons involved
in chemical reactions.
•As the interatomic distance decreases, the 3s and 3p states
interact and overlap. At the equilibrium interatomic
distance, the bands have again split. Four quantum states
per atom are in the lower band and four quantum states per
atom are in the upper band. 7

• At 0K, electrons are in the lowest energy state, so that all

states n the lower band (the valence band) will be full and all
states in the upper band ( the conduction band) will be empty.
• The bandgap energy (Eg) between the top of the valence band
and the bottom of the conduction band is the width of
forbidden energy band.

8
 Band Gap and Resistivity

Eg = 1.1 eV Eg = 8 eV

Aluminum Sodium Silicon Silicon dioxide

2.7 μΩ•cm 4.7 μΩ•cm ~ 1010 μΩ•cm > 1020 μΩ•cm

Conductors Semiconductor Insulator

9

Covalent Bonding of Pure Silicon

Si Si Si Si Si

Si Si Si Si Si

Si Si Si Si Si

Si Si Si Si Si

Si Si Si Si Si

Silicon atoms share valence electrons

to form insulator-like bonds.

10
 Why Silicon

• Abundant, 25% of the earth’s crust (inexpensive)

• Higher melting temperature (Tm,Si:1412oC; Tm,Ge: 937oC)
for wider processing range (thermal stability)
• Wider temperature range of operation (Eg,Si: 1.12 eV;
Eg,Ge: 0.66 eV)
• Nature growth of silicon dioxide (SiO2)
– A high quality, stable electronic insulator material and
strong dielectric for MOS
– A good chemical barrier to protect silicon from external
contaminants
– Mechanical properties similar to Si
– Can be used as diffusion doping mask
11

Formation of SiO2 on Silicon Wafer

• Native oxide
• Oxidation
• Growth

Silicon dioxide (SiO2)

Silicon wafer

12
 Doping of Silicon
Deposition Step Drive-in & Diffusion Step

dopant dispenser

wafer substrate Activation

dopant layer Step
diffusion of dopant
atoms through silicon Si Si PP

wafer PP Si Si

Si Si P

13

Silicon Dopants
Acceptor Impurities Semiconductor Donor Impurities

Group III (p-type) Group IV Group V (n-type)

Boron 5 Carbon 6 Nitrogen 7

Aluminum 13 Silicon 14 Phosphorus 15

Gallium 31 Germanium 32 Arsenic 33

Indium 49 Tin 50 Antimony 51

* Items underlined are the most commonly used in silicon-based IC manufacturing.

14
Electrons in N-Type Silicon with Phosphorus Dopant

Si Si Si Si Si

Si Si Si P Si Excess electron (-)

Si P Si Si Si Phosphorus atom
serves as n-type
dopant
Si Si Si P Si

Si Si Si Si Si

Donor atoms provide excess electrons

to form n-type silicon.

15

Donor Energy Band

16
 Conduction in n-Type Silicon
Positive terminal from
power supply

Negative terminal
from power supply

Free electrons flow toward

positive terminal.

17

Holes in p-Type Silicon with Boron Dopant

Si Si Si Si Si

Si Si Si B Si + Hole

Boron atom serves

Si B Si Si Si as p-type dopant

Si Si Si B Si

Si Si Si Si Si

Acceptor atoms provide a deficiency

of electrons to form p-type silicon.

18
 Accepter Energy Band and Hole Movement

19

Conduction in p-Type Silicon

Positive terminal from
voltage supply

Negative terminal
from voltage supply

-Electrons flow toward

positive terminal

+Holes flow toward

negative terminal

20
 Dopant Concentration Nomenclature

Intrinsic carrier concentration (ni) for Si at 300K: 1.5 x 1010 cm-3

21

The Temperature Dependence of Electron

Concentration in a Doped Semiconductor

22
 Silicon Resistivity Versus Dopant Concentration
1021
• Higher dopant concentration,
1020 more carriers (electrons or
holes)
Dopant Concentration (atoms/cm3)

1019 • Higher conductivity, lower

resistivity
1018
• Electrons move faster than
1017 holes
n-type p-type • N-type silicon has lower
1016 resistivity than p-type silicon
at the same dopant
1015 concentration
1014

1013
10-3 10-2 10-1 100 101 102 103
Electrical Resistivity (ohm-cm)

Redrawn from VLSI Fabrication Principles, Silicon and Gallium Arsenide, John Wiley & Sons, Inc.
23

Atomic Order of a Crystal Structure

24
Amorphous Atomic Structure

25

Unit Cell in 3-D Structure

Unit cell

26
 Faced-centered Cubic (FCC) Unit Cell

27

Silicon Unit Cell: FCC Diamond Structure

28
 Diamond Structure

29

Unit Cell of Single Crystal Silicon

30
Polycrystalline and Monocrystalline Structures

Polycrystalline structure Monocrystalline structure

31

Axes of Orientation for Unit Cells

Z

0 Y
1

1
X
32
 Miller Indices of Crystal Planes

Z Z Z

Y Y Y

X X X
(100) (110) (111)

33

(100) Orientation Plane

Basic lattice cell Atom

34
 (111) Orientation Plane

Basic lattice cell Silicon atom

35

(100) Wafer Etch Pits

36
 (111) Wafer Etch Pits

37

Principle silicon crystal orientations:

(111) & (100)
• Largest No. of atom /cm2: {111}
• Lowest No. of atom /cm2: {100}

• {111} planes oxidized faster than {100}

• {111} surfaces have higher densities of electrical
defect (interface states)
• Dopant diffusion coefficients

• (100) silicon is dominant in manufacturing today due

to the superior electronic properties of the Si (100)
/SiO2 interface.

38
 Semiconductor-Grade Silicon

39

From Sand to Wafer

• Quartz sand: silicon dioxide

• Sand to metallic grade silicon (MGS)
• React MGS powder with HCl to form TCS
• Purify TCS by vaporization and
condensation
• React TCS to H2 to form polysilicon (EGS)
• Melt EGS and pull single crystal ingot

40
 From Sand to Wafer (cont.)

• Cut end, polish side, and make notch or flat

• Saw ingot into wafers
• Edge rounding, lap, wet etch, and CMP
• Laser scribe

• Epitaxy deposition

41

From Sand to Silicon

• Quartz sand: silicon dioxide

• Sand to crude silicon or metallurgical grade
silicon (MGS, 98-99%)
Heat (2000 ° C)
SiO2 + C → Si + CO2
Sand Carbon MGS Carbon Dioxide

42
 Silicon Purification I
• React MGS powder with HCl to form TCS

Hydrochloride Reactor,
300 °C

Si + HCl Silicon MGS

Powder
→ SiHCl3 (TCS)
Condenser
Filters

Pure TCS with

Purifier
99.9999999%
43

Silicon Purification II
• Polysilicon Deposition, EGS
Process
Chamber EGS
H2

H2 and TCS
Liquid
TCS TCS+H2→EGS+HCl

Carrier gas bubbles

Heat (1100 ° C)

SiHCl 3 + H2 → Si + 3HCl
TCS Hydrogen EGS Hydrochloride 44
 Electronic Grade Silicon

45

CZ (Czochralski) Crystal Puller

Crystal puller
and rotation
mechanism Crystal seed

Ar ambient
Single crystal Molten
silicon polysilicon
(>1417oC)
Quartz Heat shield
crucible
Carbon heating
element Water jacket

46
Silicon Ingot Grown by CZ Method

Photograph courtesy of Kayex Corp., 300 mm Si ingot

47

CZ Crystal Puller

Photograph courtesy of Kayex Corp., 300 mm Si crystal puller

48
 CZ Crystal Pullers

Mitsubish Materials Silicon

49

CZ Crystal Pulling

• Crystal Orientation determined by that of seed

• Diameter controlled by the temperature and pulling rate
• Impurities: oxygen & carbon from the crucible materials
16 18 -3 16 17 -3
oxygen: 1.0 x 10 – 1.5 x 10 cm ; carbon: 2.0 x 10 – 1.0 x 10 cm 50
 Float Zone Crystal Growth
Gas inlet (inert)

Chuck

Polycrystalline
rod (silicon) Molten zone

Traveling
RF RF coil

Seed crystal
Chuck
Inert gas out

51

Floating Zone Method

Poly Si
Molten Silicon
Rod
Heating Coils
Movement Heating
Coils

Single Crystal
Silicon

Seed Crystal • Higher silicon purity

• Difficult getting
dislocation-free crystal
• More expensive 52
 Comparison of the Two Methods

• CZ method is more popular

– Cheaper
– Larger wafer size (300 mm in production)
– Reusable materials
• Floating Zone
– Pure silicon crystal (no crucible)
– More expensive, smaller wafer size (150 mm)
– Mainly for power devices.

53

Wafer Diameter Trends

300 mm

200 mm

150 mm
125 mm
100 mm

75 mm

3″ 4″ 5″ 6″ 8″ 12″
2000
1950s 54
 Wafer Dimensions & Attributes

300-mm diameter wafer:

• ingot : 1 meter long
•150~300 kg SG silicon needed

55

Reasons for Large Ingot Diameter

• The cost benefits to the wafer fabrication

process due to increasing the wafer diameter
– Improve equipment productivity for less handling per
chip and less processing time per chip due to more
chip per wafer (e.g. from 200 mm to 300 mm, 30%
fabrication cost down per chip)
– Translate into higher production yield due to fewer
chip near the edge of the wafer
– A benefit from tool repeatability from chip to chip
since more chips are exposed to the same process
conditions
56
 Crystal Defects in Silicon
A crystal defect (microdefect) is any
interruption in the repetitive nature of the
unit cell crystal structure.

Three general types of crystal defects in silicon:

1. Point defects

2. Dislocations
3. Gross defects

57

Illustration of the Defects

Impurity on substitutional site Silicon Atom

Impurity in
Interstitial Site
Silicon
Interstitial

Vacancy or Schottky Defect Frenkel Defect

58
 Illustration of the Defects

59

Crystal Slip
(Gross Defects)

(a) (b) (c)

Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon and

Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 49

60
 Crystal Twin Planes
(Gross Defects)

X X’

Redrawn from Sorab K. Ghandi, VLSI Fabrication Principles: Silicon and

Gallium Arsenide, 2nd edition, New York, Wiley, 1994, page 55

61

Basic Process Steps for Wafer Preparation

Wafer Lapping
Crystal Growth and Edge Grind Cleaning

Shaping Etching Inspection

Wafer Slicing Polishing Packaging

62
 Ingot Diameter Grind

Preparing crystal ingot for grinding

Diameter
grind

Flat grind

63

Wafer Identifying Flats

P-type (111) P-type (100)

N-type (111) N-type (100)

64
 Wafer Notch and Laser Scribe
for wafer 200 mm and larger

Notch Scribed identification number

65

Internal Diameter Saw

Internal diameter
wafer saw

66
 Wafer Sawing

Orientation Coolant
Notch
Crystal Ingot
Saw Blade Ingot
Movement

Diamond Coating

67

Parameters of Silicon Wafer

Wafer Size (mm) Thickness (μm) Area (cm 2) Weight (grams)

50.8 (2 in) 279 20.26 1.32
76.2 (3in) 381 45.61 4.05
100 525 78.65 9.67
125 625 112.72 17.87
150 675 176.72 27.82
200 725 314.16 52,98
300 775 706.21 127.62

68
 Wafer Lapping

• Rough polished
• conventional, abrasive, slurry-lapping
• To remove majority of surface damage
• To create a flat surface

69

Wafer Edge Rounding

Wafer movement
Wafer

Wafer Before Edge Rounding

Wafer After Edge Rounding

70
 Polished Wafer Edge

71

Chemical Etch of Wafer Surface

to Remove Damage

72
 Wet Etch

• Remove defects from wafer surface

• 4:1:3 mixture of HNO3 (79 wt% in H2O), HF (49
wt% in H2O), and pure CH3COOH.
• Chemical reaction:

3 Si + 4 HNO3 + 18 HF → 3 H2SiF6 + 4 NO + 8 H2O

73

Double-Sided Wafer Polish

Upper polishing pad

Wafer

Slurry
Lower polishing pad

74
 Chemical Mechanical Polishing

Pressure
Slurry
Wafer Holder
Wafer

Polishing Pad

75

Chemical Mechanical Polishing

76
 200 mm Wafer Thickness and Surface Roughness
Changes
76 μm
After Wafer Sawing
914 μm

76 μm
After Edge Rounding 914 μm
12.5 μm
After Lapping 814 μm
<2.5 μm
After Etch 750 μm
Virtually Defect Free
After CMP 725 μm
77

• Cleaning
• Wafer evaluation
• Packaging

78
 Quality Measures

• Physical
dimensions
• Flatness
• Microroughness
• Oxygen content
• Crystal defects
• Particles
• Bulk resistivity
79

Epitaxy

• Greek origin
• epi: upon
• taxy: orderly, arranged

• Epitaxial layer is a single crystal layer on a

single crystal substrate.
– Homoepitaxial layer, e.g. Si on Si
– Heteroepitaxial layer, e.g. GaN on ZnO

80
 Epitaxy: Purpose
• Improve device performance for CMOS and
DRAM because much lower oxygen, carbon
concentration than the wafer crystal.

Metal 1, Al•Cu
W
BPSG

STI n+ n+ USG p+ p+
P-Well N-Well
P-type Epitaxy Silicon
P-Wafer
81

Substrate Engineering

Silicon-On-Insulator (SOI)
• Better device isolation
• Higher speed
• Higher packing density
• Better performance
• Bonded
• Oxygen implantation
 CMOS on SOI Substrate

n+ source/drain p+ source/drain
Gate oxide

Polysilicon

p-Si STI n-Si USG

Buried oxide
Balk Si

Oxygen Implantation SOI

Oxygen Ion Implantation High temperature annealing

(a) (b)
 Bonded SOI

• Two wafers
• One grow oxide
• One implanted with hydrogen
• Bond two wafers at high temperature
• Hydrogen rich silicon has high wet etch rate
• Wet etch separates two wafers
• CMP to smooth wafer surface

Bonded SOI Formation Process

Hydrogen induced silicon voids

Anneal

Wet Etch

CMP 86
 Hybrid Orientation Technique

• Electron has higher mobility in <100> orientation

silicon
• Hole has higher mobility in <110> orientation
silicon
• Make NMOS and PMOS in different orientation of
single crystal silicon and optimize the device
performance.
• Not in mainstream because it is not cost-effective.

Hybrid Orientation SOI Wafer for CMOS

(a)

(b)

(c)

(d)