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filters is to remove the unwanted signal and reserve the wanted signal at
which are low-pass filter (LPF), high-pass filter (HPF), bandpass filter (BPF)
and band reject filter BRF). Figure 1-1 shows the frequency responses of
there are two popular types, which are Butterworth filter and Chebyshev
1-2
Chapter 1 Second Order Filters
appeared at the inner part of stopband and the attenuation of transition band
is not sharp enough. Chebyshev filter is also known as equal ripple filter
since the ripple is equally in its passband. There are no ripples in the
filter.
H ( j ) H ( j )
f f
fo fo
H ( j ) H ( j )
BW BW
f f
fo fo
Ripples
H ( j ) H ( j )
Ripples
f f
1-3
Analog Communication Trainer
active filter and passive filter. Early days, filter is formed by resistors,
capacitors and inductors, so this type of filter is called passive filter. Recent
used; therefore we called this type of filter as active filter. The advantages of
2. Since operation amplifier (OP) has high input impedance and low output
impedance, so the isolation is very good and can easily be used for series
application.
provides gain.
order low-pass filter, high-pass filter, bandpass filter and bandstop filter.
through and high frequency signal attenuate. Figure 1-3 shows the inverting
1-4
Chapter 1 Second Order Filters
1 1
Vout ( S )
SC RC 0 (1-1)
Vin ( S ) R S S
Where
1
o
RC
From equation (1-1), we know that the Miller integrator circuit is the
first order low-pass filter. If we want to design the second order active
amplifier.
Figure 1-4 shows the block diagram of the second order active
inverting amplifier and an adder. Assume that the output of the adder is A(s),
o 1
A (S) KVin (S) ( )A(S) (( o ) 2 )A (S)
S Q S
1
A (S) 1 ( o ) ( o ) 2 KVin (S)
Q S S
o 2 KVin (S)
Vout (S) ( ) A(S) ( o ) 2
S S 1 1 ( o ) ( o ) 2
Q S S
1-5
Analog Communication Trainer
R
Input
Vin A Output
Vout
1
1
Q
Input K o o
(Vin )
S
-1
A(S) S
Output
(Vout )
Figure 1-4 Block diagram of second order active low-pass filter.
low-pass filter, if we follow the block diagram to design the circuit, we can
Figure 1-5 shows the circuit diagram of the second order active
combine the adder and the first Miller integrator circuit by replacing an OP
(U1). So we can save an OP, but the calculation of the circuit parameters will
1-6
Chapter 1 Second Order Filters
C1 C 2 C
R6 R5 R4
R3 1
Vout (S) R1 R 3R 4C 2
Vin (S) S2 1 S 1
CR 2 R 3R 4C 2
R3 1
R1 R 3R 4 C 2
(1-3)
R 3R 4 1 1
S2 S
R 2 C R 3R 4 R 3R 4C 2
R3
R 2 10 k 15 k
C1 10 nF
C2
R1 12 V
R
(I/P) 6
R 10 nF
13 4
7.5 k
6 R5 15 k
14 15 k
12
7 10
5 15 k
12 V 8
U1:B
U1 : A 9
U1 : LM 348 U1:C
LPF O/P
1-7
Analog Communication Trainer
R3
K (1-4)
R1
1
0 (1-5)
C R 3R 4
R2
Q (1-6)
R 3R 4
From the circuit diagram at figure 1-5, R1, R2, R3, C1 and U1 : A not
only comprise a Miler integrator circuit, but also have the function of
input signal and the output signal of U1 : C . After that make a summation
frequency signal pass through and attenuate low frequency signal. Figure
1-8
Chapter 1 Second Order Filters
integrator circuits, an inverting amplifier and two adders. We can obtain the
transfer function as
Vout (S) KS 2
(1-7)
Vin (S)
S 2 0 S 02
Q
design and obtain the circuit of second order high-pass filter by following
Q K
1Q
o
KQ o
Input
(Vin ) -1
S S
K Output
(Vout )
R7
15 k
R3
15 k
C1
R5 C2
R1 2.2 nF
I/P R4 15 k 2.2 nF
2
7.5 k R6 12 V
1 15 k 6
3 7 9
U1 : A 15 k
5 8
R2 U1 : LM348 U1 : B 1
0 12 V
7.5 k
U1 : C
HPF O/P
1-9
Analog Communication Trainer
Figure 1-7 is the circuit diagram of second order high-pass filter, which
is based on the block diagram of figure 1-6. The first adder and the first Miler
operation amplifiers, but for the circuit parameters, the calculation will
C1 C 2 C
R7 R6 R5
R5 2 R5 1 R2
S
Vout (S) R2 CR 2 R 3 R 1R 4
(1-8)
Vin (S) 1 1
S2 S
R 3C R 4 R 5C 2
If assume R 1R 4 R 2 R 3 ,
Then
R5 2
S
Vout (S) R2
Vin (S) S2 1 S 1
R 3C R 4 R 5C 2
R5 2
S
R2
(1-9)
R 4R 5 S 1
S2
R3 C R 4 R 5 R 4 R 5C 2
1-10
Chapter 1 Second Order Filters
R5
K (1-10)
R2
1
o (1-11)
C R 4R 5
R3
Q (1-12)
R 4R 5
From figure 1-7, R1, R3, R7, C1 and U1 : A not only comprise a Miler
integrator circuit, but also have the function of weighted summer. The
objective is to multiply an individual weight for input signal and the output
summer circuit, which can multiply an individual weight for input signal
because of its pole overlapping, therefore the curve for frequency response
frequency signal attenuate, but enable a certain frequency band signal pass
1-11
Analog Communication Trainer
through. From Figure 1-8, we can see that the characteristic curve is a
f2 f 1 .
Voltage
Gain
(dB) BW
3 dB 3 dB
HPF LPF
f1 fo f2 Frequency (Hz)
1
1
Q
Input K o o
(Vin )
S
-1
S
Output
(Vout )
1-12
Chapter 1 Second Order Filters
Figure 1-9 shows the block diagram of the second order active
bandpass filter, which consists of two Miller integrator circuits, a unit gain
bandpass filter, if we follow the block diagram to design the circuit, we can
R3
R 2 10 k 15 k
C1
C2
R1
10 nF R
6
(I/P) 13 R4 10 nF
7.5 k :
U1 R5
A 14 6 15 k
15 k :
12 U1
:LM34 B 7 10 :
U1 5 15 k U1
8 C 8
9
(BPF O/P)
Figure 1-10 is the circuit diagram of the second order active bandpass
filter, which is based on the block diagram in figure 1-9. We combine the
1-13
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we can save an OP, but the calculation of the circuit parameters will be more
complicated. If we assume
C1 C 2 C
R6 R5 R 4
R 3R 4 1
S
Vout (S) R1 R 3R 4 C
(1-14)
Vin (S) R 3R 4 1 1
S
2
S
R2 C R 3R 4 R 3R 4C 2
R 3R 4
K (1-15)
R1
1
0 (1-16)
C R 3R 4
R2
Q (1-17)
R 3R 4
Miller integrator circuit, but also provide the function of weighted summer.
The objective is to multiply a weighted to the input signal and output signal
of U1 : C , respectively, after that sum the input signal and output signal of
1-14
Chapter 1 Second Order Filters
frequency signal pass through, but disable a certain frequency band signal
pass through. On the other words, if a circuit rejects a finite frequency band
that does not include zero (DC) and infinite frequency, then it is known as
band reject filter. Thus band reject filter is specified by two stopband
frequencies to set the frequency band as shown in figure 1-11. From figure
and high-pass filters. The band reject filter consists of a f 3dB f1 low-pass
Figure 1-12 shows the block diagram of the second order active band
reject filter, which consists of a low-pass filter, high-pass filter and an adder.
Let the output of the low-pass filter be VLPF(S) and the output of the
1-15
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where
Substitute TLPF (S) and THPF (S) by using equation (1-2) and
Voltage
Gain
(dB) BW
3 dB 3 dB
LPF HPF
f1 fo f2 Frequency (Hz)
1-16
Chapter 1 Second Order Filters
band reject filter, if we follow the block diagram to design the circuit, we
can obtain the second order bandpass filter. Therefore, practically, we just
need to sum the outputs of figure 1-5 and figure 1-7 by using the adder in
LPF
K1
Input Output
( Vin ) ( Vout )
K2
HPF
Figure 1-12 Block diagram of second order active band reject filter.
R1 R3
LPF I/P
10 k 10 k
R2
HPF I/P
10 k A 741 BRF O/P
Figure 1-13 Circuit diagram of second order active band reject filter.
1-17
Analog Communication Trainer
comparing their transfer functions, we know that the order of the filters is
than the order of the numerator, then the filter is a low-pass filter. On the
other hand, if the order of the denominator is smaller than the order of the
numerator, then the filter is a high-pass filter. For higher levels filter, we
can series the mentioned circuits to obtain the required efficiency (Only
LM348 package with four operation amplifiers (A741). The unit gain
1-18
Chapter 1 Second Order Filters
4. Find the voltage gain of each frequency and records the measured results
in table 1-1.
5. From the data in table 1-1, sketch and label the voltage gain in Bode
plots in figure 1-14.
7. Repeat step 2 to step 5 and record the measured results in table 1-2 and
figure 1-15.
1-19
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3. The input amplitude remains, change the frequency to 100 Hz, 300
Hz, 500 Hz, 700 Hz,1 kHz, 3 kHz, 5 kHz, 7 kHz, 10 kHz, 30 kHz, 50
kHz and 100 kHz. Then by using oscilloscope, observe on the output
signal port (HPF O/P) and record the measured results in table 1-3.
4. Find the voltage gain of each frequency and record the measured
results in table 1-3.
5. From the data in table 1-3, sketch and label the voltage gain in Bode
plots in figure 1-16.
7. Repeat step 2 to step 5 and record the measured results in table 1-4 and
figure 1-17.
1-20
Chapter 1 Second Order Filters
4. Find the voltage gain of each frequency and record the measured results
in table 1-5.
5. From the data in table 1-3, sketch and label the voltage gain in Bode
plots in figure 1-18.
7. Repeat step 2 to step 5 and record the measured results in table 1-6 and
figure 1-19.
1-21
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1. Refer to the block diagram in figure 1-12, by using the low-pass filter in
figure 1-5, the high-pass filter in figure 1-7, the adder in figure 1-13 to
sum the low-pass and high-pass filters. Or refer to figure ACS1-1 and
ACS1-2 on ACT-17300-01 module.
3. Connect the input ports of figure ACS1-1 and figure ACS1-2 together.
Connect the LPF O/P of the low-pass filter in figure ACS1-1 to the LPF
I/P of the linear adder in figure ACS1-2; Connect the HPF O/P of the
high-pass filter in figure ACS1-2 to the HPF I/P of the linear adder in
figure ACS1-2.
6. Find the voltage gain of each frequency and record the measured results
in table 1-7.
1-22
Chapter 1 Second Order Filters
7. From the data in table 1-7, sketch and label the voltage gain in Bode
plots in figure 1-20.
9. Repeat step 3 to step 7 and record the measured results in table 1-8 and
figure 1-21.
1-23
Analog Communication Trainer
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-24
Chapter 1 Second Order Filters
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-25
Analog Communication Trainer
Input Signal
Frequency 70 100 300 500 700 1k 3k 5k 7k 10k 30k 50k 100k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-26
Chapter 1 Second Order Filters
Input Signal
Frequency 70 100 300 500 700 1k 3k 5k 7k 10k 30k 50k 100k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-27
Analog Communication Trainer
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-28
Chapter 1 Second Order Filters
Input Signal
Frequency 10 30 50 70 100 300 500 700 1k 3k 5k 7k 10k
(Hz)
Output Signal
Amplitude
(mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-29
Analog Communication Trainer
Input Signal
30 50 70 100 300 500 700 1k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Input Signal
3k 5k 7k 10 k 30 k 50 k 70 k 100 k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-30
Chapter 1 Second Order Filters
Input Signal
30 50 70 100 300 500 700 1k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Input Signal
3k 5k 7k 10 k 30 k 50 k 70 k 100 k
Frequency (Hz)
Output Signal
Amplitude (mV)
Voltage Gain
(dB)
Voltage
Gain
(dB)
Frequency
10 100 1k 10k 100k (Hz)
1-31
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1-32
Chapter 2
RF Oscillators
Analog Communication Trainer
2-2
Chapter 2 RF Oscillators
Figure 2-1 shows the basic block diagram of the oscillator circuit. It
network. When we switch on the power, the circuit will produce noise. The
noise will be amplified by the amplifier, and pass through a resonator circuit
which has filter function. At last what’s left is the signal in the passband.
The unwanted signal is filtered by the resonator. So the pass through signal
will then send to the input port of amplifier and combine to the original
signal, which their phases are same and will be amplified again. In figure
Vo ( j) A( j)
A f ( j) (2-1)
Vi ( j) 1 A( j)( j)
that the open loop gain L( jo ) is equal to 1, and the phase must be 0o ,
that is
2-3
Analog Communication Trainer
Vf Feedback Network
( j)
From the above mention, in order to satisfy equations (2-3) and (2-4),
we should make sure that the product of the feedback factor and the
after feedback. Therefore, figure 2-1 can be changed to figure 2-2 for
Non-inverting Amplifier
Vs
Vi A ( j) Vo
Vf 0o
( j)
Inverting Amplifier
Vs
Vi A ( j) Vo
Vf 180 o
( j)
2-4
Chapter 2 RF Oscillators
( Z 2 Z 3 ) || Z1 Z2
A ( A )
ro ( Z 2 Z 3 ) || Z1 Z 2 Z 3
(2-5)
Z1 Z 2
( A )
ro ( Z1 Z 2 Z 3 ) Z1 ( Z 2 Z 3 )
( jX 1 ) ( jX 2 )
A ( A )
ro ( jX 1 jX 2 jX 3 ) jX 1 ( jX 2 jX 3 )
(2-6)
A X1 X 2
ro j( X1 X 2 X 3 ) X1 ( X 2 X 3 )
From equation (2-4), we know that the A is real number, therefore, the first
X1 X 2 X 3 0 (2-7)
A X1 X 2 X
A ( j o ) ( j o ) A 2 1
X1 ( X 2 X 3 ) X1
2-5
Analog Communication Trainer
X1
A (2-8)
X2
Vo
-A
z2 z1
z3
ro Vo
Vi AVi
z3
z1
z2
a feedback network. When we switch on the power, the circuit will produce
2-6
Chapter 2 RF Oscillators
noise. The noise will be amplified by the amplifier, and pass through a
resonator circuit which has filter function. At last what’s left is the signal in
the passband. The unwanted signal is filtered by the resonator. So the pass
through signal will then send to the input port of amplifier and combine with
the original signal, which their phases are same and be amplified again. This
is how the oscillation been formed. On the other hand, base on Barkhausen
1. Since the voltage gain of the amplifier is real number, therefore Z1 and
Z2 are same components with same reactance and Z3 is another
component with different reactance.
2. The voltage gain, A of the amplifier must be greater than the ratio of Z1
and Z2.
utilizing either common gate mode, common drain mode or common source
mode, then there are many types of oscillators mode for selection.
parallel LC resonant circuit links between the base and collector of transistor.
So part of the voltage come from the voltage divider formed by C1 and C2,
and feedback to the base of the transistor. R represents the total summation
of output resistor, load resistor together with the equivalent resistor of the
2-7
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Output
R C1
L
C2
1 1
X1 X 2 X 3 o L 0
oC1 o C2
1
fo (Hz) (2-9)
CC
2 L 1 2
C1 C 2
condition of oscillation is
2-8
Chapter 2 RF Oscillators
1
X1 oC1 C2
A
X2 1 C1
oC2
C2
gmR (2-10)
C1
Figure 2-7 is the circuit diagram of Colpitts oscillator. R1, R2, R3 and
operation frequency.
+12V
R1 R3
22 k 2k Output
C1 TP1 Q1
2N3904 C3
1 nF 1 nF
L1
R2 27 uH
10 k
R4 C2
1k 100 nF
C4
15 nF
Output
R L1
L2
2-9
Analog Communication Trainer
base and collector of the transistor, the difference is part of the voltage come
from the voltage divider formed by L1 and L2, and feedback to the base of
resistor together with the equivalent resistor of the inductor and capacitor of
a transistor.
1
X1 X 2 X 3 o L1 o L 2 0
o C
1
f0 ( Hz ) (2-11)
2 L1 L 2 C
oscillation as
X1 o L1 L1
A
X 2 o L 2 L 2
L1
gmR (2-12)
L2
2-10
Chapter 2 RF Oscillators
+12V
R1
Output
C1
Q1
L1
R2 C3
R3 C2
L2
transistors with piezoelectric effect, for example, quartz, ceramic and so on.
These transistors are usually used to design the oscillator circuits with high
stability due to the reason that the loss of the transistors is very low and the
2-11
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made by cutting a pure quartz crystal in a very thin slice and then plating the
property that makes the crystal useful in designing the oscillator is the
piezoelectric effect. When the crystal is excited by the voltage, it will cause
In addition, we can choose specific oscillation type and high order harmonic
via different product process of crystals. Figure 2-10 shows the equivalent
sequence and mass of the crystal. Generally, the value of Cs is about 0.05
which mainly comes from plating, brace of the crystal and the impedance
high, therefore, r seems to be very small, only few ohms. Besides, we also
can get the series or parallel resonant frequency, respectively. In figure 2-10,
we have
1
fs (2-13)
2 LCs
1
fp (2-14)
CC
2 L s p
Cs C p
2-12
Chapter 2 RF Oscillators
Zx Z r (Q 2 1)
Cs Cp
r
r
f
fs fp
0.36 %.
Cs
f p (1 )f s (2-15)
2Cp
oscillation frequency can be higher than using the general inductors and
oscillation circuit with parallel mode, the crystal can be seen as an inductor.
On the other hand, if the crystal is operated in series resonant circuit, then it
the oscillation circuit with series mode, the crystal can be seen as a capacitor.
2-13
Analog Communication Trainer
without using crystals. However, we should pay more attention to design the
bias circuit for the reason that the DC signal may not pass through the
crystal.
C1 C1
'
X tal L
X ' tal
C2 C2
(a) Parallel mode crystal oscillator circuit (b) Series mode crystal oscillator circuit
Figure 2-11 Circuit structures of crystal oscillator
+12V
R2
270
C4
R1 100 pF
22 k
X'tal 輸出
C 2 680 pF
6 MHz
C1 TP1
R3 C3
51 680 pF
Figure 2-12 is the circuit diagram of the Colpitts crystal oscillator. The
C1 and C 2 are the external parallel capacitors added on the crystal. The
values that we choose should be higher until the parasitic capacitor can be
2-14
Chapter 2 RF Oscillators
frequency can be varied by voltage. The main design concepts and methods
only difference is that we use varactor diode, which the capacitance can be
not discuss the theory of the oscillator but we will focus on the theory of the
varactor diode.
the tunable range of the whole voltage controlled oscillator. Varactor diode
region becomes wide, this will cause the capacitance value decreases;
nevertheless when reverse bias voltage decreases, the depletion region will
be reduced, this will cause the capacitance value increases. Varactor diode
2-15
Analog Communication Trainer
from minor carriers at pn junction. Then these carriers will diffuse and
positive ions, then the n type depletion region carries negative ions. We can
A
C (2-16)
d
where
o 8.85 1012
will increase but the cross section area A remains same, therefore the
and an inductor (Ls) as shown in figure 2-14. From figure 2-14, Cj is the
2-16
Chapter 2 RF Oscillators
material.
- - +
+
- +
P - + N
- +
- +
Depletion Region
_
_ _ _ +
+ + +
_ _ _
+ + +
_ _
+ +
Parallel Plate Capacitor Dielectric
CV Cj Rs
Figure 2-14 Circuit symbol and equivalent circuit diagram of varactor diode.
2-17
Analog Communication Trainer
+12V
L1 R2
100 uH
270
+12V
C4
CV1 R1 100 pF
1SV55 22 k
Output
VR 1 Vt C2
5k 680 pF
CV2 C1
1SV55 100 nF R3 C3
680 pF
2-18
Chapter 2 RF Oscillators
2-19
Analog Communication Trainer
4. Adjust the variable resistor, VR1 , so that the DC voltage (Vt) of the
varactor diode is varied from the values in table 2-3.
6. According to the data in table 2-3, sketch the characteristic curve with
frequency versus voltage in figure 2-16.
2-20
Chapter 2 RF Oscillators
Components
Values of Colpitts Output Signal Waveforms
Oscillator
O/P
L1 :
C3 :
C4 :
TP1
Theoretical value fo =
Measured value fo =
Components
Values of Hartley Output Signal Waveforms
Oscillator
O/P
L2 :
L3 :
C5 :
TP1
Theoretical value fo =
Measured value fo =
2-21
Analog Communication Trainer
(O/P)
Theoretical value fo =
Measured value fo =
TP1
Theoretical value fo =
Measured value fo =
2-22
Chapter 2 RF Oscillators
Input DC Bias
3 4 5 6 7 8 9 10 11 12
( Vt )
Output Signal
Frequency
(MHz)
Output Signal
Frequency (MHz)
Input DC
Bias
3 4 5 6 7 8 9 10 11 12 (Vt )
2-23
Analog Communication Trainer
2-24
Chapter 3
AM Modulator
Analog Communication Trainer
signal to modulate the amplitude of carrier signal, which means that the
generate the AM signal, we just need to add a DC signal with the audio
signal, and then multiply the added signal with the carrier signal.
3-2
Chapter 3 AM Modulator
Am Ac
E min
Audio
AM Output
Signal Input
Where
3-3
Analog Communication Trainer
m A m / A DC .
A DC : DC signal magnitude.
parameter “m”. This means that we can change the magnitude of the audio
signal (Am) or DC signal (ADC) to control the level or depth of the carrier
The first term represents double sideband signals; the second term
represents carrier signal. From equation (3-2), we can sketch the frequency
3-4
Chapter 3 AM Modulator
signal is hidden in the double sidebands and the carrier signal does not
much simpler.
ADC Ac
f
fc fm fc fc fm
3-5
Analog Communication Trainer
E max E min
m 100 % (3-4)
E max E min
Where E max and E min as shown in figure 3-1 are E max A C A m and
E min A C A m .
the double sidebands, so if the double sideband signals are getting stronger,
that the double sideband signals are proportional to the modulation index.
Thus the larger the modulation index, the better the transmission efficiency.
we call it over modulation, as shown in figure 3-4. Figure 3-4 shows the
waveforms of the over modulation. In figure 3-4, we can see that the
next chapter.
Emax
Emin
3-6
Chapter 3 AM Modulator
balanced modulator.
In figure 3-5, the audio signal ( A m cos (2 f m t ) ) will pass through a
transformer and send into the base of the transistor. The carrier signal
( A c cos (2 f c t ) ) also passes through a transformer and sends into the
emitter of the transistor. These two signals will form a small amount of
small signal voltage difference at the base and emitter of the transistor. The
I c I s e Vbe VT
(3-6)
I c aVbe bVbe
2
(3-7)
3-7
Analog Communication Trainer
+12 V
C2 C4
100 nF 10 uF
L1
R1 100 uH
120 k C3
TP2 AM
Signal
Audio C1 TP1 Output
Signal
Q1 1 nF
TR1 R3
Input 100 nF 3904 3k3
TP3
R2
5k6
VR1
TR2
Carrier 500
Signal
Input
In equation (3-7), we notice that after the audio signal and the carrier
signal input into the base and collector of the transistor, we can obtain
cos 2 (2 f m t ) , cos 2 (2 f c t ) and cos (2 f m t ) cos (2 f c t ) signals at the
collector. Then we utilize the filter to obtain the modulated AM signal
cos (2 f m t ) cos (2 f c t ) . In figure 3-5, the inductor L1, capacitor C3 and
resistor R3 comprise a high-pass filter, which is used to obtain the modulated
AM signal. Capacitor C1 is the coupling capacitor. Capacitor C2 and C3 are
the bypass capacitors. Resistors R1 and R2 are the bias resistors. Variable
resistor VR1 is used to change the operation point of the transistor and it also
used to control the magnitude of the carrier, which inputs into the collector
of the transistor. Therefore, it can adjust the output signal waveform of the
modulator.
3-8
Chapter 3 AM Modulator
balanced modulator and the transistor is that we can use the theory of
signal, output signal and circuit characteristics are shown in table 3-1.
Table 3-1 Three different types of modulation signal produced by different signals
frequency of balanced modulator.
Frequency
fc fc 2f c
Multiplier
Amplitude
fc fm fc , fc f m , fc f m
Modulator
DSB-SC
fc fm fc fm , fc fm
Modulator
3-9
Analog Communication Trainer
Figure 3-6 is the internal circuit diagram of MC1496, where D1, R1, R2,
R3, Q7 and Q8 comprise an electric current source, which can supply DC
bias current for Q5 and Q6. Q5 and Q6 comprise a differential combination to
drive the dual differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1
and 4 are the inputs of audio signal, after that this signal will be amplified
by the differential amplifier, which is comprised by Q5 and Q6. Pin 8 and 10
are the inputs of carrier signal. Then the amplified audio signal will multiply
by the carrier signal at the dual differential amplifiers constructed by Q1, Q2,
Q3 and Q4. Finally, the output signals can be obtain at the collectors of Q1,
Q2, Q3 and Q4, respectively. The resistor between pins 2 and 3 controls the
gain of the balanced modulator; the resistor of pin 5 determines the
magnitude of bias current for amplifier.
(12)
Output
Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal
Input
(8) Q5 Q6
(4)
Audio
Signal
Input (2)
Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 3-6 Internal circuit diagram of MC1496.
3-10
Chapter 3 AM Modulator
Figure 3-7 is the circuit diagram of AM modulator. We can see that the
carrier signal and audio signal belong to single ended input. The carrier
signal input from pin 10 and the audio signal input from pin 1. Therefore R8
determine the gain of the whole circuit and R9 determine the magnitude of
bias current. If we adjust the variable resistor VR1 or change the input
AM modulator.
C3 R7 1 k
+12 V
100 uF
+
R4 C5 C8
VR2
10 k 100 nF 100 uF
1k
Carrier TP1 8
Signal R9 R11
Input R5 3k9 3k9
C2 100 C6
100 uF TP2 100 nF
10 6 AM
Audio + TP5 Output
C1 TP3 MC1496
Signal Signal
1 Balanced 12
Input
100 nF Modulator TP6 C7
R1 100 nF
10 k TP4 TP7
4 5
R2 R3 R6 R10
VR1 14
100 6k8
100 k 10 k 100
R8
-12 V
100
+
C4 Z1
100 uF 5V
3-11
Analog Communication Trainer
2. At audio signal input port (Audio I/P), input 100 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
7. Substitute the measured results into equation (3-4), find the modulation
percentage and record in table 3-2.
3-12
Chapter 3 AM Modulator
8. According to the input signals in table 3-2, repeat step 4 to 7 and record
the measured results in table 3-2.
9. According to the input signals in table 3-3, repeat step 2 to 7 and record
the measured results in table 3-3.
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
3-13
Analog Communication Trainer
7. Substitute the measured results into equation (3-4), find the modulation
percentage and record in table 3-4.
8. According to the input signals in table 3-4, repeat step 4 to 7 and record
the measured results in table 3-4.
9. Let J1 be open circuit and J2 be short circuit, i.e. change the resistor R10
= 6.8 k to R12 = 3.3 k. Repeat step 2 to step 8 and record the
measured results in table 3-5.
10. According to the input signals in table 3-6, repeat step 2 to 7 and record
the measured results in table 3-6.
3-14
Chapter 3 AM Modulator
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 200 mV
amplitude, 500 kHz sine wave frequency.
7. Substitute the measured results into equation (3-4), find the modulation
percentage and record in table 3-7.
8. According to the input signals in table 3-7, repeat step 4 to 7 and record
the measured results in table 3-7.
9. According to the input signals in table 3-8, repeat step 2 to 7 and record
the measured results in table 3-8.
3-15
Analog Communication Trainer
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
5. Substitute the measured results into equation (3-4), find the modulation
percentage and record in table 3-9.
6. According to the input signals in table 3-9, repeat step 2 to 5 and record
the measured results in table 3-9.
3-16
Chapter 3 AM Modulator
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 1 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
4. Adjust VR2 so that the resistance are 0 , 5 k and 10 k, the others
remain. Then record the measured results in table 3-10.
3-17
Analog Communication Trainer
AM O/P
TP1
TP3
TP2
AM O/P
Output Signal
Spectrums
TP2
Output Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-18
Chapter 3 AM Modulator
AM O/P
TP1
TP3
TP2
AM O/P
Output Signal
Spectrums
TP2
Output Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-19
Analog Communication Trainer
AM O/P1
AM O/P2
TP3
TP4
3-20
Chapter 3 AM Modulator
TP1
TP2
TP5
TP6
3-21
Analog Communication Trainer
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-22
Chapter 3 AM Modulator
AM O/P1
AM O/P2
TP3
TP4
3-23
Analog Communication Trainer
TP1
TP2
TP5
TP6
3-24
Chapter 3 AM Modulator
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-25
Analog Communication Trainer
AM O/P1
AM O/P2
TP3
TP4
3-26
Chapter 3 AM Modulator
TP1
TP2
TP5
TP6
3-27
Analog Communication Trainer
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-28
Chapter 3 AM Modulator
AM O/P1
AM O/P2
TP3
TP4
3-29
Analog Communication Trainer
TP1
TP2
TP5
TP6
3-30
Chapter 3 AM Modulator
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-31
Analog Communication Trainer
AM O/P1
AM O/P2
TP3
TP4
3-32
Chapter 3 AM Modulator
TP1
TP2
TP5
TP6
3-33
Analog Communication Trainer
TP7
AM O/P1
Output
Signal
Spectrums
AM O/P2
Output
Signal
Spectrums
TP5
Output
Signal
Spectrums
TP6
Output
Signal
Spectrums
E max E max
Modulation
Index E min E min
m % m %
3-34
Chapter 3 AM Modulator
Table 3-9 Observe on the variation of amplitude modulation by changing the variable
resistor VR1. (Vm = 600 mV, fm = 1 kHz, Vc = 300 mV, fc = 500 kHz, R12 =
3.3 k)
E max
AM
O/P1 E min
m= %
30 %
E max
AM
O/P2 E min
m= %
E max
AM
O/P1 E min
m= %
50 %
E max
AM
O/P2 E min
m= %
E max
AM
O/P1 E min
m= %
110 %
E max
AM
O/P2 E min
m= %
3-35
Analog Communication Trainer
Magnitudes of
Output Signal Output Signal Modulation
Variable
Waveforms Spectrums Percentages
Resistor VR2
E max
AM
O/P1 E min
m= %
0
E max
AM
O/P2 E min
m= %
E max
AM
O/P1 E min
m= %
5 k
E max
AM
O/P2 E min
m= %
E max
AM
O/P1 E min
m= %
10 k
E max
AM
O/P2 E min
m= %
3-36
Chapter 3 AM Modulator
4. Refer to figure 3-7, if we let J2 be short circuit, J1 be open circuit, i.e. R10
changes to R12, which its value is 6.8 k changed to 3.3 k. Then
describe the variation of the DC bias current of MC1496.
5. Refer to figure 3-7, if we adjust the magnitude of the variable resistor VR2
from small to large, then describe the variation of the output signal of AM
modulator.
6. When modulation index, m = 50 % and 110 %, what are the ratio of Emax
and Emin?
3-37
Analog Communication Trainer
3-38
Chapter 4
AM Demodulator
Analog Communication Trainer
need to restore the audio signal. Figure 4-1 is the theory diagram of
4-2
Chapter 4 AM Demodulator
signal and obtains a positive half wave signal. After that the signal will pass
through a low-pass filter and obtain an envelop detection. Then get rid of the
DC signal, the audio signal will be recovered. If the input signal of the diode
are unable to recover the distorted signal to the audio signal by the diode
detector. As for the over modulated AM signal, we need to use the product
section.
AM
Demodulator
4-3
Analog Communication Trainer
Modulated AM Signal
Low-pass
Rectifier DC Block Audio Signal
Filter
R2 2k2
R4 4k7
R1 +12 V
AM
R3 +12 V D1
Signal C3
Input 1k uA741 1N4004
TP3 R5 TP4 100 nF
Audio
Signal
TP1 1k LM318
Output
-12 V TP2 1k
-12 V C1 C2 R6
10 nF 10 nF 4k7
R1, R2, R3, R4, U1 and U2 form two groups of inverting amplifiers to amplify
the input signal, the amplified rate is 10 times of the original signal; Diode
D1 is the rectifier diode which can make the amplitude modulation signal
become a positive half wave signal; Capacitors C1, C2 and resistors R5, R6
block the DC level and we can obtain a pure audio signal at output port.
4-4
Chapter 4 AM Demodulator
figure 4-4, we notice that the design of product detector is to multiply the
When these two signals input into two different ports of balanced
x out (t ) kx c (t ) x AM (t )
k A DC A c2 k A DC A c2
m cos (2f m t )
2 2
k A DC A c2
1 m cos (2f m t)cos2 (2f c t) (4-3)
2
(4-3), the first term is the DC signal, second term is the audio signal and
4-5
Analog Communication Trainer
out the second term from xout (t) by using the low-pass filter as shown in
figure 4-4, then we can obtain the exact demodulated AM signal or audio
signal.
Modulated Audio
AM signal LPF
Signal
Input Output
Carrier Signal
VR1 controls the input magnitude of carrier signal; variable resistor VR2
low-pass filter which can remove the unwanted third term of equation
which is the first term of equation (4-3), can be blocked by C10. Therefore
k A DC A c2
x out ( t ) m cos (2 f m t ) (4-4)
2
4-6
Chapter 4 AM Demodulator
circuit is simple but the performances are not as better as product detector.
Further more it also requires synchronous for both carrier signal and
R2 1 k R4 2 k
+12 V
+
C4 C8
C1 R1 VR3
10 k 100 uF
100 nF 1k
100 nF
TP1 8
R6 R7
VR1 R3 2k 2k
100 k C3 1k
Carrier 100 nF
Signal
TP2
10 MC1496 6 TP5 C10
Input C2 R8
TP3 Balanced TP6 TP7 2u2 F Audio
AM 1 Modulator 12 + Signal
Output
+
Signal 100 nF 1k
C6
Input 2u2 F C7 C9
R5 1 nF 1 nF
VR2 TP4 10 k
100 k 4
5
C5 14
100 nF
4-7
Analog Communication Trainer
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 3 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 300 kHz sine wave frequency.
4. Connect the output signal of the AM modulator (AM O/P1) to the input
port (AM I/P) of diode detector in figure 4-3 or figure ACS4-1 on
ACT-17300-02 module.
4-8
Chapter 4 AM Demodulator
8. According to the input signals in table 4-1, repeat step 4 to step 7 and
record the measured results in table 4-1.
9. According to the input signals in table 4-2, repeat step 3 to step 7 and
record the measured results in table 4-2.
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 3 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
4. Connect the output signal of the AM modulator (AM O/P1) to the input
port (AM I/P) of product detector in figure 4-5 or figure ACS4-2 on
ACT-17300-02 module. At the same time, also connect the carrier
signal input port (Carrier I/P) of the product detector with the same
carrier signal in AM modulator.
4-9
Analog Communication Trainer
Audio O/P is optimum without distortion. Adjust VR3 so that the signal
at Audio O/P is the maximum without distortion.
9. According to the input signals in table 4-3, repeat step 6 to step 9 and
record the measured results in table 4-3.
10. According to the input signals in table 4-4, repeat step 3 to step 9 and
record the measured results in table 4-4.
4-10
Chapter 4 AM Demodulator
2. At audio signal input port (Audio I/P), input 600 mV amplitude, 3 kHz sine
wave frequency; at carrier signal input port (Carrier I/P), input 300 mV
amplitude, 500 kHz sine wave frequency.
4. Connect the output signal of the AM modulator (AM O/P1) to the input
port (AM I/P) of product detector in figure 4-5 or figure ACS4-2 on
ACT-17300-02 module. At the same time, also connect the carrier
signal input port (Carrier I/P) of the product detector with the same
carrier signal in AM modulator.
4-11
Analog Communication Trainer
9. According to the input signals in table 4-5, repeat step 6 to step 9 and
record the measured results in table 4-5.
10. According to the input signals in table 4-6, repeat step 3 to step 9 and
record the measured results in table 4-6.
4-12
Chapter 4 AM Demodulator
AM I/P
TP1
TP2
TP3
TP4
Audio O/P
4-13
Analog Communication Trainer
AM I/P
TP1
TP2
TP3
TP4
Audio O/P
4-14
Chapter 4 AM Demodulator
AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4-15
Analog Communication Trainer
TP1
TP2
TP5
TP6
TP7
4-16
Chapter 4 AM Demodulator
AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4-17
Analog Communication Trainer
TP1
TP2
TP5
TP6
TP7
4-18
Chapter 4 AM Demodulator
AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4-19
Analog Communication Trainer
TP1
TP2
TP5
TP6
TP7
4-20
Chapter 4 AM Demodulator
AM I/P
Carrier I/P
Audio O/P
TP3
TP4
4-21
Analog Communication Trainer
TP1
TP2
TP5
TP6
TP7
4-22
Chapter 4 AM Demodulator
4. Refer to figure 4-5, explain the results if the carrier signal and
modulated AM signal are asynchronous.
4-23
Chapter 5
5-2
Chapter 5 DSB-SC and SSB Modulator
Am Ac
E min
where
m A m / A DC .
A DC : DC signal magnitude.
5-3
Analog Communication Trainer
The first term represents the double sideband signals; the second term
represents the carrier signal. From equation (5-2), we can sketch the
Since the AM signal is hidden in the double sidebands and the carrier signal
does not contain any signal, therefore the power is consumed in carrier
signal and only left the double sideband. We can use the DSB-SC
modulators and let the phase difference between the two audio signals and
Equations (5-3) and (5-4) show that both (DSB SC) Q and
( DSB SC) I signals connect to the adder, then we can obtain USSB or
5-4
Chapter 5 DSB-SC and SSB Modulator
f c and f c f m . The output voltage of fc is higher than the other two signals,
therefore, the carrier signal does not contain any signal, and the power is
Figure 5-2(b) is the frequency spectrum of DSB-SC signal. We can see that
therefore, by using this type of modulation, the power will not consume in
the carrier. Besides, as a result of the audio signal is hidden in the double
sideband, so, the stronger the double sideband signal, the transmission
efficiency will be better. From equation (5-2), we notice that the larger the
than 1, we call this situation as over modulation. Figure 5-2(c) and figure
5-2(d) are the frequency spectrum of SSB signal. We can see that the
5-5
Analog Communication Trainer
know that the sequence of power consumption of the three different types of
x AM ( f )
A DC A c
0 .5 mA DC A c 0 .5 mA DC A c
f (Hz)
fc fm fc fc fm
(a) Frequency spectrum of AM.
x AM (f )
f (Hz)
fc fm fc fc fm
(b) Frequency spectrum of DSB-SC.
x AM (f )
0.5mADCA c
f (Hz)
fc fm fc fc fm
(c) Frequency spectrum of SSB.
5-6
Chapter 5 DSB-SC and SSB Modulator
x AM (f )
0.5mA DCA c
f (Hz)
fc fm fc f c fm
(d) Frequency spectrum of SSB.
Carrier Signal
the internal circuit diagram of MC1496, where D1, R1, R2, R3, Q7 and Q8
5-7
Analog Communication Trainer
comprise an electric current source, which can supply DC bias current for
differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1 and 4 are the
inputs of audio signal; Pin 8 and 10 are the inputs of carrier signal. The
resistor between pins 2 and 3 controls the gain of the balanced modulator;
the resistor of pin 5 determines the magnitude of bias current for amplifier.
(12)
Output
Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal
Input
(8) Q5 Q6
(4)
Audio
Signal
Input (2)
Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
Figure 5-5 is the circuit diagram of AM modulator. We can see that the
carrier signal and audio signal belong to single ended input. The carrier
signal is inputted from pin 10 and the audio signal is inputted from pin 1.
Therefore R8 determine the gain of the whole circuit and R9 determine the
5-8
Chapter 5 DSB-SC and SSB Modulator
the input amplitude of audio signal, then we can control the percentage
control the magnitude of the output amplitude, which is also the gain.
R7
1k 1k
+12
V
R3 C3 R8 1 k
0.1uF
R10 R11
3.9 k 3.9 k
C1 R4 2 3 DSB-SC
Carrier 51 8
0.1uF 6 Signal
Signal C4
10 Output
Input 0.1uF
MC1496
Audio C2
1 12
Signal
0.1uF 4
Input 14 5
R1 R2 R5 R6
10 k 10 k 300 1k
R9
50 k 6.8 k
VR1
5 V
From equations (5-5) and (5-6), we know that the SSB modulator is
diagram of SSB modulator, where the phase difference of each audio signal
degree phase difference between TP1 and TP2, and 90 degree phase
5-9
Analog Communication Trainer
difference between TP3 and TP4). In figure 5-6, the block of the quadrature
phase shift and the phase shift represent the phase shifter. The circuit
resistor, we can control the phase difference between the input and output
similar to the circuit diagram in figure 5-5. Then the output terminals of the
two balanced modulators, which are TP5 and TP6 will be added by the
linearity adder, then we can obtain the modulated SSB signal. The circuit
adjusting the variable resistor VR2, we can control the gain of the DSB-SC
adjust VR1 of the balanced modulator 2, so that the output is the modulated
DSB-SC signal. By adjusting the variable resistor VR2, we can control the
output signal terminal is whether the modulated SSB signal. If the frequency
spectrum is not true, we can adjust the variable resistor of the quadrature
phase shift.
5-10
Chapter 5 DSB-SC and SSB Modulator
TP1 TP5
Balance
Modulator 1 DSB Q
Quadrature Phase Signal
TP3
Phase
Shifter
45 45 Phase Linear
Phase Shift Adder
Audio Carrier 45 SSB
I/P Shifter I/P O/P
45
TP4
R2
10 k
R1 1 nF
C2 +12
10 k V
Signal uA741
Signal
Input Port Output Port
C1 -12 V
Phase 100 k
adjustment 100 pF
5-11
Analog Communication Trainer
R4
100 k
R1
+12 V
100 k
DSB Q
uA741
SSB
DSB I O/P
R2
100 k -12 V
R3
47 k
5-12
Chapter 5 DSB-SC and SSB Modulator
2. At the audio signal input port (Audio I/P), input a 300 mV amplitude and
1 kHz sine wave frequency. Next at the carrier signal input port (Carrier
I/P), input a 300 mV amplitude and 100 kHz sine wave frequency.
3. By using oscilloscope, observe on both the audio signal output ports TP1
and TP2 at the same time. Next adjust variable resistor “QPS” so that the
phase difference between TP1 and TP2 is 90. Then record the measured
results in table 5-1. By using oscilloscope, observe on both the carrier
signal output ports TP3 and TP4 at the same time. Next adjust variable
resistor “Phase Adjust” so that the phase difference between TP3 and TP4
is 90. Then record the measured results in table 5-1.
5-13
Analog Communication Trainer
8. According to the input signals in table 5-4, repeat step 3 and record the
measured results in table 5-4.
9. According to the input signals in table 5-4, repeat steps 4 and 5, then
record the measured results in table 5-5.
10. According to the input signals in table 5-4, repeat steps 6 and 7, then
observe on TP6 and the DSB SC I output port (DSB-SC O/P). Finally,
record the measured results in table 5-6.
11. According to the input signals in table 5-7, repeat step 3 and record the
measured results in table 5-7.
12. According to the input signals in table 5-7, repeat steps 4 and 5, then
record the measured results in table 5-8.
13. According to the input signals in table 5-7, repeat steps 6 and 7, then
observe on TP6 and the DSB SC I output port (DSB-SC O/P). Finally,
record the measured results in table 5-9.
5-14
Chapter 5 DSB-SC and SSB Modulator
2. At the audio signal input port (Audio I/P), input a 300 mV amplitude
and 1 kHz sine wave frequency. Next at the carrier signal input port
(Carrier I/P), input a 300 mV amplitude and 200 kHz sine wave
frequency.
3. By using oscilloscope, observe on both the audio signal output ports TP1
and TP2 at the same time. Next adjust variable resistor “QPS” so that the
phase difference between TP1 and TP2 is 90. Then record the measured
results in table 5-10. By using oscilloscope, observe on both the carrier
signal output ports TP3 and TP4 at the same time. Next adjust variable
resistor “Phase Adjust” so that the phase difference between TP3 and
TP4 is 90. Then record the measured results in table 5-10.
5-15
Analog Communication Trainer
5-16
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 100 kHz)
TP1
and
TP2
TP3
and
TP4
5-17
Analog Communication Trainer
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 100 kHz)
Oscilloscope
Spectrum
Analyzer
5-18
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 100 kHz)
Oscilloscope
Spectrum
Analyzer
5-19
Analog Communication Trainer
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 100 kHz)
Oscilloscope
Spectrum
Analyzer
5-20
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 300 kHz)
TP1
and
TP2
TP3
and
TP4
5-21
Analog Communication Trainer
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 300 kHz)
Oscilloscope
Spectrum
Analyzer
5-22
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 300 kHz)
Oscilloscope
Spectrum
Analyzer
5-23
Analog Communication Trainer
Table 5-6 Measured results of modulated DSB-SC signal (DSB-SC O/P). (Continue)
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 300 kHz)
Oscilloscope
Spectrum
Analyzer
5-24
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 500 mV, f = 1 kHz; Carrier I/P Vp = 500 mV, f = 500 kHz)
TP1
and
TP2
TP3
and
TP4
5-25
Analog Communication Trainer
(Audio I/P Vp = 500 mV, f = 1 kHz; Carrier I/P Vp = 500 mV, f = 500 kHz)
Oscilloscope
Spectrum
Analyzer
5-26
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 500 mV, f = 1 kHz; Carrier I/P Vp = 500 mV, f = 500 kHz)
Oscilloscope
Spectrum
Analyzer
5-27
Analog Communication Trainer
Table 5-9 Measured results of modulated DSB-SC signal (DSB-SC O/P). (Continue)
(Audio I/P Vp = 500 mV, f = 1 kHz; Carrier I/P Vp = 500 mV, f = 500 kHz)
Oscilloscope
Spectrum
Analyzer
5-28
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 200 kHz)
TP1
and
TP2
TP3
and
TP4
5-29
Analog Communication Trainer
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 200 kHz)
Oscilloscope
Spectrum
Analyzer
5-30
Chapter 5 DSB-SC and SSB Modulator
(Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 200 kHz)
Oscilloscope
Spectrum
Analyzer
5-31
Analog Communication Trainer
( Audio I/P Vp = 300 mV, f = 1 kHz; Carrier I/P Vp = 300 mV, f = 200 kHz )
Oscilloscope
Spectrum
Analyzer
5-32
Chapter 5 DSB-SC and SSB Modulator
2. Explain the reasons that why the audio signal and the carrier signal need
phase shifter to produce the orthogonal signal.
4. Explain the output signal waveform of SSB O/P, if the phase difference of
DSB - SC Q and DSB - SC I is same. (Refer to the measured results from
5-33
Analog Communication Trainer
5-34
Chapter 6
m(t) represents the audio signal or the low frequency signal. If this signal is
y D kX DSSC ( t )2 cos(2f C t )
0.5m( t )[cos(4f C t ) 1]
6-2
Chapter 6 DSB-SC and SSB Demodulator
expression as
smaller than 2fc, then the only term left in equation (6-2) is
X D (f ) 0.5M (f ) (6-3)
x D ( t ) 0 .5 m ( t ) (6-4)
demodulator in figure 6-1 can recover the m(t) signal from the DSB-SC
signal.
yD (t )
Balanced
x DSSC ( t ) LPF x D (t)
Modulator
Carrier Signal
6-3
Analog Communication Trainer
On the other hand, if we consider the phase difference (t) between the
carrier signals of the demodulator and modulator, then this situation will
cause the signal distortion and the demodulator is unable to recover the
y D ( t ) kx DSSC ( t )2 cos(2f C t ( t ))
a time domain function, then the signal will critically distort and unable to
As for the SSB signal, it can be divided into upper SSB signal and
6-4
Chapter 6 DSB-SC and SSB Demodulator
or
where
or
6-5
Analog Communication Trainer
x D ( t ) cos(2f m t ) (6-11)
demodulator in figure 6-2 can recover the m(t) signal from the SSB signal.
On the other hand, if we consider the phase difference (t) between the
carrier signals of the demodulator and modulator, then this situation will
cause the signal distortion and the demodulator is unable to recover the
cos(2f m t ( t )) cos[2(2f C f m ) t ( t )]
or
cos(2f m t ( t )) cos[2(2f C f m ) t ( t )]
Therefore, when yDU(t) pass through the low-pass filter, then we get
6-6
Chapter 6 DSB-SC and SSB Demodulator
x USSB ( t ) y DU ( t )
Balanced
LPF x D (t )
x LSSB ( t ) Modulator y DL ( t )
Carrier Signal
x D ( t ) cos(2f m t ( t ))
(6-14)
cos(2f m t ) cos(( t )) sin(2f m t ) sin(( t ))
x D ( t ) cos(2f m t ( t ))
(6-15)
cos(2f m t ) cos(( t )) sin( 2f m t ) sin(( t ))
the audio signal can be recovered. If the phase difference is not zero, then
we notice that the demodulated signal will distort and unable to recover to
6-7
Analog Communication Trainer
Assume that xAM(t) be the modulated DSB-SC and SSB signal, xc(t) be the
When these two signals input into two differential ports of balanced
x out (t ) kx c ( t ) x AM ( t )
k A DC A c2 k A DC A c2 (6-18)
m cos (2f m t )
2 2
k A DC A c2
1 m cos (2f m t)cos2 (2f c t)
2
Where k represents the gain of the balanced modulator. The first term
is the DC signal, second term is the audio signal and third term is the second
harmonic of modulated AM signal. If we can take out the second term from
xout (t), then we can obtain the exact demodulated DSB-SC and SSB signals
or audio signal.
6-8
Chapter 6 DSB-SC and SSB Demodulator
the output signal of MC1496 is located at pin 12. Capacitors C7, C9 and
resistor R9 comprise a low-pass filter which can remove the unwanted third
term of equation (6-18), i.e. second harmonic of modulated AM signal.
Since the active low-pass filter provides gain, so, the objective of the
low-pass filter is to prevent attenuation on the output signal due to the RC
circuit. The DC signal, which is the first term of equation (6-18), can be
blocked by C10. Therefore the signal that we obtain at output port will be
k A DC A c2
x out ( t ) m cos (2 f m t ) (6-19)
2
R2 R4
1k 1k
+12 V
C1 R1 C4 R 51 k
100 nF 1k 100 nF C8
R7 R8 100 nF
C2 8 2 3 2k 2k
VR1 R3
10
Carrier100 k 1k 6
100 nF TP1
I/P MC1496
DSB-SC or SSB C3100 nF
1 Balanced +12V
I/P R9
Modulator TP2
12 + C10
1k Audio
C9 uA741
VR 2
14
100 nF O/P
+ 10 nF
100 k 4 5 C6 C7 -12V
2 u2F 100 nF
C5 R6 R11
100 nF R10
10 k
10 k +12 V 10 k
Figure 6-3 Circuit diagram of synchronous product detector.
6-9
Analog Communication Trainer
3. At the audio signal input port (Audio I/P) in figure ACS5-1, input a 300
mV amplitude and 1 kHz sine wave frequency. Then at the carrier signal
input port (Carrier I/P) in figure ACS5-1, input a 300 mV amplitude and
200 kHz sine wave frequency.
4. By using oscilloscope, observe on both the audio signal output ports TP1
and TP2 in figure ACS5-1 at the same time. Next adjust variable resistor
“QPS” so that the phase difference between TP1 and TP2 is 90. Then
by using oscilloscope, observe on both the carrier signal output ports
TP3 and TP4 in figure 5-1 at the same time. Next adjust variable resistor
“Phase Adjust” so that the phase difference between TP3 and TP4 is 90.
VR1 (gain adjustment) so that the output amplitude of the carrier signal
is maximum without distortion, and also adjust variable resistor VR3
6-10
Chapter 6 DSB-SC and SSB Demodulator
(modulation index adjustment) so that the center level of upper peak and
lower peak are 0 V or the modulation index is 100 %. By using
oscilloscope again, observe on the output signal waveforms of
DSB SC I modulation output port (TP6). Next adjust variable resistor
VR2 (gain adjustment) so that the output amplitude of the carrier signal
is maximum without distortion, and also adjust variable resistor VR4
(modulation index adjustment) so that the center level of upper peak and
lower peak are 0 V or the modulation index is 100 %.
8. Let J1 be open circuit and J2 be short circuit. Then repeat step 7 and
record the measured results in table 6-2.
6-11
Analog Communication Trainer
3. At the audio signal input port (Audio I/P) in figure ACS5-1, input a 300
mV amplitude and 2 kHz sine wave frequency. Then at the carrier signal
input port (Carrier I/P) in figure ACS5-1, input a 300 mV amplitude and
200 kHz sine wave frequency.
4. By using oscilloscope, observe on both the audio signal output ports TP1
and TP2 in figure ACS5-1 at the same time. Next adjust variable resistor
“QPS” so that the phase difference between TP1 and TP2 is 90. Then
by using oscilloscope, observe on both the carrier signal output ports
TP3 and TP4 in figure 5-1 at the same time. Next adjust variable resistor
“Phase Adjust” so that the phase difference between TP3 and TP4 is 90.
VR1 (gain adjustment) so that the output amplitude of the carrier signal
is maximum without distortion, and also adjust variable resistor VR3
(modulation index adjustment) so that the center level of upper peak and
lower peak are 0 V or the modulation index is 100 %. By using
6-12
Chapter 6 DSB-SC and SSB Demodulator
6. Connect the modulated SSB signal (SSB O/P) in figure ACS5-1 to the
input terminal (DSB-SC/SSB I/P) of the product detector in figure
ACS6-1. At the same time, input the same carrier signal in figure
ACS5-1 to the carrier signal input port (Carrier I/P) in figure ACS6-1.
8. Let J1 be open circuit and J2 be short circuit. Then repeat step 7 and
record the measured results in table 6-4.
6-13
Analog Communication Trainer
TP1
TP2
Audio
O/P
6-14
Chapter 6 DSB-SC and SSB Demodulator
TP1
TP2
Audio
O/P
6-15
Analog Communication Trainer
TP1
TP2
Audio
O/P
6-16
Chapter 6 DSB-SC and SSB Demodulator
TP1
TP2
Audio
O/P
6-17
Analog Communication Trainer
6-18
Chapter 7
FM Modulator
Analog Communication Trainer
7-2
Chapter 7 FM Modulator
modulate the frequency of carrier signal. The transmitted high and low
frequency signals will follow the received audio signal, which has different
expressed as
Then
f Am
x FM ( t ) A c cos [ 2 f c t sin (2 f m t )]
fm
Where
f c : Carrier frequency.
: Modulation index, A m (f / f m ) .
f : Frequency deviation.
7-3
Analog Communication Trainer
1 d 1 d
f ( t ) [ 2 f c t sin (2 f m t ) ]
2 dt 2 dt
f c f m cos (2 f m t ) f c A m f cos (2 f m t ) (7-3)
signal changes, the frequency of FM will change too, and it uses the center
A f
BW 2( 2) f m 2 m 2 f m 2 (A m f 2f m )
fm
If the FM signal is the largest amplitude and largest frequency (i.e. Am=1
BW 2 (f W )
which its capacitance can be varied by adding a reverse bias voltage to the pn
junction. When reverse bias voltage increases, the depletion region becomes
wide, this will cause the capacitance value decreases; nevertheless when
7-4
Chapter 7 FM Modulator
reverse bias voltage decreases, the depletion region will be reduced, this will
cause the capacitance value increases. Varactor diode also can be varied from
modulating signal.
a varactor diode does not have bias, the concentration will be different from
minor carriers at pn junction. Then these carriers will diffuse and become
depletion region. The p type depletion region carries electron positive ions,
then the n type depletion region carries negative ions. We can use parallel
PN Junction
+
- ++
N
P
+
+
+
Depletion Region
_ _ +
_ _ _ + + +
_ _ _ + + +
_ + +
Parallel Board
Substract
7-5
Analog Communication Trainer
A
C (7-4)
d
Where
o 8.85x10 12 .
d : Depletion width.
When reverse bias voltage increases, the width of depletion region d will
increase but the cross section area A remains, therefore the capacitance value
would be reduced. On the other hand, the capacitance value will increase
an inductor (Ls) as shown in figure 7-2. From figure 7-2, Cj is the junction
7-6
Chapter 7 FM Modulator
Cj RS
Figure 7-2 Equivalent circuit diagram varactor diode.
CV2
TR (7-5)
C V1
Where
TR : Tuning ratio.
shown as below
TR 2.65 (3 V ~ 30 V).
7-7
Analog Communication Trainer
VCC
16
Phase 2 Phase Comp. 1
3 Comp. Out
Comp. In 13 Phase Comp. 2
1
14 Phase Out
Signal In
1 Comp.
Phase Pulses 2
4 VCO Out
6 CLA
VCO In 9 VCO 7
CLB
11 Max. Freq.
Demodulator 10 12 Min. Freq.
Out
8 5
GND INH
MC4046 is the phase locked loop (PLL) integrated circuit. Figure 7-3 is
the internal structure diagram of MC4046. Pin 1, pin 10 and pin 15 are in N.C.
mode. Pin 5 is the input of INH, which is situated in low voltage level. The
VCO oscillation frequency of MC4046 is determined by the input voltage at
pin 9, the capacitances at pin 6 and pin 7, the resistances at pin 11 and pin 12.
7-8
Chapter 7 FM Modulator
adjusting the variable resistor VR1 (DC level), we can control the output
frequency at pin 4, which is the frequency fo; capacitor C2, resistor R6 and R7
R4
10 k
+12V
C1 R1 +12 V
A u di o
+
uA741 9 16
I/ P 10 k
100 nF -
+12V -12 V
R5 6
C2 4046 4 FM
7
R 2 4 k7 VCO O/P
10 nF 11
20 k
12
V R1 3 5 8
R6
10 k 56 k R7
R 100 k
3
20 k
the internal structure diagram of LM566. Figure 7-6 shows the circuit
7-9
Analog Communication Trainer
controlled by C3, VR1 and audio signal input terminal voltage. C2 is used to
output signal frequency and the voltage difference between pin 8 and pin 5
decrease, the output signal frequency will decrease as well. But, when input
Another factor that affects the output signal frequency is VR 1 C 3 value, the
But when the VR 1 C 3 value is getting smaller then the output signal
frequency is getting higher. From figure 7-6, when we short circuit SW1, then
The center frequency (fo) can be adjusted by using VR1. If audio signal input
terminal is inputted with an AC signal, the VCO output signal frequency will
follow the change of the input audio signal voltage, which the FM signal is
deviated.
7-10
Chapter 7 FM Modulator
GND 1 8 Vcc
Schmitt Trigger
Timing
2 7
Capacitor
Triangle Modulation
Wave Output 4 5
Input
+5V
VR1
R1 5k
3 k3 8
FM
6 3
O/P
C2 LM566
C1 R3
10 nF VCO 4 k7
Audio 5
I/P R2 1 7
100 nF
8 k2 C3
DC
I/P 100 nF
-5V
7-11
Analog Communication Trainer
7-3: Experiment
3. At the audio signal input port (Audio I/P), input 300 mV amplitude and 1
kHz sine wave frequency. By using oscilloscope, observe on the output
signal waveforms of FM O/P, then record the measured results in table
7-2.
4. According to the input signals in table 7-2, repeat step 3 and record the
measured results in table 7-2.
7-12
Chapter 7 FM Modulator
3. At the audio signal input port (Audio I/P), input 300 mV amplitude and 1
kHz sine wave frequency. By using oscilloscope, observe on the output
signal waveforms of FM O/P, then record the measured results in table
7-4.
4. According to the input signals in table 7-4, repeat step 3 and record the
measured results in table 7-4.
7-13
Analog Communication Trainer
FM O/P
7-14
Chapter 7 FM Modulator
FM O/P
7-15
Analog Communication Trainer
FM O/P
7-16
Chapter 7 FM Modulator
FM O/P
7-17
Analog Communication Trainer
FM O/P
7-18
Chapter 7 FM Modulator
FM O/P
7-19
Analog Communication Trainer
7-20
Chapter 8
FM Demodulator
Analog Communication Trainer
8-2
Chapter 8 FM Demodulator
Phase locked loop or PLL is a feedback circuit. In the feedback loop, the
feedback signal will lock the output signal frequency and phase with the same
frequency and phase of the input signal. So, for wireless communication, if
the frequency of the carrier signal deviates during transmission, then the PLL
in the receiver will operate and lock the carrier signal. In this experiment,
there are two types of using PLL, and the first type is demodulator, which is
used for demodulation by following the variation of phase and frequency. The
second is the carrier frequency tracking which is used to track the changes of
Normally, phase locked loop can be divided into 3 sections, there are
8-3
Analog Communication Trainer
From figure 8-1, the function of phase detector is to receive input signal
and VCO signal, then the two signals are compared by phase detector and
provided an output signal, which is a pulse signal. After that this signal is then
sent to a low-pass filter to remove the unwanted signal and left the DC
voltage.
Vo
VCO Ko
8-4
Chapter 8 FM Demodulator
From figure 8-2(a) shows the phase difference between two input signals is
the smallest, so the output signal pulse width is the narrowest. Then figure
8-2(b) shows the phase difference between two input signals is larger than
figure 8-2(a), so the output signal pulse width is wider than figure 8-2(a).
Figure 8-2(c) shows the phase difference between two input signals is the
largest and therefore the output signal pulse width is the widest. If this three
output signals pass through the low-pass filter to remove the AC signal, then
the magnitude of DC voltage in figure 8-2 is as follow: 1. figure 8-2(c) has the
highest DC voltage, 2. figure 8-2(b) is the second higher, and 3. figure 8-2(a)
8-5
Analog Communication Trainer
Input A
XOR Output
Input B
A
Input
B
Output
(a) (b) (c)
DC
Output
Signal
(V)
Input Signal
Phase Difference
0 90 180 270 360
(d)
From figure 8-3, assume that the free-running frequency of a VCO is set
to 1 kHz (assume the bias voltage is 2 V). If inputting a signal A is below 1
kHz and a signal B is higher than 1 kHz. From figure 8-3, we found that,
when input signal A frequency lower than the free-running frequency of VCO,
then the output of low-pass filter will receive a lower voltage level (assume is
1 V), this lower voltage level will adjust the oscillation frequency of VCO, so
that the oscillation frequency will decrease until the frequency of output
signal of VCO and the frequency of signal A equal to each other. When input
signal B frequency is higher than the basic frequency of VCO, the output
terminal of low-pass filter will receive a higher voltage (assume is 3 V), so
8-6
Chapter 8 FM Demodulator
that the oscillation frequency of VCO will increase until the frequency of
output signal of VCO and the frequency of signal B equal to each other.
Normally the time needed for VCO locked frequency is very short. The
above-mentioned discussion is only the description of the concept, however,
practically; the circuit of phase detector is quite difficult and complicated.
Signal A Small DC
980Hz Voltage
XOR Output
VCO
1 kHz Large DC
XOR Voltage
Signal B
Output
1.2 kHz
Figure 8-4 is a LM565 phase locked loop circuit diagram, from figure
8-4, when input terminal does not input any signal, the output signal
1
Free-running frequency: f o (8-1)
3.7 VR 1 C 2
8-7
Analog Communication Trainer
33.6f o
Closed loop gain: K L K d K a K o (8-2)
Vc
+5V
6 10
C1
1 uF
Signal Vi 2 C3
Input Phase Vd R3 0.1 uF
Amp. Signal
3 Detector
R1 Ka 7 Output
0.68 k 3.6 k
5
Kd
SW1 C4
VCO 0.001uF
Ko LM565
4 Vo
R2
0.68 k
1 9 8
C2
0.1uF VR1
5K
5V +5V
the input signal frequency (fi) slowly move away from fo, when fi reaches at a
certain frequency, the PLL will leave the locked situation. At this moment,
8 fo
fL (8-3)
VC
8-8
Chapter 8 FM Demodulator
At the beginning, PLL is at not locked situation, and then let the input
1 2 f L
fc (8-4)
2 3.6 10 C 2
3
fL fL
fc fc
f Lh
fi
f L1 f Cl fo fch Hz
increases, then the output signal voltage decrease. However, when the input
signal frequency decreases, the output signal voltage will increase, therefore,
8-9
Analog Communication Trainer
we can utilize the relationship between the voltage of PLL and frequency to
LM565 phase detector and VCO are designed in the IC package, this
VCO and LM566 are the same. The free-running frequency fo of VCO is
decided by the external C2 and VR1. The low-pass filter is comprised by the
parasitic oscillation.
Audio Signal
Input d Envelop DC
xFM(t) dt Detector Output
Blocked
Figure 8-6 is a MC4046 phase locked loop circuit diagram. From figure
8-6, when input terminal does not input any signal, the output signal
8-10
Chapter 8 FM Demodulator
1
Free-running frequency: f o (8-5)
VR 1 C 2
the input signal frequency (fi) slowly move away from fo, when fi reaches at a
certain frequency, the PLL will leave the locked situation. At this moment,
At the beginning, PLL is at not locked situation, and then let the input
1 2 f L
2f c (8-7)
R 1 R 2 C1
8-11
Analog Communication Trainer
+12 V
2 16 3 VCO
R1 9 4
4 k7 O/P
6
R2 C2 7
4046
PLL
680 10 nF 11 4 Audio
C1 12
3 5 8
O/P
10 nF R3
56 k VR1
100 k
demodulator. When the input signal frequency increases, then the output
signal voltage decrease. However, when the input signal frequency decreases,
the output signal voltage will increase, therefore, we can utilize the
demodulator.
therefore, we utilize the low-pass filter in figure 8-7 to remove all the
unwanted signals. Capacitors C1, C2, resistors R1, R2, R3, R4 and A741
8-12
Chapter 8 FM Demodulator
R4
Av 1 (8-8)
R1
Cutoff frequency is
1
fo (8-9)
2 R 2 R 3C1C 2
If R 2 R 3 R and C1 C 2 C , then
1
fo (8-10)
2RC
R 4 1 k5
R1
1 k5 +12 V
Audio
uA741
O/P
C1 R 2 -12 V
1 nF 10 k
Audio
I/P R3 C2
1 k5 1 nF
8-13
Analog Communication Trainer
2. Let J2 be short circuit and J3 be open circuit, i.e. C2 = 100 nF. Let J1 be
open circuit, i.e. SW1 be open circuit.
3. Adjust the variable resistor VR1, then measure the maximum ( f oh ) and
minimum ( f ol ) free-running frequencies (refer to figure 8-5) at the VCO
output port (VCO O/P). Then record the measured results in table 8-1.
5. Let J1 short circuit, and at the input port, input 0.25 V amplitude and 2
kHz square wave frequency.
8-14
Chapter 8 FM Demodulator
9. Increase the input signal frequency so that the output signal frequency of
Audio O/P is unable to lock the input signal. Then slightly decrease the
input signal frequency until the Audio O/P locks the input signal. Then
observe on the input signal frequency f Ch and record the measured
results in table 8-1.
10. Decrease the input signal frequency so that the output signal frequency of
Audio O/P is unable to lock the input signal. Then slightly increase the
input signal frequency until the Audio O/P locks the input signal. Then
observe on the input signal frequency f Cl and record the measured
results in table 8-1.
12. Let J1 be open circuit, J3 be short circuit and J2 be open circuit, which
means that C2 changes to C5, i.e. 100 nF changes to 10 nF, then repeat
step 3.
8-15
Analog Communication Trainer
13. Adjust the variable resistor VR1, so that the free-running frequency (fo) of
the VCO O/P is 20 kHz. Let J1 be short circuit and at the input terminal,
input 0.25 V amplitude and 20 kHz square wave frequency, then repeat
step 6 to step 11.
2. Let J2 be short circuit and J3 be open circuit, i.e. C2 = 100 nF. Let J1 be
open circuit and adjust the variable resistor VR1 so that the free-running
frequency (fo) of VCO O/P is 2 kHz.
4. At the demodulated FM input port (FM I/P), input 0.25 V amplitude and
2 kHz square wave frequency. Then measure the voltage of Audio O/P
and record the measured results in table 8-2.
5. Change the input signal frequencies to 0.5 kHz, 1 kHz, 1.5 kHz, 2 kHz,
2.5 kHz, 3 kHz, 3.5 kHz. Then measure the voltage of Audio O/P and
record the measured results in table 8-2.
8-16
Chapter 8 FM Demodulator
8. Let J1 be open circuit and adjust the variable resistor VR1, so that the
free-running frequency (fo) of the VCO O/P is 20 kHz.
10. At the FM I/P, input 0.25 V amplitude and 20 kHz square wave
frequency. Then measure the voltage of Audio O/P and record the
measured results in table 8-3.
11. Change the input signal frequencies to 16.5 kHz, 17.5 kHz, 18.5 kHz, 20
kHz, 21.5 kHz, 22.5 kHz, 23.5 kHz. Then measure the voltage of Audio
O/P and record the measured results in table 8-3.
12. Sketch the characteristic diagram with voltage versus frequency in figure
8-9.
8-17
Analog Communication Trainer
i.e. C5 = 10 nF. Adjust the variable resistor VR1, so that the free-running
frequency (fo) of the VCO O/P is 20 kHz.
3. Connect the output port (FM O/P) of the VCO LM566 to the input port
(FM I/P) of the PLL LM565.
4. At the audio input port (Audio I/P) of the VCO LM566, input 250 mV
amplitude and 1 kHz sine wave frequency. By using oscilloscope,
observe on the output signal waveforms of the demodulated FM signal
(Audio O/P) at PLL LM565. Then record the measured results in table
8-4.
5. According to the input signals in table 8-4, repeat step 4 and record the
measured results in table 8-4.
6. According to the input signals in table 8-5, repeat step 4 and record the
measured results in table 8-5.
8-18
Chapter 8 FM Demodulator
3. Connect the output port (FM O/P) of the VCO MC4046 to the input port
(FM I/P) of the PLL MC4046.
4. At the audio input port (Audio I/P) of the VCO MC4046, input 250 mV
amplitude and 1 kHz sine wave frequency. By using oscilloscope,
observe on the output signal waveforms of the demodulated FM signal
(Audio O/P) at PLL MC4046. Then record the measured results in table
8-6.
5. According to the input signals in table 8-6, repeat step 4 and record the
measured results in table 8-6.
6. According to the input signals in table 8-7, repeat step 4 and record the
measured results in table 8-7.
8-19
Analog Communication Trainer
Free-running
Locked Range fL Captured Range fC
Frequency Range
C2 fo
foh fol fLh fLl fCh fCl
Hz Hz Hz Hz
100
2 kHz
nF
Hz Hz fL = Hz fC = Hz
Hz Hz Hz Hz
10 20
nF kHz
Hz Hz fL = Hz fC = Hz
8-20
Chapter 8 FM Demodulator
Table 8-2 Measured results of the voltage and frequency conversion characteristics of
LM565 PLL. (Vm = 0.25 V, fo =2 kHz, C2 = 100 nF)
Input Signal
Frequencies 0.5 1.0 1.5 2.0 2.5 3.0 3.5
(kHz)
Output Voltages
(V)
Output
Voltage
(V)
Input Signal
Frequency
0.5 1.0 1.5 2.0 2.5 3.0 3.5 ( kHz )
8-21
Analog Communication Trainer
Table 8-3 Measured results of the voltage and frequency conversion characteristics of
LM565 PLL. (Vm = 0.25 V, fo =20 kHz, C5 = 10 nF)
Input Signal
Frequencies 16.5 17.5 18.5 20 21.5 22.5 23.5
(kHz)
Output Voltages
(V)
Output
Voltage
(V)
Input Signal
Frequency
0.5 1.0 1.5 2.0 2.5 3.0 3.5 ( kHz )
8-22
Chapter 8 FM Demodulator
Table 8-4 Measured results of the input and output signal waveforms of PLL frequency
demodulator. ( Vm 250 mV , f o 20 kHz )
Audio signal
FM I/P Audio O/P
frequencies
1 kHz
2 kHz
3 kHz
8-23
Analog Communication Trainer
Table 8-5 Measured results of the input and output signal waveforms of PLL frequency
demodulator. ( Vm 500 mV , f o 20 kHz )
Audio Signal
FM I/P Audio O/P
Frequencies
1 kHz
2 kHz
3 kHz
8-24
Chapter 8 FM Demodulator
Table 8-6 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. ( Vm 250 mV , f o 20 kHz )
Audio Signal
1 kHz 2 kHz
Frequencies
FM I/P
TP2
LPF IN
Audio O/P
8-25
Analog Communication Trainer
Table 8-7 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. ( Vm 500 mV , f o 20 kHz )
Audio Signal
1 kHz 2 kHz
Frequencies
FM I/P
TP2
LPF IN
Audio O/P
8-26
Chapter 8 FM Demodulator
2. For LM565 PLL, compare the locked range and the captured range.
3. In figure 8-4, what are the functions for capacitor C3? If let C3 change
from 0.1 F to 0.01 F, what are the changes of the pin 7 of LM565?
5. How to use the PLL circuit and the logic circuit to comprise a doubler
frequency circuit?
8-27
Analog Communication Trainer
8-28
Chapter 9
TDM Multiplexer
Analog Communication Trainer
signal is varied from time. If the signal is separated into several slots of time,
9-2
Chapter 9 TDM Multiplexer
bandwidth (fM) and a constant sample rate (TS), then the expression of the
S(t)= X ( t ) ( t nTS ) (9-1)
n
X(t) S(t)
t t
n
(t nTS )
S(f)= f S X (f nf S ) (9-2)
n
9-3
Analog Communication Trainer
1
Where f S .
TS
X(t) with a frequency bandwidth (fM), we can sample the signal with a
certain period sampling function t nTS . Assume that the amplitude
of the sampling function is 1, the period is TS, the width of the slot is , then
by sampling the signal X(t) with the sampling function, we can obtain Y(t)
as follow
t nTS
Y(t)= X ( t ) ( ) (9-3)
n
X(t) Y(t)
t t
t nTS
n
(
)
9-4
Chapter 9 TDM Multiplexer
(9-3), by using Fourier transform, we can obtain the spectrum of the ideal
sampling Y(f) as
Y(f)= f S sin c( nf S ) X (f nf S ) (9-4)
n
instantaneous sampling, we will obtain the sampling function S(t) and its
fS > 2fM, then the permutation of the spectrum will separate without
S(f) LPF
f
-f S -f M fM fS-fM fS
Figure 9-3 Output signal spectrum of sampling when fS > 2fM.
In figure 9-3, we can see that if S(f) passes through a low-pass filter
(LPF), the frequency band will smaller than fS-fM but greater than fM, then
we can recover the original signal from the signal after sampling. However,
9-5
Analog Communication Trainer
2fM, or else, after sampling the signal will overlap and unable to recover the
S(f) LPF
f
-f S fS
value is transmitted with a gap Ts, and the sampling value can be assumed
value of other signal. Let the numbers of the input signals are M, then the
r = M f S ≧2M f M (9-5)
9-6
Chapter 9 TDM Multiplexer
transmitted over the same transmission channel. Time division indicates the
signal is divided into several slots in time domain, then these slots will
transmit to the receiver by following a fixed time slot. It uses the technique
of sampling to divide the signal into several slots, therefore, these slots is
also called as sampling values. If the fixed time slot is large enough for
other sampling value of other signal to fill in, then this method can achieve
the function of multiplexing. As for the TDM system with several input
signals, we can refer to the basic structure as shown in figures 9-5 and 9-6.
Y(t)
m1(t)
m2(t)
Figure 9-5 TDM system with two signals m1(t) and m2(t).
9-7
Analog Communication Trainer
modulation. The following are the discussion of the sinusoidal, square and
R3
A ( j) 1 (9-6)
R1
9-8
Chapter 9 TDM Multiplexer
1
R2
jC1
1
R2
Vf jC1
( j)
Vo 1
R2
1 jC1
R4
jC 2 1
R2
jC1
R2 1 R2 R4 R2
( )
C 2 2 C1 C 2 C 2
1 1 R R R
(R 2 R 4 2 )2 2 ( 2 4 2 )
C1 C 2 C1 C 2 C 2
1 R2 1
(R 2 R 4 2 )
C2 C1C 2
j (9-7)
1 1 R R R
(R 2 R 4 2 )2 2 ( 2 4 2 )
C1C 2 C1 C 2 C2
R3
Vf R3 Vo
A 1
R1 R1
+12V
Vo
A
-12V Output C2 R4
Vf
C2 R4 R2 C1
R2 C1 ( j)
Feedback
Network
(a) Circuit diagram of oscillator. (b) Oscillator feedback structure.
9-9
Analog Communication Trainer
should be a real number and the phase must be 0o during oscillation. From
equation (9-6), A ( jo ) is a real number, and from equation (9-7), the
1 R2 1
(R 2 R 4 2 )
o C 2 o C1C 2
0 (9-8)
1 1 R2 R4 R2
(R 2 R 4 2 ) 2(
2
)
o C1C 2 o C1 C 2 C 2
1
o2 (9-9)
R 2 R 4 C1C 2
1
o (9-10a)
RC
1
fo (9-10b)
2RC
9-10
Chapter 9 TDM Multiplexer
R2 1 R2 R4 R2
( )
C 2 o2 C1 C 2 C 2
A 1 (9-11b)
1 1 R R R
(R 2 R 4 2 )2 2 ( 2 4 2 )
o C1C 2 o C1 C 2 C 2
into equation (9-11b). At the same time, when oscillation occurs, the loop
R3
A (1 )3 (9-12a)
R1
R3
2 (9-12b)
R1
1
1. f o
2RC
R3
2. A (1 )3
R1
Practically, when the gain achieves the oscillation condition, the circuit will
9-11
Analog Communication Trainer
f o 1 2RC . In addition, the output voltage may become larger and larger,
oscillators.
therefore, we can adjust the magnitude of VR1 to satisfy the condition for
oscillation and let the gain of the amplifier larger than 3, i.e., a sinusoidal
is very large, the diodes D1 and D 2 will conduct ( D 2 conducts when the
positive half cycles is very large, D1 conducts when the negative half
as shunt the forward-conducted resistor of diode and the result is the same
non-linear distortion.
9-12
Chapter 9 TDM Multiplexer
Assume that the output of U1 (O/P1) is positive voltage, and the two
port is larger than U1- port, therefore, the output port (O/P1) is always
through resistor R2 and variable resistor VR1. When the charge of capacitor
positive voltage to negative voltage. The reason is the voltage at U1+ port is
smaller than U1- port, thus U1 can be used as a square wave generator. At
this moment, the output O/P1 is negative voltage and the capacitor C1 is
will start to change from negative voltage to positive voltage. Then this
circuit can be used to produce triangle wave and square wave as shown in
figure 9-10. The function of variable resistor VR1 is to adjust the operation
period of the triangle wave, i.e. to adjust the frequency of the triangle wave.
Then U2, R4 and VR1 comprise a tunable inverting amplifier. The output
9-13
Analog Communication Trainer
R3
D1 1N4148
R 5 3k3
VR 1 D 2 1N4148
5k
+12V
uA741
R1 O/P
2k -12V
C2
100 pF R 4
R2 C1 1k2
1k2 100 pF
R2
100
VR 1 +12V
100 k
O/P1 O/P2
C1
10 nF uA741 uA741
-12V VR 1
R1 R3
10 k 100 k R4 100 k
10 k
Figure 9-9 Circuit diagram of triangle wave and square wave generators.
9-14
Chapter 9 TDM Multiplexer
V O/P1
+Vcc
-Vcc
O/P2
need to produce a time generator circuit, which can generate a fixed timing
as the switching circuit. Figure 9-11 is the circuit diagram of the switching
circuit with fixed timing. In figure 9-11, we utilize timer (NE555) and
9-15
Analog Communication Trainer
finally match up the circuit with the analog switch (CD4066), we can obtain
the TDM circuit as shown in figure 9-13. When Q0 is at “High” level (ON),
the triangle wave will occur at the output port. When Q1 is at “High” level
(ON), the square wave will occur at the output port. When Q2 is at “High”
level (ON), the sinusoidal wave will occur at the output port. When the
counter counts to Q4, the IC CD4017 will reset and start to recount from Q0.
With this method, we can transmit the three different signals by using one
impedance matching.
The operation time (T) of NE555 is the time of every time slot, therefore,
the operation period is same. Then with this reference, we can obtain the
9-16
Chapter 9 TDM Multiplexer
R1
100 k 16
4 8
7 3 t1
2 t2
R2
+
555 3 13
Vcc 10 k Timer 4017 4 t3
2 Counter
6 15 7
Vc C1 1 5 8
100 nF
C2
10 nF
t0
t1
t2
Clk
Figure 9-12 Time sequence of the time generator.
9-17
Analog Communication Trainer
CD 4066
Triangle
Wave
t1
-
Square U1
Wave +
TDM
Output Signal
t2
Sinusoidal
Wave
t3
Figure 9-13 Circuit diagram of TDM multiplexer.
9-18
Chapter 9 TDM Multiplexer
1. Refer to the sinusoidal, triangle and square waves generator in figure 9-8
and figure 9-9 or refer to figure ACS9-1 of ACT-17300-05 module.
9-19
Analog Communication Trainer
1. Refer to the time generator and analog switch in figure 9-11 and figure
9-12 or refer to figure ACS9-1 of ACT-17300-05 module.
2. Turn the variable resistor “Clock Adj.” left to the end, at this moment, the
counter of the clock is slow. By using the CH1 of the oscilloscope,
observe on the output signal waveform of triangle wave output port (TP4).
Then by using CH2 of the oscilloscope, observe on the output signal
waveform of the TDM output port (TDM O/P). Finally record the output
signal waveforms and voltages in table 9-2.
9-20
Chapter 9 TDM Multiplexer
TP1
TP2
TP3
9-21
Analog Communication Trainer
TP4
and
TDM O/P
TP5
and
TDM O/P
TP6
and
TDM O/P
9-22
Chapter 9 TDM Multiplexer
9-23
Analog Communication Trainer
9-24
Chapter 10
TDM Demultiplexer
Analog Communication Trainer
time to divide the time of the transmission channel into several time slots.
There is a small gap between each time slots, which is known as guard time
and it is used to prevent the interference between the symbol and jitter of the
synchronous signal at the transmitter, the receiver can also separate the
Therefore, for every time slot in packet switching, the transmitted data is not
10-2
Chapter 10 TDM Demultiplexer
10-2. When S1 and S2 rotated, the signal at the transmission path can be
transmitted repeatedly and the receiver can also utilize the synchronous
S2 S2
S3 S3
S4 S4
S1 S1
S2 S2
S3 S3
S4 S4
S1 S2 S3 S4 S1 S2 S3 S4
10-3
Analog Communication Trainer
In chapter 9, we utilize the timer (NE 555) and counter (CD 4017) to
generate the sampling signal and then by using the analog switch (CD 4066)
channel, that channel will be ON, therefore, the signal at the input port will
occur at the output port. Similarly, for the TDM demultiplexer, we also
utilize the timer (NE 555) and the counter (CD 4017) to implement the
NE 555 is
counts to Q3, the CD 4017 will reset and start to count from Q0. Thus, this
circuit is just similar to the three signals in the TDM multiplexer. Therefore,
we just need to obtain the synchronous signals, then we can recover the
original signal.
can obtain the input sequences, which are the triangle, square and sinusoidal
waveforms.
10-4
Chapter 10 TDM Demultiplexer
R1
100 k 16
4 8
7 3 t1
2 t2
R2
+
10 k 555 3 13
Vcc
Timer 4017 4 t3
2 Counter
6
15 7
Vc C1 1 5 8
100 nF
C2
10 nF
-
uA741
+ Triangle
Wave
t1
-
- uA741
TDM uA741 + Square
Signal +
Input Wave
t2
-
uA741
+ Sinusoidal
Wave
t3
10-5
Analog Communication Trainer
1. Refer to the circuits in figure 10-3 and figure 10-4 or refer to figure
ACS10-1 of ACT-17300-05 module.
4. Connect the triangle wave output port (TP4) of the TDM multiplexer to
the triangle wave input port (TP2) of the TDM demultiplexer. By using
CH1 of the oscilloscope, observe on the output signal waveforms of
triangle wave input port (TP2). Then by using CH2 of the oscilloscope,
observe on the output signal waveforms of triangle wave output port
(O/P1) of the TDM demultiplexer. Finally record the output signal
waveforms and voltage in table 10-2.
5. Connect the triangle wave output port (TP4) of the TDM multiplexer to
the triangle wave input port (TP2) of the TDM demultiplexer. By using
CH1 of the oscilloscope, observe on the output signal waveforms of
triangle wave input port (TP2). Then by using CH2 of the oscilloscope,
observe on the output signal waveforms of square wave output port
10-6
Chapter 10 TDM Demultiplexer
10-7
Analog Communication Trainer
square wave input port (TP3). Then by using CH2 of the oscilloscope,
observe on the output signal waveforms of sinusoidal wave output port
(O/P3) of the TDM demultiplexer. Finally record the output signal
waveforms and voltage in table 10-7.
10. Connect the sinusoidal wave output port (TP6) of the TDM multiplexer
to the sinusoidal wave input port (TP4) of the TDM demultiplexer. By
using CH1 of the oscilloscope, observe on the output signal waveforms
of sinusoidal wave input port (TP4). Then by using CH2 of the
oscilloscope, observe on the output signal waveforms of triangle wave
output port (O/P1) of the TDM demultiplexer. Finally record the output
signal waveforms and voltage in table 10-8.
11. Connect the sinusoidal wave output port (TP6) of the TDM multiplexer
to the sinusoidal wave input port (TP4) of the TDM demultiplexer. By
using CH1 of the oscilloscope, observe on the output signal waveforms
of sinusoidal wave input port (TP4). Then by using CH2 of the
oscilloscope, observe on the output signal waveforms of square wave
output port (O/P2) of the TDM demultiplexer. Finally record the output
signal waveforms and voltage in table 10-9.
12. Connect the sinusoidal wave output port (TP6) of the TDM multiplexer
to the sinusoidal wave input port (TP4) of the TDM demultiplexer. By
using CH1 of the oscilloscope, observe on the output signal waveforms
of sinusoidal wave input port (TP4). Then by using CH2 of the
oscilloscope, observe on the output signal waveforms of sinusoidal wave
output port (O/P3) of the TDM demultiplexer. Finally record the output
signal waveforms and voltage in table 10-10.
10-8
Chapter 10 TDM Demultiplexer
10-9
Analog Communication Trainer
10-10
Chapter 10 TDM Demultiplexer
10-11
Analog Communication Trainer
10-12
Chapter 10 TDM Demultiplexer
10-13
Analog Communication Trainer
10-14
Chapter 11
FDM Multiplexer
Analog Communication Trainer
channel only consists of one modulated signal, then the usage of channel is
very low and the efficiency is also not good. Therefore, in order to comfort
with the economic benefit, the channel must be able to transmit multiple
signals, such as in the telephone system, the frequency range of the sound is
300 Hz to 3 kHz. In order to transmit this kind of signal via a single channel,
we must divide the signal into several slots to prevent the interference, then
we can obtain the original signal at the receiver. Generally, there are two
11-2
Chapter 11 FDM Multiplexer
Audio Balanced
Signal 1 Modulator
Carrier
Signal
Audio Balanced
Linearity Adder
Signal 2 Modulator
FDM
O/P
Carrier
Signal
Audio Balanced
Signal 3 Modulator
Carrier
Signal
Figure 11-1 is the system block diagram of FDM. Like TDM, FDM is
simultaneously. However, unlike TDM, FDM does not use pulse modulation.
In figure 11-1, assume that all the input audio signals are low-pass pattern
and after each input signal, there will be a low-pass filter. The objective is to
remove all the unwanted signals except the audio signals. Then the audio
signals will be sent into the modulator so that the frequency range of the
11-3
Analog Communication Trainer
modulated signals will pass through the bandpass filter, which can limit the
signal bandwidth to prevent the interference between each signal. Finally, all
We use ICL8038 to design the audio generator, which can produce sine
wave, triangle wave and square wave. The range of the output frequency
this circuit, we only use sine wave with 2 V output amplitude and 300 Hz to
1.5 kHz output frequency. In figure 11-2, the VR1 is to adjust the output
frequency, which can change the time of charge and discharge. The faster
the time of charge and discharge (the smaller the value of resistor), the
higher the output frequency; nevertheless, the slower the time of charge and
discharge (the larger the value of resistor), the lower the output frequency.
VR2 is used to adjust the output amplitude where the output amplitude can
be varied from 0 V to 2 V.
11-4
Chapter 11 FDM Multiplexer
C 1 10 nF
R3
100 k
+12 V
Frequency
VR 2 Adjustment
14 13 12 11 10 9 8
10 k Audio Signal
Vo VR 1
Generator (ICL8038) 10 k
Output 1 2 3 4 5 6 7
Amplitude R4
Adjustment 1k
R2 R1
Q1
22 k 22 k
3904
+12 V
carrier signal generator. Figure 11-3 is the circuit diagram of Wien Bridge
R3
A ( j) 1 (11-1)
R1
11-5
Analog Communication Trainer
1
R2
jC1
1
R2
Vf jC1
( j)
Vo 1
R2
1 jC1
R4
jC 2 R 1
2
jC1
R2 1 R2 R4 R2
( )
C 2 2 C1 C 2 C 2
1 1 R R R
(R 2 R 4 2 )2 2 ( 2 4 2 )
C1C 2 C1 C 2 C 2
1 R2 1
(R 2R 4 2 )
C2 C1C 2
j (11-2)
1 1 R R R
(R 2R 4 2 )2 2 ( 2 4 2 )
C1C 2 C1 C2 C 2
R3
Vf R3 Vo
A 1
R1 +12V R1
Vo
A
-12V
Output
C2 R4
Vf
C2 R4 R2 C1
R2 C1 ( j)
Feedback
Network
(a) Oscillator circuit diagram. (b) Oscillator feedback structure.
Figure 11-3 Circuit diagram of Wien Bridge oscillator.
11-6
Chapter 11 FDM Multiplexer
real number and the phase must be 0o during oscillation. From equation
(11-1), A( jo ) is a real number, and from equation (11-2), the imaginary
part of ( jo ) is at the second term. Obviously, we can assume this term
1 R2 1
(R 2 R 4 2 )
o C 2 o C1C 2
0 (11-3)
1 1 R2 R4 R2
(R 2 R 4 2 ) 2(
2
)
o C1C 2 o C1 C 2 C 2
1
o2 (11-4)
R 2 R 4 C1C 2
1
o (11-5a)
RC
1
fo (11-5b)
2RC
and we get
11-7
Analog Communication Trainer
R2 1 R2 R4 R2
( )
C 2 o2 C1 C 2 C 2
A 1 (11-6b)
1 1 R R R
(R 2 R 4 2 )2 2 ( 2 4 2 )
o C1C 2 o C1 C 2 C 2
into equation (11-5b). At the same time, when oscillation occurs, the loop
R3
A (1 )3 (11-7a)
R1
R3
2 (11-7b)
R1
1
1. f o
2RC
R3
2. A (1 )3
R1
11-8
Chapter 11 FDM Multiplexer
f o 1 2RC . In addition, the output voltage may become larger and larger,
and then generate a non-linear distortion in the output waveform of
oscillators.
R3
D1
R5
VR1 D2
+12V
A
R1 -12V O/P
C2 R4
R2 C1
therefore, we can adjust the magnitude of VR1 to satisfy the condition for
oscillation and let the gain of the amplifier larger than 3, i.e., a sinusoidal
is very large, the diodes D1 and D2 will conduct ( D 2 conducts when the
positive half cycles is very large, D1 conducts when the negative half
11-9
Analog Communication Trainer
as shunt the forward-conducted resistor of diode and the result is the same
non-linear distortion.
Figure 11-5 is the frequency spectrum between the AM signal and DSB-SC
that the frequency spectrum consists of three kinds of signals, which are
two signals, therefore, the carrier signal does not contain any signal, and the
see that the frequency spectrum consists of two kinds of signals, which are
signal, therefore, by using this type of modulation, the power will not
the double sideband, so, the stronger the double sideband signal, the
11-10
Chapter 11 FDM Multiplexer
Figure 11-7 is the internal circuit diagram of MC1496, where D1, R1, R2, R3,
drive the dual differential amplifiers constructed by Q1, Q2, Q3 and Q4. Pin 1
and 4 are the inputs of audio signal; Pin 8 and 10 are the inputs of carrier
signal. The resistor between pins 2 and 3 controls the gain of the balanced
modulator; the resistor of pin 5 determines the magnitude of bias current for
amplifier.
the carrier signal and audio signal belong to single ended input. The carrier
signal is inputted from pin 10 and the audio signal is inputted from pin 1.
Therefore R8 determine the gain of the whole circuit and R9 determine the
the input amplitude of audio signal, then we can control the percentage
control the magnitude of the output amplitude, which is also the gain.
11-11
Analog Communication Trainer
x AM ( f )
A DC A c
0 .5 mA DC A c 0 . 5 mA DC A c
f (Hz)
fc fm fc fc fm
x AM (f )
0.5mADCA c 0.5mA DC A c
f (Hz)
fc fm fc fc fm
Carrier Signal
11-12
Chapter 11 FDM Multiplexer
(12)
Output
Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal
Input
(8) Q5 Q6
(4)
Audio
Signal
Input (2)
Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
R7
1k 1k
+12
V
R3 C3 R8 1 k
0.1uF
R10 R11
3.9 k 3.9 k
C1 R4 2 3 DSB-SC
Carrier 51 8
0.1uF 6 Signal
Signal C4
10 Output
Input 0.1uF
MC1496
Audio C2
1 12
Signal
0.1uF 4 1
Input 5
R1 R2 R5 R6 4
10 k 10 k 300 1k
R9
50 k 6.8 k
VR1
5V
11-13
Analog Communication Trainer
R1 R4
100 k 100 k
DSB - SC1
R2 +12 V
DSB - SC2 FDM
100 k uA741
O/P
DSB - SC3
R3 -12 V
100 k
11-14
Chapter 11 FDM Multiplexer
11-15
Analog Communication Trainer
11-16
Chapter 11 FDM Multiplexer
11-17
Analog Communication Trainer
11-18
Chapter 11 FDM Multiplexer
TP1
TP3
11-19
Analog Communication Trainer
TP7
TP2
11-20
Chapter 11 FDM Multiplexer
TP4
TP8
11-21
Analog Communication Trainer
TP5
TP6
11-22
Chapter 11 FDM Multiplexer
TP9
FDM O/P
11-23
Analog Communication Trainer
11-24
Chapter 12
FDM Demultiplexer
Analog Communication Trainer
several audio signal and also use different carrier signals to modulate the
signals at different frequency ranges, then finally, we use the linearity adder
There are two ways to implement the FDM demultiplexer. The first
way is shown in figure 12-1(a). Let the FDM signals pass through a
remove the signal, which its frequency is larger and lower than fo, then only
left a single DSB-SC modulated signal. After that this signal will pass
through a low-pass filter, then we can recover the modulated signal and
obtain the original audio signal. The second way to implement the FDM
12-2
Chapter 12 FDM Demultiplexer
the synchronous product detector, we will add a low-pass filter to remove all
the unwanted signal and recover the original audio signal. In this chapter,
we will discuss the operation theory and the design of synchronous product
detector.
FDM Audio
Multiplier
I/P Signal
Carrier Signal
Figure 12-1(b) Block diagram of synchronous product detector.
Figure 12-1 Block diagram of FDM demultiplexer.
12-3
Analog Communication Trainer
Let xAM(t) be the modulated DSB-SC signal and xC(t) be the carrier
signal, then
When these two signals input into two differential ports of balanced
x out (t ) kx c ( t ) x AM ( t )
k A DC A c2 k A DC A c2 (12-3)
m cos (2f m t )
2 2
k A DC A c2
1 m cos (2f m t)cos2 (2f c t)
2
Where k represents the gain of the balanced modulator, the first term is
the DC signal, second term is the audio signal and third term is the second
harmonic of amplitude modulated signal. If we can take out the second term
from xout (t), then we can obtain the demodulated DSB-SC signal or audio
signal.
12-4
Chapter 12 FDM Demultiplexer
The variable resistor VR1 controls the input magnitude of carrier signal;
and R 9 comprise a low-pass filter which can remove the unwanted third
signal. The DC signal, which is the first term of equation (12-3), can be
blocked by C10. Therefore the signal that we obtain at output port will be:
k A DC A c2
x out ( t ) m cos (2 f m t ) (12-4)
2
original amplitude modulated signal can be taken out via product detector.
R2 R4
1k 1k
+12 V
C1 R1 C4 R 51 k
100 nF 1k 100 nF C8
R7 R8 100 nF
C2 8 2 3 2k 2k
VR1 R3
10
Carrier 100 k 100 nF
1k 6 TP1
I/P MC1496
C3100 nF
FDM 1 Balanced +12V
I/P Modulator TP2 R9
12 + C10
1k Audio
C9 uA741
100 nF O/P
14
VR 2 10 nF
100 k +
4 5 C6 C7 -12V
2 u2F 100 nF
C5 R6 R11
100 nF R10
10 k
10 k +12 V 10 k
12-5
Analog Communication Trainer
amplifier U1 not only comprise a Miller integrator circuit, but also provide
after that sum the input signal and output signal of U 3 . Resistor, R 4 ,
gain inverting amplifier. Since we utilize the network synthesize theory, this
R3
R2 15 k
15 k
C1 R 15 k
C2 6
Input R1
10 nF
(Vin ) R4 10 nF
7 k5 uA741 +12 V
R5
15 k uA741
U1 15 k uA741
U2
U3 -12 V Output
(Vout )
12-6
Chapter 12 FDM Demultiplexer
12-7
Analog Communication Trainer
ACT-17300-06 module.
12-8
Chapter 12 FDM Demultiplexer
Audio O/P1
12-9
Analog Communication Trainer
Audio O/P2
12-10
Chapter 12 FDM Demultiplexer
Audio O/P3
12-11
Analog Communication Trainer
1. Describe the types of FDM demultiplexer. And also explain the type of
the FDM demultiplexer in this chapter.
12-12
Chapter 13
Analog to Digital
Converter
Analog Communication Trainer
status is called as analog signal. If via a device that can convert the analog
converter (ADC). ADC can reduce the effect of noise and by using the
technique of coding, ADC has the function of debugging. On the other hand,
digital signal can also be easily stored. Next we will discuss on the basic
13-2
Chapter 13 Analog to Digital Converter
divide the input signal into 8 (23 = 8) ranges, at each range all the analog
values use the same binary code to represent, and this binary code is
that has the analog error, then all of the errors comprise the error value of
ADC. One of the methods to reduce the quantization error is to increase the
number of bits of the converter. The more the numbers of bits, the more the
numbers of ranges and the data signal will be more detail. This is because
reduce. Quantization value (Q) means when the digital output changes 1
LSB, the required input voltage value also changes, the expression is
FS
Q (13-1)
2 1
n
defined as resolution, where n is the ADC digital output bit, so when the
larger the value of n, the higher the resolution. In general, the ADC technical
is 8 bits.
13-3
Analog Communication Trainer
Digital Output
7/8 111
6/8 110
5/8 101
Ideal Steps
4/8 100
Q
1/8 001
which is provided with 8-bit resolution. When we input the analog signal,
sample-and-hold, S&H circuit will capture the input signal Vin to avoid
13-4
Chapter 13 Analog to Digital Converter
any signal change during conversion period. At this moment, the control
logic will store all the bits and reset to" 0 ", follow by the most significant
bit, MSB D 7 is set to " 1 ". Thus, the output voltage of DAC is
Vref 1
V (D) 2 n 1 Q 2 n 1 Vref (13-2)
2n 2
V(D)
DAC Register
Vref
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
Digital Output
This voltage is half of the reference voltage, Vref . If the input voltage
Vin is higher than V(D), then D 7 remains at " 1 ", otherwise alters to " 0 ".
Next, make second bit D6 as " 1 ", after passing through a DAC then obtain
an output voltage V(D), at this moment comparing the new V(D) and Vin ,
if Vin is higher than V(D), then D6 remains at " 1 " otherwise alters to " 0 ".
13-5
Analog Communication Trainer
channel IC. The analog input voltage range is from 0 V to 5 V with single 5
error.
Figure 13-3 shows the pins diagram of ADC0804. In figure 13-3, the D 0
to D7 of ADC0804 is the 8-bit output pins, when CS and RD are low, the
digital data will be sent to the output pins. If any pins of CS and RD are
ADC0804 will do the clear action, when WR backs to high, ADC will start
the conversion. CLK IN (Pin 4) is the clock input, the frequency range starts
from 100 kHz to 800 kHz. During the conversion period, INTR is at high
level and then after the conversion completed, INTR will alter to low. Pin 6
Vin () and pin 7 Vin () are differential analog signal inputs, ordinarily used
13-6
Chapter 13 Analog to Digital Converter
single input terminal and Vin () is connected to ground. ADC0804 has two
ground terminals, one is analog ground (A GND) and another one is digital
floating, then the 1/2 reference voltage equals to power supply voltage Vcc.
resistor and capacitor at CLK R (pin 19) and CLK IN (pin 4), then we can
1
f CLK (Hz) (13-3)
1.1 RC
terminal. We can determine the clock signal by the external R and C via pin
CS 1 20 Vcc
RD 2 19 CLK R
WR 3 18 D0 (LSB)
CLK IN 4 17 D1
INTR 5 16 D2
VIN (+) 6 15 D3
VIN ( ) 7 14 D4
A GND 8 13 D5
VREF /2 9 12 D6
D GND 10 11 D 7 (MSB)
13-7
Analog Communication Trainer
converter, the analog signal input range is controlled by VR2 and input
through the Vin ( ) terminal and at the same time, the Vin () is short
the clock of the circuit, CS and RD are short circuit, so that the IC is
enable, then let WR and INTR connect to SW1 in order to simulate the
control signal.
input signals to operate, the frequency range of the clock signal starts from
13-8
Chapter 13 Analog to Digital Converter
10 kHz to 1280 kHz. At 640 kHz clock frequency, the typical conversion
19
CLK R
4
CLK
CLK IN
ADC0804
+5 V
R 3 10k C4
0.1 uF
C1 Vcc
1 20
150 pF 9-pin network resistors
CLK R
2 19
D0 150
3 18
D1 150
4 17
SW 1
D2 150
5 16
R1 D3 150
2k 6 15
C2 D4 150
7 14
VR1 0.1 uF 150
D5
500 8 13
VR 2 10k D6 150
9 12
R2 C3 D7 150
2k 10 11
0.1 uF
13-9
Analog Communication Trainer
ADC0809 pins 5, 4, 3, 2, 1, 28, 27 and 26 are the 8 input ports, which is IN7
to IN0. Pins 21, 20, 19, 18, 8, 15, 14 and 17 are the output ports, which are D7
to D0 and pin 10 is the clock input port. Pin 11 is the power supply Vcc input
port and pin 12 is the positive reference voltage Vref () input port. Normally,
pins 11 and 12 are connected together. Pin 13 is grounded and pin 16 is the
negative reference voltage Vref () input port that normally connects to
ground pin 13. The selections of channels are controlled by pins 25, 24 and 23
which are ADD A, ADD B and ADD C. If select pin 26 (IN0) as input port,
(START), pin 7 (end of conversion, EOC), pin 9 (output enable, OE) and
pin 22 (address latch enable, ALE) are normally used to control the ADC
conversion is finished, EOC can enable the central processing unit (CPU).
When CPU is ready to receive data, it will enable pin OE and read the data.
After that enables ALE and START, to let ADC0809 continue the next
(ADD C), 24 (ADD B) and 25 (ADD A), ALE and START must be set
13-10
Chapter 13 Analog to Digital Converter
converter, which EOC (pin 7) output signal is the START input signal, and
the ALE and CLK output signal are the clock signal. The input signal range
of analog input port IN0 is determined by VR1. The IN1 to IN7 input signal
The channel selection is controlled by SW1, SW2 and SW3. We use LED to
represent the digital output, therefore, LED “on” represents “1” and LED
IN3 1 28 IN2
IN4 2 27 IN1
IN5 3 26 IN0
IN6 4 25 ADD A
IN7 5 24 ADD B
START 6 23 ADD C
EOC 7 22 ALE
D3 8 21 D7
O/P ENABLE 9 20 D6
CLOCK 10 19 D5
Vcc 11 18 D4
Vref (+) 12 17 D0
GND 13 16 Vref ( )
D1 14 15 D2
13-11
Analog Communication Trainer
+5 V
VR1 5k 9-pin network
resistor
11
C1 26 150
17
IN0 Vcc D0
0.1 F 27 150
R1 IN1 D1 14
1k 150
28
IN2 D2 15
R2 1 8
150
1k IN3 D3
2
150
IN4 D4 18
R3 150
1k 3 19
IN5 D5
4 20 150
R4 IN6 D6
1k 5 150
21
IN7 D7
R5 12 23 5V
1k Vref ( ) ADD C
SW3
16 24 5V
Vref () ADD B
R6 SW2
9 25 5V
1k OE ADD A
SW1
10 13
R7 CLK GND
1k 22 6
ALE START
7
EOC
Clock Input
13-12
Chapter 13 Analog to Digital Converter
2. Use the digital voltage meter to measure the reference voltage input
port (TP1). Adjust VR1 so that the voltage of TP1 is 2.5 V. At this
moment, ADC0804 analog voltage input range is 0 V to 5 V.
4. Adjust VR2 so that the input voltage of the analog signal input port
(TP3) is 0 V.
5. Let J1 be short circuit, i.e. to maintain the output digital signal. Observe
on the changes of LED, LED “on” represents “1”, LED “off” represents
“0”, finally record the measured results in table 13-1.
6. Let J1 be open circuit, i.e. the digital output signal will be varied from
the analog input signal.
7. Adjust VR2 so that the input voltage of TP3 is similar to the values in
table 13-1, then repeat step 5 and record the measured results in table
13-1..
13-13
Analog Communication Trainer
2. At the CLK input port (CLK I/P), input 120 kHz frequency and a TTL
signal with 5 V offset.
3. Let SW3, SW2 and SW1 switch to GND (push down the slide switch), at
this moment, the multiplexer selects to channel 0 and the analog signal
is inputted from the IN0 input.
4. Use the digital voltage meter to measure the TP1 of channel 0. Adjust
VR1 so that the input voltage of TP1 is similar to the values in table
13-2. Observe on the changes of LED, LED “on” represents “1”, LED
“off” represents “0”, then record the measured results in table 13-2.
5. Adjust VR1 so that the input voltage of TP1 is similar to the values in
table 13-2. Repeat step 4 and record the measured results in table 13-2.
6. Use the digital voltage meter to measure the TP2 of channel 1 until TP7
of channel 6, then record the measured results in table 13-3.
7. Refer to table 13-3, by using SW3, SW2 and SW1, select the different
input terminals as the analog input. Then observe on the changes of
LED and record the measured results in table 13-3.
13-14
Chapter 13 Analog to Digital Converter
TP2
Output Signal
Waveforms
Digital Output
Analog Input
Ideal Values Experiment Values
Voltages (V)
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
13-15
Analog Communication Trainer
Digital Output
Analog Input
Ideal Values Experiment Values
Voltages ( V )
Binary Digits Binary Digits
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
13-16
Chapter 13 Analog to Digital Converter
GND + 5 V + 5 V TP4
+ 5 V GND + 5 V TP6
+ 5 V + 5V GND TP7
13-17
Analog Communication Trainer
13-18
Chapter 14
Digital to Analog
Converter
Analog Communication Trainer
receives the digital modulation signal, then after via a demodulator and a
decoder, we can obtain the digital signal, and follow by using DAC to
convert this digital signal to the analog signal. Next we will discuss the
14-2
Chapter 14 Digital to Analog Converter
codes, the digital input terminal D3, D2, D1 and D0 are manipulated by the
binary value, as shown in figure 14-1(b). For every binary code input, DAC
will output a voltage (Vout), which is double or other order of the binary
value. According to this, analog output voltage Vout and the digital input
binary values are the equivalent. If the DAC output is current, Iout, the
theory is similarly.
Assume that the input is 10112, then after passed through the DAC, the
Figure 14-2 is the basic block diagram of DAC. The reference voltage
(Vref) is used to provide the reference voltage during conversion. Then due
to the magnitude of the input binary code, the digital control switch will
output different binary codes to the resistors network. Normally, the DAC
14-3
Analog Communication Trainer
D3
Digital D2 Analog Output
Inputs D1 DDAC
A DAC
C V out or I out
D0
(a)
D3 D2 D1 D0 Vout D3 D2 D1 D0 Vout
0 0 0 0 0 1 0 0 0 8
0 0 0 1 1 1 0 0 1 9
0 0 1 0 2 1 0 1 0 10
0 0 1 1 3 1 0 1 1 11
0 1 0 0 4 1 1 0 0 12
0 1 0 1 5 1 1 0 1 13
0 1 1 0 6 1 1 1 0 14
0 1 1 1 7 1 1 1 1 15
(b)
Figure 14-1 (a) 4-bit DAC binary codes; (b) Truth table.
Reference
Voltage
Vref
RF
MSB
.
Digital . Digital . Resistors Analog
Inputs . Control . OP
LSB Switch . Network I Voltage Output
out
Analog
Current Output
Figure 14-2 Basic block diagram of DAC.
The resistors network is the main structure of DAC circuit, the most
figure 14-3(a) and R-2R ladder resistors network, as shown in figure 14-3(b).
14-4
Chapter 14 Digital to Analog Converter
value range is too large. Due to the high accuracy demand, this wide range
integrated circuit (IC), which is a big problem. But for the R-2R ladder
resistors network, it just needs two resistor values, which are R and 2R
resistors. The resistor values are simple and just twice of the relation,
the R-2R ladder resistors network, therefore, we will discuss the theory of
RF
+12V
+5 V 1
D3
- VO
R uA741
0
+5 V 1
+
D2
12V
2R
0
+5 V 1
D1
4R
0
V0 VRF ( D 2 D1 4 D 2 8 D 3 )
8R 0
+5 V 1
D0
8R
0
14-5
Analog Communication Trainer
R9
1k R 11
1k
+12V
R1
+5 V 1
D3 2k TP1 R 10
- 1k
0
uA741 - Output
R2 TP5
+5 V 1 R3 1k
+ uA741
Vout
D2 2k +
TP2
12V
0 R4
+5 V 1 R5 1k
D1 2k
TP3
0 R6
R7 1k
+5 V 1
D0 2k
TP4
0 R8
2k
Figure 14-3(b) is the circuit diagram of DAC with 4-bit R-2R ladder
first we consider D3 and let the rest of the diodes connect to ground. Also, by
using the concept of virtual ground, then we know that the current flows into
calculate D2. As for the consideration of D1, as shown in figure 14-4, by using
the concept of virtual ground, we can obtain the current flows into the negative
terminal of the amplifier is 5 V 8 R . Similarly for D0, the current flows into
14-6
Chapter 14 Digital to Analog Converter
R T R 2 R // R
R R A R Amplifier
R 2R 2R 2R
2R//2R R=
Virtual V/2R 5R/3
2R//2R
Ground
(Can be
+5 V Neglected)
Then simplify the circuit as shown in figure 14-4 (b), we can obtain the
5V R 15 V
I RT
2R 5 16R
R
3R
and
2R 15V 2R 5 V
I IN ( ) I RT (14-2)
R 2R 16R 3R 8R
By adding all the currents flow through the negative terminal of the
I OUT I D3 I D2 I D1 I D0
1 5V 0 V 5V 5V
R 2 4 8 16
5V
8 2 1 5 11 V (14-3 )
16R 16R
14-7
Analog Communication Trainer
Vout I out R
5 11 55
R V
16R 16
Input weight illustrates that from the DAC digital input, when only
one of the bits is 1 and the other bits are 0, the DAC output signal range is
called input weight. From Figure 14-1(a), if every time we let one of the bits
of D3, D2, D1 and D0 as high level, the other bits is zero level, then the power
weight starts from the lowest bit and then increases by following the weight.
So we can say that Vout is the sum of weight of the digital input. For
example, to find the Vout of digital input 0111, we can sum D2, D1 and D0
14-8
Chapter 14 Digital to Analog Converter
The resolution of DAC illustrates that when the digital input terminal
changes a unit, it will produce a small change at the analog output terminal,
which is normally the LSB levels. Refer to figure 14-1(b), when the digital
input value changes a unit, Vout will change at least 1 V, so the resolution is
1 V.
Resolution is also called step size because Vout will change, when the
digital input step varies from one to another. Figure 14-5 shows a 4-bit
binary counter as DAC digital input signal, the counter has a clock input, so
call this situation as full-scale output. When the counter generates 0000, the
between two steps. For example, if the step size is 1 V then the difference
only 15 steps size. Generally, N bits of DAC will produce 2N different levels
14-9
Analog Communication Trainer
D3
四 位 元 D2 DAC
4-bit
Resolution Vout
Counter D1
Clock
計 數 器 1V
D0
15 V Full-scale
10V
5V
4V
3V
2V
Resolution = Step Size = 1 V
0V
Time
Figure 14-5 Input of DAC output waveform by using the binary counter.
DAC 0800 is a cheap and commonly used 8-bit DAC, the internal
network and transistor switch. The voltage power supply range is between
14-10
Chapter 14 Digital to Analog Converter
output, which D 7 ~ D o are the 8-bit digital inputs. The positive reference
Vref () ( pin 15 ). The reference current I ref that passes through R1 can be
expressed as
Vref
I ref (14-4)
R1
Vref D7 D 6 D5 D 4 D3 D 2 D1 D
I out ( 0 ) (14-5)
R1 2 4 8 16 32 64 128 256
Threshold
Control VLC 1 16 Compensation
V 3 14 Vref ()
Iout 4 13 +V
D7 5 12 D0
D6 6 11 D1
D5 7 10 D2
D4 8 9 D3
14-11
Analog Communication Trainer
12V +12V
C1 C2 C3 R3
4. 7 k
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
output into the voltage output. In figure 14-7, the output voltage ( Vout ) of
A741 is
DAC0800, the main different of figure 14-7 unipolar output voltage is the
14-12
Chapter 14 Digital to Analog Converter
Where I out and Iout is the complementary output current, I out I out is
-12 V +12 V
R4
C1 C2 C3
4.7 k
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
so when I out equals I FS , I out is zero. When I out is zero, then Iout is
I FS . From the above mentioned and equation (14-9), we know that the
14-13
Analog Communication Trainer
many types of DAC in the market, such as DAC0808 and etc. The theory
and usage are almost the same, if interested, you can refer to related books.
combine both of them into one circuit, as shown in figure 14-9, so that the
I ref 0.1F
+12V
3 16 13
Vref 14 I out
+5V
R1 DAC0800 4 J1 -
4.7 k Output
DAC uA741
Vout
2 J2 +
15 MSB LSB
5 6 7 8 9 10 11 12 1 J3
R2 I out
R 3 12V
4.7 k 4.7 k
D 7 D 6 D5 D 4 D 3 D 2 D1 D0
Digital Inputs
14-14
Chapter 14 Digital to Analog Converter
2. Let SW1, SW2, SW3 and SW4 switch to 1 (“0” represents as GND, “1”
represents as “+5 V”).
3. By using voltage meter to measure TP1, TP2, TP3, TP4, TP5 of R-2R
network and output port of D/A converter (Vout). Then record the
measured results in table 14-1.
4. According to the switching of SW1, SW2, SW3 and SW4 in table 14-1,
repeat step 3 and record the measured results in table 14-1.
14-15
Analog Communication Trainer
2. Calculate the step size and record the calculation in table 14-2.
3. In table 14-2, the binary values are used as the digital inputs, which " 0 "
represents GND, " 1 " represents 5 V .
5. Let J1 be open circuit, then connect the digital current meter to J1 for
measuring the output current, I out . Finally record the measured results
in table 14-2.
6. Remove the current meter and let J1 be short circuit. Using digital
voltage meter to measure the output voltage (O/P) of A741. Then
record the measured results in table 14-2.
14-16
Chapter 14 Digital to Analog Converter
2. Calculate the step values and record the calculation in table 14-3.
3. In table 14-3, the binary values are used as the digital inputs, which " 0
" represents GND, " 1 " represents 5 V .
8. Calculate I out I out and record the measured results in table 14-3.
14-17
Analog Communication Trainer
Step Value = V
SW1 SW2 SW3 SW4 TP1 TP2 TP3 TP4 TP5 O/P
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
Voltage Unit: V
14-18
Chapter 14 Digital to Analog Converter
Step Value = V
Vout I out
D7 D6 D5 D4 D3 D2 D1 D0 Theoretical Measured Theoretical Measured
Results Results Results Results
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
14-19
Analog Communication Trainer
Step Value = V
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0
0 0 1 0 0 0 0 0
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
1 0 0 0 0 0 1 0
1 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0
1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1
14-20
Chapter 14 Digital to Analog Converter
2. Try to use the step value and the output voltage range to compare the
differences between the DAC0800 unipolar voltage output and bipolar
voltage output.
14-21
Analog Communication Trainer
14-22
Chapter 15
Frequency Converter
Analog Communication Trainer
signal and the frequency of the transceiver. On the other hand, we will also
15-2
Chapter 15 Frequency Converter
Figure 15-1 is the input and output signal waveforms of the frequency
audio signal by the carrier signal directly at frequency fo, then we get
X DF t A m cos(2f o t ) A c cos(2f o t )
A m A c [cos(2f o t ) cos(2f o t )]
A m A c cos 22f o t 1
1
(15-1)
2
where
represents the output term of the double frequency signal; the second term
(15-1), we can sketch out the output signal spectrums of the frequency
15-3
Analog Communication Trainer
Am
Audio Signal
Frequency
Multiplier
Am
Frequency
Multiplied Signal
Carrier Signal
Figure 15-1 Input and output signal waveforms of the frequency multiplier.
X D F f
1
2
AM A M
f (Hz)
0 fM fM
15-4
Chapter 15 Frequency Converter
see that the carrier signal and audio signal belong to single ended input. The
carrier signal input from pin 10 and the audio signal input from pin 1.
Therefore R6 determines the gain of the whole circuit and R10 determines
change the input amplitude of audio signal, then we can change the
15-5
Analog Communication Trainer
(12)
Output
Q1 Q2 Q3 Q4 (6)
Carrier (10)
Signal
Input
(8) Q5 Q6
(4)
Audio
Signal
Input (2)
Gain
(1) Q7 Adjustment
Terminal
Bias Q8 (3)
Adjustment
(5) D1
Terminal
R2 R3
R1 500
(14) 500
500
V
R4
1k R8 1 k +12 V
+
R 6 100 C6 C7
+ 100 nF
C3 100 uF
100 uF J3
J2 R9
R7 1 k R1
3k9 1
TP1 3k9
R5 2 3 Doubler
100 8 6
TP5 C4
O/P1
10 MC1496
+ 100 nF
C2 TP2 Balanced
C1 J1 TP3
RF 100 uF Modulator TP6 Doubler
1 12
I/P 100 nF 4 C5 O/P2
TP4 14 5 TP7
R3 100 nF
R1 R2 R6
10 k 100 R 10
10 k 100
V 6k8
R1
100 k C3 +
100 uF -12 V
15-6
Chapter 15 Frequency Converter
signal at the same frequency, then we can obtain the double frequency
different signals (i.e. let the audio signal be A S1 cos(2f S1t ) and the carrier
multiplier will be
signal and carrier signal that is the up frequency signal; the second term
between the audio signal and the carrier signal that is the down frequency
15-7
Analog Communication Trainer
signal. On the other hand, from equation (15-2), we can sketch out the
figure 15-6.
signal and the carrier signal as the transmitted frequency. After the
sum of the signal frequency, which is the up converter. The output signal
other hand, in order to design a receiver, we can assume the audio signal as
the RF signal received from the antenna and the carrier signal as the LO
which is the down converter. The output signal spectrum of the down
X FC f
1 A S1 A S2
2
f (Hz)
f S1 f S2 f S1 f S2
15-8
Chapter 15 Frequency Converter
X FC f
1 A S1 A S2
2
f (Hz)
f S1 f S2 f S1 f S2
X FC f
1 A S1 A S2
2
f (Hz)
f S1 f S2 f S1 f S2
with the assistant of the high-pass filter or low-pass filter, we can obtain the
figure 15-5. Resistors R12, R14 and capacitors C9, C11 comprise the low-pass
filter in figure 15-9. The objective is the remove the high frequency signal
15-9
Analog Communication Trainer
f s1 f s 2 , so that the frequency at the output port is the low frequency signal
f s1 f s 2 , i.e. the down converter. Resistors R13, R15 and capacitors C8, C10
comprise the high-pass filter in figure 15-9. The objective is the remove the
low frequency signal f s1 f s 2 , so that the frequency at the output port is the
High-pass
fs1 fs 2
Filter
Input Multiplier
Signal 1
Low-pass
Filter
fs1 fs 2
Input
Signal 2
C9 C 11
R 12 1 nF 1 nF
S1 LO Doubler Down Con.
I/P I/P O/P1 1k5 O/P
R 14 1k5
S2 RF C8 C 10 Up Con.
Doubler
I/P I/P O/P2 O/P
1 nF 1 nF
R 13 R 15
1k5 1k5
15-10
Chapter 15 Frequency Converter
3. At the RF input port (RF I/P), input 300 mV amplitude and 10 kHz sine
wave frequency.
15-11
Analog Communication Trainer
8. According to the input signals in table 15-1, repeat step 4 to step 7, then
record the measured results in table 15-1.
10. According to the input signals in table 15-2, repeat step 3 to step 8, then
record the measured results in table 15-2.
15-12
Chapter 15 Frequency Converter
3. At the LO signal input port (LO I/P), input 300 mV amplitude and 100
kHz sine wave frequency. At the RF signal input port (RF I/P), input
300 mV amplitude and 120 kHz sine wave frequency.
15-13
Analog Communication Trainer
8. At the LO signal input port (LO I/P), change the frequency of the LO
signal to 120 kHz. At the RF signal input port (RF I/P), change the
frequency of the RF signal to 100 kHz. Repeat step 4 to step 7 and
record the measured results in table 15-3.
15-14
Chapter 15 Frequency Converter
Doubler O/P1
Doubler O/P2
TP1
TP2
15-15
Analog Communication Trainer
TP3
TP4
TP5
TP6
TP7
15-16
Chapter 15 Frequency Converter
Doubler O/P1
Doubler O/P2
TP1
TP2
15-17
Analog Communication Trainer
TP3
TP4
TP5
TP6
TP7
15-18
Chapter 15 Frequency Converter
Up Con.
O/P
Down Con.
O/P
TP1
TP2
15-19
Analog Communication Trainer
TP3
TP4
TP5
TP6
TP7
15-20
Chapter 15 Frequency Converter
Up Con.
O/P
Down Con.
O/P
TP1
TP2
15-21
Analog Communication Trainer
TP3
TP4
TP5
TP6
TP7
15-22
Chapter 15 Frequency Converter
15-23
Analog Communication Trainer
15-24
Chapter 16
Signal Recovery
Analog Communication Trainer
circuit.
signal is not only being used in the transmitter. In the receiver, if we are
unable to obtain the clock signal, which is synchronous with the transmitter,
then the receiver is unable to read the initial bit of the data signal. This
situation will also cause the loss and error of the data signal during decoding.
16-2
Chapter 16 Signal Recovery
also includes the modulated signal. Therefore, in the carrier signal recovery
circuit, the objective of the first stage circuit is to remove the modulated
signal by using the frequency multiplier, and then generates a double
frequency carrier signal. After that amplify the signal by using the amplifier.
The second stage of the carrier signal recovery circuit is to lock the double
frequency carrier signal by using phase locked loop (PLL). As a result of the
the recovery circuit is the doubler frequency carrier signal of the transmitter,
therefore, in the third stage, we utilize the frequency divider to recover the
doubler frequency signal to the original frequency signal, which is similar to
16-3
Analog Communication Trainer
carrier signal at the transmitter. This means that the output signal of the
frequency divider is synchronous and similar to the carrier signal of the
transmitter. Figure 16-1 is the completed structure diagram of the carrier
In figure 16-1, for the block of the frequency multiplier, we can utilize
the frequency multiplier in chapter 15 to implement. As for the operation
section. As for the final stage, which is the waveform shaping circuit, we
know that it is a low-pass filter, therefore, we can utilize the concept of
low-pass filter in chapter 1 to implement the waveform shaping circuit.
can implement the carrier signal recovery circuit easily. Figure 16-2 is the
circuit diagram of the carrier signal recovery circuit. In figure 16-2, the
circuit of the frequency multiplier is shown in figure 15-5. Resistors R1, R2,
R3, capacitor C1 and A741 comprise the amplifier. As for the PLL part, it
is comprised by Resistors R4, R5, R6, variable resistor VR1, capacitors C2, C3,
16-4
Chapter 16 Signal Recovery
initial bit of the data signal and the required clock signal during decoding,
clock recovery circuit is needed. The objective of the clock recovery circuit
is to recover the clock signal of the data signal and with this clock signal,
16-5
Analog Communication Trainer
figure 16-3, the can see that the clock recovery circuit is quite simple. It
only needs a delay circuit, exclusion OR (XOR) gate and PLL. As for the
signal, which can hide the clock signal of the data signal in the transmitted
signal. Then the receiver is able to recover the clock signal from the
figure 16-4, we notice that the received data signal (Coded O/P) will be
delayed and operate again with the original data signal by the exclusion OR
gate (XOR). Then the output signal is a pulse (XOR O/P), which the
frequency is similar to the original clock signal. The only different is the
time delay, which means these two signals are synchronized. However, since
the output of the operation of XOR is pulse signal, therefore, this signal is
unable to be a standard clock signal. So, we utilize the phase locked loop
(PLL) to produce the standard clock signal and the reference signal, which
is required by the PLL, is provided by XOR. Finally, the clock signal from
16-5, the frequency divider (74HC393) and the exclusion OR gate (XOR)
16-6
Chapter 16 Signal Recovery
data signal. Resistor R1, capacitors C1, C2 comprise a delay circuit. The PLL
is comprised by resistors R2, R3, R4, R5, R6, variable resistor VR1, capacitors
C3, C4, C5, C6 and LM565. Among the components, resistor R5 and
capacitor C5 comprise the loop filter of the PLL; variable resistor VR1 and
CLK I/P A
2
B
XOR Recovered
D
XOR PLL CLK O/P
Delay C
Circuit
CLK I/P
t
1/2 O/P
1 0 1 0 1 0 1 0 1 0 1
(A)
t
Coded
O/P
(B)
t
Delay
O/P
(C)
t
XOR
O/P
(D)
t
16-7
Analog Communication Trainer
C4
100 nF
R2 +5 V
R3
Clock 10 k 4k7
+5 V 3 16 Recpvered
4
TP1 R4 O/P
14 XOR:A TP4 4k7 5
Clock R 1 TP3
2 3 XOR:B 2
I/P 74HC393 74HC86 C3 C5 LM565
(1/2) C1 100 nF
1 7 8 15
1k C 2 74HC86 7
10 nF PLL
330 pF 220 nF 12 +5 V
6 9
R5 C6 VR 1
1 8
10 k 220 pF 50 k
-5 V R6
20 k
16-8
Chapter 16 Signal Recovery
1. Refer to the circuit diagram of carrier signal recovery in figure 16-2 and
the frequency multiplier in figure 15-5 or refer to figure ACS 16-1 and
figure ACS15-1 of ACT-17300-08 module.
3. At the RF input port (RF I/P), input 300 mV amplitude and 10 kHz sine
wave frequency.
16-9
Analog Communication Trainer
8. According to the input signal in table 16-1, repeat step 4 to step 7 and
record the measured results in table 16-1.
16-10
Chapter 16 Signal Recovery
2. At the clock signal input port (Clock I/P), input 2.5 V amplitude, 2.5 V
offset (i.e. High is 5 V, Low is 0 V TTL signal) and 10 kHz square wave
frequency.
6. According to the input signal in table 16-2, repeat step 3 to step 5 and
record the measured results in table 16-2.
16-11
Analog Communication Trainer
Doubler O/P1
TP4
TP1
TP2
16-12
Chapter 16 Signal Recovery
Table 16-1 Measured results of the carrier signal recovery circuit. (Continued) (R7 = 1 k)
TP3
TP5
TP6
TP7
Recovered
O/P
16-13
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Data
Clock
TP1
Recovered
O/P
16-14
Chapter 16 Signal Recovery
TP2
TP3
TP4
16-15
Analog Communication Trainer
1. Describe the applications of the carrier signal recovery and the clock
recovery in the application of communication.
2. Explain the operation theory of the carrier signal recovery circuit and
its circuit block diagram.
4. Explain the operation theory of the clock recovery circuit and its circuit
block diagram.
5. Refer to figure 16-5, explain what are the components comprised the
delay circuit.
16-16