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Approximate Computing
for Low Power
and Security in the
Internet of Things
Mingze Gao, Qian Wang, and Md Tanvir Arafin, University of Maryland, College Park
Yongqiang Lyu, Tsinghua University
Gang Qu, University of Maryland, College Park
T
he Internet of Things (IoT) has become ubiqui- lifetime.3,4 Security and privacy are another concern
tous in our daily life, with an estimated 30–75 because IoT devices cannot afford resource-demanding
million IoT devices expected to be connected cryptographic protocols. Here, we assess a popular low-
through the Internet infrastructure by 2020.1,2 power design methodology known as approximate com-
The explosive growth in the number and diversity of these puting and demonstrate how it can both reduce power
devices and their applications are inevitably bringing and increase the security of IoT devices.
many nontraditional challenges to the circuit and system
design community.3 Perhaps the most crucial challenge APPROXIMATE COMPUTING
is how to power these tens of billions of devices, as a sig- Many low-power VLSI design techniques—including
nificant portion of them are wireless and battery oper- dynamic power and thermal management, dynamic
ated, with power consumption directly affecting their voltage scaling, multiple-threshold voltage design, and
C O M P U T E R 0 0 1 8 - 9 1 6 2 / 1 7/ $ 3 3 .0 0 © 2 0 1 7 I E E E J U N E 2 0 1 7 27
VLSI FOR THE INTERNET OF THINGS
TABLE 1. Area and power cost comparison of approximate function units (FUs) of various bit widths.*
Adder Multiplier
FU bit width No. cells Area (µm2) Power (nW) No. cells Area (µm2) Power (nW)
*The shaded area indicates the value normalized to that of precise 32-bit FUs.
energy harvesting—along with the use correctness. A recent survey classifies less significant bits could be neglected
of nanoscale materials like memris- state-of-the-art approximate comput- without causing significant error,
tors can improve the power efficiency ing approaches at the levels of com- thereby allowing use of an approximate
of IoT devices. To complement these puting, software, compilers, architec- adder. Existing approximate adders
approaches, researchers have pro- ture, memory, and circuit.8 with a fixed bit position for addition
posed novel methods to leverage spe- Most existing research focuses on cannot address both scenarios.
cific features in IoT applications for the arithmetic field, where the power/
power reduction. energy savings can be achieved by APPROXIMATE ADDITION
One such method is approximate well-designed approximate computing BASED ON APPROXIMATE
computing, which offers resource sav- function units (FUs) such as approx- INTEGER FORMAT
ings at the cost of reduced accuracy and imate adders9 and multipliers.10 To To save more system resources, we
has found applications in many fields study the potential of these approxi- extend approximate computing from
such as multimedia and signal pro- mate FUs, we design circuits in Verilog the existing static approach to a
cessing, wireless communication, and for adders and multipliers with differ- more data-oriented dynamic one. We
data mining and analysis. A common ent bit widths and synthesize them achieve this via a segmentation of
feature of these applications is their using the Cadence RTL Compiler with operands based on approximate inte-
ability to tolerate a certain amount of the FreePDK 45-nm open cell library. ger format (AIF) and corresponding
computational error. In this respect, As Table 1 shows, the area and power basic arithmetic operations that can
approximate computing is conceptu- consumption of adders decrease about be carried out by approximate FUs for
ally similar to the use of probabilistic linearly with the number of bits, while almost all applications.11
design techniques to reduce energy in the area and power savings of multi- An n-bit positive integer N is seg-
multimedia applications, an approach pliers are almost exponential. Most mented into ⎡n/k⎤ blocks with k bits in
that has been around for more than a approximate FUs take advantage of each block (except the first and leading
decade. As far back as 2003, research- this by using adders and multipliers block if N is not a multiple of k). A valid
ers proposed dropping the decoding with fewer bits whenever possible. block is a block that contains at least
of some frames as long as humans However, existing approximate FUs one bit of value 1 or is after some valid
cannot tell the difference.5 The error are fully customized for a specific blocks. The precision control (pc) value
tolerance in image compression later operation, either addition or multi is the number of valid blocks that will
motivated development of an adaptive plication, with a given accuracy. When be used in the approximate computa-
pixel and coefficient truncation tech- FUs are used for other computations— tion. For the ith block of the given pos-
nique for energy minimization at sys- for example, approximate adders for itive number, the sentinel bits st[i] are
tem level.6,7 multiplication—the error can accu- defined as:
Generally, low-power approximate mulate and get out of control. More
⎪⎧1, block i is a valid block
computing is achieved in a system importantly, the large data range sig- st[i ] = ⎨
either by using voltage overscaling nificantly limits the power savings of ⎩⎪0, block i is not a valid block
(VOS) techniques to reduce the system’s approximate FUs from reaching their For example, consider two integers
operating voltage below the required potential. Consider a 32-bit adder: when 1,500 and 800, which we can express
threshold level or by redesigning the both operands have small values with in binary form as 1,50010 = 0000 0101
system’s functionality at different many leading zeros, an approximate 1101 11002 and 80010 = 0000 0011
levels—algorithm, application, archi- adder with fewer bits could be used to 0010 00002, respectively. When we
tecture, or circuit—to save power at add only the non-zero bits; on the other choose the block size k = 4, both values
the cost of computational accuracy or hand, if one operand or both are large, will have three valid blocks (shown in
JUNE 2017 29
VLSI FOR THE INTERNET OF THINGS
1–13 0 0 0
14 –0.00984 0 0
15 –0.01317 0 0
for power and energy minimization.
16 –0.01691 0 0 These include clock gating, transistor
17 –0.01858 0 0 sizing, glitch and path balancing, tech-
nology mapping, temperature/thermal
18 –0.01985 0 0 awareness, and dual-threshold voltage
19 –0.02173 –0.00044 0 and input vector control, and don’t-care
condition optimization.
20 –0.02905 0.000183 0 Dynamic voltage and frequency sched-
uling. DVFS varies the supply volt-
21 –0.02625 –5.65E–05 0
age and clock frequency based on
22 –0.02732 3.49E–05 0 the computational load and deadline
requirements to provide the required
23 –0.02692 0 0
performance while minimizing the
24 –0.02707 1.33E–05 0 total amount of energy consumption.
State-of-the-art DVFS design has been
25 –0.02912 0.000404 8.24E–06 proposed for the functionalities that
26 –0.03225 0.000336 1.02E–05 are conventionally used in IoT devices.
This can be naturally integrated with
27 –0.03750 0.000362 9.44E–06 approximate FUs.
Probabilistic design. This design meth-
28 –0.03947 0.000352 9.72E–06
odology aims at not overdesigning sys-
29 –0.04118 0.000356 9.61E–06 tems for their worst-case scenario.5 It
utilizes the fact that many real-time IoT
30 –0.04205 0.000354 9.66E–06
applications do not require high perfor-
31 –0.02291 –0.000350 2.30E–06 mance and can tolerate a certain degree
of faultiness. Probabilistic design uses
32 –0.02267 –0.000590 –8.51E–06
prior or posterior execution information
33 –0.02276 –0.000500 –4.38E–06 and takes advantages of the unique fea-
tures of IoT devices’ functionalities to
34 –0.02273 –0.000530 –5.96E–06 relax overly rigid hardware or software
35 –0.02274 –0.000520 –5.36E–06 design implementations.
JUNE 2017 31
VLSI FOR THE INTERNET OF THINGS
T
insider.com/75-billion-devices-will
Digital fingerprinting. Similar to IP he main advantage of our pro- -be-connected-to-the-internet-by
watermarking, each device’s unique posed approximate computing– -2020-2013-10.
fingerprint can be embedded as the based information-hiding method 3. G. Qu and L. Yuan, “Design Things
error value in the LSBs. For the same is its low implementation cost with for the Internet of Things: An EDA
verification inputs or operands, differ- guaranteed results: it utilizes the energy Perspective,” Proc. IEEE/ACM Int’l
ent Key values and F()s can be used to efficiency of approximate computing Conf. Computer-Aided Design (ICCAD
distinguish individual devices. and introduces tolerable error. The hid- 14), 2014, pp. 411–416.
den information can be verified easily 4. H. Jayakumar et al., “Powering the
Lightweight encryption. As the by disabling the approximate comput- Internet of Things,” Proc. Int’l Symp.
result will be encrypted, the entire ing. This security primitive can pro- Low Power Electronics and Design
32-bit space can be used for informa- vide lightweight security for multiple (ISLPED 14), 2014, pp. 375–380.
tion hiding. For example, an encryp- security applications such as device 5. S. Hua, G. Qu, and S.S. Bhattacha-
tion key up to 32 bits can be generated authentication and IP protection. ryya, “Energy Reduction Techniques
from F() based on the values of oper- for Multimedia Applications with
ands and some given Key values to ACKNOWLEDGMENTS Tolerance to Deadline Misses,” Proc.
encrypt the (approximated) computa- This work was supported in part by AFOSR 40th Ann. Design Automation Conf.
tional result—for example, by the effi- MURI under award number FA9550-14-1- (DAC 03), 2003, pp. 131–136.
cient bitwise XOR operation. This is 0351. Yongqiang Lyu was supported in 6. S.H. Kim, S. Mukhopadhyay, and M.
symmetric encryption and the result part by Tsinghua University Initiative Wolf, “System-Level Energy Opti-
can be decrypted easily once the key Scientific Research Program and Chinese mization for Error-Tolerant Image
is available. National Key Research and Development Compression,” IEEE Embedded System
There are two potential threats Program 2016YFB1000102. Letters, vol. 2, no. 3, 2010, pp. 81–84.
to this information-hiding protocol. 7. S.H. Kim, S. Mukhopadhyay, and
First, an attacker can study the values REFERENCES M. Wolf, “Modeling and Analysis of
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JUNE 2017 33
VLSI FOR THE INTERNET OF THINGS
Computer-Aided Design of Integrated QIAN WANG is a PhD student in the Maryland Embedded Systems and Hard-
Circuits and Systems, vol. 30, no. 8, ware Security (MeshSec) lab at the University of Maryland, College Park. Her
2011, pp. 1163–1172. research interests include embedded systems and hardware security. Contact
8. Q. Xu, T. Mytkowicz, and N.S. Kim, her at qwang126@umd.edu.
“Approximate Computing: A Sur-
vey,” IEEE Design & Test, vol. 33, no. 1, MD TANVIR ARAFIN is a PhD student in the Department of Electrical and Com-
2016, pp. 8–22. puter Engineering at the University of Maryland, College Park. His research
9. R. Ye et al., “On Reconfiguration- interests include semiconductor physics, integrated circuits, and embedded
Oriented Approximate Adder Design security of microelectronic devices. Contact him at marafin@umd.edu.
and Its Application,” Proc. Int’l Conf.
Computer-Aided Design (ICCAD 13), YONGQIANG LYU is an associate professor at the Research Institute of Information
2013, pp. 48–54. Technology at Tsinghua University. His research focuses on the hardware–software
10. S. Hashemi, R.I. Bahar, and S. Reda, fusion architecture in advanced computing systems and high-performance net-
“DRUM: A Dynamic Range Unbiased works. Lyu received a PhD in computer science from Tsinghua University. He is
Multiplier for Approximate Appli- a member of IEEE, ACM, and the China Computer Federation. Contact him at
cations,” Proc. IEEE/ACM Int’l Conf. luyq@tsinghua.edu.cn.
Computer-Aided Design (ICCAD 15),
2015, pp. 418–425. GANG QU is a professor in the Department of Electrical and Computer Engi-
11. M. Gao et al., “A Novel Data Format neering and at the Institute for Systems Research at the University of Maryland,
for Approximate Arithmetic Com- College Park, where he also directs the MeshSec and Wireless Sensor labs. His
puting,” Proc. 22nd Asia and South research interests include optimization and combinatorial problems and their
Pacific Design Automation Conf. application to very large-scale integration and computer-aided design, wire-
(ASP-DAC 17), 2017; doi:10.1109 less sensor networks, bioinformatics, cybersecurity, and hardware security and
/ASPDAC.2017.7858354. its impact on Internet of Things and embedded systems. Qu received a PhD in
12. M. Katagi and S. Moriai, “Light- computer science from the University of California, Los Angeles. He is a Senior
weight Cryptography for the Internet Member of IEEE. Contact him at gangqu@umd.edu.
of Things,” Sony Corp., 2008; www
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july • august 2016
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