1

Application of JFET on Low Power

Photovoltaic Inverters
Fajar Dwi Kuncoro, Rahma Dewi Kartika Sari, and Dinda Cahya Firdausi
Engineering Physics, FTI, Institut Teknologi Sepuluh Nopember (ITS)

Abstract— The new generation of semiconductor switching
devices based on silicon carbide makes higher efficiency and power
density possible in photovoltaic (PV) inverters among many
applications. The new type of JFET requires new driver circuits
and a more careful arrangement of them. The main circuit
arrangement has to have low stray inductance to ensure low
overvoltage spikes and switching losses. It is well known that
converter efficiency is an important parameter in the PV industry.
SiC devices offer a good possibility to achieve efficiency. This paper
approaches the topic from the application point of view.
Keywords— JFET; Photovoltaic Inverter
I. INTRODUCTION
As a result of recent researches and developments new
switching devices have become available on the market.
Among the appeared products, SiC normally on and normally
off JFETs have favorable attributions. As for SiC transistors,
the JFET is considered favorable because it has a relatively
simple structure.
In many countries transformerless PV systems became the
main market trend due to its higher efficiency and reduced
weight. In order to extend the PV voltage range or to ensure a
safe operating area of the PV panel, a boost converter is often
included in medium power solar inverters. Power
semiconductors usually work in hard switching operation
mode in PV inverters. There are some basic requirements to
provide optimal operation of JFETs. Driver circuits of the
JFET have a crucial role to ensure proper operation during
conduction state and during turn on and turn off . The high
frequency operation with low switching losses enables high
power density in converters. Basically, there are two types of
JFETs: normally off and normally on. Normally off JFETs are
in turned off state when gate-source voltage is below its
threshold voltage. While, normally on JFETs are in turned on
state when gate-source voltage is below its threshold voltage.
current flowing in-between the drain and the source
terminals. A JFET is a three terminal semiconductor
device in which current conduction is by one type of
carrier i.e. electrons or holes. JFET can be divided
depending upon their structure into the following two
categories are n-channel and p-channel JFET.
2.1.1 n-channel JFET
From the layered structure shown by Figure 1a,
the n-channel JFET has its major portion made of n-
type semiconductor. Thus, here, the source and the
drain terminals are of n-type while the gate is of p-
type. Further the circuit symbol shown by Figure 1b
has an arrow pointing towards the device at its Gate
terminal which indicates the direction in which the
current would flow, provided the pn junction is
forward biased.
Figure 1. n-channel JFET a) Layered Structure
b) Circuit Symbol
In n-channel JFET, the majority charge carriers will
be the electrons as the channel formed in-between
the source and the drain is of n-type. Further, the
working of these devices depends upon the voltages
applied at its terminals (Figure 2)

II. BASIC THEORY .

Figure 2. n-channel JFET in a Biased State
2.1 JFET (Junction Field Effect Transistors)
JFET are a type of FET which have three terminals
2.1.2 p-channel JFET
namely, Source (S), Gate (G) and Drain (D). These devices
The p-channel JFET (Figure 3a) exhibits the mode
are also called voltage controlled devices as the voltage
of working which is similar to that of its counter-
applied at the gate terminal determines the amount of

part, the n-channel JFET except a few differences.
In the case of p-channel JFET, the major portion
made of the device is made of p-type into which
embedded are the two small n-type regions. Thus it
has an n-type gate terminal and p-type source and
drain, causing the channel to be of p-type where the
holes will be the majority charge carriers.
Figure 3. p-channel JFET a) Layered Structure
b) Circuit Symbol
Similar to the case of n-channel JFETs, the working
of these devices also depends upon the voltages
applied at its terminals (Figure 4)
.
Figure 4. P-channel JFET in a Biased State
2.2 JFET Working
JFET operations is like a garden hose where the flow of
water through a hose can be controlled by squeezing it to
reduce the cross section, similarly the flow of electric
charge through a JFET is controlled by constricting the
current-carrying channel. The current also depends on the
electric between source and drain.
2.3 JFET’s Characteristics
Figure 5. Analogy JFET
Construction of the conducting channel is accomplished
using the field effect: a voltage between the gate and
source is applied to reverse bias the gate-source pn-
junction, thereby widening the depletion layer of this
junction encroaching upon the conducting channel and
restricting its cross-sectional area. The depletion layer is
so-called because it is depleted of mobile carriers and so is
electrically non-conducting for practical purpose.
2
Figure 6. JFET with no bias voltage
When the depletion layer expands thw width of the
conduction channel, “pinch-off” is achieved and drain to
source conduction stops. Pinch-off occurs at a particular
reverse bias (VGS) of the gate-source junction. The pinch-
off voltage (Vp) varies considerably, even among devices
of the same type to switch off an n-channel device requires
a negative gate-source voltage (VGS). Conversely, to
switch off a p-channel device requires positive VGS
Figure 7. JFET when channel is pinched-off.
In normal operation, the electric field developed by the
gate blocks source-drain conduction to some extent. Some
JFET devices are symmetrical with respect to the source
and drain. The channel does not totally pinched-off
because if the channel is totally pinched-off then no
current flows through the channel and there will be no
voltage drop through the channel and make diode will not
be reverse bias and it forms a symmetrical shape instead of
wedge shape. Therefore a minimum ammount of current
flows through the junction which is called pinched-off
current and the region is known as saturation region.
In this characteristics we can find three regions, are:
1. The linear or the ohmic region: Here the drain to
source voltage is small and drain current in nearly
proportional to the drain to source voltage. When a
positive drain to source voltage is applied, this voltage
increases from zero to a small value, the depletion
region width remain very small and under this
condition the semi conductor bar behaves just like
a resistor. So, drain current increases almost linearly
with drain to source voltage.

2. The saturation of the active region: Here the drain
current is almost constant and it is not dependent on the
drain to source voltage actually. When the drain to
source voltage continuous to increase the channel
resistance increases and at some point, the depletion
regions meet near the drain to pinch off the channel.
Beyond that pinch off voltage, the drain, current attains
saturation.
3. The breakdown voltage: Here the drain current
increases rapidly with a small increase of the drain to
source voltage. Actually for large value of drain to
source voltage, a breakdown of the gate junction takes
place which results a sharp increase of the drain
current.
Figure 8. Characteristics of JFET
III. IMPLEMENTATION
A. Application of JFET on Low Power Photovoltaic Inverters
Basically, there are two types of JFETs: normally off and
normally on. Normally off JFET’s are in turned off state
when gate-source voltage is below its threshold voltage
and normally on JFET’s are in turned on state gate-source
voltage is below its threshold voltage.
1. Normally on JFET Application
This JFET is turned on when gate source voltage is
below threshold voltage. As a result of this, normally
on types JFETs are not allowed to be used in H-Bridge
without any measure. Auxiliary MOSFETS should be
used in order to avoid the short-circuit of the DC link.
Figure 10 shows the cascade configuration where in
this configuration, the JFET getting energy is provided
by the main circuit. This means that only the low
voltage MOSFETS requires energy from an auxiliary
power supply. The surge current capability of cascade
configuration is deteriorated, because the short-circuit
withstand time of normally on JFETs is much higher
than low voltage MOSFET. Due to this fact, the short-
circuit at DC link by half bridge leg destroys first the
MOSFET and then the JFET very fast. As a
consequence, the protection system has very short time
3
to handle the failure, so it is difficult to design short
circuit protection similar to IGBTs
Cascade structure is very sensitive to parasitic
inductance MOSFET-JFET gate loop. It can cause
oscillation during the switching, which increases
switching losses. Due to the fact that the
aforementioned PCB stray capacitances are parallel
with SiC JFET, they make SiC JFET slower and
therefore, the voltage ocan be dangerously high.
There is a possibility to drive JFET and MOSFET
separately. Before the voltage level at power supply
reaches the nominal range, MOSFET and JFET are in
off state. When the auxiliary power supply is high
enough, MOSFET is turned on continuously and only
JFET is controlled. This solution provides a better
switching behavior but requires a higher gating power
supply energy.
Figure 9. Cascade arrangement of a switching device
2. Normally off JFET Application
Drivers of JFETs need energy from the auxiliary
power supply to turn on the devices, but without the
auxiliary power supply, the semiconductors are in
turned off state. JFETs have robust short circuit
withstand capability, therefore it is easy to equip them
with overcurrent protection.
B. Test Result of JFET Application in PV Inverter
The tests were carried out an experimental 3 kW single-
phase, transformless H-bridge inverter.
1. Main Technical Data
Rated power: 3 kW
Max. DC input voltage: 550 V dc
Input current max.: 17 A
MPP range: 150-450 V
Output current: 16 ARMS
Output voltage: 230 VRMS
Output frequency: 50/60 Hz
cos(φ): 0.8-1 leading or lagging
Applied instruments:
Oscilloscope: type Yokogawa DLM 6054/500 MHz
Voltage probes: type Yokogawa DLM 701939 / 500
MHz
 4

Voltage probes: type Yokogawa DLM 701945 / 500

MHz
Voltage probes: type PBA 1000 Yokogawa 701912
/1GHz
Current probe: type DLM 701933 /50 MHz
2. Boost Unit Operation
Figure 10 shows the switching behavior of JFET with
switching frequency of approximately 60 kHz. There is
a current spike during turn on caused by the booster
SiC diode capacitive charge. Current spike can also be Figure 11a. CH1 cascade voltage, CH2 cascade drain
reduced by the application of a ferrite bead in the gate current (100 mV/A)
circuit. Results are shown in Figure 11. This is also
effective against gate ringing current, however its
consequences are slower switching speed and
additional switching losses.
Figure 10a shows a turn on and a turn off transition at
app. 50% duty cycle with boosted voltage of 550 VDC
and load current of 13 A.

Figure 11b. CH1 cascade voltage, CH2 cascade drain

current (100 mV/A)

3. H-Bridge Unit Operation

There is a dangerous effect in the phase legs during on
state of the top JFET device. The bottom JFET can
have a parasitic turn on due to the miller effect.
Figure 10a. CH1 cascade voltage, CH2 Cascade Drain It is advisable to apply a negative gate-source voltage
current to keep the JFET in the turned off state.
Aforementioned sensitivity can be further decreased by
means of parallel connected gate capacitor of few nF.
The experimental H-bridge was not sensitive to those
voltage stresses. Figure 13 shows current and voltage
of the top semiconductor.

Figure 10b. CH1 cascade voltage, CH2 cascade drain

current

Figure 12. CH1 cascade voltage, CH2 cascade drain

Figure 10c. CH1 cascade voltage, CH2 cascade drain
current
Figure 11 shows similar operation condition that figure
10, but the gate contains a ferrite bead.
current (20 mV/A)
A half sinusoidal output current of the inverter is
recorded in Figure 12, where the switching frequency
was 30 kHz. In the same figure the output modulated
voltage was recorded in blue. Enlarged signals can be
seen at the bottom of Figure 12b.
 5

Figure 13a. Output current and output voltage of the

inverter

Figure 13b. Half sinusoidal output current 500 VDC (500

V/DIV) voltage and 20 A (13.33 A/DIV) load current,
modulation frequency 30 kHz

IV. CONCLUSION
This paper focuses on the application of a new
semiconductor class in low power PV inverters. In addition it
introduces various solutions and some key rules for circuit
design and construction. The paper points out the advantages
and disadvantages of normally on and off JFET’s.
Furthermore, it presents the measurement results of an
experimental PV inverter.

REFERENCE
[1] Balázs Farkas, Ernő Paál, Károly Veszprémi “Low
Power Photovoltaic Inverters Built up with SIC JFET’s.
Budapest : Acta Polytechnica Hungarica, 2015, Vol. 12.
[2] Kirti “Basic study of Junction Field Effect Transistor
(JFET)” Haryana : International Journal of Science and
Research (IJSR), 2014, Vol. 3.