Professional Documents
Culture Documents
http://www.unhas.ac.id/amil/S1TE/SD2018/
2
Administrasi Kuliah
Penilaian
• Quiz, Final, Tugas, Presentasi, dll.
Perbaikan Nilai:
• Tidak ada (waktu) perbaikan nilai.
• Ujian susulan hanya akan diberikan jika berhalangan hadir pada saat ujian
karena:
• Sakit atau alasan pribadi lain yang dapat diterima.
• Ada pemberitahuan pada saat ujian atau sebelum ujian (Do not hesitate to let me know!)
3
Rules!
• Please be aware that:
• No mark (zero) for late assignments
without prior permission or urgent
reasons.
• No mark (zero) for cheated assignments or
exams.
• No talks via mobile phone during class.
• Silent mode is OK
• You can leave class if you have an urgent call.
• No FB, Twitter, SMS, etc, during class.
• No “kaos oblong” and “sandal”.
• No smoking!
• Snack/candy is OK during class.
4
Contact info
• HP: 0853-9883-1853 (SMS and URGENT CALL ONLY)
• amil_ai@yahoo.com
5
Digital system
Introduction
6
Simple Switch Circuit
• Switch open:
• No current through circuit
• Light is off
• Vout is +2.9V
• Switch closed:
• Short circuit across switch
• Current flows
• Light is on
• Vout is 0V
9
N-type MOS Transistor
• MOS = Metal Oxide Semiconductor
• two types: N-type and P-type
• N-type
• when Gate has positive voltage,
short circuit between #1 and #2
(switch closed)
• when Gate has zero voltage,
open circuit between #1 and #2
(switch open)
Terminal #2 must be
connected to GND (0V). 10
P-type MOS Transistor
• P-type is complementary to N-type
• when Gate has positive voltage,
open circuit between #1 and #2
(switch open)
• when Gate has zero voltage,
short circuit between #1 and #2
(switch closed)
Terminal #1 must be
connected to +2.9V. 11
CMOS Circuit
• Complementary MOS
• Uses both N-type and P-type MOS transistors
• P-type
• Attached to + voltage
• N-type
• Attached to GND
• For all inputs, make sure that output is either connected to GND or to +,
but not both!
12
Inverter (NOT Gate)
2.9 V
In Out In Out
0 V 2.9 V 0 1
2.9 V 0V 1 0
13
NOR Gate
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Note: Serial structure on top, parallel on bottom. 14
OR Gate A B C
0 0 0
0 1 1
1 0 1
1 1 1
15
Decoder
• n inputs, 2n outputs
• exactly one output is 1 for each possible input pattern
2-bit
decoder
Note the use of the
bubbles (NOT) in the
input.
16
Multiplexer (MUX)
• n-bit selector and 2n inputs, one output
• output equals one of the inputs, depending on selector
4-to-1 MUX
17
Full Adder
• Add A, B and Cin, produce one-bit S and Cout.
18
Four-bit Adder
19
R-S Latch: Simple Storage Element
0 1
0
1 0
20
Gated D-Latch
21
Register
input bits
Memory
write
enable
output bits 23