a Precision Single Supply

Instrumentation Amplifier
AMP04
FEATURES FUNCTIONAL BLOCK DIAGRAM
Single Supply Operation 100k

Low Supply Current: 700 A Max RGAIN
Wide Gain Range: 1 to 1000 IN(–)
Low Offset Voltage: 150 V Max INPUT BUFFERS VOUT
IN(+)
Zero-In/Zero-Out
Single-Resistor Gain Set
11k

8-Lead Mini-DIP and SO Packages
11k

APPLICATIONS
Strain Gages 100k

Thermocouples
RTDs REF
Battery-Powered Equipment
Medical Instrumentation
Data Acquisition Systems
PC-Based Instruments
Portable Instrumentation
The AMP04 is specified over the extended industrial (–40°C to
GENERAL DESCRIPTION +85°C) temperature range. AMP04s are available in plastic and
The AMP04 is a single-supply instrumentation amplifier ceramic DIP plus SO-8 surface mount packages.
designed to work over a +5 volt to ± 15 volt supply range. It Contact your local sales office for MIL-STD-883 data sheet
offers an excellent combination of accuracy, low power con- and availability.
sumption, wide input voltage range, and excellent gain
performance. PIN CONNECTIONS
Gain is set by a single external resistor and can be from 1 to
8-Lead Epoxy DIP 8-Lead Narrow-Body SO
1000. Input common-mode voltage range allows the AMP04 to
(P Suffix) (S Suffix)
handle signals with full accuracy from ground to within 1 volt of
the positive supply. And the output can swing to within 1 volt of RGAIN 1 8 RGAIN RGAIN RGAIN
the positive supply. Gain bandwidth is over 700 kHz. In addi- –IN 2 AMP04 7 V+ –IN AMP04 V+
tion to being easy to use, the AMP04 draws only 700 µA of +IN 3 6 VOUT +IN VOUT
supply current. V– 4 5 REF V– REF
For high resolution data acquisition systems, laser trimming of
low drift thin-film resistors limits the input offset voltage to
under 150 µV, and allows the AMP04 to offer gain nonlinearity
of 0.005% and a gain tempco of 30 ppm/°C.
A proprietary input structure limits input offset currents to
less than 5 nA with drift of only 8 pA/°C, allowing direct con-
nection of the AMP04 to high impedance transducers and
other signal sources.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
AMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = 5 V, VCM = 2.5 V, TA = 25C unless otherwise noted)
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
OFFSET VOLTAGE
Input Offset Voltage VIOS 30 150 300 µV
–40°C ≤ TA ≤ +85°C 300 600 µV
Input Offset Voltage Drift TCVIOS 3 6 µV/°C
Output Offset Voltage VOOS 0.5 1.5 3 mV
–40°C ≤ TA ≤ +85°C 3 6 mV
Output Offset Voltage Drift TCVOOS 30 50 µV/°C
INPUT CURRENT
Input Bias Current IB 22 30 40 nA
–40°C ≤ TA ≤ +85°C 50 60 nA
Input Bias Current Drift TCIB 65 65 pA/°C
Input Offset Current IOS 1 5 10 nA
–40°C ≤ TA ≤ +85°C 10 15 nA
Input Offset Current Drift TCIOS 8 8 pA/°C
INPUT
Common-Mode Input Resistance 4 4 GΩ
Differential Input Resistance 4 4 GΩ
Input Voltage Range VIN 0 3.0 0 3.0 V
Common-Mode Rejection CMR 0 V ≤ VCM ≤ 3.0 V
G=1 60 80 55 dB
G = 10 80 100 75 dB
G = 100 90 105 80 dB
G = 1000 90 105 80 dB
Common-Mode Rejection CMR 0 V ≤ VCM ≤ 2.5 V
–40°C ≤ TA ≤ +85°C
G=1 55 50 dB
G = 10 75 70 dB
G = 100 85 75 dB
G = 1000 85 75 dB
Power Supply Rejection PSRR 4.0 V ≤ VS ≤ 12 V
–40°C ≤ TA ≤ +85°C
G=1 95 85 dB
G = 10 105 95 dB
G = 100 105 95 dB
G = 1000 105 95 dB
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy G = 1 to 100 0.2 0.5 0.75 %
G = 1 to 100
–40°C ≤ TA ≤ +85°C 0.8 1.0 %
G = 1000 0.4 0.75 %
Gain Range G 1 1000 1 1000 V/V
Nonlinearity G = 1, RL = 5 kΩ 0.005 %
G = 10, RL = 5 kΩ 0.015 %
G = 100, RL = 5 kΩ 0.025 %
Gain Temperature Coefficient ∆G/∆T 30 50 ppm/°C
OUTPUT
Output Voltage Swing High VOH RL = 2 kΩ 4.0 4.2 4.0 V
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C 3.8 3.8 V
Output Voltage Swing Low VOL RL = 2 kΩ
–40°C ≤ TA ≤ +85°C 2.0 2.5 mV
Output Current Limit Sink 30 30 mA
Source 15 15 mA

–2– REV. B
 AMP04
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
NOISE
Noise Voltage Density, RTI eN f = 1 kHz, G = 1 270 270 nV/√Hz
f = 1 kHz, G = 10 45 45 nV/√Hz
f = 100 Hz, G = 100 30 30 nV/√Hz
f = 100 Hz, G = 1000 25 25 nV/√Hz
Noise Current Density, RTI iN f = 100 Hz, G = 100 4 4 pA/√Hz
Input Noise Voltage eN p-p 0.1 Hz to 10 Hz, G = 1 7 7 µV p-p
0.1 Hz to 10 Hz, G = 10 1.5 1.5 µV p-p
0.1 Hz to 10 Hz, G = 100 0.7 0.7 µV p-p
DYNAMIC RESPONSE
Small Signal Bandwidth BW G = 1, –3 dB 300 300 kHz
POWER SUPPLY
Supply Current ISY 550 700 700 µA
–40°C ≤ TA ≤ +85°C 850 850 µA
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (V = 15 V, V S CM = 0 V, TA = 25C unless otherwise noted)

AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
OFFSET VOLTAGE
Input Offset Voltage VIOS 80 400 600 µV
–40°C ≤ TA ≤ +85°C 600 900 µV
Input Offset Voltage Drift TCVIOS 3 6 µV/°C
Output Offset Voltage VOOS 1 3 6 mV
–40°C ≤ TA ≤ +85°C 6 9 mV
Output Offset Voltage Drift TCVOOS 30 50 µV/°C
INPUT CURRENT
Input Bias Current IB 17 30 40 nA
–40°C ≤ TA ≤ +85°C 50 60 nA
Input Bias Current Drift TCIB 65 65 pA/°C
Input Offset Current IOS 2 5 10 nA
–40°C ≤ TA ≤ +85°C 15 20 nA
Input Offset Current Drift TCIOS 28 28 pA/°C
INPUT
Common-Mode Input Resistance 4 4 GΩ
Differential Input Resistance 4 4 GΩ
Input Voltage Range VIN –12 +12 –12 +12 V
Common-Mode Rejection CMR –12 V ≤ VCM ≤ +12 V
G=1 60 80 55 dB
G = 10 80 100 75 dB
G = 100 90 105 80 dB
G = 1000 90 105 80 dB
Common-Mode Rejection CMR –11 V ≤ VCM ≤ +11 V
–40°C ≤ TA ≤ +85°C
G=1 55 50 dB
G = 10 75 70 dB
G = 100 85 75 dB
G = 1000 85 75 dB
Power Supply Rejection PSRR ± 2.5 V ≤ VS ≤ ± 18 V
–40°C ≤ TA ≤ +85°C
G=1 75 70 dB
G = 10 90 80 dB
G = 100 95 85 dB
G = 1000 95 85 dB

REV. B –3–
AMP04
AMP04E AMP04F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy G = 1 to 100 0.2 0.5 0.75 %
G = 1000 0.4 0.75 %
G = 1 to 100
–40°C ≤ TA ≤ +85°C 0.8 1.0 %
Gain Range G 1 1000 1 1000 V/V
Nonlinearity G = 1, RL = 5 kΩ 0.005 0.005 %
G = 10, RL = 5 kΩ 0.015 0.015 %
G = 100, RL = 5 kΩ 0.025 0.025 %
Gain Temperature Coefficient ∆G/∆T 30 50 ppm/°C
OUTPUT
Output Voltage Swing High VOH RL = 2 kΩ 13 13.4 13 V
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C 12.5 12.5 V
Output Voltage Swing Low VOL RL = 2 kΩ
–40°C ≤ TA ≤ +85°C –14.5 –14.5 V
Output Current Limit Sink 30 30 mA
Source 15 15 mA
NOISE
Noise Voltage Density, RTI eN f = 1 kHz, G = 1 270 270 nV/√Hz
f = 1 kHz, G = 10 45 45 nV/√Hz
f = 100 Hz, G = 100 30 30 nV/√Hz
f = 100 Hz, G = 1000 25 25 nV/√Hz
Noise Current Density, RTI iN f = 100 Hz, G = 100 4 4 pA/√Hz
Input Noise Voltage eN p-p 0.1 Hz to 10 Hz, G = 1 5 5 µV p-p
0.1 Hz to 10 Hz, G = 10 1 1 µV p-p
0.1 Hz to 10 Hz, G = 100 0.5 0.5 µV p-p
DYNAMIC RESPONSE
Small Signal Bandwidth BW G = 1, –3 dB 700 700 kHz
POWER SUPPLY
Supply Current ISY 750 900 900 µA
–40°C ≤ TA ≤ +85°C 1100 1100 µA
Specifications subject to change without notice.

WAFER TEST LIMITS (V = 5 V, V S CM = 2.5 V, TA = 25C unless otherwise noted)

Parameter Symbol Conditions Limit Unit
OFFSET VOLTAGE
Input Offset Voltage VIOS 300 µV max
Output Offset Voltage VOOS 3 mV max
INPUT CURRENT
Input Bias Current IB 40 nA max
Input Offset Current IOS 10 nA max
INPUT
Common-Mode Rejection CMR 0 V ≤ VCM ≤ 3.0 V
G=1 55 dB min
G = 10 75 dB min
G = 100 80 dB min
G = 1000 80 dB min
Common-Mode Rejection CMR VS = ± 15 V, –12 V ≤ VCM ≤ +12 V
G=1 55 dB min
G = 10 75 dB min
G = 100 80 dB min

–4– REV. B
 AMP04
Parameter Symbol Conditions Limit Unit
G = 1000 80 dB min
Power Supply Rejection PSRR 4.0 V ≤ VS ≤ 12 V
G=1 85 dB min
G = 10 95 dB min
G = 100 95 dB min
G = 1000 95 dB min
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy G = 1 to 100 0.75 % max
OUTPUT
Output Voltage Swing High VOH RL = 2 kΩ 4.0 V min
Output Voltage Swing Low VOL RL = 2 kΩ 2.5 mV max
POWER SUPPLY
Supply Current ISY VS = ± 15 900 µA max
700 µA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V
Common-Mode Input Voltage2 . . . . . . . . . . . . . . . . . . . ± 18 V RGAIN
1
RGAIN
8
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C 7 V+
Operating Temperature Range –IN 2

AMP04A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

AMP04E, F . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C +IN 3
6 VOUT
Junction Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

V– 4
Package Type JA3 JC Unit
5 REF
8-Lead Cerdip (Z) 148 16 °C/W
8-Lead Plastic DIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W AMP04 Die Size 0.075 × 0.99 inch, 7,425 sq. mils.
NOTES Substrate (Die Backside) Is Connected to V+.
1
Absolute maximum ratings apply to both DICE and packaged parts, unless Transistor Count, 81.
otherwise noted.
2
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
3
θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP, and LCC packages; θJA is specified for device
soldered in circuit board for SOIC package.

ORDERING GUIDE

Temperature VOS @ 5 V Package Package

Model Range TA = 25C Description Option
AMP04EP XIND 150 µV Plastic DIP N-8
AMP04ES XIND 150 µV SOIC SO-8
AMP04ES-REEL7 XIND 150 µV SOIC SO-8
AMP04FP XIND 300 µV Plastic DIP N-8
AMP04FS XIND 300 µV SOIC SO-8
AMP04FS-REEL XIND 150 µV SOIC SO-8
AMP04FS-REEL7 XIND 150 µV SOIC SO-8
AMP04GBC 25°C 300 µV

REV. B –5–
AMP04
APPLICATIONS
Common-Mode Rejection
The purpose of the instrumentation amplifier is to amplify the
difference between the two input signals while ignoring offset
and noise voltages common to both inputs. One way of judging
the device’s ability to reject this offset is the common-mode
gain, which is the ratio between a change in the common-mode
voltage and the resulting output voltage change. Instrumenta-
tion amplifiers are often judged by the common-mode rejection
ratio, which is equal to 20 × log10 of the ratio of the user-selected
differential signal gain to the common-mode gain, commonly
called the CMRR. The AMP04 offers excellent CMRR, guaran-
teed to be greater than 90 dB at gains of 100 or greater. Input
offsets attain very low temperature drift by proprietary laser-
trimmed thin-film resistors and high gain amplifiers.
Input Common-Mode Range Includes Ground
The AMP04 employs a patented topology (Figure 1) that uniquely
allows the common-mode input voltage to truly extend to zero
volts where other instrumentation amplifiers fail. To illustrate,
take for example the single supply, gain of 100 instrumentation
amplifier as in Figure 2. As the inputs approach zero volts, in
order for the output to go positive, amplifier A’s output (VOA)
must be allowed to go below ground, to –0.094 volts. Clearly
this is not possible in a single supply environment. Consequently
this instrumentation amplifier configuration’s input common-mode
voltage cannot go below about 0.4 volts. In comparison, the
AMP04 has no such restriction. Its inputs will function with a
zero-volt common-mode voltage.
Input Common-Mode Voltage Below Ground
Although not tested and guaranteed, the AMP04 inputs are
biased in a way that they can amplify signals linearly with common-
mode voltage as low as –0.25 volts below ground. This holds
true over the industrial temperature range from –40°C to +85°C.
Extended Positive Common-Mode Range
On the high side, other instrumentation amplifier configurations,
such as the three op amp instrumentation amplifier, can have
severe positive common-mode range limitations. Figure 3 shows
an example of a gain of 1001 amplifier, with an input common-
mode voltage of 10 volts. For this circuit to function, VOB must
swing to 15.01 volts in order for the output to go to 10.01 volts.
Clearly no op amp can handle this swing range (given a 15 V
supply) as the output will saturate long before it reaches the
supply rails. Again the AMP04’s topology does not have this
limitation. Figure 4 illustrates the AMP04 operating at the same
common-mode conditions as in Figure 3. None of the internal
nodes has a signal high enough to cause amplifier saturation. As
a result, the AMP04 can accommodate much wider common-
mode range than most instrumentation amplifiers.
10.00V
A
R
100k
5V R
200

VOA
10.01V
50A VOB R
100k
15.01V
R
B
10.01V

100k

RGAIN Figure 3. Gain = 1001, Three Op Amp Instrumentation

IN(–)
INPUT BUFFERS VOUT Amplifier
IN(+)
100k

11k
0.1A

10.00V 100
+15V

11k
10.01V
VOUT
100A 10V
100k

10.01V –15V
+15V 11k

100.1A
REF

Figure 1. Functional Block Diagram –15V 11.111V

11k

100k

0.01V
+ VOB
VIN B VOUT
0V Figure 4. Gain = 1000, AMP04
– VOA
A

100k
20k
20k
100k

0V –0.094V 0.01V
4.7A 5.2A
4.7A
2127

Figure 2. Gain = 100 Instrumentation Amplifier

–6– REV. B

Programming the Gain
The gain of the AMP04 is programmed by the user by selecting
a single external resistor—RGAIN:
Gain = 100 kΩ/RGAIN
The output voltage is then defined as the differential input
voltage times the gain.
VOUT = (VIN+ – VIN–) × Gain
In single supply systems, offsetting the ground is often desired
for several reasons. Ground may be offset from zero to provide
a quieter signal reference point, or to offset “zero” to allow a
unipolar signal range to represent both positive and negative
values.
In noisy environments such as those having digital switching,
switching power supplies or externally generated noise, ground
may not be the ideal place to reference a signal in a high accu-
racy system.
Often, real world signals such as temperature or pressure may
generate voltages that are represented by changes in polarity. In
a single supply system the signal input cannot be allowed to go
below ground, and therefore the signal must be offset to accom-
modate this change in polarity. On the AMP04, a reference
input pin is provided to allow offsetting of the input range.
The gain equation is more accurately represented by including
this reference input.
VOUT = (VIN+ – VIN–) × Gain + VREF
Grounding
The most common problems encountered in high performance
analog instrumentation and data acquisition system designs are
found in the management of offset errors and ground noise.
Primarily, the designer must consider temperature differentials
and thermocouple effects due to dissimilar metals, IR volt-
age drops, and the effects of stray capacitance. The problem
is greatly compounded when high speed digital circuitry, such
as that accompanying data conversion components, is brought
into the proximity of the analog section. Considerable noise and
error contributions such as fast-moving logic signals that easily
propagate into sensitive analog lines, and the unavoidable noise
common to digital supply lines must all be dealt with if the accu-
racy of the carefully designed analog section is to be preserved.
Besides the temperature drift errors encountered in the ampli-
fier, thermal errors due to the supporting discrete components
should be evaluated. The use of high quality, low-TC compo-
nents where appropriate is encouraged. What is more important,
large thermal gradients can create not only unexpected changes
in component values, but also generate significant thermoelec-
tric voltages due to the interface between dissimilar metals such
as lead solder, copper wire, gold socket contacts, Kovar lead
frames, etc. Thermocouple voltages developed at these junctions
commonly exceed the TCVOS contribution of the AMP04.
Component layout that takes into account the power dissipation
at critical locations in the circuit and minimizes gradient effects
and differential common-mode voltages by taking advantage of
input symmetry will minimize many of these errors.
REV. B
AMP04
High accuracy circuitry can experience considerable error con-
tributions due to the coupling of stray voltages into sensitive
areas, including high impedance amplifier inputs which benefit
from such techniques as ground planes, guard rings, and shields.
Careful circuit layout, including good grounding and signal
routing practice to minimize stray coupling and ground loops is
recommended. Leakage currents can be minimized by using
high quality socket and circuit board materials, and by carefully
cleaning and coating complete board assemblies.
As mentioned above, the high speed transition noise found in
logic circuitry is the sworn enemy of the analog circuit designer.
Great care must be taken to maintain separation between them
to minimize coupling. A major path for these error voltages will
be found in the power supply lines. Low impedance, load related
variations and noise levels that are completely acceptable in the
high thresholds of the digital domain make the digital supply
unusable in nearly all high performance analog applications.
The user is encouraged to maintain separate power and ground
between the analog and digital systems wherever possible,
joining only at the supply itself if necessary, and to observe
careful grounding layout and bypass capacitor scheduling in
sensitive areas.
Input Shield Drivers
High impedance sources and long cable runs from remote trans-
ducers in noisy industrial environments commonly experience
significant amounts of noise coupled to the inputs. Both stray
capacitance errors and noise coupling from external sources can
be minimized by running the input signal through shielded
cable. The cable shield is often grounded at the analog input
common, however improved dynamic noise rejection and a
reduction in effective cable capacitance is achieved by driving
the shield with a buffer amplifier at a potential equal to the
voltage seen at the input. Driven shields are easily realized with
the AMP04. Examination of the simplified schematic shows that
the potentials at the gain set resistor pins of the AMP04 follow
the inputs precisely. As shown in Figure 5, shield drivers are
easily realized by buffering the potential at these pins by a dual,
single supply op amp such as the OP213. Alternatively, applica-
tions with single-ended sources or that use twisted-pair cable
could drive a single shield. To minimize error contributions due
to this additional circuitry, all components and wiring should
remain in proximity to the AMP04 and careful grounding and
bypassing techniques should be observed.
1/2 OP213
VOUT
1/2 OP213
Figure 5. Cable Shield Drivers
–7–
AMP04
Compensating for Input and Output Errors Noise Filtering
To achieve optimal performance, the user needs to take into Unlike most previous instrumentation amplifiers, the output
account a number of error sources found in instrumentation stage’s inverting input (Pin 8) is accessible. By placing a capaci-
amplifiers. These consist primarily of input and output offset tor across the AMP04’s feedback path (Figure 6, Pins 6 and 8)
voltages and leakage currents.
CEXT
The input and output offset voltages are independent from one
another, and must be considered separately. The input offset
component will of course be directly multiplied by the gain of 100k

RGAIN
the amplifier, in contrast to the output offset voltage that is IN(–)
independent of gain. Therefore, the output error is the domi- INPUT BUFFERS VOUT
nant factor at low gains, and the input error grows to become IN(+)

the greater problem as gain is increased. The overall equation

11k

for offset voltage error referred to the output (RTO) is:
VOS (RTO) = (VIOS × G) + VOOS 11k

LP =
1
2 (100k
) CEXT
where VIOS is the input offset voltage and VOOS the output offset 100k

voltage, and G is the programmed amplifier gain.
The change in these error voltages with temperature must also REF

be taken into account. The specification TCVOS, referred to the Figure 6. Noise Band Limiting
output, is a combination of the input and output drift specifica-
a single-pole low-pass filter is produced. The cutoff frequency
tions. Again, the gain influences the input error but not the
(fLP) follows the relationship:
output, and the equation is:
TCVOS (RTO) = (TCVIOS × G) + TCVOOS 1
f LP =
In some applications the user may wish to define the error con- 2π (100 kΩ) CEXT
tribution as referred to the input, and treat it as an input error.
The relationship is: Filtering can be applied to reduce wide band noise. Figure 7a
shows a 10 Hz low-pass filter, gain of 1000 for the AMP04.
TCVOS (RTI) = TCVIOS + (TCVOOS / G) Figures 7b and 7c illustrate the effect of filtering on noise. The
The bias and offset currents of the input transistors also have an photo in Figure 7b shows the output noise before filtering. By
impact on the overall accuracy of the input signal. The input adding a 0.15 µF capacitor, the noise is reduced by about a
leakage, or bias currents of both inputs will generate an addi- factor of 4 as shown in Figure 7c.
tional offset voltage when flowing through the signal source
resistance. Changes in this error component due to variations +15V

with signal voltage and temperature can be minimized if both 100k

input source resistances are equal, reducing the error to a 0.15F
common-mode voltage which can be rejected. The difference in
bias current between the inputs, the offset current, generates a
differential error voltage across the source resistance that should
be taken into account in the user’s design.
In applications utilizing floating sources such as thermocouples,
transformers, and some photo detectors, the user must take –15V
care to provide some current path between the high imped-
ance inputs and analog ground. The input bias currents of Figure 7a. 10 Hz Low-Pass Filter
the AMP04, although extremely low, will charge the stray
capacitance found in nearby circuit traces, cables, etc., and
cause the input to drift erratically or to saturate unless given a
5mV 10ms
bleed path to the analog common. Again, the use of equal resis-
tance values will create a common input error voltage that is 100
90
rejected by the amplifier.
Reference Input
The VREF input is used to set the system ground. For dual sup-
ply operation it can be connected to ground to give zero volts
out with zero volts differential input. In single supply systems it 10
0%
could be connected either to the negative supply or to a pseudo-
ground between the supplies. In any case, the REF input must
be driven with low impedance.
Figure 7b. Unfiltered AMP04 Output

–8– REV. B
 AMP04
Offset Nulling in Single Supply
1mV 2s
Nulling the offset in single supply systems is difficult because
100 the adjustment is made to try to attain zero volts. At zero volts
90
out, the output is in saturation (to the negative rail) and the
output voltage is indistinguishable from the normal offset error.
Consequently the offset nulling circuit in Figure 9 must be used
with caution.
10 First, the potentiometer should be adjusted to cause the output
0%
to swing in the positive direction; then adjust it in the reverse
direction, causing the output to swing toward ground, until
the output just stops changing. At that point the output is at
the saturation limit.
Figure 7c. 10 Hz Low-Pass Filtered Output
RG
Power Supply Considerations
In dual supply applications (for example ± 15 V) if the input is
connected to a low resistance source less than 100 Ω, a large 1 AMP04 8

current may flow in the input leads if the positive supply is 2 7 5V

INPUT
applied before the negative supply during power-up. A similar 3 6 OUTPUT
condition may also result upon a loss of the negative supply. If 4 5
these conditions could be present in you system, it is recom- OP113
mended that a series resistor up to 1 kΩ be added to the input
leads to limit the input current.
This condition can not occur in a single supply environment
as losing the negative supply effectively removes any current 5V
100
50k

return path.
Figure 9. Offset Adjust for Single Supply Applications
Offset Nulling in Dual Supply
Offset may be nulled by feeding a correcting voltage at the VREF Alternative Nulling Method
pin (Pin 5). However, it is important that the pin be driven with An alternative null correction technique is to inject an offset
a low impedance source. Any measurable resistance will degrade current into the summing node of the output amplifier as in
the amplifier’s common-mode rejection performance as well as Figure 10. This method does not require an external op amp.
its gain accuracy. An op amp may be used to buffer the offset However, the drawback is that the amplifier will move off its
null circuit as in Figure 8. null as the input common-mode voltage changes. It is a less
desirable nulling circuit than the previous method.
RG
V+ V–

100k

1 AMP04 8 RGAIN
– 5V IN(–)
2 V+ 7
INPUT INPUT BUFFERS VOUT
+ 3 6 OUTPUT IN(+)
4 V– REF 5
+5V +5V
11k

–5V
50k

*
100
11k

*OP90 FOR LOW POWER 5mV
ADJ 50k
100k

OP113 FOR LOW DRIFT –5V RANGE
–5V
REF
Figure 8. Offset Adjust for Dual Supply Applications
Figure 10. Current Injection Offsetting Is Not
Recommended

REV. B –9–
AMP04
APPLICATION CIRCUITS output. Note that a 0 volt output is also the negative output swing
Low Power Precision Single Supply RTD Amplifier limit of the AMP04 powered with a single supply. Therefore, be
Figure 11 shows a linearized RTD amplifier that is powered sure to adjust R3 to first cause the output to swing positive and
from a single 5 volt supply. However, the circuit will work up to then back off until the output just stops swinging negatively.
36 volts without modification. The RTD is excited by a 100 µA
constant current that is regulated by amplifier A (OP295). The Next, set the LINEARITY ADJ potentiometer to the midrange.
0.202 volts reference voltage used to generate the constant current Substitute an exact 247.04 Ω resistor (equivalent to 400°C
is divided down from the 2.500 volt reference. The AMP04 ampli- temperature) in place of the RTD. Adjust the FULL-SCALE
fies the bridge output to a 10 mV/°C output coefficient. potentiometer for a 4.000 volts output.
Finally substitute a 175.84 Ω resistor (equivalent to 200°C
R9 temperature), and adjust the LINEARITY ADJ potentiometer
5V 50

for a 2.000 volts at the output. Repeat the full-scale and the
C3 R8 R10
R3
BALANCE 0.1F 383
100
half-scale adjustments as needed.
FULL-SCALE
R1 500
R2 ADJ When properly calibrated, the circuit achieves better than
26.7k
26.7k
3 7
1 C1 ± 0.5°C accuracy within a temperature measurement range
8 0.47F
AMP04 VOUT
from 0°C to 400°C.
6
RTD 2 5 0 4.00V Precision 4-20 mA Loop Transmitter with Noninteractive Trim
100
1 4
R4 (0C TO 400C) Figure 12 shows a full bridge strain gage transducer amplifier
100

1/2 A circuit that is powered off the 4-20 mA current loop. The AMP04
OP295 5V
R7 8 6 amplifies the bridge signal differentially and is converted to a
2 3
121k
7 1/2 B current by the output amplifier. The total quiescent current
OP295
0.202V 5 drawn by the circuit, which includes the bridge, the amplifiers,
4 50k

R5
1.02k

R6 and the resistor biasing, is only a fraction of the 4 mA null
11.5k
LINEARITY
ADJ. current that flows through the current-sense resistor RSENSE.
2.5V 6
RSENSE (@1/2 FS) The voltage across RSENSE feeds back to the OP90’s input,
1k
OUT
2 whose common-mode is fixed at the current summing reference
REF43 IN 5V
C2
GND 0.1F voltage, thus regulating the output current.
4
With no bridge signal, the 4 mA null is simply set up by the
NOTES: ALL RESISTORS 0.5%, 25 PPM/C 50 kΩ NULL potentiometer plus the 976 kΩ resistors that
ALL POTENTIOMETERS 25 PPM/C
inject an offset that forces an 80 mV drop across RSENSE. At a
Figure 11. Precision Single Supply RTD Thermometer 50 mV full-scale bridge voltage, the AMP04 amplifies the
Amplifier voltage-to-current converter for a full-scale of 20 mA at the
The RTD is linearized by feeding a portion of the signal back to output. Since the OP90’s input operates at a constant 0 volt
the reference circuit, increasing the reference voltage as the common-mode voltage, the null and the span adjustments do
temperature increases. When calibrated properly, the RTD’s not interact with one another. Calibration is simple and easy
nonlinearity error will be canceled. with the NULL adjusted first, followed by SPAN adjust. The
entire circuit can be remotely placed, and powered from the
To calibrate, either immerse the RTD into a zero-degree ice
4-20 mA 2-wire loop.
bath or substitute an exact 100 Ω resistor in place of the RTD.
Then adjust bridge BALANCE potentiometer R3 for a 0 volt

U3
5.00V 4mA NULL 6 REF02 2
OUT N
3500
STRAIN 2.49k

GAGE BRIDGE GND
0.22F 50k
1N4002
4
50mV 3 7
FS 1 5k
976k
0.1F
U1 8 10-TURN 97.6k
3 7 2k

AMP04 6 5%
U2 6
2 5 B T1P29A
OP90
20mA 2
4
SPAN HP 4 220pF
5082-2810 +VS

100k
12V TO 36V

13.3k

5%

RSENSE RLOAD
4-20mA
UNLESS OTHERWISE SPECIFIED, ALL RESISTORS 1% 20
100

15.8k

OR BETTER POTENTIOMETER < 50 PPM/C

INULL + ISPAN

Figure 12. Precision 4-20 mA Loop Transmitter Features Noninteractive Trims

–10– REV. B
 AMP04
4-20 mA Loop Receiver Single Supply Programmable Gain Instrumentation Amplifier
At the receiving end of a 4-20 mA loop, the AMP04 makes a Combining with the single supply ADG221 quad analog switch,
convenient differential receiver to convert the current back to the AMP04 makes a useful programmable gain amplifier that
a usable voltage (Figure 13). The 4-20 mA signal current passes can handle input and output signals at zero volts. Figure 15
through a 100 Ω sense resistor. The voltage drop is differentially shows the implementation. A logic low input to any of the gain
amplified by the AMP04. The 4 mA offset is removed by the control ports will cause the gain to change by shorting a gain-
offset correction circuit. set resistor across AMP04’s Pins 1 and 8. Trimming is required
at higher gains to improve accuracy because the switch ON-
+15V resistance becomes a more significant part of the gain-set
1N4002
4–20mA 100k
resistance. The gain of 500 setting has two switches connected
4–20mA 1k
7
0.15F in parallel to reduce the switch resistance.
3 1
TRANSMITTER 8
100
6
AMP04 VOUT 5V TO 30V
4–20mA 1% 1k
2 5 0–1.6V FS 13 ADG221 5
WIRE 4
4 –0.400V 10F 0.1F 10
RESISTANCE 11
2 9
–15V 200

OP177 7 6
POWER 3
6 8
SUPPLY GAIN OF 500 200

15 14
10k
16 715

GAIN GAIN OF 100
27k
CONTROL 2 3
–15V 1 10.9k

AD589 GAIN OF 10

Figure 13. 4-to-20 mA Line Receiver WR 12 100k

Low Power, Pulsed Load-Cell Amplifier 0.22F

RG RG
Figure 14 shows a 350 Ω load cell that is pulsed with a low duty
1 8

2
5V TO
V+ 7
cycle to conserve power. The OP295’s rail-to-rail output capa- INPUT
30V
3 VOUT
bility allows a maximum voltage of 10 volts to be applied to the 6

bridge. The bridge voltage is selectively pulsed on when a mea- 4 V–

AMP04
REF 5 0.1F

surement is made. A negative-going pulse lasting 200 ms should

be applied to the MEASURE input. The long pulsewidth is
necessary to allow ample settling time for the long time constant
of the low-pass filter around the AMP04. A much faster settling Figure 15. Single Supply Programmable Gain Instrumen-
time can be achieved by omitting the filter capacitor. tation Amplifier
The switch ON resistance is lower if the supply voltage is 12 volts
12V or higher. Additionally, the overall amplifier’s temperature coeffi-
IN cient also improves with higher supply voltage.
1k
10k

OUT REF01
330
1/2
OP295 GND

50k
MEASURE
2N3904
1N4148
12V

7 0.22F
3 1
8
6
AMP04 VOUT
350
2
5
4

Figure 14. Pulsed Load Cell Bridge Amplifier

REV. B –11–
AMP04
120 120

BASED ON 300 UNITS TA = 25C BASED ON 300 UNITS TA = 25C

VS = 5V 100 3 RUNS VS = 15V
100 3 RUNS VCM = 0V
VCM = 2.5V

NUMBER OF UNITS
NUMBER OF UNITS

80 80

60 60

40 40

20 20

0 0
–200 –160 –120 –80 –40 0 40 80 120 160 200 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
INPUT OFFSET VOLTAGE – V INPUT OFFSET VOLTAGE – mV

Figure 16. Input Offset (VIOS) Distribution @ 5 V Figure 19. Input Offset (VIOS) Distribution @ ± 15 V

120 120

300 UNITS 300 UNITS

VS = 5V 100 VS = 15V
100 VCM = 0V
VCM = 2.5V

NUMBER OF UNITS
NUMBER OF UNITS

80 80

60 60

40 40

20 20

0 0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
TCVIOS – V/ C TCVIOS – V/ C

Figure 17. Input Offset Drift (TCVIOS) Distribution @ 5 V Figure 20. Input Offset Drift (TCVIOS) Distribution @ ± 15 V

120 120

BASED ON 300 UNITS TA = 25C BASED ON 300 UNITS TA = 25C

100 3 RUNS VS = 5V 100 3 RUNS VS = 15V
VCM = 2.5V VCM = 0V
NUMBER OF UNITS
NUMBER OF UNITS

80 80

60 60

40 40

20 20

0 0
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT OFFSET – mV OUTPUT OFFSET – mV

Figure 18. Output Offset (VOOS) Distribution @ 5 V Figure 21. Output Offset (VOOS) Distribution @ ± 15 V

–12– REV. B
 AMP04
120 120

300 UNITS 300 UNITS

100 VS = 5V 100 VS = 15V
VCM = 0V VCM = 0V
NUMBER OF UNITS

NUMBER OF UNITS
80 80

60 60

40 40

20 20

0 0
0 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 22 24
TCVOOS – V/ C TCVOOS – V/ C

Figure 22. Output Offset Drift (TCVOOS) Distribution Figure 25. Output Offset Drift (TCVOOS) Distribution
@5V @ ± 15 V

+OUTPUT SWING – Volts

5.0 15.0
RL = 100k
VS = 5V
VS = 5V 14.5
OUTPUT VOLTAGE SWING – Volts

4.8 14.0
RL = 10k

13.5
4.6 13.0
RL = 100k
RL = 2k

12.5
4.4
–OUTPUT SWING – Volts

–14.6
RL = 2k

–14.7
4.2
RL = 2k
–14.8 RL = 10k

RL = 10k
–14.9
4.0
–15.0
RL = 100k

3.8 –15.1
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE – C TEMPERATURE – C

Figure 23. Output Voltage Swing vs. Temperature Figure 26. Output Voltage Swing vs. Temperature
@5V @ +15 V

40 8

VS = 5V, VCM = 2.5V VS = 5V, VCM = 2.5V

35
VS = 15V, VCM = 0V VS = 15V, VCM = 0V
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA

30 6

25 VS = 5V

20 4

15 VS = 15V
VS = 15V
10 2

5
VS = 5V
0 0
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE – C TEMPERATURE – C

Figure 24. Input Bias Current vs. Temperature Figure 27. Input Offset Current vs. Temperature

REV. B –13–
AMP04
50 120
TA = 25C TA = 25C
G = 100 VS = 15V G=1
100
40

OUTPUT IMPEDANCE –

80
30
VOLTAGE GAIN – dB

G = 10
60
20 VS = 15V

40
10

G=1
0 20
VS = 5V

–10 0

–20 –20
100 1k 10k 100k 1M 10 100 1k 10k 100k
FREQUENCY – Hz FREQUENCY – Hz

Figure 28. Closed-Loop Voltage Gain vs. Frequency Figure 31. Closed-Loop Output Impedance vs. Frequency

120
120
TA = 25C
TA = 25C VS = 15V
VS = 15V 110 VCM = 2V p-p

COMMON-MODE REJECTION – dB
100
COMMON-MODE REJECTION – dB

VCM = 2V p-p

80 100
G = 100

60 90

80
40
G=1

20 70
G = 10
60
0

–20 50
1 10 100 1k
1 10 100 1k 10k 100k
VOLTAGE GAIN – G
FREQUENCY – Hz

Figure 29. Common-Mode Rejection vs. Frequency Figure 32. Common-Mode Rejection vs. Voltage Gain

140 140
TA = 25C TA = 25C
120 VS = 15V 120 VS = 15V
POWER SUPPLY REJECTION – dB

POWER SUPPLY REJECTION – dB

VS = 1V VS = 1V

100 100
G = 100

80 80 G = 100

60 60

G=1 G=1
40 40

20 20
G = 10 G = 10

0 0
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz

Figure 30. Positive Power Supply Rejection vs. Frequency Figure 33. Negative Power Supply Rejection vs. Frequency

–14– REV. B
 AMP04
1k 1k
TA = 25C TA = 25C
VS = 15V VS = 15V
= 100Hz = 1kHz
VOLTAGE NOISE – nV/ Hz

VOLTAGE NOISE – nV/ Hz

100 100

10 10

1 1
1 10 100 1k 1 10 100 1k
VOLTAGE GAIN – G VOLTAGE GAIN – G

Figure 34. Voltage Noise Density vs. Gain Figure 37. Voltage Noise Density vs. Gain, f = 1 kHz

140
TA = 25C
VS = 15V 20mV 1s
120
VOLTAGE NOISE DENSITY – nV/ Hz

G = 100
100
90
100

80

60

40 10
0%

20

0
1 10 100 1k 10k VS = 15V, GAIN = 1000, 0.1 TO 10 Hz BANDPASS
FREQUENCY – Hz

Figure 35. Voltage Noise Density vs. Frequency Figure 38. Input Noise Voltage

1200 16
TA = 25C
VS = 15V
14
1000
12
SUPPLY CURRENT – A

VS = 15V
OUTPUT VOLTAGE – V

800
10

600 8
VS = 5V
6
400

4
200
2

0 0
–50 –25 0 25 50 75 100 10 100 1k 10k 100k
TEMPERATURE – C LOAD RESISTANCE –

Figure 36. Supply Current vs. Temperature Figure 39. Maximum Output Voltage vs. Load Resistance

REV. B –15–
AMP04
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP (N-8)

0.430 (10.92)

C00250–0–11/00 (rev. B)
0.348 (8.84)

8 5
0.280 (7.11)
0.240 (6.10)
1 4

PIN 1 0.325 (8.25)

0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52)
0.210 0.015 (0.38) 0.195 (4.95)
(5.33) 0.115 (2.93)
MAX
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.070 (1.77) SEATING 0.008 (0.204)
0.014 (0.356) 0.045 (1.15) PLANE

8-Lead Cerdip (Q-8)

0.005 (0.13) 0.055 (1.4)

MIN MAX

8 5

0.310 (7.87)
PIN 1 0.220 (5.59)
1 4

0.100 (2.54) BSC

0.320 (8.13)
0.405 (10.29) MAX
0.290 (7.37)
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
0.015 (0.38)
SEATING
0.023 (0.58) 0.070 (1.78) PLANE 15° 0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

8-Lead Narrow-Body SO (SO-8)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1
0.0500 (1.27) 0.0196 (0.50)
45
PRINTED IN U.S.A.
BSC 0.0099 (0.25)
0.0688 (1.75)
0.0098 (0.25) 0.0532 (1.35)
0.0040 (0.10) 8
0.0192 (0.49) 0.0500 (1.27)
SEATING 0.0098 (0.25) 0
PLANE 0.0138 (0.35) 0.0160 (0.41)
0.0075 (0.19)

–16– REV. B