ROUND 1:

 EDTbypass is passing. EDT chain patterns are failing. What could be the
reasons?
 (lockup latches not present between edtclock, shiftclock.)
 Two subchips are there. Shifting power is huge. HOw to reduce power
dissipation?
 What are the options you have, without affecting coverage and test time?
(HW or SW options)
 Setup vioations are there in your design. Which patterns would fail? (s@ or
@speed?)
 Hold vioations are there. Which patterns would fail?
 -ve, +ve flops are connected, +ve, -ve flops are connected without lockup
latch.
 Which one is better in terms of setup and hold timing?
 Why do we need a lockup latch at all? what happens if we dont use it?
 Two flops will have the same values during shift. Whats the effect of it?
 JTAG : how do you connect tdi, tdo, tms, trst, from board level TAP to all
chips on the board.
 explain an algorithm for MBIST.
 Where do we use parallel testbench? Whats the use of parallel simulations?
 TEstpoint? why do we need them?
 If you have simulations failures, what are the things you would look at?
 (setup, libs, clocks, what else?)
 In synthesis, if area is not meeting the target, what would you do?
 If some flops in two clock domains are failing, (S@ patterns), and those
failures are expected.
 HOw would you make them pass them on silicon? (no design changes are
allowed.)
 Atspeed coverage is always less than STUCK-at coverage. Why?
 P1500? are you aware of it?
ROUND 2:
 AND gate - optimal input pattern set to detect all S@ faults.
 how to swap two numbers in C (using a single line of code)
 2**300, 3**200 - which one is bigger?
 explain EDT logic.
 Simulation mismatches you have seen. how did you debug?
 LOC - LOS adv and disadv.
ROUND 3:
 What is the significance of DFT?
 why atspeed coverage is low than S@ coverage?
 why is target coverage 90% at intel? and 99% at marvell?
 What is that hindering you from achieving more coverage?
 what are the issues you've faced in pattern simulations?
ROUND 4:
 What is the need to do Timing simulations of ATPG patterns, even after the
timing is analysed completely?
 What is needed between two power domains, in the DFT perspective? (level
shifters?)
 Two different clock domains are there. How do you target the at-speed
faults?
 How do you improve fault coverage?
 What are the issues you've seen in simulations? (design bugs)
 Why do we need OCC?
 Why do we need EDT?
 How do you test multicycle paths at-speed?
 What happens if you don't specify any NCPs?
 What are EDT aborted faults?

 What is LSSD and Mux-DFF?

 Draw a logic ciruit to detect a rising edge in an input signal.
 Explain how scan works.
 What are Launch Off Capture, Launch Off Shift ?
 What are mealey and moore state machines? advantages and disadvantages.
 Explain boundary scan and tap controller.
 Design rule checks in ATPG (SCAN DRCs)
 Mismatch debug in ATPG.
 What is EDT logic and how does it work?
 How do the chains connect in EDTbypass mode? Compression ratio?
 How does the tester time reduce in EDT?
 Can you put just 1 flop in EDT mode chains and reduce the tester time to just
1 shift??
 Patterns count increases if chain length is reduced. Y??
 What is LOC, LOS? How do they work? Waveforms??
 What is DFT ? what are its adv and disadv?
 Why delay increases if u use mux DFF?
 What happens to setup time of the DFF in Mux DFF??
 Some comb logic is given.. is that fully controllable and observable ??
 Some Sequential ckt.. Controllable and observable ?? what do you do to
make it become so??
 Parallel pattern mismatches? How did u debug?
 Lock up latch use?
 Positive and negative edge triggered flops.. how will u connect in a chain?
 JTAG TAP?
 Explain EDT logic. Decompressor, Compactor.
 Masking logic, Mask shift and hold regs.
 Compression ratio, EDT control signals – EDT update, EDT clock
 Fault aliasing, Masking bits generation – coverage effects.
 2x1 MUX using NAND gates.
 Generate a Clock div by 2, with 25% duty cycle.
 To detect a fault in a circuit, what are the input test vectors to be given?
 All Test Patterns for an 2-input AND gate (optimal set).
 Sequence detector, whole circuit.
 Setup time, Hold time problems.
 LOC, LOS differences.
 Scan chain diagnosis – serial pattern failing on Silicon, How do you detect?
 ATPG DRC violations?
 Simulation mismatches debug.
 JTAG – Instructions – intest, extest, preload/sample.
 LOC, LOS – main difference.
 Scan chain connections, mux-DFF. (How is a scan chain is connected?)